Power Conversion Equipment

Abstract

A first controller (40) comprises a first processor and a first memory. A second controller (50) comprises a second processor and a second memory. When transmitting data from the first controller (40) to the second controller (50), the first controller (40) repeatedly executes an operation of writing the transmission data to the first memory according to a clock signal, and reads out the transmission data from the first memory for output to a communication line. The second controller (50) writes received data, which is received from the communication line, into the second memory according to the clock signal, and reads out the received data from the second memory according to the clock signal. The second controller (50) transfers a data value in a current clock cycle to the second processor if a plurality of data values in a plurality of consecutive clock cycles, including the current clock cycle, match in the read received data.

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device, and more particularly to a power conversion device including a plurality of power conversion modules connected in parallel. [Background technology]

[0002] Uninterruptible power supplies are widely used as power conversion devices for stably supplying AC power to important loads such as computer systems. Among uninterruptible power supplies, there is a modular uninterruptible power supply device that includes a plurality of power conversion modules connected in parallel to the load.

[0003] Each power conversion module of a modular uninterruptible power supply generally includes a converter that converts AC power to DC power, an inverter that converts DC power to AC power, and a controller for controlling these power converters. The multiple power conversion modules are connected to each other via communication lines so that they can communicate with each other. The controller of each power conversion module exchanges various data with the other power conversion modules via the communication lines, thereby realizing parallel synchronous operation of the multiple power conversion modules.

[0004] The controller of each power conversion module includes a processor such as a central processing unit (CPU) and a volatile memory such as a random access memory (RAM). The volatile memory temporarily stores programs executed by the processor and data used by the processor. The volatile memory is also called a main memory.

[0005] In each power conversion module, the possibility of a transient bit error (soft error) occurring in the volatile memory is increasing with the high integration and miniaturization of semiconductor devices. Soft errors are caused, for example, by collisions with neutrons from cosmic rays. If a soft error occurs in the volatile memory in any of the multiple power conversion modules, the modular uninterruptible power supply may malfunction or temporarily stop.

[0006] As a countermeasure against soft errors, for example, JP 2021-19394 A (Patent Document 1) proposes a technology in which a majority decision maker is provided in a control device of a power conversion device. This majority decision maker is configured to input one piece of data to three identically configured logic circuits to generate three pieces of data, and output the matching data if one or more sets of data among the three pieces of data match. Note that if there is no data with matching values, the majority decision maker determines that two or more pieces of data have a soft error and outputs a signal indicating that a soft error has occurred. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2021-19394 Summary of the Invention [Problem to be solved by the invention]

[0008] In order to apply the majority decision device described in Patent Document 1 to each power conversion module of the above-mentioned modular uninterruptible power supply, it is necessary to form three logic circuits for generating multiplexed signals and three communication paths for transmitting the multiplexed signals on a control board mounted on each power conversion module. This complicates the control board of each power conversion module. As a result, there is a concern that the entire modular uninterruptible power supply will become complicated and expensive.

[0009] The present disclosure has been made in consideration of the above problems, and has an object to provide a power conversion device that has a simplified configuration and is capable of suppressing malfunctions caused by the occurrence of soft errors. [Means for solving the problem]

[0010] A power conversion device according to an embodiment of the present disclosure includes a first and a second module connected in parallel to a load, a first and a second controller provided corresponding to the first and the second modules, respectively, and a communication line connecting the first and the second controllers. The first controller includes a first processor and a first memory for temporarily storing a program executed by the first processor and data used by the first processor. The second controller includes a second processor and a second memory for temporarily storing a program executed by the second processor and data used by the second processor. When transmitting data from the first controller to the second controller, the first controller repeatedly writes the transmission data to the first memory in accordance with a clock signal, and reads the transmission data from the first memory and outputs it to the communication line. The second controller writes the received data received from the communication line to the second memory in accordance with the clock signal, and reads the received data from the second memory in accordance with the clock signal. The second controller transfers the data value in the current clock cycle to the second processor when a plurality of data values ​​in a plurality of consecutive clock cycles including the current clock cycle match in the read received data. Effect of the Invention

[0011] According to the present disclosure, malfunctions in a power conversion device caused by the occurrence of soft errors can be suppressed with a simplified configuration. [Brief description of the drawings]

[0012] [Figure 1]1 is a circuit block diagram illustrating a configuration example of a power conversion device according to an embodiment of the present disclosure. [Diagram 2] 2 is a circuit block diagram showing a configuration example of a bypass module and a UPS module shown in FIG. 1. [Diagram 3] FIG. 2 is a block diagram showing an example of the hardware configuration of a main controller and a controller. [Figure 4] FIG. 11 is a diagram illustrating a processing procedure for transmitting data from the main controller to the controller. [Diagram 5] FIG. 5 is a diagram illustrating an example of the data illustrated in FIG. 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference characters, and their description will not be repeated in principle.

[0014] <Uninterruptible power supply configuration> 1 is a circuit block diagram showing a configuration example of a power conversion device according to an embodiment of the present disclosure. The power conversion device according to the present embodiment can be applied to, for example, an uninterruptible power supply 100 that supplies power to a load by connecting a plurality of power conversion modules in parallel.

[0015] 1, the uninterruptible power supply 100 includes a bypass module B0, a plurality of UPS modules U1 to Un (n is an integer equal to or greater than 2), and a communication line 15. The bypass module B0 and the UPS modules U1 to Un are connected to each other via the communication line 15 so as to be able to communicate with each other.

[0016] The bypass module B0 has an input terminal T1, an output terminal T2, and a switch (not shown) connected between the input terminal T1 and the output terminal T2.

[0017] Each of the UPS modules U1 to Un is a "power conversion module" having a converter and an inverter. In the following description, the UPS modules U1 to Un may be collectively referred to as a "UPS module U." The UPS module U has an input terminal T1, a battery terminal T2, and an output terminal T3.

[0018] The input terminal T11 of the bypass module B0 and the input terminal T1 of each UPS module U are both connected to the commercial AC power supply 30. The input terminal T11 and each input terminal T1 receive the AC voltage Vi of the commercial frequency supplied from the commercial AC power supply 30.

[0019] The battery terminal T12 of the bypass module B0 and the battery terminal T2 of each UPS module U are both connected to a battery 32. The battery 32 stores DC power. The battery 32 corresponds to one embodiment of the "power storage device." A capacitor may be connected in place of the battery 32.

[0020] The output terminal T13 of the bypass module B0 and the output terminal T3 of each UPS module U are both connected to the load 31. That is, the bypass module B0 and the UPS modules U1 to Un are connected in parallel with each other between the commercial AC power supply 30 and the load 31. The load 31 is driven by AC power supplied from the bypass module B0 or ​​the multiple UPS modules U1 to Un.

[0021] Such an uninterruptible power supply is called a "modular uninterruptible power supply." A modular uninterruptible power supply has a parallel circuit of UPS modules built inside, the number of which corresponds to the capacity of the uninterruptible power supply. If N UPS modules are required to supply power from an uninterruptible power supply, (N+1) UPS modules can be installed to improve the quality of the power supply by providing redundancy. This method of providing redundancy on a module-by-module basis in a single uninterruptible power supply is also called the "hot swap method." The hot swap method refers to a structure in which a UPS module can be stopped during operation of the uninterruptible power supply, and the UPS module can be pulled out and inserted. This allows the UPS module to be replaced while the uninterruptible power supply continues to supply power when the UPS module breaks down or is being inspected.

[0022] The uninterruptible power supply device 100 has an inverter power supply mode and a bypass power supply mode. The inverter power supply mode is a mode in which AC power is supplied from the UPS module U to the load 31. In the inverter power supply mode, AC power supplied from the commercial AC power supply 30 is converted to DC power by a converter of the UPS module U, and the DC power is converted to AC power by an inverter and supplied to the load 31. The bypass power supply mode is a mode in which AC power is supplied from the commercial AC power supply 30 to the load 31 via the bypass module B0. In the bypass power supply mode, the AC power supplied from the commercial AC power supply 30 is supplied to the load 31 without passing through the UPS module U.

[0023] Fig. 2 is a circuit block diagram showing a configuration example of the bypass module B0 and the UPS module U shown in Fig. 1. The uninterruptible power supply 100 converts three-phase AC power from a commercial AC power supply 30 into DC power, and then converts the DC power into three-phase AC power to supply to a load 31. In Fig. 2, for the sake of simplicity of the drawing and explanation, only a portion of the circuit corresponding to one of the three phases (U phase, V phase, W phase) is shown.

[0024] (Bypass module B0) As shown in Fig. 2, the bypass module B0 includes a semiconductor switch 20, a main controller 40, and an operation unit 24. The semiconductor switch 20 is connected between an input terminal T11 and an output terminal T12. The semiconductor switch 20 is, for example, a thyristor switch having a pair of thyristors connected in anti-parallel. The semiconductor switch 20 is controlled by the main controller 40. The semiconductor switch 20 is turned off in the inverter power supply mode and turned on in the bypass power supply mode.

[0025] The operation unit 24 includes a plurality of buttons operated by a user of the uninterruptible power supply 100, a display that displays various information, etc. By operating the operation unit 24, the user can turn the power of the uninterruptible power supply 100 on and off, and select one of the bypass power supply mode and the inverter power supply mode.

[0026] The operation unit 24 is also connected to a communication network (not shown) and is capable of exchanging data with an external device of the uninterruptible power supply 100 via the communication network. The external device includes, for example, a PC or a server. The operation unit 24 may further include a USB connector. In this case, the operation unit 24 exchanges data with the external device via the USB connector.

[0027] (UPS Module U) The UPS module U includes switches S1 to S3, capacitors 1, 5, and 10, reactors 2 and 9, a converter 4, a DC line 6, a bidirectional chopper , an inverter 8, a current detector 13, and a controller .

[0028] The switch S1 and the reactor 2 are connected in series between the input terminal T1 and the input node of the converter 4. The capacitor 1 is connected to a node N1 between the switch S1 and the reactor 2. The switch S1 is turned on when the corresponding UPS module U is put into operation, and is turned off when the corresponding UPS module U is put into a stopped state. The instantaneous value of the AC input voltage Vi appearing at the node N1 is detected by the controller 50. The presence or absence of a power outage in the commercial AC power supply 30 is determined based on the instantaneous value of the AC input voltage Vi.

[0029] The capacitor 1 and the reactor 2 constitute an AC filter 3. The AC filter 3 is a low-pass filter that passes AC power of a commercial frequency from the commercial AC power supply 30 to the converter 4 and prevents a signal of a switching frequency generated in the converter 4 from passing to the commercial AC power supply 30.

[0030] The converter 4 is controlled by a controller 50, and during normal times when AC power is supplied from the commercial AC power supply 30, the converter 4 converts the AC power into DC power and outputs it to the DC line 6. When the commercial AC power supply 30 experiences a power outage, the operation of the converter 4 is stopped.

[0031] The capacitor 5 is connected to the DC line 6 and smoothes the voltage of the DC line 6. The instantaneous value of the DC voltage VD appearing on the DC line 6 is detected by a controller 50. The DC line 6 is connected to a high-voltage side node of a bidirectional chopper 7, and a low-voltage side node of the bidirectional chopper 7 is connected to a battery terminal T12 via a switch S2.

[0032] The switch S2 is turned on when the corresponding UPS module U is in use, and turned off during maintenance of the corresponding UPS module U and the battery 32. The instantaneous value of the inter-terminal voltage VB of the battery 32 appearing at the battery terminal T2 is detected by the controller 50.

[0033] The bidirectional chopper 7 is controlled by the controller 50. Under normal circumstances, the bidirectional chopper 7 stores the DC power generated by the converter 4 in the battery 32, and when the commercial AC power supply 30 experiences a power outage, the bidirectional chopper 7 supplies the DC power of the battery 32 to the inverter 8 via the DC line 6.

[0034] When storing DC power in the battery 32, the bidirectional chopper 7 steps down the DC voltage VD of the DC line 6 and supplies it to the battery 32. When supplying DC power from the battery 32 to the inverter 8, the bidirectional chopper 7 steps up the terminal voltage VB of the battery 32 and outputs it to the DC line 6. The DC line 6 is connected to the input node of the inverter 8.

[0035] An output node of the inverter 8 is connected to a first terminal of a reactor 9, and a second terminal (node ​​N2) of the reactor 9 is connected to an output terminal T3 via a switch S3. A capacitor 10 is connected to the node N2. An instantaneous value of an AC output voltage Vo appearing at the node N2 is detected by a controller 50. A current detector 13 detects an instantaneous value of a current Io flowing from the node N2 to an output terminal T13 (i.e., a load 31) via the switch S3, and provides a signal Iof indicating the detected value to the controller 50.

[0036] The reactor 9 and the capacitor 10 configure an AC filter 11. The AC filter 11 is a low-pass filter that passes AC power of the commercial frequency generated by the inverter 8 to the output terminal T3 and prevents a signal of a switching frequency generated by the inverter 8 from passing to the output terminal T3. The switch S3 is controlled by the controller 50, and is turned on when the corresponding UPS module U is put into operation and is turned off when the corresponding UPS module U is put into a stopped state.

[0037] The controller 50 controls the entire corresponding UPS module U based on the AC input voltage Vi, the DC voltage VD, the terminal voltage VB of the battery 32, the AC output current Io, and the AC output voltage Vo, etc. That is, the controller 50 detects whether or not a power outage has occurred based on the detected value of the AC input voltage Vi, and controls the converter 4 and the inverter 8 in synchronization with the phase of the AC input voltage Vi.

[0038] Moreover, the controller 50 normally controls the converter 4 so that the DC voltage VD becomes the desired target voltage VDT, and stops the operation of the converter 4 when a power outage occurs in the commercial AC power supply 30. Furthermore, the controller 50 normally controls the bidirectional chopper 7 so that the terminal voltage VB of the battery 32 becomes the desired target battery voltage VBT, and when a power outage occurs in the commercial AC power supply 30, controls the bidirectional chopper 7 so that the DC voltage VD becomes the desired target voltage VDT.

[0039] The controller 50 is also connected to the main controller 40 and the controllers 50 of the other UPS modules U by a communication line 15, and exchanges various data with the main controller 40 and the other controllers 50 via the communication line 15. A serial communication method is used as the communication method between the main controller 40 and each controller 50. The controller 50 controls the converter 4 and the inverter 8 based on the data from the main controller 40 and the other controllers 50 so that the shared currents of the multiple UPS modules U are equal.

[0040] The main controller 40 controls the entire uninterruptible power supply 100 based on signals from the multiple UPS modules U. Each controller 50 controls the corresponding UPS module U according to a control command given by the main controller 40.

[0041] Specifically, the main controller 40 calculates the sum of the output currents Io of the multiple UPS modules U, i.e., the load current IL, based on the output signals Iof of the multiple current detectors 13 transmitted from each controller 50, and calculates the appropriate number of operating UPS modules U required to supply the load current IL. Furthermore, the main controller 40 compares the calculated appropriate number of operating modules with the current number of operating modules, and determines whether to operate each UPS module U or to stop each UPS module U based on the comparison result. The main controller 40 transmits a signal indicating the determination result to each controller 50 via the communication line 15.

[0042] When the controller 50 puts the corresponding UPS module U into a stopped state, it turns off the corresponding switches S1, S3 and stops the operation of the corresponding converter 4, bidirectional chopper 7, and inverter 8. When the controller 50 puts the corresponding UPS module U into an operating state, it maintains the corresponding switches S1, S3 in an on state and continues the operation of the corresponding converter 4, bidirectional chopper 7, and inverter 8.

[0043] (Example of Hardware Configuration of Main Controller 40 and Controller 50) FIG. 3 is a block diagram showing an example of the hardware configuration of the main controller 40 and the controller 50. As shown in FIG.

[0044] 3, the main controller 40 includes a CPU (Central Processing Unit) 41, a ROM (Read Only Memory) 42, a RAM (Random Access Memory) 43, a storage device 44, and an I / F (Interface) device 45. The CPU 41, the ROM 42, the RAM 43, the storage device 44, and the I / F device 45 exchange various data through a communication bus.

[0045] The CPU 41 loads a program stored in the ROM 42 into the RAM 43 and executes it. The program stored in the ROM 42 describes the processes to be executed by the main controller 40 of the bypass module B0. The RAM 43 temporarily holds the program executed by the CPU 41 and data used by the CPU 41. The RAM 43 is a volatile memory and functions as the main memory in the main controller 40.

[0046] The I / F device 45 is an input / output device for exchanging signals and data with the controller 50 of each UPS module U. The I / F device 45 is connected to the communication line 15, and receives various signals from the controller 50 of each UPS module U via the communication line 15. In addition, the I / F device 45 transmits various signals, such as control commands generated by the CPU 41, to the controller 50 of each UPS module U via the communication line 15.

[0047] The storage device 44 is a storage for storing various information, and stores information on the uninterruptible power supply 100, information on each UPS module U, and various information received by the operation unit 24. The information on each UPS module U includes the output signal Iof of the current detector 13 in each UPS module U, and fault information indicating the presence or absence of a fault in each UPS module U. The various information from the operation unit 24 includes mode setting information indicating whether the uninterruptible power supply 100 is set to a bypass power supply mode or an inverter power supply mode, and setting information related to the priority order in which the multiple UPS modules U1 to Un are stopped. The storage device 44 is, for example, a rewritable semiconductor memory such as a flash memory, a hard disk drive (HDD: Hard Disk Drive), or the like.

[0048] A switch I / F 48 is connected to the main controller 40. The switch I / F 48 turns the semiconductor switch 20 on or off in accordance with an on command or an off command given from the main controller 40.

[0049] The controller 50 includes a CPU 51, a ROM 52, a RAM 53, a storage device 54, and an I / F device 55. The CPU 51, the ROM 52, the RAM 53, the storage device 54, and the I / F device 55 exchange various data via a communication bus.

[0050] The CPU 51 loads a program stored in the ROM 52 into the RAM 53 and executes it. The program stored in the ROM 52 describes processes to be executed by the controller 50 of the UPS module U. The RAM 53 temporarily holds the program executed by the CPU 51 and data used by the CPU 51. The RAM 53 is a volatile memory and functions as the main memory in the controller 50.

[0051] The I / F device 55 is an input / output device for exchanging signals and data with the main controller 40 of the bypass module B0 and the controllers 50 of the other UPS modules U. The I / F device 55 is connected to the communication line 15, and receives various signals such as control commands from the main controller 40 via the communication line 15. The I / F device 55 also receives various signals from the controllers 50 of the other UPS modules U. The I / F device 55 transmits the output signal Iof of the current detector 13 and fault information to the main controller 40 via the communication line 15.

[0052] The storage device 54 is a storage for storing various information, and stores information about the UPS modules U and various information received from the main controller 40. The information about the UPS modules U includes the output signal Iof of the current detector 13 in the UPS modules U and fault information indicating the presence or absence of a fault in each UPS module U. The various information received from the main controller 40 includes mode setting information and control commands. The storage device 54 is, for example, a rewritable semiconductor memory such as a flash memory, an HDD, or the like.

[0053] A detector 56, a gate driver (GD) 57, and a switch I / F 58 are connected to the controller 50. The detector 56 includes detectors for detecting instantaneous values ​​of the AC input voltage Vi, the DC voltage VD, the terminal voltage VB of the battery 32, and the AC output voltage Vo. The detector 56 further includes a current detector 13.

[0054] The gate driver 57 has a gate driver for driving a plurality of switching elements included in the converter 4, a gate driver for driving a plurality of switching elements included in the bidirectional chopper 7, and a gate driver for driving a plurality of switching elements included in the inverter 8. Each gate driver drives a corresponding plurality of switching elements in accordance with a gate signal provided from the controller 50.

[0055] The switch I / F 58 turns on or off the switches S1 to S3 in accordance with an on command or an off command given from the controller 50.

[0056] The main controller 40 and the multiple controllers 50 control the operation of the bypass module B0 and each UPS module U by exchanging data with each other via the communication lines 15. The communication lines 15 are configured to transfer data bidirectionally by serial communication. This makes it possible to suppress an increase in the number of communication lines 15 even if the number of UPS modules U (i.e., the number of controllers 50) increases.

[0057] On the other hand, in each module, the possibility of a transient bit error (soft error) occurring in the memory is increasing with the high integration and miniaturization of semiconductor devices. Soft errors are caused, for example, by the collision of cosmic ray neutrons. If a soft error occurs in the RAM in either the bypass module B0 or ​​the UPS module U, the uninterruptible power supply 100 may malfunction or temporarily stop.

[0058] As a measure against soft errors, the above-mentioned Patent Document 1 proposes a technology of providing a majority decision maker in a control device of a power conversion device. This majority decision maker is configured to input one piece of data to three identically configured logic circuits to generate three pieces of data, and output the matching data when one or more sets of data among the three pieces of data match. If there is no data with matching values, the majority decision maker determines that two or more pieces of data have a soft error, and outputs a signal indicating that a soft error has occurred.

[0059] However, in order to realize the above-mentioned majority decision unit in each module of the uninterruptible power supply 100, it is necessary to form three logic circuits for generating multiplexed signals and three communication paths for transmitting the multiplexed signals on the control board mounted on each module. This makes the control board of each module complicated, which raises concerns that the entire uninterruptible power supply 100 will become complicated and expensive.

[0060] Therefore, in this embodiment, a novel configuration is provided that can suppress malfunctions of the uninterruptible power supply 100 caused by soft errors with a simpler configuration without using a conventional majority decision device.

[0061] 4 is a diagram illustrating the processing procedure for data transmission from the main controller 40 to the controller 50. Note that the processing procedure shown below can also be applied to data transmission between a plurality of controllers 50.

[0062] 4, in the main controller 40, the RAM 43 receives transmission data D1 from the CPU 41 or the storage device 44. The transmission data D1 is data to be transmitted to each controller 50, such as a control command generated by the CPU 41 and mode setting information from the storage device 44. The RAM 43 generates transmission data D2 to be transmitted to the controller 50 from the received transmission data D1. The RAM 43 outputs the generated transmission data D2 to the communication line 15.

[0063] The RAM 43 includes a memory cell array 60, a write circuit 62, a read circuit 64, and a decoder 66. The memory cell array 60 has a plurality of memory cells MC arranged in a matrix. Each memory cell MC is configured to store one bit of data. However, a soft error may occur due to collision with a cosmic ray neutron, which may disrupt the data held in the memory cell MC.

[0064] The decoder 66 selects a memory cell MC from the memory cell array 60 in accordance with an address signal from the CPU 41. The write circuit 62, during a write operation, writes data into the memory cell MC selected by the decoder 66. The read circuit 64, during a read operation, reads data from the memory cell MC selected by the decoder 66.

[0065] The flow of generating the transmission data D2 from the transmission data D1 will be described below. The write circuit 62 writes the transmission data D1 to the selected memory cell MC. At this time, the write circuit 62 repeatedly writes the transmission data D1 to the memory cell MC in accordance with the clock signal CLK provided from a clock generating circuit (not shown). As a result, the data held in the memory cell MC is updated every clock cycle of the clock signal CLK. Therefore, even if a soft error occurs in a certain memory cell MC, correct data is written to the memory cell MC in the next clock cycle, so that the memory cell MC can return to its original normal state.

[0066] The read circuit 64 reads out the transmission data D1 from the selected memory cell MC in accordance with the clock signal CLK, and outputs the read out transmission data D1 to the I / F device 45. The I / F device 45 outputs the transmission data D1 from the RAM 43 to the communication line 15 as data D2. The transmission data D2 is transmitted to the controller 50 via the communication line 15.

[0067] In the controller 50, when the I / F device 55 receives the data D2 from the main controller 40 via the communication line 15, the I / F device 55 stores the received data D2 in the RAM 53. The data D2 stored in the RAM 53 is transferred to the CPU 51 and used in the arithmetic processing executed by the CPU 51.

[0068] The RAM 53 includes a memory cell array 60, a write circuit 62, a read circuit 64, a decoder 66, and a determination circuit 68. The RAM 53 differs from the RAM 43 in that it includes the determination circuit 68. The determination circuit 68 is provided between the read circuit 64 and the CPU 51. The determination circuit 68 is a circuit for generating data D4 to be transferred to the CPU 51 from data D3 received from another controller (the main controller 40 or the controller 50).

[0069] The flow of generating the data D4 from the received data D2 will be described below. When the write circuit 62 receives the received data D2 from the I / F device 55, it writes the received data D2 into the memory cell MC selected by the decoder 66 in accordance with the clock signal CLK provided from a clock generating circuit (not shown). That is, the write operation of the received data D2 is executed every clock cycle, and the data held in the memory cell MC is updated. Therefore, even if a soft error occurs in a certain memory cell MC, the correct data is written into the memory cell MC in the next clock cycle, so that the memory cell MC can be restored to its original normal state.

[0070] The read circuit 64 reads the received data from the selected memory cell MC in accordance with the clock signal CLK, and outputs the read received data D3 to the decision circuit 68.

[0071] The decision circuit 68 receives the received data D3 from the read circuit 64 for each clock cycle. The decision circuit 68 compares the values ​​of the data D3 for a number of consecutive clock cycles including the current clock cycle. In the following description, it is assumed that the decision circuit 68 compares the values ​​of the data D3 for three consecutive clock cycles. Note that the number of values ​​of the data D3 to be compared is not limited to three, and may be two or four or more.

[0072] The determination circuit 68 compares the value of the data D3 in the current clock cycle with the value of the data D3 in the previous clock cycle and the value of the data D3 in the clock cycle before the previous cycle. If these three data values ​​all match, the determination circuit 68 determines that the value of the data D3 in the current clock cycle is correct. In this case, the determination circuit 68 transfers the data D3 in the current clock cycle to the CPU 51 as data D4 from the main controller 40.

[0073] On the other hand, if at least one of the three data values ​​is different, the decision circuit 68 decides that there is a possibility that a data error due to a soft error has occurred in one of the three data values. In this case, the decision circuit 68 does not transfer the data D3 in the current clock cycle to the CPU 51. The decision circuit 68 transfers to the CPU 51 the data D4 having the same value as the data D4 transferred in the previous clock cycle.

[0074] For example, if a temporary data error occurs in the current clock cycle due to a soft error, the value of data D3 in the current clock cycle will be different from the values ​​of data D3 in the clock cycles before the previous one and the previous one. In this case, data D3 in the current clock cycle is not transferred to CPU 51, so that CPU 51 can be prevented from executing arithmetic processing using erroneous data.

[0075] On the other hand, even if the value of the data D2 transmitted from the main controller 40 itself is changed in a situation where no soft error has occurred, the value of the data D3 in the current clock cycle may differ from the values ​​of the data D3 in the clock cycle before last and the one before that.

[0076] In such a case, the determination circuit 68 holds the value of the data D4 to be transferred to the CPU 51 and continues to compare the data D3 from the next clock cycle onwards. When the values ​​of the three pieces of data D3 in the current clock cycle, the next clock cycle and the cycle after that all match, the determination circuit 68 determines that the value of the transmission data D2 itself has been changed. In response to the match of all three pieces of data D3, the determination circuit 68 transfers the value of the data D3 to the CPU 51.

[0077] Conversely, if the value of data D3 in the next or subsequent clock cycles differs from the value of data D3 in the current clock cycle, the decision circuit 68 determines that a temporary data error occurred in the current clock cycle. In this case, the decision circuit 68 transfers the value of data D3 to the CPU 51 in response to the fact that all three data D3 values ​​match again.

[0078] Fig. 5 is a diagram showing an example of the data D1 to D4 shown in Fig. 4. In Fig. 5, from the top, transmission data D1, transmission data D2, reception data D3, and data D4 transferred to the CPU 51 are shown.

[0079] 4, the transmission data D1 generated by the CPU 41 of the main controller 40 on the transmitting side is provided as data D4 to the CPU 51 of the controller 50 on the receiving side. In the following description, the value of the transmission data D1 is assumed to be "A" as an initial value, and is changed from "A" to "B" while the uninterruptible power supply 100 is in operation.

[0080] In the main controller 40, the transmission data D1 is repeatedly written to the memory cells MC of the RAM 43 in accordance with the clock signal CLK. The written transmission data D1 is read from the memory cells MC in accordance with the clock signal CLK, and is output as transmission data D2 from the I / F device 45 to the communication line 15. By this write / read operation to the RAM 43, the transmission data D2 is updated every clock cycle. Therefore, the transmission data D2 in each clock cycle has the same value "A" as the transmission data D1.

[0081] However, if a soft error occurs in the RAM 43 of the main controller 40 in a certain clock cycle, the transmission data D2 in that clock cycle will have a value different from the transmission data D1. In Fig. 5, it is assumed that the value of the transmission data D2 is changed from "A" to "B" due to the influence of the soft error.

[0082] In the next clock cycle, the transmission data D1 is again written to the memory cell MC of the RAM 43. Therefore, the value of the transmission data D2 in the next clock cycle becomes the same value "A" as the transmission data D1. By repeatedly executing the writing operation of the transmission data D1 in this manner, the error in the transmission data D2 due to the soft error can be corrected.

[0083] When the value of the transmission data D1 is changed from "A" to "B", the value of the transmission data D2 is also changed from "A" to "B" in response to this change.

[0084] In the receiving controller 50, the transmission data D2 is written to the memory cell MC of the RAM 53 in accordance with the clock signal CLK. The written transmission data D2 is read from the memory cell MC in accordance with the clock signal CLK and is provided to the decision circuit 68 as the reception data D3. The reception data D3 and the transmission data D2 are basically the same. Therefore, the reception data D3 contains the same data error as the reception data D2.

[0085] When the decision circuit 68 receives the received data D3 from the read circuit 64 for each clock cycle, it compares the values ​​of the data D3 for three consecutive clock cycles including the current clock cycle. That is, the decision circuit 68 compares the value of the data D3 in the current clock cycle with the value of the data D3 in the previous clock cycle and the value of the data D3 in the clock cycle before the previous one.

[0086] 5, if all three values ​​are "A," the determination circuit 68 determines that the value "A" of the data D3 in the current clock cycle is correct. Therefore, the determination circuit 68 transfers the data D3 in the current clock cycle to the CPU 51 as data D4 from the main controller 40.

[0087] On the other hand, if these three values ​​do not match, the decision circuit 68 determines that there is a possibility that an error due to a soft error has occurred in one of the three values. If two are "A" and the remaining one is "B" as in Fig. 5, the decision circuit 68 determines that there is a possibility that "B" is a data error. Therefore, the decision circuit 68 does not transfer data D3 in the current clock cycle to the CPU 51, but transfers data D4 having the same value "A" as data D4 transferred in the previous clock cycle to the CPU 51.

[0088] The determination circuit 68 repeatedly executes the above determination operation for each clock cycle. Therefore, a temporary data error due to a soft error contained in the received data D3 is masked by the correct data located before and after this data, and as a result, is not reflected in the data D4. This makes it possible to prevent the data D4 containing the error from being transferred to the CPU 51 and used for arithmetic processing. Therefore, it is possible to suppress malfunction or temporary stop of the uninterruptible power supply 100.

[0089] Although not shown in the figure, when the transmission data D2 does not contain a data error, but a soft error occurs in the RAM 53 of the controller 50, the reception data D3 may contain a data error. Even in such a case, the determination circuit 68 masks the temporary data error contained in the reception data D3 with correct data located before and after this data, so that the data D4 is not affected.

[0090] 5, when the value of the transmission data D1 is changed from "A" to "B", the values ​​of the transmission data D2 and the reception data D3 in each clock cycle are also changed from "A" to "B". The determination circuit 68 determines that the value of the transmission data D2 itself has been changed since the values ​​of the data D3 in the current clock cycle, the previous clock cycle, and the clock cycle before the previous all become "B". Therefore, the determination circuit 68 transfers the data D3 in the current clock cycle to the CPU 51 as data D4.

[0091] 4 and 5, the processing procedure when transmitting data from the main controller 40 to the controller 50 has been described, but similar processing is also performed when transmitting data from a controller 50 to the main controller 40, and when transmitting data from a controller 50 to another controller 50.

[0092] That is, in the transmitting controller 50, the transmission data is repeatedly written to the memory cells MC of the RAM 53 in accordance with the clock signal CLK. Also, the transmission data is read out from the RAM 53 and output to the communication line 15 in accordance with the clock signal CLK.

[0093] In the receiving main controller 40 or other controller 50, the data received via the communication line 15 is written to memory cells MC of the RAM 43 or 53 in accordance with the clock signal CLK, and is also read from the RAM 43 or 53 in accordance with the clock signal CLK and output to the decision circuit 68. The decision circuit 68 compares the values ​​of the received data in a number of successive clock cycles including the current clock cycle. When the values ​​of the multiple received data all match, the decision circuit 68 transfers the value of the data in the current clock cycle to the CPU 41 or 51.

[0094] With the above-mentioned configuration, according to this embodiment, it is possible to prevent the use of erroneous data due to a soft error occurring in the RAM in any of the modules without providing a majority decision device in the controller of each module, and as a result, it is possible to prevent the uninterruptible power supply 100 from malfunctioning or temporarily stopping.

[0095] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0096] 1,5,10 capacitor, 2,9 reactor, 3,11 AC filter, 4 converter, 6 DC line, 7 bidirectional chopper, 8 inverter, 13 current detector, 15 communication line, 20 semiconductor switch, 24 operation unit, 30 commercial AC power supply, 31 load, 32 battery, 40 main controller, 41,51 CPU, 42,52 ROM, 43,53 RAM, 44,54 storage device, 45,55 I / F device, 48,58 switch I / F, 50 controller, 56 detector, 57 gate driver, 60 memory cell array, 62 write circuit, 64 read circuit, 66 decoder, 100 uninterruptible power supply, B0 bypass module, U1~Un,U UPS module, S1~S3 switch.

Claims

1. A power conversion device, first and second modules connected in parallel to a load; a first controller and a second controller provided corresponding to the first module and the second module, respectively; a communication line communicatively connecting the first and second controllers; The first controller includes: A first processor; a first memory for temporarily storing a program executed by the first processor and data used by the first processor; The second controller includes: A second processor; and a second memory for temporarily storing a program executed by the second processor and data used by the second processor; When transmitting data from the first controller to the second controller, The first controller includes: repeatedly executing an operation of writing transmission data to the first memory in accordance with a clock signal, and reading the transmission data from the first memory in accordance with the clock signal and outputting the transmission data to the communication line; The second controller includes: writing received data received from the communication line into the second memory in accordance with the clock signal, and reading the received data from the second memory in accordance with the clock signal; When data values ​​in the read received data match in a plurality of successive clock cycles including the current clock cycle, the power conversion device transfers the received data in the current clock cycle to the second processor.

2. 2. The power conversion device according to claim 1, wherein the second controller retransfers the received data transferred in a previous clock cycle to the second processor when all of the data values ​​in the plurality of clock cycles do not match.

3. the first and second modules are first and second power conversion modules connected in parallel between an AC power source and the load; each of the first and second power conversion modules includes a power converter that receives AC power from the AC power source and generates AC power to be supplied to the load; The power conversion device according to claim 1 or 2, wherein the first controller transmits data relating to an operating state of the power converter of the first power conversion module to the second controller.

4. The power conversion device according to claim 3 , wherein the data relating to the operating state of the power converter of the first power conversion module includes a detected value of an output current of the power converter and information relating to the presence or absence of a fault in the power converter.

5. the first module is a bypass module connected between an AC power source and the load; the second module is one of a plurality of power conversion modules connected in parallel between the AC power source and the load; The power conversion device according to claim 1 , wherein the first controller transmits data related to settings of the power conversion device and data related to control of the plurality of power conversion modules to the second controller.

6. the power conversion device is configured to be capable of selectively executing an inverter power supply mode in which AC power is supplied from the plurality of power conversion modules to the load, and a bypass power supply mode in which AC power is supplied from the AC power source to the load via the bypass module, The power converter of claim 5 , wherein the data regarding the settings of the power converter includes information regarding a mode of the power converter.

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