Semiconductor Device

Abstract

A semiconductor device capable of preventing a decrease in yield due to electrostatic breakdown. A scanning line driving circuit for supplying a signal for selecting a plurality of pixels to a scanning line is provided on the upper The shift register generates the signal, and the shift register includes a plurality of transistors. A conductive film that functions as a gate electrode of a transistor is divided into a plurality of parts, and the divided conductive films are The films are electrically connected to each other by a conductive film formed in a different layer from the divided conductive film. The plurality of transistors include a transistor on the output side of a shift register. This is to be included.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device using an insulated gate field effect transistor. [Background technology]

[0002] In recent years, the high mobility provided by polycrystalline silicon and microcrystalline silicon and the high mobility provided by amorphous silicon have been Oxide semiconductors are a new semiconductor material that combines uniform device characteristics with Metal oxides that exhibit semiconducting properties, known as semiconductors, are attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid crystal displays. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors using metal oxides that exhibit excellent semiconductor properties in the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0004] By the way, a semiconductor display including a transistor having amorphous silicon or an oxide semiconductor The equipment is capable of handling glass substrates of 5th generation or higher (1200mm wide x 1300mm long). Therefore, it has the advantage of high productivity and low cost. In the pixel section of a display device, wiring called a bus line connected to multiple pixels, e.g. The load on the scanning lines and signal lines increases. Therefore, the driving Since the circuit requires a large current supply capacity, the transistors that make up the driver circuit, especially The transistors located on the output side, depending on their electrical characteristics, are becoming smaller as the panels become larger. There is a tendency for noise to increase.

[0005] As the size of the transistor increases, the gate electrode of the transistor in the driving circuit The area of ​​the wiring that functions as a wiring is increased due to layout reasons. In manufacturing processes using plasma, such as ion implantation, electric charges accumulate on wiring, resulting in the so-called antenna effect. This phenomenon, called electrostatic discharge, is likely to occur, and the discharge of the charge accumulated in the wiring can cause electrostatic damage to the wiring. The probability of being infected increases.

[0006] In particular, a transistor having an amorphous silicon or oxide semiconductor is Amorphous silicon transistors tend to have smaller on-state current than silicon transistors. By using a transistor having a silicon or oxide semiconductor, it is possible to increase the size of the panel in terms of the process. However, in order to meet the current supply capacity of the driving circuit, a larger transistor must be designed. Therefore, the probability of electrostatic breakdown of the wiring increases due to the increase in the area of ​​the wiring. This tends to result in a decrease in yield.

[0007] In light of the above technical background, the present invention aims to prevent a decrease in yield due to electrostatic breakdown. It is an object of the present invention to provide a semiconductor device capable of achieving the above. [Means for solving the problem]

[0008] In one aspect of the present invention, in order to prevent accumulation of electric charges in a conductive film due to an antenna effect, a plurality of transistors are provided. A single conductive film that functions as a gate electrode of a transistor is divided into a plurality of parts. The divided conductive films are separated from each other by a different conductive film. The plurality of transistors are electrically connected to each other through a conductive film. This includes the output transistor.

[0009] Alternatively, in one aspect of the present invention, a scanning device that supplies signals for selecting a plurality of pixels to a scanning line is provided. The line driver circuit has a shift register for generating the signal, and the shift register In this method, one conductive film functioning as gate electrodes of a plurality of transistors is divided into a plurality of parts. The divided conductive films are separated from each other. The plurality of transistors are electrically connected to each other by a conductive film different from the conductive film formed on the transistor. The transistors in the shift register include those on the output side of the shift register.

[0010] The conductive film different from the divided conductive film is provided in a layer different from the divided conductive film. The conductive films formed in the different layers may be used as the sources of the plurality of transistors. The source electrode and the drain electrode may be formed in the same layer.

[0011] Note that in one embodiment of the present invention, the plurality of transistors are made of amorphous silicon or oxide semiconductor. The active layer may include a conductor.

[0012] In one embodiment of the present invention, a plurality of conductive films functioning as gate electrodes are formed in different layers. By electrically connecting the gate electrodes with the conductive film, one conductive film functions as a plurality of gate electrodes. In this case, the area of ​​each conductive film functioning as a gate electrode can be made smaller than that in the case where the conductive film is formed by a metal film. Therefore, as the panel size increases, the size of the transistor located on the output side of the driving circuit also increases. However, the area of ​​the conductive film functioning as the gate electrode of the transistor can be reduced. This allows processes using plasma, such as forming a gate electrode by etching, to be carried out. In the manufacturing process, the conductive film can be prevented from being damaged by electrostatic discharge due to the antenna effect. Cut.

[0013] Specifically, a semiconductor device according to one embodiment of the present invention includes a driver circuit for supplying signals to a plurality of pixels. The driving circuit has a plurality of transistors, and among the plurality of transistors, At least one transistor on the output side of the signal, and at least one transistor other than the output side The gate electrodes of the two transistors are electrically isolated by a conductive film different from that of the gate electrodes. are electrically connected. Effect of the Invention

[0014] In the semiconductor device according to one aspect of the present invention, the above-described structure reduces a decrease in yield due to electrostatic breakdown. This can be prevented. [Brief description of the drawings]

[0015] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device of the present invention; [Diagram 2] 1A and 1B are a top view and a cross-sectional view of a transistor. [Diagram 3] 1A and 1B are a top view and a cross-sectional view of a transistor. [Figure 4] FIG. 1 is a circuit diagram showing a configuration of a semiconductor device of the present invention. [Diagram 5]FIG. 2 is a diagram showing a configuration of a shift register. [Figure 6] 4 is a timing chart showing the operation of a pulse output circuit. [Figure 7] FIG. 2 is a schematic diagram showing a jth pulse generating circuit. [Figure 8] FIG. 2 is a diagram showing the configuration of a pulse generating circuit. [Figure 9] FIG. 2 is a diagram showing the configuration of a pulse generating circuit. [Figure 10] FIG. 2 is a diagram showing the configuration of a pulse generating circuit. [Figure 11] FIG. 2 is a cross-sectional view of a driver circuit and a pixel. [Figure 12] FIG. 2 is a diagram showing the configuration of a panel. [Figure 13] Electronic devices illustration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0017] The present invention can be applied to any device using transistors, such as integrated circuits, RF tags, and semiconductor display devices. The category includes all semiconductor devices. Control circuit, DSP (Digital Signal Processor), Microcomputer Large Scale Integrated Circuit (LSI), including the t), FPGA (Field Programmable Gate Array) and C Programmable logic circuits such as PLD (Complex PLD) The category includes semiconductor devices such as ammable logic devices. The display device uses light-emitting elements such as liquid crystal displays and organic light-emitting diodes (OLEDs) for each pixel. Equipped with light-emitting device, electronic paper, DMD (Digital Micromirror D device), PDP (Plasma Display Panel), FED (Fie Circuit elements using semiconductor films, such as LD Emission Displays, are used as driving circuits. The semiconductor display device having the above-mentioned features is included in the category.

[0018] In this specification, the term "semiconductor display device" refers to a display device in which display elements such as liquid crystal elements and light emitting elements are used for each screen. A panel formed as a base and a model in which ICs including a controller are mounted on the panel This category includes modules.

[0019] (Embodiment 1) FIG 1 illustrates an example of a circuit configuration of a semiconductor device according to one embodiment of the present invention. The device 100 includes a plurality of transistors including at least a transistor 101 and a transistor 102. It has a transistor.

[0020] The semiconductor device 100 is supplied with a high-level potential VH or In FIG. 1, the potential VH is applied via the wiring 105. A potential VL is applied to the semiconductor device 100 via the wiring 106. The semiconductor device 100 is connected to the input terminal 102 via a wiring 103. In the semiconductor device 100, a transistor 101 and a transistor A plurality of transistors including the transistor 102 perform switching in accordance with the potential Vin. Then, either the potential VH or the potential VL is selected by the above switching. The potential thus obtained is output as an output signal potential Vout from the semiconductor device 100 via the wiring 104. Be encouraged.

[0021] The transistor 102 has one of its source terminal and drain terminal connected to a wiring 104. That is, the transistor 102 is located on the output side of the semiconductor device 100 and is arranged The output of the potential Vout to the line 104 is controlled. The gate electrode of the transistor 101 (indicated by G) and the gate electrode of the transistor 102 (indicated by G) are electrically connected to the gate electrode by a wiring 107 different from the gate electrode. .

[0022] In this specification, unless otherwise specified, the term "connection" refers to both electrical connection and direct connection. It means both, and corresponds to a state in which a current, voltage or potential can be supplied or transmitted. Therefore, the state of being connected does not necessarily mean the state of being directly connected. , a wiring, a conductive film, a resistor, etc., so that a current, a voltage, or a potential can be supplied or transmitted. This also includes indirect connections through elements such as diodes and transistors. Included.

[0023] The source terminal of a transistor is a source region that is a part of the active layer, or a Similarly, the drain terminal of a transistor refers to the connected source electrode of the active layer. The term "drain electrode" refers to a drain region that is a part of the active layer, or a drain electrode that is connected to the active layer.

[0024] The source terminal and the drain terminal of the transistor are connected to the polarity of the transistor and the electrodes. The name is changed depending on the level of the potential that can be applied. In a transistor, the electrode to which a low potential is applied is called the source terminal, and the electrode to which a high potential is applied is called the The electrode is called the drain terminal. In a p-channel transistor, a low potential is applied to The electrode to which the high potential is applied is called the drain terminal, and the electrode to which the high potential is applied is called the source terminal. For convenience, in this specification, it is assumed that the source and drain terminals are fixed. Although the connection relationship of the transistors may be explained, in reality, the source and drain are connected according to the above potential relationship. The names of the source and drain terminals are interchangeable.

[0025] In addition, wiring with a large load called a bus line connected to multiple pixels, such as a scanning line When a potential Vout output from the semiconductor device 100 is supplied to a signal line or the like, The transistor 102 that controls the output of Vout is required to have a large current supply capability. Therefore, the channel width W of the transistor 102 is It is desirable to design it to a value larger than W.

[0026] FIG. 2A is a top view of the transistor 101 and the transistor 102 shown in FIG. In FIG. 2A, the transistors 101 and 102 are shown as an example. In order to clarify the layout, a top view is shown in which the gate insulating film 111 is omitted. 2(A) is a cross-sectional view of a transistor 102 taken along dashed line A1-A2 in FIG. Shown in Figure 2(B).

[0027] In FIG. 2A, a transistor 101 includes a conductive film 110 functioning as a gate electrode and a conductive A gate insulating film 111 is formed on the conductive film 110, and the conductive film 110 is overlapped on the gate insulating film 111. A semiconductor film 112 is provided at a position corresponding to the source electrode or the drain electrode. The pixel electrode includes a conductive film 113 and a conductive film 114 which function as drain electrodes.

[0028] In addition, in FIG. 2A and FIG. 2B, the transistor 102 functions as a gate electrode. A conductive film 115, a gate insulating film 111 on the conductive film 115, and a gate insulating film 111 on the gate insulating film 111. A semiconductor film 116 is provided in a position overlapping with the conductive film 115, and a The conductive film 117 and the conductive film 118 function as a source electrode and a drain electrode. do.

[0029] In one embodiment of the present invention, the transistor 102 located on the output side is a transistor. 2A. Therefore, in one embodiment of the present invention, Thus, the channel length L of the transistor 102 102 Channel width W 102 The ratio of Channel length L of transistor 101 101 Channel width W 101 Greater than the ratio of It is desirable to design it to a value of 0.1 mm. Specifically, the channel length L 102 Channel width W 10 2 The ratio of 101 Channel width W 101 More than twice the ratio of It is desirable that the size be at least three times as large.

[0030] In addition, the conductive film 110 and the conductive film 115 are spaced apart. means that they are physically separated. In FIG. 2(A) and FIG. 2(B), The conductive film 110 and the conductive film 115 are electrically connected to each other through the conductive film 119 functioning as a wiring. Specifically, the conductive film 110 and the conductive film 115 are formed on the gate insulating film 111. The conductive film 119 is connected to the conductive film 119 via the openings 120 and 121 formed therein.

[0031] The conductive film 110 and the conductive film 115 shown in FIG. 2A and FIG. 2B are formed on an insulating surface. The first conductive film is then processed into a desired shape by etching or the like. Then, the conductive films 113 and 114, the conductive films 117 and 118 are The conductive film 119 is formed on the gate insulating film 111 so as to cover the openings 120 and 121. The first conductive film formed on the first insulating film is processed into a desired shape by etching or the like. That is, the conductive film 119 can be formed in a different manner from the conductive film 110 and the conductive film 115. The layer is formed.

[0032] As shown in FIG. 2A and FIG. 2B, in one embodiment of the present invention, The conductive film 110 and the conductive film 115 are formed in a layer different from the conductive film 110 and the conductive film 115. The electrodes are electrically connected to each other via a conductive film 119 .

[0033] As a comparative example, FIG. 2C shows a transistor 101 and a transistor 102 shown in FIG. 2C is a top view of the transistor 101 and the transistor 102. In order to clarify the layout of the transistor 102, a top view is shown with the gate insulating film omitted. vinegar.

[0034] In FIG. 2C, the transistor 101 includes a conductive film 122 functioning as a gate electrode and a conductive A gate insulating film is provided on the conductive film 122, and a gate insulating film is provided at a position overlapping the conductive film 122 on the gate insulating film. A semiconductor film 123 is formed on the semiconductor film 123, and a source electrode or a drain electrode is formed on the semiconductor film 123. The conductive film 124 and the conductive film 125 function as the conductive film.

[0035] In addition, in FIG. 2C, the transistor 102 has a conductive film 122 functioning as a gate electrode. A gate insulating film on the conductive film 122 and a position on the gate insulating film that overlaps the conductive film 122 A semiconductor film 126 is provided in the position, and a source electrode or a drain electrode is provided on the semiconductor film 126. The semiconductor device includes a conductive film 127 and a conductive film 128 which function as electrodes.

[0036] That is, in FIG. 2C, the transistor 101 and the transistor 102 are formed by the conductive film 12. 2, and the conductive film 122 is the gate electrode of the transistor 101 and the transistor 1 Therefore, in the case of FIG. 2(C), The area of ​​the conductive film 122 that functions as a gate electrode in FIG. 2(A) and FIG. 2(B) is The area is larger than each of the conductive films 110 and 115 .

[0037] Therefore, in one embodiment of the present invention, the conductive film 110 and the conductive film 115 function as gate electrodes. Since the area of ​​each of the conductive films 121 and 122 can be reduced compared to the area of ​​the conductive film 122 of the comparative example, When the conductive film 110 and the conductive film 115 are formed by etching, To keep the amount of charge stored in each small, i.e. to reduce the antenna effect Therefore, in one embodiment of the present invention, the conductive film 110 and the conductive film 115 are etched. When the conductive film 110 and the conductive film 11 are fabricated by the same method, the discharge of the electric charge is smaller than that in the comparative example. 5. Electrostatic destruction can be made less likely to occur.

[0038] In one embodiment of the present invention, the semiconductor film 112 and the semiconductor film 113 over the conductive film 110 and the conductive film 115 are When the conductive film 116 is formed by etching, the conductive film 110 and the conductive film This makes it possible to make electrostatic damage in the form of 115 less likely to occur.

[0039] Next, FIG. 3A shows a top view of the transistor 101 and the transistor 102 shown in FIG. 3A shows an example different from that shown in FIG. 2A. However, in FIG. 3A, the transistor 101 and In order to clarify the layout of the transistor 102, the gate insulating film 211 is omitted. 3A. Also, the transistor 102 shown in FIG. An example of a cross-sectional view of the above is shown in FIG.

[0040] In FIG. 3A, the transistor 101 functions as a source electrode or a drain electrode. A conductive film 213 and a conductive film 214, and a semiconductor film 212 on the conductive film 213 and the conductive film 214. 2, a gate insulating film 211 on the semiconductor film 212, and a semiconductor film 2 12 and a conductive film 210 that functions as a gate electrode.

[0041] In addition, in FIG. 3A and FIG. 3B, the transistor 102 has a source electrode or a drain electrode. The conductive film 217 and the conductive film 218 function as a conductive electrode. a semiconductor film 216 on the gate insulating film 211; A conductive film that functions as a gate electrode and is provided on the semiconductor film 216 at a position overlapping the semiconductor film 216. 215.

[0042] In one embodiment of the present invention, the transistor 102 located on the output side is a transistor. 3A, the current supply capability is higher than that of the capacitor 101. Thus, the channel length L of the transistor 102 102 Channel width W 102 The ratio of Channel length L of transistor 101 101 Channel width W 101 Greater than the ratio of It is desirable to design it to a value of 0.1 mm. Specifically, the channel length L 102 Channel width W 10 2 The ratio of 101 Channel width W 101 More than twice the ratio of It is desirable that the size be at least three times as large.

[0043] The conductive film 210 and the conductive film 215 are spaced apart from each other. In B), the conductive film 210 and the conductive film 215 are connected via the conductive film 219 that functions as wiring. Specifically, the conductive film 210 and the conductive film 215 are a gate insulating film. The conductive film 219 is connected to the conductive film 211 through the openings 220 and 221 formed in the conductive film 211. There are.

[0044] The conductive film 210 and the conductive film 215 shown in FIG. 3(A) and FIG. 3(B) are formed in an opening 220. A conductive film formed on the gate insulating film 211 so as to cover the opening 221 is etched. The conductive film 21 can be formed by processing the conductive film 21 into a desired shape by etching or the like. 3 and the conductive film 214, the conductive film 217, the conductive film 218, and the conductive film 219 are insulating surfaces. The first conductive film formed on the first insulating film is processed into a desired shape by etching or the like. That is, the conductive film 219 can be formed in a different manner from the conductive film 210 and the conductive film 215. The layer is formed.

[0045] As shown in FIG. 3A and FIG. 3B, in one embodiment of the present invention, The conductive film 210 and the conductive film 215 are formed in a layer different from the conductive film 210 and the conductive film 215. The electrodes are electrically connected to each other via a conductive film 219 .

[0046] As a comparative example, FIG. 3C shows a transistor 101 and a transistor 102 shown in FIG. 3C is a top view of the transistor 101 and the transistor 102. In order to clarify the layout of the transistor 102, a top view is shown with the gate insulating film omitted. vinegar.

[0047] In FIG. 3C, the transistor 101 functions as a source electrode or a drain electrode. The conductive film 224 and the conductive film 225, and the semiconductor film 223 on the conductive film 224 and the conductive film 225 , a gate insulating film on the semiconductor film 223, and a semiconductor film 223 overlapping the gate insulating film and a conductive film 222 that functions as a gate electrode.

[0048] In FIG. 3C, the transistor 102 functions as a source electrode or a drain electrode. The conductive film 227 and the conductive film 228 function as a semiconductor film 2 on the conductive film 227 and the conductive film 228. 26, a gate insulating film on the semiconductor film 226, and a semiconductor film 226 on the gate insulating film. A conductive film 222 which functions as a gate electrode is provided in an overlapping position.

[0049] That is, in FIG. 3C, the transistor 101 and the transistor 102 are formed by the conductive film 22 2, and the conductive film 222 is the gate electrode of the transistor 101 and the transistor 1 Therefore, in the case of FIG. 3(C), The area of ​​the conductive film 222 that functions as a gate electrode in FIG. 3(A) and FIG. 3(B) is The area is larger than each of the conductive films 210 and 215 .

[0050] Therefore, in one embodiment of the present invention, the conductive film 210 and the conductive film 215 function as gate electrodes. Since the area of ​​each of the conductive films 221 and 222 can be reduced compared to the area of ​​the conductive film 222 of the comparative example, When the conductive film 210 and the conductive film 215 are formed by etching, To keep the amount of charge stored in each small, i.e. to reduce the antenna effect Therefore, in one embodiment of the present invention, the conductive film 210 and the conductive film 215 are etched. When the conductive film 210 and the conductive film 211 are fabricated by the same method, the conductive film 210 and the conductive film 212 are formed by discharging the electric charge. 5. Electrostatic destruction can be made less likely to occur.

[0051] In one embodiment of the present invention, various conductive films on the conductive film 210 and the conductive film 215 are etched. When the conductive film 210 and the conductive film 215 are processed into a desired shape by the antenna effect, This can make electrical breakdown less likely to occur.

[0052] Next, a configuration of a pulse generating circuit, which is one of the semiconductor devices according to one embodiment of the present invention, will be described. FIG. 4 illustrates an example of a pulse generating circuit included in a semiconductor device according to one embodiment of the present invention. show.

[0053] The pulse generating circuit 300 shown in FIG. The transistor 302 has a capacitance element 316. The transistor 309, the transistor 312, or the transistor 315 corresponds to The pulse generating circuit 300 corresponds to the transistor 102 shown in FIG. Various potentials are applied from the wirings 327 to 329. It has a configuration.

[0054] A shift register can be configured by connecting the above pulse generating circuit 300 in multiple stages. can.

[0055] Specifically, when the transistors 301 to 315 are n-channel transistors, A high-level potential VDD is applied to the wiring 317, and a low-level potential VSS is applied to the wiring 318. A low-level potential VEE is applied to the wiring 326. It is desirable that the potential of the wiring 319 is equal to or higher than VSS. A potential LIN is applied to the wiring 320, a potential INRES is applied to the wiring 321, A potential CLK2 is applied, a potential RIN is applied to the wiring 322, and a potential C LK1 is applied, a potential PWC2 is applied to the wiring 324, and a potential PWC 1 is given.

[0056] The potential GOUT1 output from the pulse generating circuit 300 is applied to the wiring 327. The potential GOUT2 output from the pulse generating circuit 300 is applied to a wiring 328. The potential SROUT output from the pulse generating circuit 300 is applied to a wiring 329.

[0057] The potentials LIN, RIN, CLK2, and INRES are the semiconductor These correspond to the potential Vin in the device 100. SROUT corresponds to the potential Vout in the semiconductor device 100 shown in FIG. S, the potential VEE, the potential PWC1, the potential PWC2, and the potential CLK1 are the semiconductor This corresponds to the potential VH or potential VL in the device 100.

[0058] Specifically, the gate electrode of the transistor 301 is connected to the wiring 319. One of the source terminal and the drain terminal of the transistor 301 is connected to the wiring 317, and the other are connected to one of the source terminal and the drain terminal of the transistor 302, respectively. The transistor 302 has its gate electrode connected to the gate electrode of the transistor 315. The other of the source terminal and the drain terminal of the transistor 302 is connected to a wiring. The transistor 303 has its gate electrode connected to the wiring 320. In addition, one of the source terminal and the drain terminal of the transistor 303 is connected to a wiring. The other end is connected to the gate electrode of the transistor 302. The gate electrode of the transistor 304 is connected to the wiring 321. 04, one of the source terminal and the drain terminal is connected to the wiring 317, and the other is connected to the transistor 3 02. The gate electrodes of the transistors 305 and 306 are connected to the gate electrodes of the transistors 302 and 306. is connected to the wiring 322. The transistor 305 has a source terminal and a drain terminal. One of the input terminals is connected to a wiring 317, and the other is connected to a gate electrode of a transistor 302. The transistor 306 has a gate electrode connected to a wiring 319. In addition, one of the source terminal and drain terminal of the transistor 306 is connected to the transistor 3 The other end is connected to the gate electrode of transistor 30. The gate electrode of the transistor 307 is connected to the wiring 317. One of the source terminal and drain terminal of the transistor 301 is The other terminal is connected to the gate electrode of the transistor 308. The transistor 308 has one of its source terminal and drain terminal connected to the wiring 323 and the other connected to the wiring The gate electrode of the transistor 309 is connected to the transistor 329. The source terminal of the transistor 309 is connected to the gate electrode of the transistor 302. One of the drain terminal and the drain terminal is connected to the wiring 329, and the other is connected to the wiring 318. The gate electrode of the transistor 310 is connected to the wiring 317. Transistor 310 has one of its source and drain terminals connected to the source of transistor 301. the other of the source and drain terminals is connected to the gate electrode of the transistor 311, The transistor 311 has one of its source terminal and drain terminal connected to a wiring. The other end is connected to a wiring 324 and the other end is connected to a wiring 328. The gate electrode of the transistor 302 is connected to the gate electrode of the transistor 303. 12, one of its source terminal and drain terminal is connected to the wiring 328, and the other is connected to the wiring 318. The transistor 313 has its gate electrode connected to the wiring 317. In addition, the transistor 313 has one of its source terminal and drain terminal connected to a transistor. The other of the source terminal and drain terminal of the transistor 301 is connected to the gate of the transistor 314. The transistor 314 has its source terminal and drain terminal connected to One of the IN terminals is connected to a wiring 325, and the other is connected to a wiring 327. The transistor 315 has one of its source and drain terminals connected to the wiring 327 and the other connected to the wiring 327. 26. The capacitor 316 has one electrode connected to the transistor 302. The gate electrode of the first transistor is connected to the first gate electrode, and the other electrode is connected to a wiring 318.

[0059] In FIG. 4, the other of the source terminal and the drain terminal of the output transistor 315 is arranged The output transistor is connected to the line 326, but the present invention is not limited to this configuration. The other of the source terminal and the drain terminal of 315 may be connected to a wiring 318. However, since the size of the output transistor 315 is large, the transistor 315 is normal. In the case of an on-state transistor, the drain current is larger than that of other transistors. When transistor 315 is normally on, the source and drain terminals of transistor 315 When the other end of the drain electrode is connected to the wiring 318, the potential of the wiring 318 is increased by the drain current. This easily causes a phenomenon in which the amplitude of the potential GOUT1, which is the output potential, becomes smaller. However, as shown in FIG. 4, the source and drain terminals of the transistor 315 on the output side If the other terminal of the transistor 315 is connected to the wiring 326 instead of the wiring 318, the transistor 315 will If the potential of the wiring 326 rises, the transistor The potential of the wiring 318 for supplying a potential to the gate electrode of the transistor is higher than the potential of the wiring 326. Therefore, the drain current of the transistor 315 causes the potential of the wiring 326 to rise. As the potential rises, the gate voltage of transistor 315 approaches the threshold voltage, which has a negative value. Therefore, even if transistor 315 is normally on, it can be turned off.

[0060] In one embodiment of the present invention, a transistor 309 corresponding to an output side transistor, At least one of the transistors 312 and 315 and the transistor 302 are mutually The gate electrode is electrically connected to the gate electrode via a conductive film different from that of the gate electrode. With the above configuration, the transistor 309, the transistor 312, the transistor 315, and the transistor Compared with the case where all the gate electrodes of the transistor 302 are made of a single conductive film, Therefore, the area of ​​each conductive film functioning as a gate electrode can be reduced. The conductive film functions as an antenna, so that electrostatic damage caused by the antenna effect can be prevented. .

[0061] In one embodiment of the present invention, the two conductive films functioning as gate electrodes are The present invention is not limited to a configuration in which the film is electrically connected to the other film via a conductive film different from the other film. For example, Two conductive films functioning as gate electrodes are formed through multiple conductive films different from the above two conductive films. In this case, at least one of the plurality of conductive films may be It is assumed that the gate electrodes are formed in a layer different from the two conductive films that function as the gate electrodes.

[0062] In one embodiment of the present invention, a plurality of conductive films functioning as gate electrodes and the plurality of conductive films The present invention is not limited to a configuration in which an insulating film is provided between a conductive film for electrically connecting the film and the insulating film. In one embodiment of the present invention, a plurality of conductive films functioning as gate electrodes and the plurality of conductive films It is only necessary that the conductive film for electrically connecting the first and second electrodes and the second electrode are formed in different manufacturing steps. Therefore, the plurality of conductive films functioning as gate electrodes and the plurality of conductive films are electrically connected to each other. For this purpose, an insulating film does not necessarily have to be formed between the conductive film and the insulating film.

[0063] (Embodiment 2) In this embodiment, the pulse generating circuit 300 shown in FIG. 4 is connected in multiple stages. The shift register used in this embodiment will now be described.

[0064] The shift register shown in FIG. 5 includes pulse generating circuits 300_1 to 300_y. (y is a natural number) and a dummy pulse generating circuit 300_d. 0_1 to 300_y are the same as the pulse generating circuit 300 shown in FIG. The pulse generating circuit 300_d has the same configuration as that of the wiring 300_d to which the potential RIN is applied. 4 in that it is not connected to 322 and does not have transistor 305. The configuration is different from that of the pulse generating circuit 300 shown in FIG.

[0065] In the shift register shown in FIG. 5, a pulse generating circuit 300_j (j is y or less) The positions of the wiring 319 to the wiring 325 and the wiring 327 to the wiring 329 connected to the 5 and 7, the wiring of the pulse generating circuit 300_j is A potential SR output from a wiring 329 of the preceding stage pulse generating circuit 300_j-1 is input to a terminal 319. OUTj-1 is given as a potential LIN. However, the first-stage pulse generating circuit 300 The wiring 319 of _1 is configured to receive the potential of a start pulse signal GSP.

[0066] In addition, the wiring 322 connected to the pulse generating circuit 300_j is connected to the pulse generating circuit 300_j. The potential SROUTj+1 output from the wiring 329 of the circuit 300_j+1 is set as the potential RIN. However, the wiring 322 of the y-th stage pulse generating circuit 300_y is provided with a pulse generating The SROUTd output from the wiring 329 of the output circuit 300_d is applied as a potential RIN. The configuration will be as follows.

[0067] The wiring 321 and the wiring 323 are connected to the clock signals GCK1 to GCK4. Specifically, the potentials of the two clock signals are given to the pulse generating circuit. In the circuit 300_4m+1, the potential of the clock signal GCK1 is supplied to the wiring 32 as the potential CLK1. 3, and the potential of the clock signal GCK2 is applied to the wiring 321 as the potential CLK2. In the pulse generating circuit 300_4m+2, the potential of the clock signal GCK2 is set to the potential CL K1 is applied to the wiring 323, and the potential of the clock signal GCK3 is applied to the wiring 323 as the potential CLK2. The clock signal GCK3 is applied to the wiring 321. The potential of the clock signal GCK4 is supplied to the wiring 323 as the potential CLK1. The potential CLK2 is applied to the wiring 321. The potential of the clock signal GCK4 is applied to the wiring 323 as the potential CLK1, and the clock signal The potential of GCK1 is applied to the wiring 321 as the potential CLK2. In _d, the potential of the clock signal GCK1 is applied to the wiring 323 as the potential CLK1. The potential of the clock signal GCK2 is applied to the wiring 321 as the potential CLK2. m is an arbitrary integer that satisfies the total number of pulse generating circuits 300 is y.

[0068] The wiring 324 and the wiring 325 are connected to a pulse width control signal PWCA and a pulse width control signal PWCD and any one of the pulse width control signal PWCa to the pulse width control signal PWCd. The potentials of the two pulse width control signals are respectively given. In the case of 0_4m+1, the potential of the pulse width control signal PWCa is set to the potential PWC1 on the wiring 325. , and the potential of the pulse width control signal PWCA is applied to the wiring 324 as a potential PWC2. In the pulse generating circuit 300_4m+2, the potential of the pulse width control signal PWCb is The potential of the pulse width control signal PWCB is applied to the wiring 325 as a potential PWC1. C2 is applied to the wiring 324. In the pulse generating circuit 300_4m+3, a pulse width control The potential of the control signal PWCc is applied to the wiring 325 as the potential PWC1, and the pulse width control signal The potential of PWCC is applied to the wiring 324 as the potential PWC2. In the case of _4m+4, the potential of the pulse width control signal PWCd is applied to the wiring 325 as the potential PWC1. The potential of the pulse width control signal PWCD is applied to the wiring 324 as a potential PWC2. In the pulse generating circuit 300_d, the potential of the pulse width control signal PWCa is set to the potential PWC 1 is applied to the wiring 325, and the potential of the pulse width control signal PWCA is set to a potential PWC2. and provided to wiring 324.

[0069] The potential GOUT1 of the wiring 327 connected to the pulse generating circuit 300_j is is given to.

[0070] The potential SROUT_j of the wiring 329 connected to the pulse generating circuit 300_j is The polarity of the signal is inverted by the signal 351_j and is applied to the scanning line GLbj. The clock signal GCK2 is input to the converter 351_4m+1, and the clock signal GC When the potential of K2 is at a low level, the polarity of the potential SROUT_4m+1 is inverted, and the scan line The inverter 351_4m+2 receives the clock signal GCK3. When the potential of the clock signal GCK3 is at low level, the potential SROUT_4m+ The polarity of 2 is inverted and applied to the scanning line GLb4m+2. The clock signal GCK4 is input, and the potential of the clock signal GCK4 is at a low level. At this time, the polarity of the potential SROUT_4m+3 is inverted and applied to the scanning line GLb4m+3. The inverter 351_4m+4 receives the clock signal GCK1. When the potential of GCK1 is at low level, the polarity of the potential SROUT_4m+4 is inverted to The inverter 351_d receives the clock signal GCK2. When the potential of the clock signal GCK2 is at a low level, the polarity of the potential SROUT_d is is inverted and applied to the scan line GLbd.

[0071] The potential GOUT2 of the wiring 328 connected to the pulse generating circuit 300_j is an inverter. The polarity of the signal is inverted by the input 350_j and applied to the scanning line GLcj. The inverter 350_4m+1 receives the clock signal GCK2. When the potential of CK2 is at low level, the polarity of the potential GOUT2 is inverted, and the scanning line GLc4 The inverter 350_4m+2 receives the clock signal GCK3. When the potential of the clock signal GCK3 is at a low level, the polarity of the potential GOUT2 is inverted. The inverter 350_4m+3 outputs the clock signal GC When K4 is input and the potential of the clock signal GCK4 is at a low level, the potential GOUT The polarity of 2 is inverted and applied to the scanning line GLc4m+3. The inverter 350_4m+4 The clock signal GCK1 is input, and the potential of the clock signal GCK1 is at a low level. At this time, the polarity of the potential GOUT2 is inverted and applied to the scanning line GLc4m+4. 350_d receives the clock signal GCK2, and the potential of the clock signal GCK2 is When at a low level, the polarity of the potential GOUT2 is inverted and applied to the scanning line GLcd.

[0072] Next, the operation of the pulse generating circuit 300 shown in FIG. 4 will be described with reference to the timing chart shown in FIG. The following explanation will be given using the chart. Note that the potential INRES is at a low level throughout the entire period. This shall be the case.

[0073] As shown in FIG. 6, in a period t1, the potential CLK1 applied to the wiring 323 is low. The potential CLK2 applied to the wiring 321 is at a low level, and the pulse The potential of the width control signal PWC1 is at a low level, and the pulse width control signal PW The potential of C2 is low level, the potential LIN applied to the wiring 319 is high level, and the potential of the wiring 322 is low level. The potential RIN applied to the input terminal becomes low level.

[0074] Therefore, in the period t1, the pulse generating circuit 300 applies a pulse The potential (low level) of the width control signal PWC1 is applied to the wiring 327 as the potential GOUT1. In addition, the potential (low level) of the pulse width control signal PWC2 applied to the wiring 324 is , is applied to the wiring 328 as a potential GOUT2. Also, a potential C LK1 (low level) is applied to the wiring 329 as the potential SROUT.

[0075] Next, in a period t2 as shown in FIG. 6, the potential CLK1 applied to the wiring 323 is The potential CLK2 applied to the wiring 321 is at a high level, and the potential CLK3 applied to the wiring 325 is at a low level. The potential of the pulse width control signal PWC1 changes from low level to high level, and the potential of the wiring 324 The potential of the pulse width control signal PWC2 is low, and the potential of the wiring 319 is LIN is at high level, and the potential RIN applied to the wiring 322 is at low level.

[0076] Therefore, in the period t2, the pulse generating circuit 300 applies a pulse to the wiring 325. The potential of the width control signal PWC1 (which changes from low level to high level) is equal to the potential GOUT1. The pulse width control signal PWC2 is applied to the wiring 324. The potential (low level) of the line 328 is applied as the potential GOUT2 to the line 328. The potential CLK1 (high level) applied to the line 23 is applied to the line 329 as the potential SROUT. can be obtained.

[0077] Next, in a period t3 as shown in FIG. 6, the potential CLK1 applied to the wiring 323 is The potential CLK2 applied to the wiring 321 is at a high level, and the potential CLK3 applied to the wiring 325 is at a low level. The potential of the pulse width control signal PWC1 is at a high level, and the potential of the pulse width control signal PWC2 is at a high level. The potential of the signal PWC2 is at a high level, and the potential LIN applied to the wiring 319 is changed from a high level to The potential RIN applied to the wiring 322 becomes low.

[0078] Therefore, in the period t3, the pulse generating circuit 300 applies a pulse to the wiring 325. The potential (high level) of the width control signal PWC1 is applied to the wiring 327 as the potential GOUT1. In addition, the potential (high level) of the pulse width control signal PWC2 applied to the wiring 324 is , is applied to the wiring 328 as a potential GOUT2. Also, a potential C LK1 (high level) is applied to the wiring 329 as the potential SROUT.

[0079] Next, in a period t4 as shown in FIG. 6, the potential CLK1 applied to the wiring 323 is The potential CLK2 applied to the wiring 321 is at a high level, and the potential CLK3 applied to the wiring 325 is at a low level. The potential of the pulse width control signal PWC1 changes from high level to low level, and the potential of the wiring 324 The potential of the pulse width control signal PWC2 is high, and the potential of the wiring 319 is LIN is at low level, and the potential RIN applied to the wiring 322 is at low level.

[0080] Therefore, in the period t4, the pulse generating circuit 300 applies a pulse to the wiring 325. The potential of the width control signal PWC1 (which changes from high level to low level) is equal to the potential GOUT1. The pulse width control signal PWC2 is applied to the wiring 324. The potential (high level) of the line 328 is applied as the potential GOUT2 to the line 328. The potential CLK1 (high level) applied to the line 23 is applied to the line 329 as the potential SROUT. can be obtained.

[0081] Next, in a period t5 as shown in FIG. 6, the potential CLK1 applied to the wiring 323 is The potential CLK2 applied to the wiring 321 is at a low level, and the potential CLK3 applied to the wiring 325 is at a high level. The potential of the pulse width control signal PWC1 applied to the wiring 324 is at a low level. The potential of the signal PWC2 is at a low level, the potential LIN applied to the wiring 319 is at a low level, The potential RIN applied to the line 322 becomes high level.

[0082] Therefore, in the period t5, in the pulse generating circuit 300, the potential V EE (low level) is applied to the wiring 327 as the potential GOUT1. The potential VSS (low level) applied to the terminal 8 is applied to the wiring 328 as the potential GOUT2. In addition, the potential VSS (low level) applied to the wiring 318 is set as the potential SROUT. and provided to wiring 329.

[0083] In one aspect of the present invention, as described in the first embodiment, At least one of a transistor 309, a transistor 312, and a transistor 315 The gate electrodes of the transistors 301 and 302 are connected to each other through a conductive film different from the gate electrode of the transistor 302. With the above configuration, the transistor 309 and the transistor 3 12, the gate electrodes of the transistor 315 and the transistor 302 are all made of a single conductive film. The area of ​​each conductive film functioning as a gate electrode is reduced compared to when the gate electrode is formed. Therefore, the electrostatic breakdown due to the antenna effect of the conductive film functioning as the gate electrode can be prevented. Therefore, the present invention using the above shift register makes it possible to prevent breakdown. In the semiconductor device according to the embodiment, a decrease in yield due to electrostatic breakdown is unlikely to occur.

[0084] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0085] (Embodiment 3) A configuration example of a pulse generating circuit included in a semiconductor device according to one embodiment of the present invention will be described.

[0086] The pulse generating circuit 400 shown in FIG. 8A includes transistors 402 to 404. and transistors 415 to 420. By connecting multiple stages, a shift register can be formed.

[0087] The gate electrode of the transistor 402 is connected to the gate electrodes of the transistors 403 and 404. The gate electrode is connected to the source terminal and the drain terminal, one of which is connected to the wiring 406 and the other is connected to the The gate electrode of transistor 420 is connected to the source of transistor 403. One of the terminal and the drain terminal is connected to the wiring 406, and the other is connected to the wiring 414. One of the source terminal and the drain terminal of the transistor 404 is connected to the wiring 407. and the other end is connected to a wiring 413.

[0088] The gate electrode of the transistor 415 is connected to the wiring 408, and the source terminal One of the drain terminals is connected to the gate electrode of the transistor 420, and the other is connected to the wiring 40 5. The transistor 416 has its gate electrode connected to the wiring 409. The source terminal and the drain terminal of each of the transistors 402, 403, and The other end is connected to the gate electrode of the transistor 404, and the other end is connected to the wiring 405. The transistor 417 has a gate electrode connected to the wiring 410 and a source terminal and a drain terminal. One of the in terminals of the transistors 402, 403, and 404 The other end is connected to a gate electrode 405. The gate electrode of the transistor is connected to the wiring 408, and one of the source terminal and the drain terminal of the transistor is connected to the wiring 408. 06, and the other is connected to transistor 402, transistor 403, and transistor 404. Transistor 419 is connected to the gate electrode of transistor 414. The gate electrode of the transistor 420 is connected to the source terminal and the drain terminal of the transistor 420. 4 and the other end is connected to the wiring 411. The transistor 420 has a source One of the terminal and the drain terminal is connected to a wiring 413, and the other is connected to a wiring 412. do.

[0089] Transistors 402 to 404 and transistors 415 to 4 Specifically, when the wiring 20 is an n-channel type, a potential VDD is applied to the wiring 405, and A potential VSS is applied to the line 406, and a potential VEE is applied to the wiring 407. The potentials of various signals such as clock signals are applied to the lines 408 to 412. Thus, a potential GOUT is output from the wiring 413 and a potential SROUT is output from the wiring 414 .

[0090] In one embodiment of the present invention, a transistor 403 corresponding to an output transistor and a transistor At least one of the transistors 404 and the transistor 402 has a gate electrode that is The gate electrode is electrically connected to the conductive film provided in a layer different from that of the gate electrode. As a result, all of the gates of the transistors 403, 404, and 402 are turned on. Compared with the case where the gate electrode is composed of a single conductive film, each conductive film that functions as a gate electrode Therefore, the area of ​​the conductive film that functions as the gate electrode can be reduced. Therefore, the above-mentioned pulse generation can reduce the occurrence of electrostatic breakdown due to the antenna effect. The semiconductor device according to one embodiment of the present invention uses the read circuit 400 as a shift register or the like. This can make it difficult for a decrease in yield due to destruction to occur.

[0091] Alternatively, in one embodiment of the present invention, a transistor 420 corresponding to an output transistor and The transistor 419 has a gate electrode formed in a layer different from that of the above gate electrode. The pulse generating circuit may be electrically connected to the first and second electrodes via a conductive film. 400 is used for a shift register or the like, the semiconductor device according to one embodiment of the present invention is This can make it possible to prevent a decrease in yield due to the above-mentioned problem.

[0092] In FIG. 8A, one of the source terminal and the drain terminal of the output transistor 404 The output side of the transformer is connected to the wiring 407, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 404 may be connected to the wiring 406. However, as shown in FIG. 8A, the source terminal and the drain terminal of the transistor 404 on the output side If one of the drain terminals is connected to the wire 407 instead of the wire 406, the transistor 4 Even if transistor 404 is normally on, it is necessary to turn off transistor 404 when it should be turned off. can be done.

[0093] The pulse generating circuit 430 shown in FIG. 8B includes transistors 432 to 434. and transistors 446 to 452. By connecting multiple stages, a shift register can be formed.

[0094] The gate electrode of the transistor 432 is connected to the gate electrodes of the transistors 433 and 434. The gate electrode is connected to the gate electrode, and one of the source terminal and drain terminal is connected to the wiring 436. The other terminal is connected to the gate electrodes of the transistor 451 and the transistor 452. The transistor 433 has one of its source terminal and drain terminal connected to a wiring 436. The other terminal is connected to a wiring 445. The transistor 434 has a source terminal and a drain terminal. One of the pin terminals is connected to a wiring 437 and the other is connected to a wiring 444 .

[0095] The gate electrode of the transistor 446 is connected to the wiring 438, and the source terminal and one of the drain terminals is connected to the gate electrodes of the transistors 451 and 452. The other end is connected to the wiring 435. The transistor 447 has a gate electrode A wiring 439 is connected to the transistor 432, and one of the source terminal and the drain terminal of the transistor 432 is connected to the wiring 439. The other terminal is connected to the gate electrodes of the transistors 433 and 434. 5. The transistor 448 has its gate electrode connected to the wiring 440. The source terminal and the drain terminal of each of the transistors 432, 433, and The other end is connected to the gate electrode of the transistor 434, and the other end is connected to the wiring 435. The transistor 449 has a gate electrode connected to the wiring 438 and a source terminal and a drain terminal. One of the in terminals is connected to the wiring 436, and the other is connected to the transistor 432 and the transistor 43 3, and the gate electrode of transistor 434. Transistor 450 is The gate electrode of the transistor is connected to the wiring 441, and one of the source terminal and the drain terminal of the transistor is connected to the transistor. The gate electrodes of the transistors 432, 433, and 434 are connected to the The other terminal is connected to the wiring 435. The transistor 451 has a source terminal and a drain terminal. One of the terminals is connected to the wiring 445, and the other is connected to the wiring 442. The capacitor 452 has one of its source terminal and drain terminal connected to the wiring 444 and the other connected to the wiring 444. It is connected to line 443.

[0096] Transistors 432 to 434 and transistors 446 to 448 In the case where the wiring 52 is an n-channel type, specifically, a potential VDD is applied to the wiring 435, and A potential VSS is applied to the line 436, and a potential VEE is applied to the wiring 437. The potentials of various signals such as a clock signal are applied to the lines 438 to 443. Thus, a potential GOUT is output from the wiring 444, and a potential SROUT is output from the wiring 445.

[0097] In one embodiment of the present invention, a transistor 433 corresponding to an output transistor and a transistor At least one of the transistors 434 and the transistor 432 has a gate electrode that is The gate electrode is electrically connected to the conductive film provided in a layer different from that of the gate electrode. As a result, all of the gates of the transistors 433, 434, and 432 are turned on. Compared with the case where the gate electrode is composed of a single conductive film, each conductive film that functions as a gate electrode Therefore, the area of ​​the conductive film that functions as the gate electrode can be reduced. Therefore, the above-mentioned pulse generation can reduce the occurrence of electrostatic breakdown due to the antenna effect. The electrostatic discharge circuit 430 is used as a shift register or the like in a semiconductor device according to one embodiment of the present invention. This can make it difficult for a decrease in yield due to destruction to occur.

[0098] Alternatively, in one embodiment of the present invention, a transistor 452 corresponding to an output transistor and The transistor 451 has a gate electrode formed in a layer different from that of the transistor 451. The pulse generating circuit may be electrically connected to the first and second electrodes via a conductive film. 430 is used in a shift register or the like, the semiconductor device according to one embodiment of the present invention is This can make it possible to prevent a decrease in yield due to the above-mentioned problem.

[0099] In FIG. 8B, one of the source terminal and the drain terminal of the output transistor 434 The output side of the transformer is connected to the wiring 437, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 434 may be connected to a wiring 436. However, as shown in FIG. 8B, the source terminal and the drain terminal of the transistor 434 on the output side If one of the drain terminals is connected to wire 437 instead of wire 436, transistor 4 Even if transistor 34 is normally on, transistor 434 can be turned off when it should be turned off. can be done.

[0100] The pulse generating circuit 460 shown in FIG. 9A includes transistors 462 to 464. and transistors 476 to 482. A shift register can be formed by connecting multiple stages.

[0101] The gate electrode of the transistor 462 is connected to the gate electrodes of the transistors 463 and 464. The gate electrode is connected to the gate electrode, and one of the source terminal and drain terminal is connected to the wiring 466. The other terminal is connected to one of the source terminal and the drain terminal of the transistor 477. The transistor 463 has one of its source terminal and drain terminal connected to a wiring 466. The other terminal is connected to a wiring 475. The transistor 464 has a source terminal and a drain terminal. One of the pin terminals is connected to a wiring 467 and the other is connected to a wiring 474 .

[0102] The gate electrode of the transistor 476 is connected to the wiring 468, and the source terminal and one of the drain terminals is connected to one of the source terminal and drain terminal of a transistor 477. The other end is connected to a wiring 465. The transistor 477 has a gate electrode The other of the source terminal and the drain terminal is connected to the wiring 465. and the gate electrode of transistor 482. Transistor 478 has its gate The source electrode is connected to the wiring 469, and one of the source terminal and the drain terminal is a transistor. 462, a transistor 463, and a transistor 464 are connected to the gate electrodes thereof. The transistor 479 has a gate electrode connected to the wiring 468. One of the source terminal and the drain terminal is connected to the wiring 466, and the other is connected to the transistor. The gate electrodes of the transistors 462, 463, and 464 are connected to the The transistor 480 has a gate electrode connected to the wiring 470 and a source terminal and one of the drain terminals of the transistor 462, the transistor 463, and the transistor The other end is connected to the gate electrode of the transistor 464 and the other end is connected to the wiring 465. One of the source terminal and the drain terminal of the transistor 1 is connected to the wiring 475, and the other is connected to the wiring 47 1. Transistor 482 has one of its source and drain terminals connected One end is connected to wiring 474 and the other end is connected to wiring 472.

[0103] Transistors 462 to 464 and transistors 476 to 4 In the case where the wiring 82 is an n-channel type, specifically, a potential VDD is applied to the wiring 465, and A potential VSS is applied to the line 466, and a potential VEE is applied to the wiring 467. The potentials of various signals such as clock signals are applied to the lines 468 to 472. Thus, a potential GOUT is output from the wiring 474, and a potential SROUT is output from the wiring 475.

[0104] In one embodiment of the present invention, a transistor 463 corresponding to an output transistor and a transistor At least one of the transistors 464 and the transistor 462 has a gate electrode that is The gate electrode is electrically connected to the conductive film provided in a layer different from that of the gate electrode. As a result, all of the gates of the transistors 463, 464, and 462 are turned on. Compared with the case where the gate electrode is composed of a single conductive film, each conductive film that functions as a gate electrode Therefore, the area of ​​the conductive film that functions as the gate electrode can be reduced. Therefore, the above-mentioned pulse generation can reduce the occurrence of electrostatic breakdown due to the antenna effect. The electrostatic discharge circuit 460 is used as a shift register or the like in the semiconductor device according to one embodiment of the present invention. This can make it difficult for a decrease in yield due to destruction to occur.

[0105] Alternatively, in one embodiment of the present invention, a transistor 482 corresponding to an output transistor and The transistor 481 has a gate electrode provided in a layer different from that of the transistor 481. The pulse generating circuit may be electrically connected to the first and second electrodes via a conductive film. 460 is used in a shift register or the like, the semiconductor device according to one embodiment of the present invention is This can make it possible to prevent a decrease in yield due to the above-mentioned problem.

[0106] In FIG. 9A, one of the source terminal and the drain terminal of the output transistor 464 The output side of the transformer is connected to the wiring 467, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 464 may be connected to a wiring 466. However, as shown in FIG. 9A, the source terminal and the drain terminal of the transistor 464 on the output side If one of the drain terminals is connected to wire 467 instead of wire 466, transistor 4 Even if transistor 464 is normally on, it is necessary to turn transistor 464 off when it should be off. can be done.

[0107] The pulse generating circuit 500 shown in FIG. 9B includes transistors 502 to 504. and transistors 516 to 523. A shift register can be formed by connecting multiple stages.

[0108] The gate electrode of the transistor 502 is connected to the gate electrodes of the transistors 503 and 504. The gate electrode is connected to the gate electrode, and one of the source terminal and drain terminal is connected to the wiring 506. The other terminal is connected to one of the source terminal and the drain terminal of the transistor 517. The transistor 503 has one of its source terminal and drain terminal connected to a wiring 506. The other terminal is connected to the wiring 515. The transistor 504 has a source terminal and a drain terminal. One of the pin terminals is connected to a wiring 507 , and the other is connected to a wiring 514 .

[0109] The gate electrode of the transistor 516 is connected to the wiring 508, and the source terminal and one of the drain terminals is connected to one of the source terminal and drain terminal of the transistor 517. The other end is connected to the wiring 505. The transistor 517 has a gate electrode The other of the source terminal and the drain terminal of the transistor 521 is connected to the wiring 505. The gate electrode of the transistor 518 is connected to the wiring 509. The source terminal and the drain terminal of each of the transistors 502 and 503 are connected to the transistor 504. 503 and the gate electrode of the transistor 504, and the other end is connected to the wiring 505. The transistor 519 has a gate electrode connected to the wiring 508 and a source terminal One of the drain terminals is connected to a wiring 506, and the other is connected to a transistor 502. The gate electrode of the transistor 503 and the gate electrode of the transistor 504 are connected to the gate electrode of the transistor 52. 0 has its gate electrode connected to the wiring 510 and one of its source terminal and drain terminal is connected to the gate electrodes of the transistor 502, the transistor 503, and the transistor 504. The other end of the transistor 521 is connected to a wiring 505. One of the drain terminals is connected to a wiring 515, and the other is connected to a wiring 511. The transistor 522 has a gate electrode connected to the wiring 505 and a source terminal and a drain terminal. One of the IN terminals is connected to the gate electrode of the transistor 521, and the other is connected to the The transistor 523 has its source terminal and drain connected to the gate electrode of the transistor 523. One of the IN terminals is connected to the wiring 514 , and the other is connected to the wiring 512 .

[0110] Transistors 502 to 504 and transistors 516 to 5 Specifically, when the wiring 505 is an n-channel type, a potential VDD is applied to the wiring 505. A potential VSS is applied to the line 506, and a potential VEE is applied to the wiring 507. The potentials of various signals such as clock signals are applied to the lines 508 to 512. Thus, a potential GOUT is output from the wiring 514 and a potential SROUT is output from the wiring 515 .

[0111] In one embodiment of the present invention, a transistor 503 corresponding to an output transistor and a transistor At least one of the transistors 504 and the transistor 502 has a gate electrode that is The gate electrode is electrically connected to the conductive film provided in a layer different from that of the gate electrode. As a result, all of the gates of the transistors 503, 504, and 502 are turned on. Compared with the case where the gate electrode is composed of a single conductive film, each conductive film that functions as a gate electrode Therefore, the area of ​​the conductive film that functions as the gate electrode can be reduced. Therefore, the above-mentioned pulse generation can reduce the occurrence of electrostatic breakdown due to the antenna effect. The semiconductor device according to one embodiment of the present invention uses the read circuit 500 as a shift register or the like. This can make it difficult for a decrease in yield due to destruction to occur.

[0112] In FIG. 9B, one of the source terminal and the drain terminal of the output transistor 504 The output side of the transformer is connected to the wiring 507, but the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 504 may be connected to a wiring 506. However, as shown in FIG. 9B, the source terminal and the drain terminal of the transistor 504 on the output side If one of the drain terminals is connected to wire 507 instead of wire 506, transistor 5 Even if transistor 504 is normally on, it is necessary to turn off transistor 504 when it should be turned off. can be done.

[0113] The pulse generating circuit 530 shown in FIG. 10 includes transistors 532 to 534. The pulse generating circuit 530 includes transistors 546 to 553. By connecting several stages, a shift register can be formed.

[0114] The gate electrode of the transistor 532 is connected to the gate electrodes of the transistors 533 and 534. The gate electrode is connected to the gate electrode, and one of the source terminal and the drain terminal is connected to the wiring 536. The other terminal is connected to one of the source terminal and the drain terminal of the transistor 452. The transistor 533 has one of its source terminal and drain terminal connected to a wiring 536. The other terminal is connected to the wiring 545. The transistor 534 has a source terminal and a drain terminal. One of the pin terminals is connected to a wiring 537 and the other is connected to a wiring 544 .

[0115] The gate electrode of the transistor 546 is connected to the wiring 538, and the source terminal and one of the drain terminals is connected to one of the source terminal and drain terminal of the transistor 532. The other end is connected to a wiring 535. The transistor 547 has a gate electrode A wiring 539 is connected to the transistor 532, and one of the source terminal and the drain terminal of the wiring 539 is connected to the transistor 532. The other end of the transistor 533 is connected to the gate electrode of the transistor 534, and the other end of the transistor 534 is connected to the wiring 53 5. The transistor 548 has its gate electrode connected to the wiring 540. The source terminal and the drain terminal of each of the transistors 532, 533, and The other end is connected to a gate electrode of a transistor 534, and the other end is connected to a wiring 535. The transistor 549 has a gate electrode connected to the wiring 538 and a source terminal and a drain terminal. One of the in terminals is connected to the wiring 536, and the other is connected to the transistor 532 and the transistor 53 3, and the gate electrode of transistor 534. Transistor 550 is The gate electrode of the transistor is connected to the wiring 535, and one of the source terminal and the drain terminal of the transistor is connected to the transistor. The other terminal is connected to one of the source terminal and drain terminal of the transistor 552. The transistor 551 has its source terminal and drain connected to the gate electrode of the transistor 551. One of the IN terminals is connected to the wiring 545, and the other is connected to the wiring 541. The gate electrode of the transistor 552 is connected to the wiring 535, and the source terminal and the drain terminal The other terminal is connected to the gate electrode of the transistor 553. The transistor 553 is One of the source terminal and the drain terminal is connected to the wiring 544, and the other is connected to the wiring 542. This is being continued.

[0116] Transistors 532 to 534 and transistors 546 to 5 In the case where the wiring 53 is an n-channel type, specifically, a potential VDD is applied to the wiring 535, and A potential VSS is applied to the line 536, and a potential VEE is applied to the wiring 537. The potentials of various signals such as clock signals are applied to the lines 538 to 542. Thus, a potential GOUT is output from the wiring 544 and a potential SROUT is output from the wiring 545 .

[0117] In one embodiment of the present invention, a transistor 533 corresponding to an output transistor and a transistor At least one of the transistors 534 and the transistor 532 has a gate electrode that is The gate electrode is electrically connected to the conductive film provided in a layer different from that of the gate electrode. As a result, all of the gates of the transistors 533, 534, and 532 are turned on. Compared with the case where the gate electrode is composed of a single conductive film, each conductive film that functions as a gate electrode Therefore, the area of ​​the conductive film that functions as the gate electrode can be reduced. Therefore, the above-mentioned pulse generation can reduce the occurrence of electrostatic breakdown due to the antenna effect. The electrostatic discharge of the semiconductor device according to one embodiment of the present invention using the read circuit 530 as a shift register or the like is This can make it difficult for a decrease in yield due to destruction to occur.

[0118] In FIG. 10, one of the source terminal and the drain terminal of the output transistor 534 is Although the output transistor is connected to the wiring 537, the present invention is not limited to this configuration. One of the source terminal and the drain terminal of the transistor 534 may be connected to the wiring 536. However, as shown in FIG. 10, the source terminal and the drain terminal of the transistor 534 on the output side If one of the terminals is connected to wire 537 instead of wire 536, transistor 534 will Even if the transistor 534 is on, it can be turned off when it should be. .

[0119] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0120] (Embodiment 4) Taking a light-emitting device using an OLED as an example, the pixel of a semiconductor display device according to one embodiment of the present invention will be described. The cross-sectional structure of the pixel 840 and the driving circuit will be described with reference to FIG. A cross-sectional view of a circuit 841 is shown as an example.

[0121] In FIG. 11, a pixel 840 includes a light emitting element 832 and a control circuit for controlling the supply of current to the light emitting element 832. The pixel 840 includes the light emitting element 832 and a transistor 831 for controlling the light emitting element. In addition to the transistor 831, a transistor that controls the input of an image signal to the pixel 840 and a The input / output terminal may include various semiconductor elements such as a capacitor element for holding the potential of the signal.

[0122] In FIG. 11, the driver circuit 841 includes a transistor 830. The register 830 is an output side transistor of a shift register corresponding to a part of the driver circuit 841. The driver circuit 841 includes, in addition to the transistor 830, The semiconductor device may include various semiconductor elements such as a transistor and a capacitor.

[0123] The transistor 831 is formed on a substrate 800 having an insulating surface, and a conductor serving as a gate electrode is formed on the substrate 800. A conductive film 816, a gate insulating film 802 on the conductive film 816, and a conductive film 816 are formed at a position overlapping the conductive film 816. A semiconductor film 817 provided on the gate insulating film 802 and a source terminal or a drain terminal The conductive film 815 and the conductive film 818 function as a semiconductor film. The conductive film 816 also functions as a scan line.

[0124] The transistor 830 is formed on a substrate 800 having an insulating surface, and a conductor that functions as a gate electrode. A conductive film 812, a gate insulating film 802 on the conductive film 812, and a conductive film 812 are formed at a position overlapping the conductive film 812. A semiconductor film 813 provided on the gate insulating film 802 and a source terminal or a drain terminal The conductive film 814 and the conductive film 819 function as a semiconductor film. .

[0125] In addition, the conductive film 850 provided over the substrate 800 having an insulating surface is a transistor 830. The conductive film 812 and the conductive film 850 is an opening provided in the conductive film 812 and the gate insulating film 802 on the conductive film 850. 8. The conductive film 851 on the gate insulating film 802 is connected thereto via a gate insulating film 802 .

[0126] In addition, on the conductive film 814, the conductive film 815, the conductive film 818, the conductive film 819, and the conductive film 851, An insulating film 820 and an insulating film 821 are provided so as to be stacked in this order. A conductive film 852 and a conductive film 853 are provided over the insulating film 821. The conductive film 853 is exposed to the conductive film 852 through the openings provided in the insulating film 820 and the insulating film 821. 51 and the conductive film 818, respectively.

[0127] An insulating film 854 is provided over the conductive film 852 and the conductive film 853. A conductive film 822 that functions as an anode is provided on the insulating film 854. The conductive film 822 is , and is connected to the conductive film 853 through an opening formed in the insulating film 854 .

[0128] In addition, the insulating film 824 having an opening through which a part of the conductive film 822 is exposed is formed on the insulating film 85. An EL layer 825 and an insulating film 854 are provided on a part of the conductive film 822 and the insulating film 854. A conductive film 826 serving as a cathode is provided in this order. The region where the light emitting element 832 is formed is an area where the EL layer 825 and the conductive film 826 overlap each other. do.

[0129] Note that in one embodiment of the present invention, the transistors 830 and 831 are amorphous and Semiconductors such as silicon or germanium, which may be crystalline, polycrystalline or single crystalline, are used for the semiconductor film. Alternatively, a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor film. It's fine if it is.

[0130] The semiconductor films of the transistors 830 and 831 may be amorphous, microcrystalline, polycrystalline, or When a semiconductor such as silicon or germanium, which is a single crystal, is used, it is necessary to give one conductivity. The semiconductor film is doped with an impurity element that functions as a source region or a drain region. For example, by adding phosphorus or arsenic to the semiconductor film, It is possible to form an impurity region having n-type conductivity. By adding this to a semiconductor film, an impurity region having p-type conductivity can be formed.

[0131] When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, In this case, a dopant is added to the semiconductor film to function as a source region or a drain region. The dopant can be added by ion implantation. Dopants include rare gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, Group 15 elements such as arsenic and antimony can be used. For example, nitrogen can be used as a dopant. When used as a sintered body, the concentration of nitrogen atoms in the impurity region is 5×10 19 / cm 3 1x or more 10 22 / cm 3 It is desirable that the following:

[0132] Silicon semiconductors are grown by vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon produced by the laser annealing method, amorphous silicon Polycrystalline silicon that has been crystallized by implanting hydrogen ions into single crystal silicon wafers. For example, single crystal silicon from which a portion has been peeled off can be used.

[0133] The oxide semiconductor contains at least indium (In) or zinc (Zn). It is preferable that the oxide contains In and Zn. In addition to these, as a stabilizer to reduce the variation in the electrical characteristics of the transistors It is preferable to have gallium (Ga). Also, tin (Sn) is used as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is also preferable to have aluminum (Al) as a stabilizer.

[0134] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may contain one or more of the elements tetraethium (Lu).

[0135] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. The oxide semiconductor may contain silicon.

[0136] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, the off-state Since it is possible to sufficiently reduce the current and the mobility is high, it is suitable for use in semiconductor devices. It is suitable as a semiconductor material.

[0137] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The oxides of In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having a molecular ratio or an oxide having a composition close to that.

[0138] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0139] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid The oxide semiconductor that has been highly purified by reducing the element vacancies is an i-type (intrinsic semiconductor) or Therefore, the off-state current of the transistor using the oxide semiconductor is In addition, the band gap of the oxide semiconductor is 2 eV or more, The energy is preferably 2.5 eV or more, and more preferably 3 eV or more. The impurity concentration is sufficiently reduced, and the oxygen deficiency is reduced, resulting in a highly purified acid. By using a nitride semiconductor film, the off-state current of a transistor can be reduced.

[0140] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor for a semiconductor film is low. For example, when the channel width is 1×10 6 μm Even with a device with a channel length of 10 μm, the voltage between the source and drain terminals (drain voltage When the applied voltage is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-state current, which is the off-state current divided by the channel width of the transistor, is 100zA / μ m or less. Also, by connecting the capacitance element and the transistor, A circuit that controls the charge flowing in or out of a capacitor using the transistor is used to In the measurement, a highly purified oxide semiconductor film was formed on the transistor. It is used in the channel formation region, and the charge amount per unit time of the capacitance element is used to calculate the capacitance of the transistor. The off-state current of the transistor was measured. As a result, the voltage between the source and drain terminals of the transistor It was found that an even lower off-state current of several tens of yA / μm can be obtained when the Therefore, a transistor in which a highly purified oxide semiconductor film is used for a channel formation region has the following characteristics: The off-state current is significantly lower than that of a transistor using crystalline silicon.

[0141] Unless otherwise specified, in this specification, the off-state current is In this case, the drain terminal is set to a higher potential than the source terminal and gate electrode. When the potential of the gate electrode is 0 or less with respect to the potential of the source terminal as the reference, The off-state current in this specification refers to the current that flows between the drain terminal and the p In a channel type transistor, the drain terminal is lower than the source terminal and the gate electrode. When the potential of the gate electrode is set to zero or less, the potential of the gate electrode is set to zero or less. This refers to the current that flows between the source and drain terminals when the transistor is on.

[0142] For example, the oxide semiconductor film may be formed using In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing In-Ga- When the Zn-based oxide semiconductor film is formed by a sputtering method, the atomic ratio is preferably In :Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or A target of In-Ga-Zn oxide with the atomic ratio of 3:1:4 is used. The oxide semiconductor film is formed by using an In-Ga-Zn oxide target having the above structure. Polycrystals or CAAC (C Axis Aligned Crystal) are formed. In addition, the relative density of the target containing In, Ga, and Zn is 90% or more. 00% or less, preferably 95% or more and less than 100%. As a result, the formed oxide semiconductor film becomes a dense film.

[0143] When an In-Zn oxide material is used as the oxide semiconductor, The atomic ratio of the metal elements is In:Zn=50:1 to 1:2 (converted to molar ratio). Then In 2 O 3 In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1 :1 (In mole ratio) 2 O 3 ZnO=10:1 to 1:2), more preferably In:Zn=1.5:1-15:1 (converted to molar ratio of In 2 O 3 :ZnO=3: For example, the In-Zn oxide semiconductor film is formed by The target has an atomic ratio of In:Zn:O=X:Y:Z, where Z>1.5X+Y. By setting the ratio of Zn within the above range, it is possible to improve the mobility.

[0144] Note that the oxide semiconductor film may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0145] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0146] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure having crystalline and amorphous parts in the amorphous phase. The crystal part must be small enough to fit within a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the The boundary between the crystal and the crystalline part is not clear. Therefore, the CAAC-OS film does not have any in-boundary defects. The resulting decrease in electron mobility is suppressed.

[0147] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that The range of 5° to 95° is also included. This also includes the range from 1° to 5°.

[0148] In the CAAC-OS film, the distribution of the crystal parts does not have to be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0149] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0150] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0151] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles may be crystalline and may be crystalline. By reaching the plate, a CAAC-OS film can be formed.

[0152] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0153] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0154] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When a plate-shaped sputtered particle reaches a substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0155] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0156] As an example of a sputtering target, an In-Ga-Zn-O compound target is The details are shown below.

[0157] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified number of moles and then pressurized. By heat treatment at a temperature between 1000 and 1500℃, polycrystalline In-Ga -Zn-O compound target, where X, Y and Z are any positive numbers. , the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2 :2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. The setting can be changed as appropriate depending on the kit.

[0158] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0159] (Embodiment 5) In this embodiment, an example of a panel, which corresponds to one mode of a semiconductor display device, will be described. The panel shown in FIG. 12 includes a substrate 700, a pixel portion 701 on the substrate 700, a signal line driver circuit, 702a, a signal line driver circuit 702b, a scanning line driver circuit 703a, and a scanning line driver circuit 70 3b and

[0160] The pixel portion 701 has a plurality of pixels, and each pixel has a display element and a control circuit for controlling the operation of the display element. A single or multiple transistors are provided. The scanning line driving circuit 703b supplies a potential to the scanning lines connected to each pixel, thereby driving the pixel section 70 The signal line driver circuit 702a and the signal line driver circuit 702b select a pixel included in the driving circuit 702. The scanning line driving circuit 703a and the scanning line driving circuit 703b are used to select pixels from the image signals. Control the supply.

[0161] In FIG. 12, the pixel portion is driven by the scanning line driver circuit 703a and the scanning line driver circuit 703b. In the example shown, a potential is supplied to each scanning line from both ends of the pixel 701. Even if the pixel section 701 becomes larger and the scanning line becomes longer, the scanning line can be This makes it possible to prevent a potential drop caused by the wiring resistance of the scan line.

[0162] In addition, the signal line driver circuits 702a and 702b drive image signals to the pixels. In FIG. 12, the signal line driver circuit 702a supplies the odd-numbered An image signal is supplied to the pixel through the second signal line, and the signal line driver circuit 702b 10 illustrates a case where image signals are supplied to pixels via even-numbered signal lines.

[0163] In addition, in FIG. 12, a scanning line driver circuit 703a and a scanning line driver circuit 703b are provided in the pixel portion 701. The signal line driver circuit 702a and The signal line driver circuit 702b is a TAB (Tape Automated Bonding) The example shows a case where the chip is mounted on a substrate 700 using the method described above. The driving circuit 703a and the scanning line driving circuit 703b may be mounted on the substrate 700. Alternatively, the signal line driver circuit 702a and the signal line driver circuit 702b may be formed on a substrate together with the pixel portion 701. It may be formed on the plate 700. Furthermore, the mounting method of the chip is not limited to the TAB method. The chip uses FPC (Flexible Printed Circuit) etc. Alternatively, the chip may be mounted on a substrate 700 by a COF (Chip On Film) method. A chip may be mounted on the substrate 700 using the same.

[0164] Since the scanning lines are connected to a plurality of pixels, the scanning line driving circuit 703a and the scanning line driving circuit The scanning line driver circuit 703a and the scanning line driver circuit 703b are required to have a large current supply capability. The transistor located on the output side of the pulse output circuit of the scanning line driving circuit 703b is In particular, when the number of pixels in the pixel section 701 is increased, or when the number of pixels in the pixel section 7 If the area of ​​01 increases, the wiring resistance of the scan line increases, or the load connected to the scan line increases. Therefore, in order to meet the larger current supply capability, the transistor As a result, the size of the transistors needs to be further increased. As a result, a plurality of transistors in the scanning line driver circuit 703a and the scanning line driver circuit 703b The area of ​​the conductive film that functions as the gate electrode of the transistor increases, and the above problem due to the antenna effect is However, in one embodiment of the present invention, a plurality of gate electrodes are The gate electrode is electrically connected to the conductive film provided in a layer different from that of the gate electrode. Therefore, the area of ​​each conductive film functioning as a gate electrode can be reduced. Even if the number of pixels in 701 is increased or the area of ​​the pixel portion 701 is increased, the antenna effect is not affected. This can make it difficult for electrostatic damage to occur.

[0165] In this embodiment, the scanning line driver circuit 703a and the scanning line driver circuit 703b are Although the case where the configuration according to the embodiment of the present invention is applied has been described, in one embodiment of the present invention, A structure according to one embodiment of the present invention is applied to the driver circuit 702a and the signal line driver circuit 702b. is also good.

[0166] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0167] (Embodiment 6) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras, digital cameras, etc. Cameras such as Talstill cameras, goggle-type displays (head-mounted displays) , navigation systems, audio playback devices (car audio, digital audio players) Copiers, fax machines, printers, printer-combination machines, automated teller machines, Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 13. .

[0168] FIG. 13A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, A driving circuit for a portable game machine, or a display unit 5003 or By using a semiconductor device according to one embodiment of the present invention for the display portion 5004, a mobile phone with high yield can be manufactured. It is possible to provide a portable game machine. The device has two display units 5003 and 5004. The number of parts is not limited to this.

[0169] FIG. 13B shows a display device, which includes a housing 5201, a display portion 5202, a support stand 5203, and the like. A semiconductor display according to one embodiment of the present invention is used for a driver circuit of a display device or the display portion 5202. By using the device, it is possible to provide a display device with a high yield. includes all information display applications such as personal computers, TV broadcast reception, and advertising displays. Display device included.

[0170] FIG. 13C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. 5403, a pointing device 5404, etc. A semiconductor display according to one embodiment of the present invention may be used for a driver circuit of a mobile computer or the display portion 5402. By using this device, it is possible to provide notebook personal computers with a high yield. can.

[0171] FIG. 13D shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 5602. 5605, and the angle between the first housing 5601 and the second housing 5602 is The first display unit 5603 is connected to the The switching is performed according to the angle between the first housing 5601 and the second housing 5602 at the portion 5605. In addition, at least the first display unit 5603 and the second display unit 5604 may be configured to display the image. On the other hand, a semiconductor display device having a function as a position input device may be used. The function as a position input device can be realized by providing a touch panel on the semiconductor display device. Alternatively, the function as a position input device can be added to a photo sensor. The light can also be added by providing a photoelectric conversion element having the same characteristics as the light source in a pixel portion of a semiconductor display device. The present invention is applied to the driving circuit of the portable information terminal, or the first display unit 5603 or the second display unit 5604. To provide a portable information terminal with high yield by using a semiconductor device according to one embodiment of the present invention. can be done.

[0172] FIG. 13E shows a mobile phone, which includes a housing 5801, a display portion 5802, an audio input portion 5803, The device has a voice output unit 5804, an operation key 5805, a light receiving unit 5806, etc. By converting the light received in the mobile phone into an electrical signal, it is possible to capture an image from the outside. The semiconductor device according to one embodiment of the present invention is used for a driver circuit or a display portion 5802 of a mobile phone. This makes it possible to provide mobile phones with a high yield rate.

[0173] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0174] 100 Semiconductor device 101 Transistor 102 Transistor 103 Wiring 104 Wiring 105 Wiring 106 Wiring 107 Wiring 110 Conductive film 111 Gate insulating film 112 Semiconductor film 113 Conductive Film 114 Conductive Film 115 Conductive Film 116 Semiconductor Film 117 Conductive Film 118 Conductive Film 119 Conductive Film 120 Opening 121 Opening 122 Conductive Film 123 Semiconductor Film 124 Conductive Film 125 Conductive Film 126 Semiconductor Film 127 Conductive Film 128 Conductive Film 210 Conductive film 211 Gate insulating film 212 Semiconductor Film 213 Conductive Film 214 Conductive Film 215 Conductive Film 216 Semiconductor Film 217 Conductive Film 218 Conductive Film 219 Conductive Film 220 Opening 221 Opening 222 Conductive Film 223 Semiconductor Film 224 Conductive Film 225 Conductive Film 226 Semiconductor Film 227 Conductive Film 228 Conductive Film 300 Pulse Generator Circuit 301 Transistor 302 Transistor 303 Transistor 304 Transistor 305 Transistor 306 Transistor 307 Transistor 308 Transistor 309 Transistor 310 Transistor 311 Transistor 312 Transistor 313 Transistor 314 Transistor 315 Transistor 316 Capacitive element 317 Wiring 318 Wiring 319 Wiring 320 Wiring 321 Wiring 322 Wiring 323 Wiring 324 Wiring 325 Wiring 326 Wiring 327 Wiring 328 Wiring 329 Wiring 350 Inverter 351 Inverter 400 Pulse Generator Circuit 402 Transistor 403 Transistor 404 Transistor 405 Wiring 406 Wiring 407 Wiring 408 Wiring 409 Wiring 410 Wiring 411 Wiring 412 Wiring 413 Wiring 414 Wiring 415 Transistor 416 Transistor 417 Transistor 418 Transistor 419 Transistor 420 Transistor 430 Pulse Generator Circuit 432 Transistor 433 Transistor 434 Transistor 435 Wiring 436 Wiring 437 Wiring 438 Wiring 439 Wiring 440 Wiring 441 Wiring 442 Wiring 443 Wiring 444 Wiring 445 Wiring 446 Transistor 447 Transistor 448 Transistor 449 Transistor 450 Transistors 451 Transistor 452 Transistor 460 Pulse Generator Circuit 462 Transistor 463 Transistor 464 Transistor 465 Wiring 466 Wiring 467 Wiring 468 Wiring 469 Wiring 470 Wiring 471 Wiring 472 Wiring 474 Wiring 475 Wiring 476 Transistors 477 Transistors 478 Transistors 479 Transistor 480 Transistors 481 Transistor 482 Transistors 500 Pulse Generator Circuit 502 Transistor 503 Transistor 504 Transistor 505 Wiring 506 Wiring 507 Wiring 508 Wiring 509 Wiring 510 Wiring 511 Wiring 512 Wiring 514 Wiring 515 Wiring 516 Transistor 517 Transistor 518 Transistor 519 Transistor 520 Transistor 521 Transistor 522 Transistor 523 Transistor 530 Pulse Generator Circuit 532 Transistor 533 Transistor 534 Transistor 535 Wiring 536 Wiring 537 Wiring 538 Wiring 539 Wiring 540 Wiring 541 Wiring 542 Wiring 544 Wiring 545 Wiring 546 Transistor 547 Transistor 548 Transistor 549 Transistor 550 Transistor 551 Transistor 552 Transistor 553 Transistor 700 Substrates 701 Pixel section 702a Signal line driver circuit 702b Signal line driver circuit 703a Scanning line driver circuit 703b Scanning line driver circuit 800 boards 802 Gate insulating film 812 Conductive film 813 Semiconductor Film 814 Conductive film 815 Conductive film 816 Conductive Film 817 Semiconductor Film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 824 Insulating film 825 EL layer 826 Conductive Film 830 Transistor 831 Transistor 832 Light emitting element 840 pixels 841 Drive circuit 850 Conductive Film 851 Conductive film 852 Conductive film 853 Conductive film 854 Insulating film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Support stand 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Case 5602 Case 5603 Display section 5604 Display section 5605 Connection 5606 Operation key 5801 Case 5802 Display section 5803 Audio input unit 5804 Audio output unit 5805 Operation key 5806 Light receiving section

Claims

1. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the sixth transistor is electrically connected to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor, a second potential supplied to the second wiring is supplied to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor; Semiconductor device.

2. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the fifth transistor is electrically connected to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor, a potential of a clock signal supplied to the fourth wiring is supplied to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor; Semiconductor device.

3. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the sixth transistor is electrically connected to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor, a second potential supplied to the second wiring is supplied to the other of the source or the drain of the fifth transistor through at least a channel formation region of the sixth transistor, a period in which a potential applied to the other of the source and the drain of the first transistor is different from a potential applied to the fourth wiring; Semiconductor device.

4. a first transistor to an eighth transistor and a first wiring to a fifth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, one of the source and the drain of the second transistor is always electrically connected to the second wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to one of the source and the drain of the fourth transistor; a gate of the third transistor is always electrically connected to the third wiring to which a first potential is supplied; the other of the source and the drain of the fourth transistor is always electrically connected to the second wiring; one of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring, one of the source and the drain of the sixth transistor is always electrically connected to the second wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the gate of the eighth transistor is always electrically connected to the fifth wiring; when one of the source or the drain of the fifth transistor is electrically connected to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor, a potential of a clock signal supplied to the fourth wiring is supplied to the other of the source or the drain of the sixth transistor through at least a channel formation region of the fifth transistor, a period in which a potential applied to the other of the source and the drain of the first transistor is different from a potential applied to the fourth wiring; Semiconductor device.

5. In any one of claims 1 to 4, The first transistor to the eighth transistor all have the same polarity. Semiconductor device.

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