Memory device

Abstract

The present invention provides a highly reliable storage device. This storage device comprises a first conductor, a second conductor that is arranged above the first conductor, a third conductor that is arranged above the second conductor, a fourth conductor that is arranged above the third conductor, a fifth conductor that is arranged above the fourth conductor, a sixth conductor that is arranged above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor and a second semiconductor. With respect to this storage device, at least the third conductor and the fourth conductor have an opening; the first insulator, the first semiconductor, the second insulator and the second semiconductor are sequentially arranged in this order on the inner lateral surface of the opening; the seventh conductor is arranged between the first semiconductor and the second insulator in a region between the third conductor and the second insulator; the first semiconductor is electrically connected to the second conductor and the fifth conductor; and the second semiconductor is electrically connected to the first conductor and the sixth conductor.

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in the present specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Thus, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, electronic devices, and the like may include semiconductor elements and semiconductor circuits. Display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. One embodiment of the present invention particularly relates to a memory device and a manufacturing method thereof. [Background technology]

[0004] In recent years, with an increase in the amount of data handled, there is a demand for semiconductor devices with larger storage capacity. In order to increase the storage capacity per unit area, it is effective to form memory cells in a stacked manner (see Patent Documents 1 and 2). By providing memory cells in a stacked manner, the storage capacity per unit area can be increased according to the number of stacked memory cells. Patent Documents 3 and 4 disclose memory devices using an oxide semiconductor. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer.

[0005] Furthermore, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Publication 2011 / 0065270A1 [Patent Document 2] U.S. Patent Publication No. 9634097B2 [Patent Document 3] JP 2018-207038 A [Patent Document 4] JP 2019-8862 A [Patent Document 5] JP 2018-157205 A [Non-patent literature]

[0007] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO” FUNDAMENTALS (USA), Wiley-SID Series in Display Technology, 2017, p.94-97 Summary of the Invention [Problem to be solved by the invention]

[0008] In Patent Documents 1 and 2, a plurality of storage elements (also called memory cells) are stacked and connected in series to form a three-dimensional memory cell array (also called a memory string).

[0009] In Patent Document 1, a semiconductor provided in a columnar shape is in contact with an insulator having a charge storage layer. In Patent Document 2, a semiconductor provided in a columnar shape is in contact with an insulator that functions as a tunnel dielectric. In both Patent Document 1 and Patent Document 2, writing information to a memory cell is performed by extracting and injecting charges through the insulator. In this case, a trap center may be formed at the interface where the semiconductor and the insulator contact. The trap center may capture electrons and cause the threshold voltage of the transistor to fluctuate. In addition, the extraction and injection of charges may deteriorate one or both of the inside of the insulator and the interface where the semiconductor and the insulator contact, and the charges held in the charge storage layer may leak and disappear. This may have a negative effect on the reliability of the memory device.

[0010] Thus, an object of one embodiment of the present invention is to provide a highly reliable memory device.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with a small occupation area.Another object of one embodiment of the present invention is to provide a memory device with low manufacturing costs.Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device.Another object of one embodiment of the present invention is to provide a semiconductor device with low manufacturing costs.Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a memory device having a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor, wherein at least the third conductor and the fourth conductor have openings, and the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in that order from the inner side of the opening, and a seventh conductor is provided between the first semiconductor and the second insulator in the region between the third conductor and the second insulator, and the first semiconductor is electrically connected to the second conductor and the fifth conductor, and the second semiconductor is electrically connected to the first conductor and the sixth conductor.

[0013] In the above, it is preferable that the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are each provided as a concentric layer inside the opening of the third conductor.

[0014] In the above, it is preferable that the first insulator, the first semiconductor, the second insulator, and the second semiconductor are each provided as a concentric layer inside the opening of the fourth conductor.

[0015] In the above, the first semiconductor is preferably a first oxide semiconductor.

[0016] In the above, the first oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0017] In the above, the second semiconductor is preferably a second oxide semiconductor.

[0018] In the above, the first oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0019] In the above, it is preferable that openings are also provided in the second conductor and the fifth conductor, a second insulator is provided between the second conductor and the second semiconductor, and a second insulator is provided between the fifth conductor and the second semiconductor.

[0020] Another embodiment of the present invention is a method for manufacturing a memory device, comprising steps of forming a first conductor, forming a second conductor above the first conductor, forming a first semiconductor electrically connected to the second conductor, forming openings in the first semiconductor and the second conductor, forming an insulator covering side surfaces of the first semiconductor and side surfaces of the second conductor within the openings, and forming a second semiconductor electrically connected to the first conductor, in which an insulator is provided between the first semiconductor and the second semiconductor and an insulator is provided between the second conductor and the second semiconductor.

[0021] In the above, the first semiconductor is preferably a first oxide semiconductor.

[0022] In the above, the first oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0023] In the above, the second semiconductor is preferably a second oxide semiconductor.

[0024] In the above, the second oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0025] Another embodiment of the present invention is a method for manufacturing a memory device, comprising steps of forming a first conductor, forming a second conductor above the first conductor, processing the first conductor and the second conductor so that the width of the second conductor is shorter than the width of the first conductor, forming a third conductor above the second conductor, forming openings in the third conductor, the second conductor, and the first conductor, forming an insulator in the opening, and forming a semiconductor in the opening, wherein the insulator is provided between the first conductor and the semiconductor and the insulator is provided between the second conductor and the semiconductor.

[0026] In the above, the semiconductor is preferably an oxide semiconductor.

[0027] In the above, the oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc. Effect of the Invention

[0028] In the fabrication of a three-dimensional memory cell array in which multiple memory elements are stacked and connected in series, the total number of steps can be less than the product of the number of stacked memory elements and the number of steps to fabricate one memory element, which is preferable. In other words, the fabrication steps of the memory cell array are not proportional to the number of stacked memory elements. For example, when comparing the number of fabrication steps of memory cell array A having four layers of memory elements with the number of fabrication steps of memory cell array B having 32 layers of memory elements, the number of fabrication steps of memory cell array B can be significantly less than eight times the number of fabrication steps of memory cell array A, even though the number of stacked memory elements is eight times.

[0029] According to one embodiment of the present invention, a highly reliable memory device can be provided. According to one embodiment of the present invention, a memory device with a large memory capacity can be provided. According to one embodiment of the present invention, a memory device with a small occupation area can be provided. According to one embodiment of the present invention, a memory device with low manufacturing costs can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low manufacturing costs can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0031] 1A and 1B are perspective views of a storage device. FIG. 2 is a cross-sectional view of the storage device. FIG. 3 is a cross-sectional view of a memory string. FIG. 4 is a circuit diagram of a memory string. 5A and 5B are cross-sectional views of a memory string. FIG. 6 is a cross-sectional view of a memory element. 7A and 7B are cross-sectional views of a memory string. FIG. 8 is a cross-sectional view of a memory string. Fig. 9A is a diagram for explaining the classification of crystal structures, Fig. 9B is a diagram for explaining the XRD spectrum of the CAAC-IGZO film, and Fig. 9C is a diagram for explaining the micro-electron beam diffraction pattern of the CAAC-IGZO film. 10A to 10C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 11A to 11C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 12A to 12C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 13A to 13C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 14A to 14C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 15A to 15C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 16A to 16C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 17A to 17C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 18A to 18C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 19A to 19C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 20A to 20C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 21A to 21C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 22A to 22C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 23A to 23C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 24A to 24C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 25A to 25C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 26A to 26C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 27A to 27C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 28A to 28C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 29A to 29C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 30A to 30C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. 31A to 31C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. Fig. 32A is a schematic diagram of a multi-chamber film forming apparatus, and Fig. 32B is a cross-sectional view of a film forming chamber. 33A to 33C are diagrams illustrating an example of the configuration of an ALD apparatus. FIG. 34 is a diagram illustrating an example of a circuit configuration of a memory string. FIG. 35 is a diagram illustrating an example of a circuit configuration of a memory string. FIG. 36 is a diagram illustrating an example of a circuit configuration of a memory string. FIG. 37 is a diagram illustrating an example of a circuit configuration of a memory string. FIG. 38 is a diagram illustrating an example of a circuit configuration of a memory string. FIG. 39 is a timing chart illustrating an example of a write operation of a memory string. 40A and 40B are circuit diagrams illustrating an example of a write operation of a memory string. 41A and 41B are circuit diagrams illustrating an example of a write operation of a memory string. FIG. 42 is a timing chart illustrating an example of a read operation of a memory string. 43A and 43B are circuit diagrams illustrating an example of a read operation of a memory string. 44A and 44B are circuit diagrams illustrating an example of a read operation of a memory string. FIG. 45 is a circuit diagram illustrating an example of a read operation of a memory string. FIG. 46 is a block diagram illustrating a configuration example of a semiconductor device. 47A to 47C are perspective views for explaining configuration examples of a semiconductor device. FIG. 48 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 49 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 50A is a perspective view for explaining an example of the configuration of a computer, and FIG. 50B is a perspective view for explaining a monolithic IC. 51A and 51B are diagrams illustrating the memory hierarchy of a computer and a monolithic IC, respectively. Fig. 52A is a schematic diagram of the semiconductor device, and Fig. 52B is a perspective view of the semiconductor device. 53A to 53E are diagrams for explaining an example of a storage device. 54A to 54G are diagrams for explaining an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated description will be omitted.

[0033] In addition, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in the actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0034] In addition, in the drawings, etc., some components may be omitted in order to make the explanation easier to understand.

[0035] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0036] In addition, in this specification and the like, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0037] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] In addition, the functions of the source and drain are interchangeable depending on the operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, so it is difficult to determine which is the source and which is the drain. For this reason, in this specification, the terms source and drain can be used interchangeably.

[0039] In addition, in this specification, "electrically connected" includes a direct connection and a connection via "something having some electrical action." Here, the "something having some electrical action" is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in the actual circuit, there may be no physical connection and only wiring extending therethrough.

[0040] In this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less.

[0041] In this specification and elsewhere, when referring to counting values ​​and measurement values, or to objects, methods, and events that can be converted into counting values ​​or measurement values, terms such as "same," "equal," and "uniform" are intended to include an error of plus or minus 20%, unless otherwise expressly stated.

[0042] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0043] Even when written as "semiconductor", for example, if the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "semiconductor" instead of "insulator". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read as interchangeable.

[0044] Furthermore, even when written as "semiconductor", if the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use "semiconductor" in place of "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be interchangeable.

[0045] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0046] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as a "non-conductive state").

[0047] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0048] In this specification and the like, high power supply potential VDD (hereinafter also simply referred to as "VDD", "H potential", or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS", "L potential", or "L"). Also, VSS refers to a power supply potential that is lower than VDD. Also, ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0049] In addition, unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field effect transistors. Therefore, the threshold voltage (also referred to as "Vth") is assumed to be higher than 0 V. In addition, unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." In addition, unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0050] In this specification and the like, a gate refers to a gate electrode and a part or the whole of a gate wiring. A gate wiring refers to a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0051] In this specification and the like, the source refers to a source region, a source electrode, and a part or all of a source wiring. The source region refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The source electrode refers to a conductive layer connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0052] In this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The drain electrode refers to a conductive layer that is connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0053] In addition, in drawings, etc., to make the potential of wiring and electrodes easier to understand, "H" indicating H potential or "L" indicating L potential may be written next to the wiring and electrode. Wiring and electrodes where a potential change has occurred may be written with "H" or "L" enclosed in a box. When a transistor is in the off state, an "x" symbol may be written over the transistor.

[0054] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., a "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., a "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0055] In addition, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying reference numeral such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second conductor WWL may be described as conductor WWL[2].

[0056] (Embodiment 1) 1A is a perspective view of a memory device 100 according to one embodiment of the present invention and a semiconductor device 200 including a driver circuit 2000. The memory device 100 has a three-dimensional stacked structure.

[0057] The drive circuit 2000 includes a WSL driver 2001, a WBL driver 2002, an RSL driver 2003, an RBL driver 2004, a WWL driver 2005, an RWL driver 2006, and a SEL driver 2007. The RBL driver 2004 may have a sense amplifier function. The RSL driver 2003 may be connected to the ground.

[0058] The WSL driver 2001 connects to the storage device 100 via the wiring WSL_A. The WBL driver 2002 connects to the storage device 100 via the wiring WBL_A. The RSL driver 2003 connects to the storage device 100 via the wiring RSL_A. The RBL driver 2004 connects to the storage device 100 via the wiring RBL_A. The WWL driver 2005 connects to the storage device 100 via one or both of the wiring WWL_A and the wiring SG_A. The RWL driver 2006 connects to the storage device 100 via the wiring RWL_A. The SEL driver 2007 connects to the storage device 100 via the wiring SEL_A. Also, the wiring BG_A connects to the back gate of the storage device 100.

[0059] The memory device 100 is preferably provided above a layer in which the driver circuit 2000 is provided. In addition, as shown in FIG. 1B, the memory device 100 is preferably provided so as to overlap with a part of the driver circuit, since this can reduce the area occupied by the semiconductor device 200. When the memory device 100 and the driver circuit are overlapped, the entire driver circuit may overlap with the memory device 100, or may overlap with a part of the driver circuit. In addition, the memory device 100 may overlap with a specific circuit included in the driver circuit. For example, a sense amplifier can be arranged so that the memory device 100 overlaps with the sense amplifier.

[0060] Although one feature of the semiconductor device 200 according to one embodiment of the present invention is that it has a wiring WSL_A that functions as a write source line and a wiring RSL_A that functions as a read source line, the semiconductor device 200 is not limited to this. The wiring WSL_A and the wiring RSL_A may be connected to each other and connected to a driver circuit that functions as a source line driver.

[0061] The semiconductor device 200 according to one embodiment of the present invention is characterized in that it includes a wiring WBL_A that functions as a write bit line and a wiring RBL_A that functions as a read bit line, but is not limited to this. The wiring WBL_A and the wiring RBL_A may be connected to each other and connected to a driver circuit that functions as a bit line driver.

[0062] In FIG. 1A and other drawings, arrows may be attached to indicate the X, Y, and Z directions. The X, Y, and Z directions are mutually orthogonal. In this specification and other documents, one of the X, Y, and Z directions may be called the "first direction" or "first direction." The other may be called the "second direction" or "second direction." The remaining may be called the "third direction" or "third direction." In this specification and other documents, the direction perpendicular to the upper surface of the base 121 described later is defined as the Z direction.

[0063] Fig. 2 shows a cross section in the XZ plane. Fig. 2 is a cross-sectional view of the portion A1-A2 shown by the dashed dotted line in Fig. 1 and the connection portion between the conductor SEL and the wiring. As mentioned above, some of the components may be omitted in Figs. 1 and 2 for ease of explanation.

[0064] <Storage device configuration example> A memory device 100 according to one embodiment of the present invention includes a memory cell array 110. The memory cell array 110 includes a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane.

[0065] 3 shows a cross-sectional configuration example of a memory string 120 according to one embodiment of the present invention, and FIG. 4 shows a corresponding circuit diagram. The memory string 120 has a configuration in which a plurality of storage elements MC (also referred to as "memory cells") are connected in series. In this embodiment, five storage elements MC are connected in series, but the number of storage elements MC included in the memory string 120 is not limited to five. When the number of storage elements MC included in the memory string 120 is n, n may be an integer of 2 or more.

[0066] The memory string 120 also has a plurality of conductors WWL, a plurality of conductors RWL, a conductor SG, and a conductor SEL. The conductor WWL functions as a part of the wiring WWL_A, the conductor RWL functions as a part of the wiring RWL_A, the conductor SG functions as a part of the wiring SG_A, and the conductor SEL functions as a part of the wiring SEL_A. The plurality of conductors WWL and the plurality of conductors RWL are alternately stacked with an insulator 123 interposed therebetween. The conductor SG is provided in a layer below the plurality of conductors WWL and the plurality of conductors RWL. A conductor WSL is provided below the conductor SG, and a conductor RSL is provided below the conductor WSL. The conductor SEL is provided in a layer above the plurality of conductors WWL and the plurality of conductors RWL. A conductor WBL is provided above the conductor SEL, and a conductor RBL is provided above the conductor WBL.

[0067] 3 and 4, the five memory elements MC are denoted as memory elements MC[1] to MC[5]. Note that when describing matters common to the memory elements MC[1] to MC[5], they are simply referred to as "memory element MC." The same applies to other components such as the conductor WWL, the conductor RWL, and the insulator 123.

[0068] The memory string 120 includes a transistor STr1 connected to the storage element MC[1] and a transistor STr2 connected to the storage element MC[5].

[0069] The conductors WWL, RWL, SG, and SEL extend in the X-axis direction beyond the memory cell array 110. The conductors WWL, RWL, SG, and SEL are stacked in a stepped manner outside the memory cell array 110 (see FIGS. 1 and 2). On the other hand, the conductors WSL, RSL, WBL, and RBL extend in the Y-axis direction beyond the memory cell array 110 (see FIGS. 1 and 3).

[0070] Fig. 5A shows a cross section of the XY plane including the portion B1-B2 shown by the dashed dotted line in Fig. 3, as seen from the Z direction. Fig. 5B shows a cross section of the XY plane including the portion C1-C2 shown by the dashed dotted line in Fig. 3, as seen from the Z direction. Fig. 6 shows an enlarged view of region 105 shown by the two-dot dashed line in Fig. 3. Fig. 6 corresponds to a cross section of memory element MC.

[0071] The memory string 120 has a conductor RSL functioning as part of the wiring RSL_A on a base 121, and has a conductor WSL functioning as part of the wiring WSL_A on the conductor RSL via an insulator 118. The base 121 may be, for example, an insulator. Also, on the conductor WSL, there are insulator 123[1], conductor SG, insulator 123[2], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], insulator 123

[12] , and conductor SEL (see FIG. 3). In addition, a conductor WBL functioning as part of the wiring WBL_A is provided on the conductor SEL via an insulator 138, and a conductor RBL functioning as part of the wiring RBL_A is provided on the conductor WBL via an insulator 186.

[0072] The memory string 120 includes an insulator 118, a conductor WSL, an insulator 123 [1], a conductor SG, an insulator 123 [2], a conductor RWL [1], an insulator 123 [3], a conductor WWL [1], an insulator 123 [4], a conductor RWL [2], an insulator 123 [5], a conductor WWL [2], an insulator 123 [6], a conductor RWL [3], an insulator 123 [7], a conductor WWL [3], an insulator 123 [8], a conductor RWL [4], an insulator 123 [9], a conductor WWL [4], an insulator 123

[10] , a conductor RWL [5], an insulator 123

[11] , a conductor WWL [5], an insulator 123

[12] , a conductor SEL, an insulator 138, and a conductor WBL. An opening 141 is provided by removing a portion of each of the insulator 186 and the conductor RBL.

[0073] The opening 141 extends in the Z direction and reaches the conductors WSL and RSL. In the opening 141, the diameter of a region 142 overlapping with the conductor RWL is larger than the diameter of a region 143 overlapping with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0074] Further, an insulator 124 and a semiconductor 125 are provided along the side surface of the opening 141. The semiconductor 125 has a region that overlaps with the side surface of the opening 141 with the insulator 124 interposed therebetween.

[0075] The memory string 120 also has a conductor 130 extending in the Z direction. The conductor 130 is provided at or near the center of the opening 141. An insulator 129, a semiconductor 127, and an insulator 126 are provided in a region of the conductor 130 that overlaps with a side surface of the opening 141. The semiconductor 127 has a region that overlaps with a side surface of the conductor 130 via the insulator 129. The insulator 126 has a region that overlaps with a side surface of the conductor 130 via the insulator 129 and the semiconductor 127. At the bottom of the opening 141, the semiconductor 127 has a region that is electrically connected to the conductor RSL, and at the upper part of the opening 141, the semiconductor 127 has a region that is electrically connected to the conductor RBL. At the bottom of the opening 141, the semiconductor 125 has a region that is electrically connected to the conductor WSL, and at the upper part of the opening 141, the semiconductor 125 has a region that is electrically connected to the conductor WBL. At the bottom of the opening 141, the conductor 130 has a region that overlaps with the conductor RSL via the insulator 129 and the semiconductor 127. In addition, in the region where the conductor RWL and the conductor 130 overlap, the conductor 128 is provided between the semiconductor 125 and the insulator 126.

[0076] Between the conductor WWL and the conductor 130, an insulator 124, a semiconductor 125, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor WWL side (see FIG. 5A). Between the conductor RWL and the conductor 130, an insulator 124, a semiconductor 125, a conductor 128, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor RWL side (see FIG. 5B).

[0077] The memory element MC has a transistor WTr and a transistor RTr (see FIG. 6). The region where the conductor WWL and the conductor 130 overlap functions as the transistor WTr. The conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the backgate electrode of the transistor WTr. A part of the semiconductor 125 functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via a part of the insulator 124. Note that in the present embodiment and the like, an example is shown in which a part of the conductor WWL functions as the gate electrode, but the gate electrode and the conductor WWL may be provided independently and electrically connected to each other.

[0078] The region where the conductor 128, the conductor RWL, and the conductor 130 overlap functions as the transistor RTr. The conductor RWL functions as the gate electrode of the transistor RTr. The conductor 130 functions as the backgate electrode of the transistor RTr. A part of the semiconductor 127 functions as a semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the gate electrode (conductor RWL) via parts of the insulator 126, the conductor 128, the semiconductor 125, and the insulator 124. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the backgate electrode (conductor 130) via part of the insulator 129.

[0079] One of the source and drain of the transistor STr1 is electrically connected to the semiconductor 125 of the transistor WTr. The other of the source and drain of the transistor STr1 is electrically connected to the conductor WSL. One of the source and drain of the transistor STr2 is electrically connected to the semiconductor 127 of the transistor RTr. The other of the source and drain of the transistor STr2 is electrically connected to the conductor RBL. One of the source and drain of the transistor STr3 is electrically connected to the semiconductor 125 of the transistor WTr. The other of the source and drain of the transistor STr3 is electrically connected to the conductor WBL. Here, the conductor SEL functions as the gates of the transistors STr2 and STr3 (see FIG. 3 and FIG. 4). A part of the semiconductor 127 functions as a semiconductor layer in which the channel of the transistor STr2 is formed, and a part of the semiconductor 125 functions as a semiconductor layer in which the channel of the transistor STr3 is formed.

[0080] Here, we will explain the backgate. The gate and the backgate are arranged so as to overlap with each other via the channel formation region of the semiconductor layer. The backgate can function in the same way as the gate. In addition, the threshold voltage of the transistor can be changed by changing the potential of the backgate. Either the gate or the backgate may be called the "first gate" or "first gate," and the other may be called the "second gate" or "second gate."

[0081] The gate and back gate are formed of a conductive layer or a semiconductor layer with low resistivity, and therefore have the function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed (particularly, an electrostatic shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity.

[0082] Also, by controlling the potential of the back gate, the threshold voltage of the transistor can be controlled. The potential of the back gate may be the same as the potential of the gate, or may be the ground potential (GND potential) or any arbitrary potential.

[0083] The semiconductor layer in which the channels of the transistors WTr and RTr are formed can be used singly or in combination, such as single-crystalline semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, for example, silicon, germanium, etc. can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used. The same applies to the transistors STr1, STr2, and STr3.

[0084] Note that the semiconductor layers used for the transistors may be laminated. When laminating the semiconductor layers, semiconductors having different crystal states may be used, or semiconductors made of different semiconductor materials may be used.

[0085] The semiconductor layers used for the transistors WTr, RTr, STr1, STr2, and STr3 are preferably oxide semiconductors having a metal oxide. A transistor using a metal oxide for the semiconductor layer can obtain a higher field-effect mobility compared to a transistor using amorphous silicon for the semiconductor layer. Also, in a transistor using polycrystalline silicon for the semiconductor layer, there is a possibility that grain boundaries may occur in the semiconductor layer. At grain boundaries, carriers are captured, which may cause a decrease in the on-current of the transistor and a decrease in the field-effect mobility. On the other hand, although details will be described later, in an oxide semiconductor, a crystal structure in which clear grain boundaries are not confirmed or a crystal structure with extremely few grain boundaries can be realized. Using such an oxide semiconductor for the semiconductor layer is suitable because it can realize a transistor having good electrical characteristics such as a high on-current and a high field-effect mobility.

[0086] In this embodiment, as the oxide semiconductor, an oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close to it, an In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to it, an In:Ga:Zn=1:1:1 [atomic ratio] or a composition close to it, or an In:Ga:Zn=1:1:0.5 [atomic ratio] or a composition close to it is used.

[0087] Furthermore, oxide semiconductors, particularly CAAC-IGZO, which is a crystalline oxide semiconductor, have a characteristic structure in which nanoclusters of a few nm (e.g., 1 to 3 nm) are linked together and their c-axes are oriented in the direction perpendicular to the surface on which they are formed. This makes it possible to form a crystal structure in which no clear crystal grain boundaries are visible even within an opening extending in the Z direction.

[0088] In particular, the transistor WTr is preferably a transistor using an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed (also referred to as an "OS transistor"). The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is extremely small. Here, a node where the conductor 128 is electrically connected to one of the source and the drain of the transistor WTr is referred to as a node ND. When an OS transistor is used as the transistor WTr, charge written to the node ND can be held for a long period of time. When an OS transistor is used as the transistor constituting the memory element MC, the memory element MC can be referred to as an "OS memory". The memory string 120 including the memory element MC can also be referred to as an "OS memory". The memory device 100 can also be referred to as an "OS memory".

[0089] The OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered as a non-volatile memory.

[0090] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0091] In addition, because OS memory uses a method of writing charge to a node via a transistor, it does not require the high voltage required for conventional flash memory, and can achieve high-speed write operations. In addition, OS memory does not require the erase operation before rewriting data, which is performed in flash memory. In addition, since no charge is injected or extracted from the floating gate or charge trapping layer, OS memory can write and read data an unlimited number of times. OS memory is less susceptible to deterioration than conventional flash memory, and is highly reliable.

[0092] In addition, the OS memory does not involve structural changes at the atomic level, as in magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), etc. Therefore, the OS memory has better rewrite endurance than the magnetoresistive random access memory and the resistive random access memory.

[0093] Moreover, the off-current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Moreover, the on-current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory is stable in operation even in a high-temperature environment, and is highly reliable. Moreover, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that is stable in operation even in a high-temperature environment and has good reliability can be realized.

[0094] The semiconductor 127 is preferably an n-type semiconductor. Also, the region of the semiconductor 125 that overlaps with the conductor WWL is preferably an i-type or substantially i-type semiconductor. In this case, the transistor WTr is an enhancement type (normally off type) transistor, and the transistor RTr is a depletion type (normally on type) transistor.

[0095] Note that the semiconductor 125 and the semiconductor 127 may be made of the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. The semiconductor 125 and the semiconductor 127 may each be a semiconductor containing silicon. The semiconductor 125 may be an oxide semiconductor, and the semiconductor 127 may be a semiconductor containing silicon. The semiconductor 125 may be a semiconductor containing silicon, and the semiconductor 127 may be an oxide semiconductor.

[0096] 5A corresponds to the XY plane at or near the center of the transistor WTr, and FIG. 5B corresponds to the XY plane at or near the center of the transistor RTr. In FIG. 5A and FIG. 5B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is provided as a concentric layer outside the conductor 130, the semiconductor 127 is provided as a concentric layer outside the insulator 129, the insulator 126 is provided as a concentric layer outside the semiconductor 127, the semiconductor 125 is provided as a concentric layer outside the insulator 126, and the insulator 124 is provided as a concentric layer outside the semiconductor 125. The conductor 128 is provided as a concentric layer between the insulator 126 and the semiconductor 125.

[0097] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. As shown in Fig. 7A, the cross-sectional shape of the conductor 130 may be rectangular. As shown in Fig. 7B, the cross-sectional shape of the conductor 130 may be triangular.

[0098] In the above, an example has been shown in which the semiconductor 125 is electrically connected to the conductor WSL and the semiconductor 127 is electrically connected to the conductor RSL at the bottom of the memory string 120, but the present embodiment is not limited to this.

[0099] 8, two memory strings adjacent to each other in the Y-axis direction can be electrically connected to form one memory string 120 A. In the memory string 120 A, memory strings 120_1 and 120_2 are electrically connected by conductors 119 and 122.

[0100] At the upper part of the memory string 120_1, the semiconductor 125 and the conductor WSL are electrically connected, and the semiconductor 127 and the conductor RSL are electrically connected. At the upper part of the memory string 120_2, the semiconductor 125 and the conductor WBL are electrically connected, and the semiconductor 127 and the conductor RBL are electrically connected. At the lower parts of the memory strings 120_1 and 120_2, the respective semiconductors 125 are electrically connected via the conductors 119, and the respective semiconductors 127 are electrically connected via the conductors 122.

[0101] The memory string 120A includes memory elements MC[1] to MC

[10] from the conductors WSL and RSL toward the conductors WBL and RBL. The memory elements MC[5] and MC[6] are electrically connected via the conductors 119 and 122.

[0102] The memory string 120 can also be called a memory device, and the memory element MC can also be called a memory device.

[0103] [Materials Constituting Semiconductor Devices] Next, materials that can be used for the storage device 100 will be described.

[0104] [substrate] The storage device 100 is provided on a base 121. Examples of the substrate that can be used as the base 121 include an insulating substrate, a semiconductor substrate, and a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of the semiconductor substrate include a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of the conductive substrate include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, substrates in which a semiconductor or an insulator is provided on a conductor substrate, etc. Alternatively, a substrate provided with an element on such a substrate may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switching element, a light-emitting element, a memory element, etc.

[0105] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0106] In this specification, etc., "oxynitride" refers to a material that contains more oxygen than nitrogen as a main component. For example, "silicon oxynitride" refers to a material that contains more oxygen than nitrogen and contains silicon, nitrogen, and oxygen. In this specification, etc., "nitride oxide" refers to a material that contains more nitrogen than oxygen as a main component. For example, "aluminum nitride oxide" refers to a material that contains more nitrogen than oxygen and contains aluminum, nitrogen, and oxygen.

[0107] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0108] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0109] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0110] In addition, the electrical characteristics of the OS transistor can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0111] When an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 125 and / or the semiconductor 127, oxygen vacancies in the semiconductor 125 and / or the semiconductor 127 can be compensated for.

[0112] [conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0113] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0114] In the case where an oxide semiconductor, which is a type of metal oxide, is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0115] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in an oxide semiconductor in which a channel is formed. The conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in an oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator or the like may be captured.

[0116] [Oxide semiconductor] A metal oxide (oxide semiconductor) functioning as a semiconductor is preferably used as the semiconductor 125 and the semiconductor 127. An oxide semiconductor that can be used for the semiconductor 125 and the semiconductor 127 will be described below.

[0117] The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable that the oxide semiconductor contains indium and zinc. In addition to these, it is preferable that the oxide semiconductor contains aluminum, gallium, yttrium, tin, etc. Furthermore, the oxide semiconductor may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0118] Here, the case where the oxide semiconductor is an In-M-Zn oxide having indium, an element M, and zinc is considered. The element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc. Other elements applicable to the element M include boron, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. However, there are cases where the element M may be a combination of a plurality of the above elements.

[0119] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0120] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 9A. Fig. 9A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0121] As shown in FIG. 9A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0122] The structure in the bold frame shown in Fig. 9A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0123] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Figure 9B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 9B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 9B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 9B is 500 nm.

[0124] As shown in Figure 9B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 9B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0125] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 9C. Figure 9C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 9C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0126] As shown in FIG. 9C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0127] [Structure of oxide semiconductor] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 9A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0128] Next, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be explained.

[0129] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0130] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0131] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing an element M, zinc (Zn), and oxygen (hereinafter, an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Note that the In layer may contain the element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0132] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0133] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0134] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0135] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0136] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0137] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0138] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0139] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0140] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0141] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0142] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0143] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0144] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0145] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0146] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0147] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0148] [Transistor Having Oxide Semiconductor] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0149] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0150] It is preferable to use an oxide semiconductor having a low carrier concentration for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 100%. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may be referred to as an i-type or substantially i-type.

[0151] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0152] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0153] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0154] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0155] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the vicinity of the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0156] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0157] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm3 To the following:

[0158] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0159] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0160] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 125 and the semiconductor 127 is not limited to the above-mentioned oxide semiconductors. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor 125 and the semiconductor 127. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may be used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0161] In this specification, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0162] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0163] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the semiconductor 125 and the semiconductor 127. Specifically, molybdenum sulfide (representatively, MoS 2 ), molybdenum selenide (represented by MoSe 2 ), molybdenum tellurium (represented by MoTe 2 ), tungsten sulfide (represented by WS 2 ), tungsten selenide (represented by WSe 2 ), tungsten tellurium (represented by WTe 2 ), hafnium sulfide (represented by HfS 2 ), hafnium selenide (represented by HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (represented by ZrSe 2 ) etc.

[0164] <Example of how to make a memory device> Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to Figs. 10A to 31C. In each of Figs. 10A to 31C, A is a top view seen from the Z direction, and B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in A. Also, C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in A. In this manufacturing method, an example is shown in which two memory strings 120 each having two (also called "two stages") memory elements MC are manufactured, but this embodiment is not limited to this. The memory string 120 may have three or more stages of memory elements MC. For example, it is preferable that the memory string 120 has 32 or more stages, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages of memory elements MC.

[0165] First, a conductor 122 is formed on a base 121 having an insulating surface, and an insulator 132 is formed around the conductor 122 (see FIGS. 10A to 10C).

[0166] Specifically, a conductive film is formed and processed by lithography to form the conductor 122. Next, an insulating film is formed on the base 121 so as to cover the conductor 122. Next, a planarization treatment is preferably performed on the insulating film. In the planarization treatment, the insulating film is preferably polished until the surface of the conductor 122 is exposed. The insulator 132 can be formed by the above method. However, the method of forming the conductor 122 and the insulator 132 is not limited to this. The insulator 132 may be formed on the base 121, and unnecessary parts of the insulator 132 may be removed to form grooves or openings, and the conductor 122 may be embedded in the grooves or openings. Such a method of forming a conductor may be called a damascene method (single damascene method, dual damascene method). The above method can obtain the structure shown in FIG. 10A to FIG. 10C.

[0167] The conductor 122 and the insulator 132 can be formed by sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0168] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0169] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0170] The ALD method includes a thermal ALD method in which the reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0171] In addition, the ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time, which has the advantages of enabling extremely thin films to be formed, films to be formed on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. In the PEALD method, the use of plasma allows films to be formed at even lower temperatures, which can be preferable in some cases.

[0172] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0173] In the CVD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment compared to the case of forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0174] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple precursors of different compositions, or by controlling the number of cycles of each precursor.

[0175] In the lithography method, first, the resist is exposed through a photomask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a photomask is not required. To remove the resist mask, a dry etching process such as ashing, a wet etching process, or a process in which the dry etching process and the wet etching process are combined can be used. When a process in which the dry etching process and the wet etching process are combined is used, the wet etching process may be performed after the dry etching process, or the dry etching process may be performed after the wet etching process.

[0176] Instead of the resist mask, a hard mask made of an insulator or a conductor may be used. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape.

[0177] The above processing can be performed by dry etching or wet etching. Dry etching is suitable for fine processing.

[0178] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0179] When a hard mask is used for etching the conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film. On the other hand, if the material of the hard mask does not affect a later process or can be used in a later process, it is not necessarily required to remove the hard mask.

[0180] The conductive film to be the conductor 122 is preferably formed by a sputtering method, and may contain a metal element. Alternatively, the conductive film can be formed by a CVD method.

[0181] If necessary, the surface of the insulator 132 is preferably subjected to planarization processing, which may be performed by chemical mechanical polishing (CMP) or reflow processing.

[0182] The insulator 118 is formed on the conductor 122 and the insulator 132. The insulator 118 can be formed of a material that can be used for the insulator 132 and by a method that can be used for forming the insulator 132.

[0183] A conductor 119 and an insulator 117 are formed on the insulator 118 (see FIGS. 10A to 10C). The conductor 119 and the insulator 117 can be formed of a material that can be used for the conductor 122 and the insulator 132, respectively, by using a method that can be used for forming the conductor 122 and the insulator 132, respectively.

[0184] An insulating film 123A, a conductive film 134A, and a conductive film 136A are alternately stacked over the conductor 119 and the insulator 117. In this embodiment, an example is shown in which the insulating film 123A is formed over the conductor 119 and the insulator 117, the conductive film 134A is formed over the insulating film 123A, the insulating film 123A is formed over the conductive film 134A, and the conductive film 136A is formed over the insulating film 123A (see FIGS. 10A to 10C). The conductive film 134A, the conductive film 136A, and the insulating film 123A can be formed by a CVD method. Alternatively, a sputtering method may be used.

[0185] The conductor 122, the conductor 119, the conductive film 134A, and the conductive film 136A can be made of a conductive material such as silicon doped with impurities or a metal. Since the conductor 136 needs to be selectively etched with respect to the conductor 119 and the conductor 134 in a later step, it is preferable that the conductive film 136A is made of a material different from the conductor 122, the conductor 119, and the conductive film 134A. On the other hand, the conductor 122, the conductor 119, and the conductive film 134A may be made of the same material or different materials. When silicon doped with impurities is used as the conductor 122, the conductor 119, the conductive film 134A, or the conductive film 136A, amorphous silicon or polysilicon can be used. Furthermore, p-type impurities or n-type impurities can be used as impurities to be doped to silicon. As a conductive material containing silicon, a silicide containing titanium, cobalt, or nickel can be used for the conductor 122, the conductive film 134A, or the conductive film 136A. When a metal material is used for the conductor 122, the conductive film 134A, or the conductive film 136A, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used.

[0186] Alternatively, one of the conductive film 134A and the conductive film 136A may be a dummy layer. The dummy layer is preferably made of a material that can be selectively etched with respect to the conductor 122, the insulator 118, the conductor 119, the insulator 123, and the other of the conductive film 134A and the conductive film 136A, and may be, for example, silicon nitride or silicon oxynitride. In a later process, the dummy layer is removed and a conductor is formed in the region where the dummy layer has been removed, thereby forming one of the conductor 134 and the conductor 136.

[0187] An insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used as the insulator 132, the insulator 118, the insulator 117, and the insulating film 123A. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having voids, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, or a nitride having silicon and hafnium can be used.

[0188] Since the conductor 136 needs to be selectively etched with respect to the conductor 137, the conductor 134, the conductor 119, the insulator 138, the insulator 123, and the like in a later step, the conductive film 136A is preferably made of a material that allows selective etching with respect to the conductive film 134A, the conductive film 134A, the insulator 138, and the insulating film 123A. For example, it is preferable that the conductive film 136A is made of a material different from that of the conductive film 134A, and the insulator 138 and the insulating film 123A are made of silicon oxide or silicon oxynitride.

[0189] In addition, in the present embodiment, an example in which six insulating films 123A, three conductive films 134A, and two conductive films 136A are formed is shown, but the number of layers is not limited to this. They can be formed according to the required performance of the semiconductor device. Here, if the number of layers of the conductive films 134A is m (m is an integer of 2 or more), the number of layers of the insulating films 123A is 2×m, and the number of layers of the conductive films 136A is m-1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and even more preferably 257 or more.

[0190] A conductive film 137A is formed on the uppermost insulating film 123A, and an insulating film 138A is formed on the conductive film 137A. The conductive film 137A can be formed of the same material as the conductive film 134A by using the same method as the insulating film 134A. The insulating film 138A can be formed of the same material as the insulating film 123A by using the same method as the insulating film 123A.

[0191] Next, the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form the step-like insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B as shown in Fig. 11B (see Figs. 11A to 11C). In processing the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A, etching of the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A and slimming of a mask are alternately performed, whereby the step-like insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B can be formed.

[0192] Next, the insulator 150 is formed (see FIGS. 11A to 11C). The insulator 150 can be formed by using a CVD method. The insulator 150 is preferably subjected to planarization treatment by using a CMP method or a reflow method.

[0193] Next, grooves are formed by processing the insulator 150, the insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B to obtain the insulator 138, the conductor 137, the insulator 123, the conductor 134, and the conductor 136. (See FIGS. 12A to 12C.)

[0194] Here, when a dummy layer is used for one of the conductive films 134A and 136A, the dummy layer may be removed from the side surface exposed by the above processing, and a conductor may be formed in the region where the dummy layer has been removed. At this time, if a conductor is also formed inside the groove, this conductor is removed. Note that the removal of the dummy layer and the formation of the conductor may be performed in a later process.

[0195] Next, the insulator 152 is formed so as to fill the groove portion (see FIGS. 12A to 12C). The insulator 152 can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a large aspect ratio. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. The insulator 152 is preferably planarized by using a CMP method or a reflow method.

[0196] Next, a conductor 184 and an insulator 185 are formed on the insulator 138, the insulator 150, and the insulator 152 (see FIGS. 13A to 13C). The conductor 184 and the insulator 185 can be formed of a material that can be used for the conductor 122 and the insulator 132, respectively, by using a method that can be used for forming the conductor 122 and the insulator 132.

[0197] Next, an insulator 186 is formed on the conductor 184 and the insulator 185 (see FIGS. 14A to 14C). The insulator 186 can be formed of a material that can be used for the insulator 132, and by a method that can be used for forming the insulator 132.

[0198] Next, a conductor 187 and an insulator 188 are formed on the insulator 186 (see FIGS. 14A to 14C). The conductor 187 and the insulator 188 can be formed of a material that can be used for the conductor 122 and the insulator 132, respectively, by using a method that can be used for forming the conductor 122 and the insulator 132.

[0199] Next, an insulator 189 is formed on the conductor 187 and the insulator 188 (see FIGS. 14A to 14C). The insulator 189 can be formed of a material that can be used for the insulator 132, and by a method that can be used for forming the insulator 132.

[0200] Next, a mask is formed on insulator 189, and insulator 189, conductor 187, insulator 186, conductor 184, insulator 138, conductor 137, insulator 123, conductor 134, and conductor 136 are processed using lithography to form a first opening to expose conductor 119 (see Figures 15A to 15C).

[0201] Here, when a dummy layer is used for either the conductor 134 or the conductor 136, the dummy layer may be removed from the side surface exposed by the above processing, and a conductor may be formed in the region from which the dummy layer has been removed. At this time, if a conductor is also formed inside the first opening, this conductor is removed.

[0202] Next, isotropic etching is performed on the conductor 136 to expand the diameter of the opening of the conductor 136 (see FIGS. 16A to 16C). By this process, the diameter of the opening of the conductor 136 becomes larger than the diameters of the openings of the insulator 138, the conductor 137, the insulator 123, and the conductor 134. It can also be said that the conductor 136 has a recess on the side of the insulator 138, the conductor 137, the insulator 123, or the conductor 134 located above or below. For such processing, isotropic etching by dry etching using gas, radicals, plasma, or the like, or isotropic etching by wet etching using a liquid can be used. The liquid used for wet etching is sometimes called an etchant. When isotropic etching is performed using dry etching, gas, radicals, plasma, or the like containing at least one of chlorine, bromine, and fluorine can be used. It is preferable to perform isotropic etching without removing the mask used for forming the first opening. The first opening obtained by the above process corresponds to the opening 141 shown in FIG.

[0203] Next, the insulating film 124A is formed on the insulator 189 and inside the first opening (see FIGS. 17A to 17C). Although not shown, the insulating film 124A may have a laminated structure. The insulating film 124A can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. In particular, the PEALD method may be preferable because it uses plasma and allows film formation at a lower temperature. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. When the insulating film 124A has a laminated structure, each insulating film may be formed by the same film formation apparatus or different film formation apparatuses.

[0204] The insulating film 124A formed by the above method has good coverage, and can be formed even in the recessed portion of the conductor 136. That is, the insulating film 124A can be formed so as to contact not only the side surfaces of the insulator 123, the conductor 134, and the conductor 136, but also part of the upper surface and part of the lower surface of the insulator 123.

[0205] Next, the insulating film 124A formed on the bottom of the first opening is removed to obtain the insulator 124B. It is preferable to use anisotropic etching to remove the insulating film 124A. At this time, the insulating film 124A on the insulator 189 is also removed, so that the insulator 124B is provided only on the sidewall of the first opening (see FIGS. 18A to 18C). By removing the insulating film 124A on the bottom of the first opening, the conductor 119 is exposed again.

[0206] Next, in the XY plane shown in Fig. 18A to Fig. 18C, the conductor 184 and the insulator 124B overlapping with the conductor 187 are removed. To remove the insulator 124B, a material 180 (also called a sacrificial layer) that can be easily removed in a later process is first formed so as to be embedded inside the first opening, and is then removed by etching or the like to a desired depth inside the first opening (see Fig. 19A to Fig. 19C). Next, the material 180 is used as a mask to remove the insulator 124B exposed by the etching, thereby obtaining the insulator 124 (see Fig. 20A to Fig. 20C). After removing the insulator 124B, the material 180 is removed.

[0207] Next, a semiconductor film 125A and a conductive film 128A are formed over the insulator 189 and inside the first opening (see FIGS. 21A to 21C). The semiconductor film 125A is preferably provided so as to be in contact with at least the conductor 119, the insulator 124, and the conductor 184 inside the first opening.

[0208] The semiconductor film 125A can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because a film of uniform thickness can be formed even in a groove or an opening with a large aspect ratio. In particular, the PEALD method may be preferable because a film can be formed at a lower temperature by using plasma. Alternatively, the semiconductor film 125A may be formed by combining the ALD method and the CVD method. The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 125A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 125A is oriented in the normal direction of the surface to be formed inside the first opening. At this time, the c-axis of the semiconductor film 125A located on the side of the insulator 138, the conductor 137, the insulator 123, the conductor 134, and the conductor 136 through the insulator 124 is oriented from the surface to be formed toward the axis 178 shown in FIG. 21B and FIG. 21C. The axis 178 can be called the central axis of the first opening. As a result, the c-axis of the semiconductor 125 located above is oriented toward the axis 178 from the surface on which it is formed.

[0209] Here, when a metal oxide is formed as the semiconductor film 125A by an ALD method, it is preferable to form an In-Ga-Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

[0210] Examples of precursors that can be used include indium-containing triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, and indium(III) chloride. Examples of precursors that can be used include gallium-containing trimethylgallium, triethylgallium, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride. Examples of precursors that can be used include zinc-containing dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0211] The conductive film 128A is only required to be formed so as to fill the recess of the conductor 136 through at least the insulator 124 and the semiconductor film 125A, and does not necessarily have to fill the entire inside of the first opening. The conductive film 128A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because a film of uniform thickness can be formed even in a groove or an opening with a large aspect ratio. In particular, the PEALD method may be preferable because it uses plasma and allows film formation at a lower temperature. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0212] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 22A to 22C). The conductive film 128A can be processed by isotropic etching or anisotropic etching. In forming the conductive film 128A, if the conductive film 128A fills the recess and the first opening is not completely filled as shown in FIGS. 21A to 21C, it is preferable to use isotropic etching to process the conductive film 128A. On the other hand, if the conductive film 128A is formed so as to fill the recess and the first opening, it is preferable to use anisotropic etching. By the above processing, the conductor 128 can be formed inside the recess.

[0213] Next, a material 181 is formed inside the first opening (see FIGS. 22A to 22C). The material 181 is used as a sacrificial layer for protecting the semiconductor film 125A in processing the semiconductor film 125A, the conductor 119, the insulator 118, and the like. The material 181 is preferably formed of an insulating material, but one embodiment of this embodiment is not limited thereto. The material 181 may be a conductive material. The material 181 is a material that can be used for the insulating film 124A, and can be formed by a method that can be used for forming the insulating film 124A.

[0214] Next, it is preferable to form a high-resistance region (I-type region) by increasing the resistance of a part of the semiconductor film 125A using the conductor 128 as a mask. The high-resistance region may be formed by irradiating the semiconductor film 125A with microwaves to remove hydrogen contained in the semiconductor film 125A. Moreover, it is preferable to perform the microwave irradiation in an atmosphere containing oxygen because oxygen is supplied to the semiconductor film 125A. In this embodiment, a part of the semiconductor film 125A is irradiated with microwaves in an atmosphere containing oxygen and argon to increase the resistance of a first region of the semiconductor film 125A that is not covered with the conductor 128.

[0215] Here, a heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at a temperature of 200° C. to 500° C., preferably 300° C. to 400° C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0216] The heat treatment can reduce the resistance of a second region of the semiconductor film 125A in contact with the conductor 128, thereby forming a low-resistance region (n-type region). When the heat treatment is performed while the semiconductor film 125A and the conductor 128 are in contact with each other, a metal compound layer containing a metal element contained in the conductor 128 and a component of the semiconductor film 125A may be formed at the interface between the conductor 128 and the semiconductor film 125A. The formation of the metal compound layer is preferable because it reduces the resistance of the semiconductor film 125A in the region in contact with the conductor 128. Furthermore, the conductor 128 may absorb oxygen contained in the semiconductor film 125A. When the heat treatment is performed while the semiconductor film 125A and the conductor 128 are in contact with each other, the resistance of the semiconductor film 125A becomes lower. The heat treatment may be performed before the microwave treatment. The second region, which has been made to have a low resistance by the heat treatment, is covered with the conductor 128 and is therefore not affected by the microwaves, and can maintain a low resistance value even after the microwave treatment.

[0217] The carrier concentration of the first region after the microwave treatment and the heat treatment is 1×10 18 / cm 3 Less than 1 x 10 17 / cm 3 Less than or equal to 1×10 16 / cm 3 The carrier concentration of the second region is preferably 1×10 18 / cm 3 More than 1×10 19 / cm 3 More preferably, 1×10 20 / cm 3 More preferably, it is equal to or greater than this.

[0218] Note that the step of performing the high resistance treatment on the semiconductor film 125A is not limited to being performed after the formation of the material 181. The high resistance treatment may be performed before the formation of the material 181. Moreover, the high resistance treatment may be performed before the formation of the insulating film 126A described later, or may be performed after the formation of the insulating film 126A.

[0219] Next, the material 181, the semiconductor film 125A, the conductor 119, and the insulator 118 formed on the bottom of the first opening are removed to obtain a semiconductor 125B. The semiconductor film 125A, the material 181, the conductor 119, and the insulator 118 are preferably removed by anisotropic etching. At this time, the semiconductor film 125A and the material 181 on the insulator 189 are also removed, so that the semiconductor 125B is provided only on the sidewall of the first opening (see FIGS. 23A to 23C). The semiconductor film 125A, the material 181, the conductor 119, and the insulator 118 on the bottom of the first opening are removed to expose the conductor 122.

[0220] Next, in the XY plane shown in Figures 24A to 24C, material 181 overlapping with conductor 187 and semiconductor 125B are removed. To remove semiconductor 125B, first, material 182 (also called a sacrificial layer) that can be easily removed in a later process is formed so as to be embedded inside the first opening, and is removed by etching or the like to a desired depth inside the first opening (see Figures 24A to 24C). Next, material 182 is used as a mask to remove material 181 and semiconductor 125B exposed by the etching, thereby obtaining semiconductor 125 (see Figures 24A to 24C). After removing semiconductor 125B, material 182 and material 181 are removed.

[0221] Next, the insulating film 126A is formed on the insulator 189 and inside the first opening (see FIGS. 25A to 25C). Although not shown, the insulating film 126A may have a laminated structure. The insulating film 126A can be formed by using a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. In particular, the PEALD method may be preferable because it uses plasma and allows film formation at a lower temperature. Alternatively, the insulating film 126A may be formed by combining the ALD method and the CVD method. When the insulating film 126A has a laminated structure, each insulating film may be formed by the same film formation apparatus or different film formation apparatuses.

[0222] Next, the insulating film 126A formed on the bottom of the first opening is removed to obtain the insulator 126B. It is preferable to use anisotropic etching to remove the insulating film 126A. At this time, the insulating film 126A on the insulator 189 is also removed, so that the insulator 126B is provided only on the sidewall of the first opening (see FIGS. 26A to 26C). By removing the insulating film 126A on the bottom of the first opening, the conductor 122 is exposed again.

[0223] Next, in the XY plane shown in Figures 27A to 27C, the insulator 126B overlapping with the conductor 187 is removed. To remove the insulator 126B, first, a material 183 (also called a sacrificial layer) that can be easily removed in a later process is formed so as to be embedded inside the first opening, and then removed by etching or the like to a desired depth inside the first opening (see Figures 27A to 27C). Next, the material 183 is used as a mask to remove the insulator 126B exposed by the etching, thereby obtaining the insulator 126 (see Figures 27A to 27C). After removing the insulator 126B, the material 183 is removed.

[0224] Next, the semiconductor film 127A is formed in the first opening so as to be in contact with the conductor 122 (see FIGS. 28A to 28C). The semiconductor film 127A can be formed by a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. In particular, the PEALD method may be preferable because a film can be formed at a lower temperature by using plasma. Alternatively, the semiconductor film 127A may be formed by combining the ALD method and the CVD method. In this case, the semiconductor film 127A is preferably formed so as to be in contact with the conductor 187. In addition, the semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 127A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 127A is oriented in the normal direction to the surface on which it is formed in the first opening. At this time, the c-axis of the semiconductor film 127A located on the side surface of the first opening is oriented from the formation surface toward the axis 178 shown in Figures 28B and 28C. As a result, the c-axis of the semiconductor 127 located above is oriented from the formation surface toward the axis 178.

[0225] Here, when a metal oxide is formed as the semiconductor film 127A by an ALD method, it is preferable to form an In-Ga-Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

[0226] Examples of precursors that can be used include indium-containing triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, and indium(III) chloride. Examples of precursors that can be used include gallium-containing trimethylgallium, triethylgallium, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride. Examples of precursors that can be used include zinc-containing dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0227] Next, the semiconductor film 127A formed on the insulator 189 is removed. To remove the semiconductor film 127A, first, a material 179 (also called a sacrificial layer) that can be easily removed in a later process is formed so as to be embedded inside the semiconductor film 127A inside the first opening. Next, the semiconductor film 127A is removed using the material 179 as a mask to obtain the semiconductor 127 (see FIGS. 29A to 29C). To remove the semiconductor film 127A, etching, a CMP method, or the like can be used. When removing the semiconductor film 127A by etching, dry etching or wet etching may be used. After removing the semiconductor film 127A, the material 179 is removed.

[0228] Next, the insulator 129 is formed on the insulator 189 and inside the semiconductor 127, and the conductor 130 is formed inside the insulator 129 (see FIGS. 30A to 30C). The insulator 129 and the conductor 130 can be formed by a CVD method or an ALD method. By using the CVD method or the ALD method, a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio, which is preferable. Alternatively, the insulator 129 and the conductor 130 may be formed by combining the ALD method and the CVD method. Also, different film formation methods and film formation apparatuses may be used for each film to be formed. For example, the insulator 129 is made of a material that can be used for the insulating film 124A, and a method that can be used for forming the insulating film 124A can be used. Also, the conductor 130 is made of a material that can be used for the conductive film 128A, and a method that can be used for forming the conductive film 128A can be used.

[0229] Here, the semiconductor 127 may be subjected to high resistance treatment similar to that performed on the semiconductor film 125A. When the semiconductor 127 is subjected to high resistance treatment, the high resistance treatment is preferably performed before the formation of the conductor 130 or before the formation of the insulator 129. When the semiconductor film 127A is subjected to high resistance treatment, the first region of the semiconductor 125 can also be made high-resistance, so the previous high resistance treatment may be omitted.

[0230] Next, a heat treatment is performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at 200° C. to 500° C., preferably 300° C. to 400° C. The atmosphere in which the heat treatment is performed is not limited to the above, and may be an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0231] The conductor 130 can be obtained by forming a conductive film on and inside the insulator 129 and removing the conductive film by a CMP method or the like until the surface of the insulator 129 is exposed (see FIGS. 30A to 30C). Note that the above-mentioned heat treatment may be performed after the conductor 130 is formed.

[0232] Next, the insulator 156 is formed over the conductor 130 and the insulator 129 (see FIGS. 31A to 31C). The insulator 156 can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0233] Next, the insulators 156, 129, 189, 188, 186, 185, 138, 150, and 123 are processed by lithography to form second openings so as to expose the conductors 134, 136, 130, and 137. The second openings are formed for the conductors 134 and 136, which are formed in a stepped shape (see FIGS. 31A to 31C). Although not shown, openings exposing the conductors 184 and 187 and openings exposing the conductors 119 and 122 may be formed in the above process.

[0234] Next, a conductor 161 electrically connected to the conductor 134, a conductor 162 electrically connected to the conductor 136, a conductor 163 electrically connected to the conductor 130, and a conductor 164 electrically connected to the conductor 137 are formed so as to be embedded in the second opening (see FIGS. 31A to 31C). The conductors 161, 162, 163, and 164 can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a large aspect ratio. Alternatively, the conductors may be formed by combining the ALD method and the CVD method. The conductors 161, 162, 163, and 164 may have a laminated structure consisting of a plurality of layers. The conductor 161, the conductor 162, the conductor 163, and the conductor 164 can be formed by forming a conductive film on the insulator 156 and inside the second opening, and removing unnecessary conductive film by a CMP method or the like. Although not shown, conductors electrically connected to the conductor 184, the conductor 187, the conductor 119, and the conductor 122, respectively, may be formed in the above process.

[0235] Next, conductor 171 electrically connected to conductor 161, conductor 172 electrically connected to conductor 162, conductor 173 electrically connected to conductor 163, and conductor 174 electrically connected to conductor 164 are formed (see Figures 31A to 31C). Conductors 171, 172, 173, and conductor 174 can be formed by forming a conductive film on insulator 156 and processing it using a lithography method. This processing can be performed using a dry etching method or a wet etching method. Processing using the dry etching method is suitable for fine processing.

[0236] Conductor 171, conductor 161, and conductor 134 can function as conductor SG or conductor WWL. Conductor 172, conductor 162, and conductor 136 can function as conductor RWL. Conductor 173, conductor 163, and conductor 130 can function as conductor BG. Conductor 174, conductor 164, and conductor 137 can function as conductor SEL. Conductor 184 can function as conductor WBL. Conductor 187 can function as conductor RBL. Through the above steps, it is possible to manufacture a transistor STr1 having the semiconductor 125 functioning as a channel formation region and the conductor 134 functioning as a gate, a transistor STr2 having the semiconductor 127 functioning as a channel formation region and the conductor 137 functioning as a gate, a transistor STr3 having the semiconductor 125 functioning as a channel formation region and the conductor 137 functioning as a gate, a transistor WTr having the semiconductor 125 functioning as a channel formation region and the conductor 134 functioning as a gate, and a transistor RTr having the semiconductor 127 functioning as a channel formation region, the conductor 136 functioning as a gate, the conductor 130 functioning as a back gate, and the conductor 128 between the semiconductor 127 and the conductor 136. In addition, a memory device including the transistor STr1, the transistor STr2, the transistor STr3, the transistor WTr, and the transistor RTr can be manufactured.

[0237] <Example of film formation equipment configuration> Here, as an example of an apparatus capable of forming a film by the ALD method, the configuration of a film formation apparatus 4000 will be described with reference to Fig. 32A and Fig. 32B. Fig. 32A is a schematic diagram of a multi-chamber type film formation apparatus 4000, and Fig. 32B is a cross-sectional view of an ALD apparatus that can be used for the film formation apparatus 4000.

[0238] The film forming apparatus 4000 includes a loading / unloading chamber 4002, a loading / unloading chamber 4004, a transfer chamber 4006, a film forming chamber 4008, a film forming chamber 4009, a film forming chamber 4010, and a transfer arm 4014. Here, the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film forming chambers 4008 to 4010 are independently connected to the transfer chamber 4006. This allows continuous film formation in the film forming chambers 4008 to 4010 without exposure to the atmosphere, and prevents impurities from being mixed into the film. In addition, contamination of the interface between the substrate and the film and the interface between each film is reduced, and clean interfaces are obtained.

[0239] In addition, in order to prevent moisture from adhering to the loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, and the film forming chambers 4008 to 4010, it is preferable to fill them with an inert gas (such as nitrogen gas) with a controlled dew point, and it is desirable to maintain a reduced pressure.

[0240] In addition, an ALD apparatus can be used in the film deposition chambers 4008 to 4010. Further, a configuration may be adopted in which a film deposition apparatus other than the ALD apparatus is used in any one of the film deposition chambers 4008 to 4010. Examples of the film deposition apparatus that can be used in the film deposition chambers 4008 to 4010 include a sputtering apparatus, a plasma CVD (PECVD: Plasma Enhanced CVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, a photo CVD apparatus, a metal CVD (MCVD: Metal CVD) apparatus, a metal organic CVD (MOCVD: Metal Organic CVD) apparatus, and the like. Further, a device having a function other than the film deposition apparatus may be provided in any one or more of the film deposition chambers 4008 to 4010. Examples of such a device include a heating device (typically, a vacuum heating device), a plasma generation device (typically, a microwave plasma generation device), and the like.

[0241] For example, when the film deposition chamber 4008 is an ALD apparatus, the film deposition chamber 4009 is a PECVD apparatus, and the film deposition chamber 4010 is a metal CVD apparatus, a metal oxide can be formed in the film deposition chamber 4008, an insulating film that functions as a gate insulating film can be formed in the film deposition chamber 4009, and a conductive film that functions as a gate electrode can be formed in the film deposition chamber 4010. At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be continuously formed without exposing them to the atmosphere.

[0242] In addition, although the film deposition apparatus 4000 is configured to include the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film deposition chambers 4008 to 4010, the present invention is not limited thereto. The film deposition apparatus 4000 may be configured to have four or more film deposition chambers. Further, the film deposition apparatus 4000 may be a single-wafer type or a batch type in which a plurality of substrates are deposited simultaneously.

[0243] <ALD apparatus> Next, the configuration of the ALD apparatus that can be used in the film forming apparatus 4000 will be described with reference to FIG. 32B. The ALD apparatus includes a film forming chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a and 4021b), a raw material supply unit 4031, high-speed valves 4022 (high-speed valves 4022a and 4022b) which are introduction amount controllers, raw material inlets 4023 (raw material inlets 4023a and 4023b), a raw material inlet 4033, a raw material outlet 4024, and an exhaust device 4025. The raw material inlets 4023a, 4023b, and 4033 installed in the chamber 4020 are respectively connected to the raw material supply units 4021a, 4021b, and 4031 via supply pipes and valves, and the raw material outlet 4024 is connected to the exhaust device 4025 via a discharge pipe, a valve, and a pressure regulator.

[0244] Also, as shown in FIG. 32B, by connecting a plasma generator 4028 to the chamber 4020, in addition to the thermal ALD method, film formation can be performed by the plasma ALD method. The plasma generator 4028 is preferably an ICP type plasma generator using a coil 4029 connected to a high-frequency power source. The high-frequency power source can output power having a frequency of 10 kHz or more and 100 MHz or less, preferably 1 MHz or more and 60 MHz or less, more preferably 10 MHz or more and 60 MHz or less. For example, it can output power having frequencies of 13.56 MHz and 60 MHz. In the plasma ALD method, film formation can be performed without reducing the film formation rate even at low temperatures, so it is preferably used in a single-wafer film forming apparatus with low film formation efficiency.

[0245] Inside the chamber, there is a substrate holder 4026, and a substrate 4030 is placed on the substrate holder 4026. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4026 may be floating or grounded. Further, a heater 4027 is provided on the outer wall of the chamber, and the temperature of the inside of the chamber 4020, the substrate holder 4026, and the surface of the substrate 4030 can be controlled. It is preferable that the heater 4027 can control the temperature of the surface of the substrate 4030 to be 100°C or higher and 500°C or lower, preferably 200°C or higher and 400°C or lower, and it is preferable that the temperature of the heater 4027 itself can be set to 100°C or higher and 500°C or lower.

[0246] In the raw material supply units 4021a, 4021b, and 4031, a raw material gas is formed from solid or liquid raw materials by a vaporizer, heating means, etc. Alternatively, the raw material supply units 4021a, 4021b, and 4031 may be configured to supply a gaseous raw material gas.

[0247] Also, in FIG. 32B, an example is shown in which two raw material supply units 4021 and one raw material supply unit 4031 are provided, but the present embodiment is not limited to this. One or three or more raw material supply units 4021 may be provided. Also, two or more raw material supply units 4031 may be provided. Further, the high-speed valves 4022a and 4022b can be precisely controlled by time, and are configured to control the supply of the raw material gas supplied from the raw material supply unit 4021a and the raw material gas supplied from the raw material supply unit 4021b.

[0248] In the film forming apparatus shown in FIG. 32B, the substrate 4030 is loaded onto the substrate holder 4026, the chamber 4020 is sealed, and then the substrate 4030 is heated to a desired temperature (for example, 100° C. to 500° C., preferably 200° C. to 400° C.) by the heater 4027. A thin film is formed on the substrate surface by repeating the supply of a source gas from the source supply unit 4021a, exhaust by the exhaust device 4025, supply of a source gas from the source supply unit 4031, and exhaust by the exhaust device 4025. In addition, in the formation of the thin film, the supply of a source gas from the source supply unit 4021b and exhaust by the exhaust device 4025 may be further performed. The temperature of the heater 4027 may be appropriately determined depending on the type of film to be formed, the source gas, the desired film quality, and the heat resistance of the substrate and the films and elements provided thereon. For example, the temperature of the heater 4027 may be set to 200° C. or higher and 300° C. or lower during film formation, or may be set to 300° C. or higher and 500° C. or lower during film formation.

[0249] By forming a film while heating the substrate 4030 using the heater 4027, it is possible to omit a heat treatment of the substrate 4030 that is required in a later step. That is, by using the chamber 4020 or the film formation apparatus 4000 provided with the heater 4027, the formation of a film on the substrate 4030 and the heat treatment of the substrate 4030 can be performed at the same time.

[0250] In the film forming apparatus shown in FIG. 32B, a metal oxide can be formed by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply unit 4021 and the raw material supply unit 4031. When forming an In-Ga-Zn oxide containing indium, gallium, and zinc as a metal oxide, it is preferable to use a film forming apparatus provided with at least three raw material supply units 4021 and at least one raw material supply unit 4031. It is preferable that a precursor containing indium is supplied from the first raw material supply unit 4021, a precursor containing gallium is supplied from the second raw material supply unit 4021, and a precursor containing zinc is supplied from the third raw material supply unit 4021. When a precursor containing gallium and zinc is used to form a metal oxide, at least two raw material supply units 4021 may be provided. The precursors described above can be used as the precursor containing indium, the precursor containing gallium, and the precursor containing zinc.

[0251] In addition, a reactant is supplied from the raw material supply unit 4031. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

[0252] In addition, by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is possible to form an insulating layer containing an oxide (including a composite oxide) containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, etc. Specifically, it is possible to form an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate. In addition, by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is also possible to form thin films such as metal layers such as a tungsten layer and a titanium layer, and nitride layers such as a titanium nitride layer.

[0253] For example, when forming a hafnium oxide layer using an ALD apparatus, a first source gas is prepared by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAHf)) and ozone (O 3 ) and oxygen (O 2 In this case, the first raw material gas supplied from the raw material supply unit 4021a is TDMAHf, and the second raw material gas supplied from the raw material supply unit 4031 is ozone and oxygen. The chemical formula of tetrakisdimethylamidohafnium is Hf[N(CH 3 ) 2 ] 4 Another example of the material liquid is tetrakis(ethylmethylamido)hafnium. Water can be used as the second source gas.

[0254] When forming an aluminum oxide layer using an ALD apparatus, a first source gas is prepared by vaporizing a liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) and ozone (O 3 ) and oxygen (O 2 In this case, the first source gas supplied from the source supply unit 4021a is TMA, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of trimethylaluminum is Al(CH 3 ) 3 Other examples of the material liquid include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). Water can be used as the second source gas.

[0255] 33A to 33C, a description will be given of different configurations of an ALD apparatus that can be used for the film formation apparatus 4000. Note that detailed description of the same configurations and functions as those of the ALD apparatus shown in FIG. 32B may be omitted.

[0256] FIG. 33A is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4100 is provided with a reaction chamber 4120 and a plasma generation chamber 4111 above the reaction chamber 4120. The reaction chamber 4120 can be called a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively called a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 has a raw material inlet 4133. In addition, a plasma generation device 4128 can apply high frequency such as RF or microwaves to a gas introduced into the plasma generation chamber 4111 to generate plasma 4131 in the plasma generation chamber 4111. When the plasma 4131 is generated using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Such plasma generated using microwaves may be called ECR (Electron Cyclotron Resonance) plasma. The reaction chamber 4120 has a substrate holder 4126 on which a substrate 4130 is placed. The source gas introduced from the source inlet 4123 is decomposed by heat from a heater provided in the reaction chamber 4120 and deposited on the substrate 4130. The source gas introduced from the source inlet 4133 is turned into a plasma state by the plasma generating device 4128. The source gas in the plasma state recombines with electrons and other molecules before reaching the surface of the substrate 4130, and reaches the substrate 4130 in a radical state. An ALD device that uses radicals to form a film in this way may be called a radical ALD (radical-enhanced ALD) device. In addition, the plasma ALD device 4100 shows a configuration in which the plasma generation chamber 4111 is provided at the top of the reaction chamber 4120, but this embodiment is not limited to this. The plasma generation chamber 4111 may be provided adjacent to the side of the reaction chamber 4120.

[0257] FIG. 33B is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4200 has a chamber 4220. The chamber 4220 has an electrode 4213, a raw material outlet 4224, and a substrate holder 4226, and a substrate 4230 is placed thereon. The electrode 4213 has a raw material inlet 4223 and a shower head 4214 that supplies the introduced raw material gas into the chamber 4220. A power source 4215 that can apply high frequency power is connected to the electrode 4213 via a capacitor 4217. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or high frequency power. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode for generating a plasma 4231, respectively. The raw material gas introduced from the raw material inlet 4223 is decomposed by heat from a heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the raw material gas introduced from the raw material inlet 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226. The raw material gas in the plasma state is incident on the substrate 4230 due to a potential difference (also called an ion sheath) generated between the plasma 4231 and the substrate 4230.

[0258] FIG. 33C is a schematic diagram showing an embodiment of a plasma ALD apparatus different from that shown in FIG. 33B. The plasma ALD apparatus 4300 has a chamber 4320. The chamber 4320 has an electrode 4313, a raw material outlet 4324, and a substrate holder 4326, and a substrate 4330 is placed thereon. The electrode 4313 has a raw material inlet 4323 and a shower head 4314 that supplies the introduced raw material gas into the chamber 4320. A power source 4315 that can apply high frequency power is connected to the electrode 4313 via a capacitor 4317. The substrate holder 4326 may be provided with a mechanism for applying a constant potential or high frequency power. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode for generating a plasma 4331, respectively. The plasma ALD apparatus 4300 is different from the plasma ALD apparatus 4200 in that it has a mesh 4319 connected to a power source 4321 capable of applying high frequency through a capacitor 4322 between the electrode 4313 and the substrate holder 4326. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The source gas introduced from the source inlet 4323 is decomposed by heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the source gas introduced from the source inlet 4323 becomes a plasma state between the electrode 4313 and the substrate holder 4326. The charge of the source gas in the plasma state is removed by the mesh 4319, and the source gas reaches the substrate 4130 in an electrically neutral state such as radicals. This allows film formation to be performed with reduced incidence of ions and damage caused by plasma.

[0259] By forming the semiconductor 125 or the semiconductor 127 using the ALD method, it may be possible to form a metal oxide having a CAAC structure in which the c-axis is oriented approximately parallel to the normal direction of the deposition surface.

[0260] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0261] (Embodiment 2) In this embodiment, a circuit configuration and operation of a memory string 120, which is a memory device, will be described. Fig. 34 shows an example of a circuit configuration of the memory string 120. Fig. 35 shows an equivalent circuit diagram of a memory element MC.

[0262] In addition, in drawings and the like, in order to make the potential of a wiring, electrode, conductor, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be added next to the wiring, electrode, conductor, etc. Furthermore, a wiring, electrode, conductor, etc. in which a potential change has occurred may be labeled with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor.

[0263] <Memory string circuit configuration example> FIG. 34 shows an example of a circuit configuration of a memory string 120 including five memory elements MC. The memory elements MC include a transistor WTr and a transistor RTr. In FIG. 34, the transistor WTr included in the memory element MC[1] is shown as a transistor WTr[1], and the transistor RTr included in the memory element MC[1] is shown as a transistor RTr[1]. Thus, the memory string 120 shown in FIG. 34 includes transistors WTr[1] to WTr[5] and transistors RTr[1] to RTr[5]. The memory string 120 shown in FIG. 34 also includes transistors STr1, STr2, and STr3. The memory string 120 is a NAND type memory device.

[0264] In an equivalent circuit diagram, "OS" may be added to the circuit symbol of a transistor to indicate that the transistor is an OS transistor. Similarly, "Si" may be added to the circuit symbol of a transistor to indicate that the transistor is a Si transistor (a transistor that uses silicon in the semiconductor layer in which the channel is formed). In FIG. 34, the transistors WTr and RTr are shown to be OS transistors.

[0265] A NAND type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device that has multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0266] The transistor WTr is a normally-off transistor. The transistor RTr is a normally-on transistor. As described in the above embodiment, the transistor RTr includes a conductor 128 between the gate and the semiconductor layer. The conductor 128 can function as a floating gate of the transistor RTr. For example, the conductor 128 included in the transistor RTr[1] is called the conductor 128[1].

[0267] A node where the conductor 128 and one of the source and drain of the transistor WTr are electrically connected is referred to as a node ND. For example, a node where the conductor 128[1] and one of the source and drain of the transistor WTr[1] are electrically connected is referred to as a node ND[1].

[0268] One of the source or drain of the transistor RTr[1] is electrically connected to the conductor RSL, and the other is electrically connected to one of the source or drain of the transistor RTr[2]. The gate of the transistor RTr[1] is electrically connected to the conductor RWL[1]. The back gate of the transistor RTr[1] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[1] is electrically connected to the conductor 128[1], and the other is electrically connected to the conductor 128[2]. The gate of the transistor WTr[1] is electrically connected to the conductor WWL[1]. In addition, one of the source or drain of the transistor STr1 is electrically connected to the conductor WSL, the other is electrically connected to the conductor 128[1], and the gate is electrically connected to the conductor SG.

[0269] 35, the transistor RTr can be expressed by replacing it with a capacitance Cs and a transistor Tr. The gate of the transistor Tr is electrically connected to the conductor RWL via the capacitance Cs.

[0270] In addition, one of the source or drain of the transistor RTr[5] is electrically connected to the other of the source or drain of the transistor RTr[4], and the other is electrically connected to one of the source or drain of the transistor STr2. The gate of the transistor RTr[5] is electrically connected to the conductor RWL[5]. The back gate of the transistor RTr[5] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[5] is electrically connected to the conductor 128[5], and the other is electrically connected to one of the source or drain of the transistor STr3. The gate of the transistor WTr[5] is electrically connected to the conductor WWL[5]. In addition, the other of the source or drain of the transistor STr2 is electrically connected to the conductor RBL, and the gate is electrically connected to the conductor SEL. In addition, the other of the source or drain of the transistor STr3 is electrically connected to the conductor WBL, and the gate is electrically connected to the conductor SEL.

[0271] When the memory string 120 includes n (n is an integer of 1 or more) memory elements MC, in the i-th (i is an integer of 2 to n-1) memory element MC[i] excluding the first and n-th memory elements MC, one of the source or drain of the transistor RTr[i] is electrically connected to the other of the source or drain of the transistor RTr[i-1], and the other is electrically connected to one of the source or drain of the transistor RTr[i+1]. The gate of the transistor RTr[i] is electrically connected to the conductor RWL[i]. The back gate of the transistor RTr[i] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[i] is electrically connected to the conductor 128[i], and the other is electrically connected to the conductor 128[i+1]. The gate of the transistor WTr[i] is electrically connected to the conductor WWL[i]. Note that for the connection relationships between the first and n-th memory elements MC and other elements and conductors, reference can be made to the connection relationships described for the memory element MC[1] and the memory element MC[5] above.

[0272] The transistors STr1, STr2, and STr3 may be, for example, OS transistors or Si transistors. At least one of the transistors STr1, STr2, and STr3 may be an OS transistor, and the others may be Si transistors. When both the transistors WTr and RTr are formed of OS transistors, it is preferable that the transistors STr1, STr2, and STr3 are also formed of OS transistors. By using the same semiconductor material for the transistors, the productivity of the semiconductor device can be improved.

[0273] Alternatively, an OS transistor may be used as the transistor WTr, and a Si transistor may be used as the transistor RTr. An equivalent circuit diagram of the memory string 120 in the case where an OS transistor is used as the transistor WTr, and a Si transistor is used as the transistor RTr is shown in FIG.

[0274] When the transistor RTr is a Si transistor, polycrystalline silicon, for example, may be used for the semiconductor 125. When the transistor WTr is an OS transistor, CAAC-IGZO, for example, may be used for the semiconductor 127. In this case, it is preferable to use OS transistors for the transistors STr1 and STr3, and a Si transistor for the transistor STr2.

[0275] As shown in Fig. 37, depending on the purpose or application, a Si transistor may be used as the transistor WTr, and an OS transistor may be used as the transistor RTr. In this case, it is preferable to use Si transistors for the transistors STr1 and STr3, and an OS transistor for the transistor STr2. Also, as shown in Fig. 38, depending on the purpose or application, a Si transistor may be used for both the transistor WTr and the transistor RTr. When using Si transistors for both the transistor WTr and the transistor RTr, it is preferable to use Si transistors for the transistors STr1, STr2, and STr3 as well.

[0276] <Memory string operation example> Next, an example of the operation of the memory string 120 shown in FIG. 34 will be described.

[0277] [Write operation] An operation example in which an H potential or an L potential is written to a memory element MC will be described. Fig. 39 is a timing chart illustrating the write operation. Fig. 40A to Fig. 41B are circuit diagrams illustrating the write operation.

[0278] In an initial state, an L potential is written to the memory elements MC[1] to MC[5]. In addition, an L potential is supplied to the conductors WWL[1] to WWL[5], the conductors RWL[1] to RWL[5], the conductor SEL, the conductor BG, the conductor WBL, the conductor RBL, the conductor SG, the conductor WSL, and the conductor RSL. Note that the conductor BG can control the threshold voltage of the transistor RTr. The potential supplied to the conductor BG may be appropriately adjusted so that the transistor RTr becomes a desired normally-on type transistor. Note that the conductor SEL is described as being a common conductor as the gates of the transistors STr2 and STr3, but may be a different conductor.

[0279] [Period T1] In a period T1, while keeping the conductor WWL[3] at an L potential, an H potential is supplied to the conductor WWL[1], the conductor WWL[2], the conductor WWL[4], the conductor WWL[5], the conductor SG, and the conductor SEL (see FIG. 40A). In addition, an arbitrary potential of an H potential or an L potential is supplied to the conductor WSL and the conductor WBL, respectively. Then, the potential of the conductor WSL is supplied to the nodes ND[1] to ND[3], and the potential of the conductor WBL is supplied to the nodes ND[4] and ND[5].

[0280] [Period T2] In period T2, an L potential is supplied to the conductors WWL[2] and WWL[4] (see FIG. 40B). Then, the transistors WTr[2] and WTr[4] are turned off, and the charges written to the nodes ND[3] and ND[4] are held.

[0281] [Period T3] In a period T3, the potential of the conductor WSL is supplied to the nodes ND[1] and ND[2], and the potential of the conductor WBL is supplied to the node ND[5] (see FIG. 40B).

[0282] [Period T4] In a period T4, an L potential is supplied to the conductors WWL[1] and WWL[5] (see FIG. 41A). Then, the transistors WTr[1] and WTr[5] are turned off, and the charges written to the nodes ND[2] and ND[5] are held.

[0283] [Period T5] In a period T5, the potential of the conductor WSL is supplied to the node ND[1] (see FIG. 41A).

[0284] [Period T6] In a period T6, an L potential is supplied to the conductor SG (see FIG. 41B). Then, the transistor STr1 is turned off, and the charge written to the node ND[1] is held. At this time, an L potential may be supplied to the conductor SEL.

[0285] In this manner, information can be written to the memory element MC.

[0286] The memory string 120 can write information from both the conductor WSL and the conductor WBL. That is, the memory element MC[3] and the memory element MC[4] can be written simultaneously. Furthermore, after writing to the memory element MC[3] and the memory element MC[4], the memory element MC[2] and the memory element MC[5] can be written simultaneously. In this way, since writing can be performed simultaneously on multiple memory elements MC in one memory string 120, the speed of writing information can be increased. In addition, the supply of electric charge corresponding to the information to be written can be more reliably performed.

[0287] Furthermore, when writing information to the i-th memory element MC, if i is close to n, the operation of writing information to the 1st to i-1th memory elements MC can be omitted by writing information from the conductor WBL side. If i is close to 1, the operation of writing information to the i+1th to nth memory elements MC can be omitted by writing information from the conductor WSL side. In the memory string 120, the time and power consumption required for the write operation can be reduced.

[0288] In the embodiment, in the write operation, an example is shown in which an L potential is always supplied to the conductor WWL[3], writing to the memory elements MC[1] to MC[3] is performed from the conductor WSL side, and writing to the memory elements MC[4] and MC[5] is performed from the conductor WBL side, but the present invention is not limited to this. With an arbitrary conductor WWL[i] as a boundary, writing to the memory elements MC[1] to MC[i] may be performed from the conductor WSL side, and writing to the memory elements MC[i+1] to MC[n] may be performed from the conductor WBL side. Moreover, writing to the memory elements MC[1] to MC[n] may be performed from the conductor WSL side, or writing to the memory elements MC[1] to MC[n] may be performed from the conductor WBL side.

[0289] [Read operation] An example of a read operation of the memory string 120 having the above circuit configuration will be described. As an initial state, it is assumed that an L potential is supplied to conductor WWL[1] to conductor WWL[5], conductor RWL[1] to conductor RWL[5], conductor SG, conductor SEL, conductor BG, conductor WSL, conductor RSL, conductor WBL, and conductor RBL. Figure 42 is a timing chart for explaining the read operation. Figures 43A to 45 are circuit diagrams for explaining the read operation.

[0290] In this embodiment, an operation of sequentially reading data from the memory elements MC[1] to MC[5] will be described.

[0291] [Period T7] In a period T7, an H potential is supplied to the conductors RWL[2] to RWL[5], the conductor SEL, and the conductor RSL (see FIG. 43A). Then, the transistors RTr[2] to RTr[5] are turned on. In addition, the transistor STr2 is turned on, and electrical conduction is established between the semiconductor 127 included in the transistor RTr and the conductor RBL.

[0292] At this time, if the node ND[1] of the memory element MC[1] holds an H potential, the transistor RTr[1] will be turned on even if the potential supplied to the conductor RWL[1] is an L potential. Therefore, the conductor RSL and the conductor RBL are in a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[1] of the memory element MC[1] is an H potential. It is preferable that the conductor RBL is functionally connected to an RBL driver 2004 equipped with a sense amplifier or the like (see FIGS. 1A and 1B).

[0293] On the other hand, when the node ND[1] of the memory element MC[1] is held at an L potential, the potential supplied to the conductor RWL[1] is an L potential, and the transistor RTr[1] is turned off. Therefore, the conductor RSL and the conductor RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[1] of the memory element MC[1] is held at an L potential.

[0294] [Period T8] Next, in period T8, an H potential is supplied to the conductor RWL[1], and an L potential is supplied to the conductor RWL[2] (see Fig. 43B). At this time, if an H potential is held at the node ND[2] of the memory element MC[2], even if the potential supplied to the conductor RWL[2] is an L potential, the transistor RTr[2] is turned on. Therefore, the conductor RSL and the conductor RBL are brought into a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. That is, it can be detected that the potential held at the node ND[2] of the memory element MC[2] is an H potential.

[0295] On the other hand, if an L potential is held at the node ND[2] of the memory element MC[2], since the potential supplied to the conductor RWL[2] is an L potential, the transistor RTr[2] is turned off. Therefore, since the conductor RSL and the conductor RBL do not conduct, the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Accordingly, on the conductor RBL side, it can be detected that an L potential is held at the node ND[2] of the memory element MC[2].

[0296] [Period T9] Next, in period T9, an H potential is supplied to the conductor RWL[2], and an L potential is supplied to the conductor RWL[3] (see Fig. 44A). At this time, if an H potential is held at the node ND[3] of the memory element MC[3], even if the potential supplied to the conductor RWL[3] is an L potential, the transistor RTr[3] is turned on. Therefore, the conductor RSL and the conductor RBL are brought into a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. That is, it can be detected that the potential held at the node ND[3] of the memory element MC[3] is an H potential.

[0297] On the other hand, when the node ND[3] of the memory element MC[3] is held at an L potential, the potential supplied to the conductor RWL[3] is an L potential, and the transistor RTr[3] is turned off. Therefore, the conductor RSL and the conductor RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[3] of the memory element MC[3] is held at an L potential.

[0298] [Period T10] Next, in period T10, an H potential is supplied to the conductor RWL[3], and an L potential is supplied to the conductor RWL[4] (see FIG. 44B). At this time, if an H potential is held at the node ND[4] of the memory element MC[4], even if the potential supplied to the conductor RWL[4] is an L potential, the transistor RTr[4] is turned on. Therefore, the conductors RSL and RBL are in a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[4] of the memory element MC[4] is an H potential.

[0299] On the other hand, when the node ND[4] of the memory element MC[4] is held at an L potential, the potential supplied to the conductor RWL[4] is an L potential, and the transistor RTr[4] is turned off. Therefore, the conductors RSL and RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[4] of the memory element MC[4] is held at an L potential.

[0300] [Period T11] Next, in period T11, an H potential is supplied to the conductor RWL[4], and an L potential is supplied to the conductor RWL[5] (see FIG. 45). At this time, if an H potential is held at the node ND[5] of the memory element MC[5], even if the potential supplied to the conductor RWL[5] is an L potential, the transistor RTr[5] is turned on. Therefore, the conductors RSL and RBL are in a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[5] of the memory element MC[5] is an H potential.

[0301] On the other hand, when the node ND[5] of the memory element MC[5] is held at an L potential, the potential supplied to the conductor RWL[5] is an L potential, and the transistor RTr[5] is turned off. Therefore, the conductors RSL and RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[5] of the memory element MC[5] is held at an L potential.

[0302] In this manner, by detecting the potentials held in the nodes ND[1] to ND[5], the information of the storage elements MC[1] to MC[5] can be read. Note that, in this embodiment, an example in which information is sequentially read from the storage element MC[1] to the storage element MC[5] has been described, but the present invention is not limited to this. Information may be sequentially read from the storage element MC[5] to the storage element MC[1].

[0303] In addition, it is not necessary to read information from the memory elements MC[1] to MC[5], and information from any memory element MC[i] can be read. In this case, an L potential is supplied to the conductor RWL[i], an H potential is supplied to the other conductors RWL, and the potential held in the node ND[i] of the memory element MC[i] is detected based on whether the potential of the conductor RSL can be detected on the conductor RBL side, and the information of the memory element MC[i] can be read.

[0304] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0305] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device 200 including a memory device 100 will be described.

[0306] Fig. 46 is a block diagram illustrating a configuration example of a semiconductor device 200 of one embodiment of the present invention. The semiconductor device 200 illustrated in Fig. 46 includes a driver circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. Fig. 46 illustrates an example in which the memory array 220 includes a plurality of memory devices 100 arranged in a matrix.

[0307] The drive circuit 210 has a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 has a peripheral circuit 211, a control circuit 212, and a voltage generating circuit 228. The semiconductor device 200 has elements or circuits having various functions, such as a memory array 220, PSWs 241 and 242, the peripheral circuit 211, the control circuit 212, and the voltage generating circuit 228. Therefore, the semiconductor device 200 may be called a system or a subsystem.

[0308] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0309] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 212.

[0310] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine an operation mode (e.g., a write operation, a read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0311] The voltage generating circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 228. For example, when an H-level signal is provided as the signal WAKE, the signal CLK is input to the voltage generating circuit 228, and the voltage generating circuit 228 generates a negative voltage.

[0312] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory device 100. The peripheral circuit 211 has a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0313] The row decoder 221 and the column decoder 222 have a function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying a row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The row driver 223 has a function of selecting a conductor WWL specified by the row decoder 221. The column driver 224 has a function of writing data to the memory device 100, a function of reading data from the memory device 100, a function of holding the read data, and the like.

[0314] The input circuit 225 has a function of holding a signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is data (Din) to be written to the memory device 100. The data (Dout) read from the memory device 100 by the column driver 224 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. In addition, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is a signal RDA.

[0315] PSW241 is the V to the peripheral circuit 215 DD The PSW 242 has the function of controlling the supply of V HM In this embodiment, the high power supply voltage of the semiconductor device 200 is V DD and the low power supply voltage is GND (ground potential). Also, V HM is the high power supply voltage used to drive the word line high, and V DD The signal PON1 controls the on / off of the PSW 241, and the signal PON2 controls the on / off of the PSW 242. In FIG. 46, in the peripheral circuit 215, V DD Although the number of power domains to which the power is supplied is set to one, it is also possible to set it to multiple. In this case, a power switch may be provided for each power domain.

[0316] The driving circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in Fig. 47A, the driving circuit 210 and the memory array 220 may be provided so as to overlap each other. By providing the driving circuit 210 and the memory array 220 so as to overlap each other, the signal propagation distance can be shortened. Also, as shown in Fig. 47B, the memory array 220 may be provided in multiple layers on the driving circuit 210.

[0317] Also, as shown in FIG. 47C, memory arrays 220 may be provided above and below the driving circuit 210. FIG. 47C shows an example in which one memory array 220 is provided above and below the driving circuit 210. By arranging the driving circuit 210 between a plurality of memory arrays 220, the signal propagation distance can be further shortened. Note that the number of layers of the memory array 220 stacked above the driving circuit 210 and the memory array 220 stacked below the driving circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 stacked above the driving circuit 210 and the number of memory arrays 220 stacked below the driving circuit 210 are equal.

[0318] <Example of Cross-Sectional Configuration of Semiconductor Device 200> Fig. 48 shows a cross-sectional configuration example of the semiconductor device 200 shown in Fig. 47A. Fig. 48 shows a part of the semiconductor device 200 shown in Fig. 47A.

[0319] In FIG. 48, a transistor 301, a transistor 302, and a transistor 303 included in the driver circuit 210 are shown. The transistors 301 and 302 function as a part of the sense amplifier 227. The transistor 303 functions as a column selection switch. Specifically, the conductor RBL included in the memory array 220 is electrically connected to one of the source and drain of the transistor 301, the gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302, and the gate of the transistor 302 is electrically connected to one of the source and drain of the transistor 301. The one of the source and drain of the transistor 301 and the gate of the transistor 302 are electrically connected to one of the source and drain of the transistor 303, which functions as a column selection switch. This makes it possible to reduce the layout area of ​​the semiconductor device 200. Note that FIG. 48 shows an example in which five memory elements MC are provided per memory string. However, the number of memory elements MC provided in one memory string is not limited to this. For example, the number of memory elements MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0320] The conductor RBL of the memory array 220 is electrically connected to the sense amplifier 227 and the transistor 303 functioning as a column selection switch through the conductor 752 formed to be embedded in the conductor 715, the conductor 714, the conductor 705, the insulator 726, the insulator 722, etc. Note that the circuits and transistors included in the driver circuit 210 are merely examples, and are not limited to the circuit configuration and transistor structure. In addition to the above, appropriate circuits and transistors such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit can be provided depending on the configuration of the semiconductor device 200 and its driving method.

[0321] The transistors 301, 302, and 303 are provided on a substrate 311, and each includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. As shown in FIG. 48, one low-resistance region may be shared by the transistors 301 and 302 as both the source region or drain region of one of them and the source region or drain region of the other.

[0322] In the transistors 301, 302, and 303, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such transistors 301, 302, and 303 are also called FIN type transistors because they use a convex portion of a semiconductor substrate. Note that an insulator that is in contact with an upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0323] The transistors 301, 302, and 303 may each be a p-channel type or an n-channel type. The transistors 301 and 302 may each be transistors having the same conductivity type or may be transistors having different conductivity types.

[0324] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistors 301, 302, and 303 may be HEMTs (High Electron Mobility Transistors) by using GaAs and GaAlAs, or the like.

[0325] Low resistance region 314a and low resistance region 314b contain, in addition to the semiconductor material applied to semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0326] The insulator 315 functions as a gate insulating film for the transistor 301 , the transistor 302 , and the transistor 303 .

[0327] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0328] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as a laminate for the conductor, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0329] Moreover, an insulator 317 functioning as an etch stopper is preferably provided above the conductor 316. Moreover, an insulator 318 functioning as a spacer is preferably provided on the side of the insulator 315. By providing the insulators 317 and 318, the region where the low resistance region 314a and the low resistance region 314b are electrically connected to the conductor 328 can be determined in a self-aligned manner. Therefore, even if misalignment occurs when forming an opening for exposing a part of the low resistance region 314a and the low resistance region 314b, an opening for exposing an intended region can be formed. By forming the conductor 328 in the opening thus formed, a good contact with reduced contact resistance can be obtained between the low resistance region 314a and the conductor 328 and the low resistance region 314b. The contact between the low resistance region 314a and the low resistance region 314b formed in this manner and the conductor 328 may be called a self-aligned contact. A conductor 329 electrically connected to the conductor 316 may also be provided so as to be embedded in the insulator 317 and the insulator 322 .

[0330] An insulator 320, an insulator 322, an insulator 324, an insulator 326, and an insulator 327 are stacked in this order to cover the transistor 301, the transistor 302, and the transistor 303.

[0331] As the insulators 320, 322, 324, 326, and 327, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0332] The insulator 320 and the insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 301 or the like provided therebelow. For example, the top surfaces of one or both of the insulator 320 and the insulator 322 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0333] In addition, the insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 301 to a region where the memory array 220 is provided.

[0334] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor such as the memory element MC may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the memory element MC and the transistor 301 or the like. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0335] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0336] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulators 326 and 327 is preferably less than 4, and more preferably less than 3. For example, the dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, and more preferably 0.6 times or less, that of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0337] Conductors 328, 329, and 330, which are electrically connected to the memory array 220, are embedded in the insulators 320, 322, 324, 326, and 327. The conductors 328, 329, and 330 function as plugs or wiring. A plurality of structures of conductors that function as plugs or wiring may be collectively given the same reference numeral. In this specification, the wiring and the plug that electrically connects to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0338] As the material for each plug and wiring (conductor 328, conductor 329, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form it from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0339] A wiring layer may be provided over the insulator 327 and the conductor 330. For example, in FIG. 48, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductors 328, 329, and 330.

[0340] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0341] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 301 or the like can be suppressed while maintaining the conductivity as a wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0342] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 48, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductors 328, 329, and 330.

[0343] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0344] An insulator 722 is provided over the insulator 364 and the conductor 366, and the memory array 220 is provided above the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0345] In the above, an example has been shown in which the memory device 100 has the memory string 120, but the present embodiment is not limited to this. As shown in Fig. 49, the memory device 100 may have a memory string 120A as described in Fig. 8.

[0346] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0347] (Embodiment 4) In this embodiment, an application example of a data processing device according to one embodiment of the present invention will be described.

[0348] Generally, a computer has components such as a processor, main memory, and storage on a motherboard, and the components are electrically connected by, for example, bus wiring. Therefore, the longer the bus wiring, the higher the parasitic resistance becomes, and the higher the power consumption required for signal transmission becomes.

[0349] Specifically, a computer may have a configuration as shown in Fig. 50A, for example. The computer has a motherboard BD, on which are provided an arithmetic processing device (processor, CPU, etc.) 10, a main memory (DRAM (Dynamic Random Access Memory) etc.) 30, a storage (a three-dimensional structure NAND type storage device, a 3D OS NAND type storage device etc.) 40, an interface 60, etc. Note that Fig. 50 also illustrates an SRAM (Static Random Access Memory) 20 that also functions as a main memory, but this does not necessarily have to be provided on the motherboard BD.

[0350] FIG. 50 illustrates a configuration in which the arithmetic processing device 10 has a register 11.

[0351] 50A, the arithmetic processing device 10 is electrically connected to the SRAM 20, the main memory 30, the storage 40, and the interface 60. The main memory 30 is also electrically connected to the SRAM 20 and the storage 40.

[0352] Note that the components of the computer in Fig. 50A are electrically connected by a bus wiring BSH. In other words, the more components of the computer are, or the larger the motherboard BD is, the longer the bus wiring BSH is routed, and the more power consumption is required to transmit signals.

[0353] Incidentally, the computer of Fig. 50A may be configured such that each component of the computer is integrated into one chip to form a monolithic IC (Integrated Circuit). In this case, the information processing device described in the above embodiment can be applied as the main memory 30 and the storage 40. Thus, the computer of Fig. 50A as a monolithic IC is shown in Fig. 50B.

[0354] 50B has a circuit layer LGC on a semiconductor substrate having Si. Also, a memory layer STR is provided on the circuit layer LGC, and a circuit layer OSC is provided on the memory layer STR.

[0355] The circuit layer LGC has, for example, a plurality of circuits including Si transistors formed on a semiconductor substrate SBT having Si. For example, a part of the plurality of circuits may be the arithmetic processing device 10, the SRAM 20, etc. in FIG. 50A. In addition, when the information processing device is applied as the main memory 30 and the storage 40, a part of the plurality of circuits may be the controller 1197 included in the information processing device 50.

[0356] In particular, the SRAM 20 can increase the driving frequency of the SRAM by using Si transistors, for example.

[0357] The memory layer STR functions as a memory unit having a Si transistor and / or an OS transistor. The memory layer STR can be, for example, a three-dimensional NAND type memory circuit, a 3D OS NAND type memory circuit, etc. Therefore, the memory layer STR has a memory unit 1196 in an information processing device, a storage 40 in FIG. 50A, etc.

[0358] It should be noted that by using a 3D OS NAND type memory circuit, the power consumption of the monolithic IC in FIG. 50B can be reduced.

[0359] The circuit layer OSC includes, for example, a plurality of circuits including OS transistors. Some of the plurality of circuits may be circuits, such as the arithmetic processing device 10 and the SRAM 20, that are different from the circuits included in the circuit layer LGC.

[0360] In the monolithic IC of Fig. 50B, since there is no bus wiring BSH for wiring on the motherboard, the wiring for electrically connecting each component is short, and therefore the power consumption required for signal transmission can be reduced.

[0361] Moreover, the monolithic IC in Fig. 50B has an information processing device 50. Therefore, the information processing device 50 functions as the storage 40 and the main memory 30 in Fig. 50A. Therefore, in the monolithic IC in Fig. 50B, the memory unit 1196 of the memory layer STR can have the function of the main memory 30.

[0362] Since the bus wiring BSH is not provided and the storage unit 1196 is used instead of the main memory 30, the monolithic IC in FIG. 50B can reduce the circuit area more than the computer in FIG. 50A.

[0363] Next, an example of a memory hierarchy for the computer of FIG. 50A and the monolithic IC of FIG. 50B is shown in FIG. 51A and FIG. 51B, respectively.

[0364] In general, in the memory hierarchy, the higher the memory device is located, the faster the operating speed is required, and the lower the memory device is located, the larger the memory capacity and the higher the recording density are required. In Fig. 51A, as an example, a register included in the CPU (arithmetic processing device 10), an SRAM, a DRAM included in the main memory 30, and a three-dimensional structure NAND type memory circuit included in the storage 40 are shown in order from the top layer.

[0365] The registers and SRAM included in the arithmetic processing device 10 are used for temporarily storing arithmetic results, and are therefore frequently accessed by the arithmetic processing device 10. Therefore, a higher operating speed is required rather than a larger memory capacity. The registers also have the function of storing setting information for the arithmetic processing device.

[0366] The DRAM included in the main memory 30 has a function of holding programs and data read from the storage 40, for example. The recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm 2 It is.

[0367] The storage 40 has a function of storing data that requires long-term storage and various programs used by the processor. Therefore, the storage 40 is required to have a large memory capacity and a high recording density rather than an operating speed. The recording density of the memory device used for the storage 40 is approximately 0.6 to 6.0 Gbit / mm 2 For this reason, the storage 40 may be a three-dimensional NAND type memory circuit, a hard disk drive (HDD), or the like.

[0368] Incidentally, since the monolithic IC in FIG. 50B has the roles of storage 40 and main memory 30 in FIG. 50A, the memory hierarchy of the monolithic IC in FIG. 50B is as shown in FIG. 51B.

[0369] That is, in the monolithic IC of Fig. 50B, the memory cells included in the storage unit of the information processing device 50 can be treated not only as the cache memory of the storage unit but also as the main memory 30 in the computer of Fig. 50A. Therefore, in the monolithic IC of Fig. 50B, there is no need to provide a main memory 30 such as DRAM, so that the circuit area of ​​the monolithic IC of Fig. 50B can be reduced, and the power consumption required to operate the main memory 30 such as DRAM can be reduced.

[0370] The configuration of the monolithic IC shown in Fig. 50B is an example and is not limited to one aspect of the present invention. The configuration of the monolithic IC shown in Fig. 50B may be changed depending on the situation. For example, in the monolithic IC of Fig. 50B, when a high-speed memory of 1 GHz or more is required as the SRAM, the SRAM may be integrated into the arithmetic processing device.

[0371] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0372] (Embodiment 5) In this embodiment, an example of a chip 1200, which is a type of semiconductor device on which a memory device of the present invention is mounted, is shown using Figures 52A and 52B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0373] As shown in FIG. 52A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0374] Chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in Fig. 52B. In addition, a plurality of bumps 1202 are provided on the back side of the first surface of PCB 1201 and are connected to a motherboard 1203.

[0375] The motherboard 1203 may be provided with a sensor 1221, a power supply circuit 1222, and the like.

[0376] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and multiplication and accumulation. By providing the GPU 1212 with an image processing circuit and a multiplication and accumulation circuit, it becomes possible to execute image processing and multiplication and accumulation with low power consumption.

[0377] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0378] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0379] The memory controller 1214 has a circuit that functions as a controller and an interface for a memory device according to one embodiment of the present invention.

[0380] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0381] The network circuit 1216 includes a network circuit for connecting to a LAN (Local Area Network), etc. It may also include a circuit for network security.

[0382] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0383] The PCB 1201 on which the chip 1200 having the GPU 1212 is provided, the motherboard 1203 on which the sensor 1221 and the power supply circuit 1222 are provided can be referred to as a GPU module 1204.

[0384] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0385] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes.

[0386] (Embodiment 6) In this embodiment, an application example of a semiconductor device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 53A to 53E show some configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0387] 53A is a schematic diagram of a USB memory. A USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The storage device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1105 or the like.

[0388] FIG. 53B is a schematic diagram of the appearance of an SD card, and FIG. 53C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113 as well. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This makes it possible to read and write data from and to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The memory chip 1114 or the like can be incorporated with the memory device or the semiconductor device described in the above embodiment.

[0389] FIG. 53D is a schematic diagram of the appearance of an SSD, and FIG. 53E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153. The memory chip 1154 or the like can be incorporated with the storage device or semiconductor device shown in the previous embodiment.

[0390] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0391] (Embodiment 7) 54A to 54G illustrate specific examples of electronic devices equipped with a memory device or a semiconductor device according to one embodiment of the present invention.

[0392] <Electronic equipment and systems> The memory device or semiconductor device according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include information terminals, computers, smartphones, e-book terminals, television devices, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, and audio playback devices. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0393] The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0394] An electronic device according to one embodiment of the present invention may have a sensor (including a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0395] The electronic device of one embodiment of the present invention can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded in a recording medium, etc.

[0396] [Information terminal] A memory device for storing programs of a microcontroller can be formed using a memory device or a semiconductor device according to one embodiment of the present invention, and therefore, according to one embodiment of the present invention, a microcontroller chip can be made smaller.

[0397] FIG. 54A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one embodiment of the present invention, a limited space inside the mobile phone can be effectively used. In addition, a storage device according to one embodiment of the present invention may be used for storage of the mobile phone. This allows the storage capacity per unit area of ​​the storage to be increased.

[0398] FIG. 54B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one embodiment of the present invention, it is possible to effectively use a limited space inside the notebook information terminal. In addition, a storage device according to one embodiment of the present invention may be used for the storage of the notebook information terminal. This allows the storage capacity per unit area of ​​the storage to be increased.

[0399] In the above description, a smartphone and a notebook type information terminal are illustrated in Fig. 54A and Fig. 54B as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0400] [Game consoles] FIG. 54C illustrates a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), a video output to the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows a plurality of players to play a game at the same time. A memory device or a semiconductor device according to one embodiment of the present invention can be incorporated into chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0401] 54D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0402] A miniaturized microcontroller according to one embodiment of the present invention can be used effectively in a game machine such as a portable game machine 5300 or a stationary game machine 5400. A storage device or a semiconductor device according to one embodiment of the present invention can be used for storage of the portable game machine. This can increase the storage capacity per unit area of ​​the storage.

[0403] 54C and 54D show a portable game machine and a stationary game machine as examples of game machines, but game machines to which the microcontroller of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the microcontroller of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0404] [Mainframe computers] A memory device or semiconductor device according to an aspect of the present invention can be applied to a large computer.

[0405] FIG. 54E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 54F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0406] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of substrates 5504, and a microcontroller according to an aspect of the present invention can be mounted on the substrate. By using a miniaturized microcontroller according to an aspect of the present invention, the limited space of a large computer can be effectively utilized. Further, a memory device or semiconductor device according to an aspect of the present invention may be used for the storage of a large computer. Thereby, the storage capacity per unit area of the storage can be increased.

[0407] In FIGS. 54E and 54F, a supercomputer is illustrated as an example of a large computer, but the large computer to which a microcontroller according to an aspect of the present invention is applied is not limited thereto. Examples of the large computer to which a microcontroller according to an aspect of the present invention is applied include, for example, a computer (server) that provides services, a large general-purpose computer (mainframe), and the like.

[0408] [Household Appliance] FIG. 54G shows an electric refrigerator-freezer 5800, which is an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0409] A memory device or a semiconductor device according to one embodiment of the present invention can also be applied to an electric refrigerator-freezer 5800. For example, by applying a miniaturized microcontroller according to one embodiment of the present invention to the electric refrigerator-freezer 5800, the limited space of the electric refrigerator-freezer can be effectively utilized.

[0410] Although an electric refrigerator-freezer has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0411] The electronic devices, functions, effects, and the like described in this embodiment mode can be appropriately combined with descriptions of other electronic devices.

[0412] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes. [Explanation of symbols]

[0413] 100 memory device, 110 memory cell array, 117 insulator, 118 insulator, 119 conductor, 120 memory string, 121 substrate, 122 conductor, 123 insulator, 124 insulator, 125 semiconductor, 126 insulator, 127 semiconductor, 128 conductor, 129 insulator, 130 conductor, 132 insulator, 134 conductor, 136 conductor, 137 conductor, 138 insulator, 141 opening, 150 insulator, 152 insulator, 156 insulator, 161 conductor, 162 conductor, 163 conductor, 1 64 conductor, 171 conductor, 172 conductor, 173 conductor, 174 conductor, 179 material, 180 material, 181 material, 182 material, 183 material, 184 conductor, 185 insulator, 186 insulator, 187 conductor, 188 insulator, 189 insulator, 200 semiconductor device, 2000 driver, 2001 WSL driver, 2002 WBL driver, 2003 RSL driver, 2004 RBL driver, 2005 WWL driver, 2006 RWL driver, 2007 SEL driver

Claims

1. A first conductor; a second conductor above the first conductor; a third conductor above the second conductor; a fourth conductor above the third conductor; and a fifth conductor above the fourth conductor; a sixth conductor above the fifth conductor; A seventh conductor; and A first insulator; A second insulator; and A first semiconductor; a second semiconductor; At least the third conductor and the fourth conductor each have an opening; In each of the openings, the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order from an inner side surface, the seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator; the first semiconductor is in contact with an upper surface of the second conductor and a side surface of the fifth conductor; the second semiconductor is in contact with an upper surface of the first conductor and a side surface of the sixth conductor; the third conductor functions as a gate electrode of a first transistor; the second semiconductor has a region in which a channel of the first transistor is formed; the fourth conductor functions as a gate electrode of a second transistor; The first semiconductor has a region in which a channel of the second transistor is formed.

2. The first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are provided as concentric layers inside the opening of the third conductor. The storage device according to claim 1 .

3. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided as concentric layers inside the opening of the fourth conductor. The storage device according to claim 1 or 2.

4. The first semiconductor is a first oxide semiconductor. The storage device according to any one of claims 1 to 3.

5. 5 . The storage device according to claim 4 , wherein the first oxide semiconductor contains indium, an element M (wherein the element M is one or more selected from the group consisting of aluminum, gallium, yttrium, tin, and titanium), and zinc.

6. The second semiconductor is a second oxide semiconductor. The storage device according to any one of claims 1 to 5.

7. 7. The storage device according to claim 6, wherein the second oxide semiconductor contains indium, an element M (wherein the element M is one or more selected from the group consisting of aluminum, gallium, yttrium, tin, and titanium), and zinc.

8. the opening is also provided in the second conductor and the fifth conductor; The second insulator is provided between the second conductor and the second semiconductor, The second insulator is provided between the fifth conductor and the second semiconductor. The storage device according to any one of claims 1 to 7.

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