Level shifter and display device including same

Abstract

To reduce EMI of a level shifter.SOLUTION: A level shifter comprises: a first power input terminal to which a first gate voltage is applied; a second power input terminal to which a second gate voltage lower than the first gate voltage is applied; a third power input terminal to which a third gate voltage lower than the first gate voltage and higher than the second gate voltage is applied; an output terminal through which a shift clock is outputted; a first switch element configured to electrically connect the first power input terminal to the output terminal in response to a voltage of on-intervals of a first control signal; a second switch element configured to electrically connect the second power input terminal to the output terminal in response to a voltage of on-intervals of a second control signal; and a third switch element configured to electrically connect the third power input terminal to the output terminal in response to a voltage of on-intervals of a third control signal, where a portion of a first on-interval of the third control signal overlaps with a portion of the on-intervals of the first control signal.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a level shifter and a display device including the same. [Background technology]

[0002] A driving circuit of a flat panel display (FPD) writes pixel data of an input image to pixels of a display panel to reproduce the input image on a pixel array. The driving circuit of such a display device includes a data driving circuit that supplies data signals to data lines, a gate driving circuit that supplies gate pulses to gate lines, and a timing controller that controls the operation timing of the data driving circuit and the gate driving circuit.

[0003] The timing controller can control the outputs of the data driving circuit and the gate driving circuit. The timing controller generates a clock signal to control the gate driving circuit. The level shifter outputs a shift clock for driving the gate driving circuit in response to the clock input from the timing controller. The gate driving circuit sequentially outputs gate pulses using a shift register to which the shift clock from the level shifter is input. Summary of the Invention [Problem to be solved by the invention]

[0004] Various researches are being conducted to reduce EMI (Electromagnetic Interference) of display devices. In the case of a level shifter, methods such as adding an EMI filter to the output terminal of the level shifter or connecting multiple transistors in parallel to adjust the on-resistance of the transistor of the output terminal buffer of the level shifter are being considered. However, this method may cause power consumption in the EMI filter added to the output terminal of the level shifter and increase the size and cost of the chip of the integrated circuit (IC) in which the level shifter is built. If there is a dead time between the on / off timing of the switching element constituting the level shifter, the effect of reducing EMI is limited due to harmonics and peak currents generated when the voltage of the control signal changes suddenly after the dead time.

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a level shifter capable of reducing EMI and a display device including the same.

[0006] The object of the present invention is not limited to the above-mentioned objects, and further objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] A level shifter according to an embodiment of the present invention includes a first power supply input terminal to which a first gate voltage is applied, a second power supply input terminal to which a second gate voltage lower than the first gate voltage is applied, a third power supply input terminal to which a third gate voltage lower than the first gate voltage and higher than the second gate voltage is applied, an output terminal to which a shift clock is output, a first switch element electrically connecting the first power supply input terminal to the output terminal in response to a voltage during an on-period of a first control signal, a second switch element electrically connecting the second power supply input terminal to the output terminal in response to a voltage during an on-period of a second control signal, and a third switch element electrically connecting the third power supply input terminal to the output terminal in response to a voltage during an on-period of a third control signal. A part of the first on-period of the third control signal overlaps a part of the on-period of the first control signal. A part of the second on-period of the third control signal overlaps a part of the on-period of the second control signal.

[0008] The first on-period of the third control signal may include a first non-overlapping period that does not overlap with the on-period of the first control signal and the on-period of the second control signal, and a first overlapping period that overlaps with a partial period including a rising edge of a pulse, of the on-period of the first control signal. The second on-period of the third control signal may include a second non-overlapping period that does not overlap with the on-period of the first control signal and the on-period of the second control signal, and a second overlapping period that overlaps with a partial period including a rising edge of a pulse, of the on-period of the second control signal.

[0009] During the first superposition period, a current can flow between the first power supply input terminal and the output terminal, and a current can flow between the third power supply input terminal and the output terminal, and during the second superposition period, a current can flow between the second power supply input terminal and the output terminal, and a current can flow between the third power supply input terminal and the second power supply input terminal.

[0010] The level shifter may further include a control unit that receives a first input clock and a second input clock having the same frequency and phase difference with respect to the first input clock, and outputs the first control signal, the second control signal, and the third control signal.

[0011] The first overlap period and the second overlap period may not overlap with the first input clock and the second input clock, respectively.

[0012] During the first overlapping period and the second overlapping period, a current may flow through the power supply wiring to which the third gate voltage is applied, and pulses of the first input clock and the second input clock may not be input.

[0013] The first non-overlapping period and the second non-overlapping period may not overlap with an ON period of the first control signal and an ON period of the second control signal, respectively.

[0014] The on-period of the first control signal may include the first overlapping period, the on-period of the second control signal, and a third non-overlapping period that does not overlap with the first and second on-periods of a third control signal. The on-period of the second control signal may include the second overlapping period, the on-period of the second control signal, and a fourth non-overlapping period that does not overlap with the first and second on-periods of the third control signal.

[0015] A display device according to one embodiment of the present invention includes a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged, a data driver that outputs data signals to be applied to the data lines, and a gate driver that receives a shift clock from the level shifter and supplies a gate pulse to the gate lines.

[0016] A display device according to another embodiment of the present invention includes a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of pixels arranged thereon, a data driver outputting a data signal to be applied to the data lines, a gate driver receiving a shift clock and supplying a gate pulse to the gate lines, a power supply unit outputting a first gate voltage, a second gate voltage lower than the first gate voltage, and a third gate voltage having a voltage level between the first gate voltage and the second gate voltage, and a level shifter receiving a first input clock, a second input clock having the same frequency and a different phase from the first input clock, the first gate voltage, the second gate voltage, and the third gate voltage, and outputting the shift clock. A current flows through a power supply line to which the third gate voltage is applied, among power supply lines connected between the power supply unit and the level shifter, during at least a portion of a time when there is no pulse of the first input clock and no pulse of the second input clock. Effect of the Invention

[0017] According to the present invention, the slew rate can be reduced and EMI characteristics can be improved by setting an overlap period in which gate voltages having different voltage levels are short-circuited at the rising edge and falling edge of the shift clock input to the gate driver.

[0018] According to the present invention, by superimposing a portion of a control signal for controlling a switch element that switches a gate voltage input to a level shifter, it is possible to reduce the dead time between pulses of the control signal and thereby reduce EMI.

[0019] The effects of the present invention are not limited to those mentioned above, and further effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief description of the drawings]

[0020] [Figure 1]1 is a block diagram showing a display device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a circuit diagram showing an example of a pixel circuit. [Figure 3a] 1 is a diagram showing an example in which a level shifter according to an embodiment of the present invention is applied to a display device. [Figure 3b] 1 is a diagram showing an example in which a level shifter according to an embodiment of the present invention is applied to a display device. [Figure 3c] 1 is a diagram showing an example in which a level shifter according to an embodiment of the present invention is applied to a display device. [Figure 4] FIG. 2 is a block diagram showing a configuration of a level shifter. [Diagram 5] 4 is a waveform diagram showing input and output signals of a level shifter. FIG. [Figure 6] 4 is a circuit diagram illustrating a shift register of a gate driver; FIG. [Figure 7] 5 is a circuit diagram showing in detail a clock output section shown in FIG. 4. [Figure 8] 5 is a waveform diagram showing a method of driving a level shifter according to an embodiment of the present invention. [Figure 9] FIG. 11 is a circuit diagram showing a third control signal generating circuit according to an embodiment of the present invention. [Figure 10] 10 is a waveform diagram showing input and output signals of the third control signal generating circuit shown in FIG. [Figure 11] 11 is a waveform diagram showing a method of driving a level shifter according to another embodiment of the present invention. [Figure 12] FIG. 11 is a circuit diagram showing a third control signal generating circuit according to an embodiment of the present invention. [Figure 13] 13 is a waveform diagram showing input and output signals of the third control signal generating circuit shown in FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The advantages and features of the present invention, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and the embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those skilled in the art of the invention, and the present invention is only defined by the scope of the claims.

[0022] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely illustrative, and the present invention is not limited to the matters shown in the drawings. The same reference numerals refer to substantially the same components throughout the specification. In addition, when describing the present invention, detailed descriptions of related known technologies are omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0023] When the terms "comprise", "include", "have", "consist of", etc. mentioned in the present specification are used, other parts may be added unless "only" is used. When an element is expressed in the singular, it may be interpreted as being plural unless otherwise expressly stated.

[0024] When interpreting elements, they are interpreted as including a margin of error unless otherwise expressly stated.

[0025] When a positional relationship or interconnection between two elements is described, such as "on," "above," "below," "to the side of," "connect," "couple," "crossing," "intersecting," and the like, there may be one or more other elements between those elements, unless there is reference to "immediately" or "directly."

[0026] When a temporal relationship is explained using "after," "following," "next to," "before," etc., it may not be continuous on the timeline, since "immediately" or "directly" is not used.

[0027] Although the terms "1" and "2" may be used to distinguish between elements, the functions and structures of these elements are not limited by the ordinal numbers preceding the elements or the names of the elements. Since the claims are described with a focus on essential elements, the ordinal numbers preceding the names of elements in the claims may not match the ordinal numbers preceding the names of elements in the embodiments.

[0028] The following embodiments can be partially or fully combined or combined with each other, and various technical interlocking and driving are possible. Each embodiment can be implemented independently of each other, or can be implemented together in a linked relationship.

[0029] In the display device of the present invention, the display panel driving circuit, the pixel array, the level shifter, etc. may include transistors. The transistors may be implemented as an Oxide TFT (Thin Film Transistor) including an oxide semiconductor, an LTPSTFT including low temperature polysilicon (LTPS), etc.

[0030] A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies carriers to a transistor. In a transistor, carriers flow out from the source. The drain is an electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In an n-channel transistor, the carriers are electrons, so the source voltage is lower than the drain voltage so that electrons flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source side. In a p-channel transistor, the carriers are holes, so the source voltage is higher than the drain voltage so that holes flow from the source to the drain. In a p-channel transistor, the holes flow from the source to the drain side, so that current flows from the source to the drain side. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the invention is not limited by the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first and second electrodes.

[0031] The present invention is applicable to any flat panel display that requires integrated circuits and power circuits to drive pixels, such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLED Displays).

[0032] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] 1 to 3c, a display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

[0034] The screen of the display panel 100 includes a pixel array AA that displays pixel data of an input image. The pixel data of the input image is displayed on pixels of the pixel array AA. The pixel array AA includes a number of data lines DL, a number of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. The pixels may be arranged in various ways, such as a matrix shape, a shape in which pixels emitting the same color are shared, a stripe shape, a diamond shape, etc.

[0035] When the resolution of the pixel array AA is n*m, the pixel array AA includes n pixel columns and m pixel lines L1 to Lm intersecting the pixel columns. The pixel lines include pixels arranged along a first direction X. The pixel columns include pixels arranged along the first direction. One horizontal period 1H is the time obtained by dividing one frame period by the number of m pixel lines L1 to Lm. In one horizontal period 1H, pixel data is written to the pixels of one pixel line.

[0036] Each pixel includes two or more sub-pixels 101 to realize a color. For example, each pixel may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each pixel may further include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit. The pixel circuit includes a pixel electrode, one or more TFTs (Thin Film Transistors), and a capacitor. The pixel circuit is connected to a data line DL and a gate line GL. In the case of an organic light emitting display device, the pixel circuit may be realized by, but is not limited to, the circuit shown in FIG. 2.

[0037] 2, the pixel circuit includes a light emitting element EL, a driving element DT for supplying a current to the light emitting element EL, a switching element ST for supplying a data signal Vdata to a gate electrode of the driving element DT in response to a gate pulse GATE, and a capacitor Cst connected between the gate electrode and source electrode of the driving element DT. The driving element DT and the switching element ST may be implemented as n-channel transistors.

[0038] A pixel driving voltage EVDD may be applied to a drain electrode of the driving element DT. The driving element DT supplies a current to the light emitting element EL in response to a gate-source voltage Vgs to drive the light emitting element EL. The switching element ST is turned on in response to a gate high voltage VGH of a gate pulse GATE and turned off in response to a gate low voltage VGL. The light emitting element EL is turned on to emit light when a forward voltage between the anode electrode and the cathode electrode is equal to or higher than a threshold voltage. A pixel base voltage EVSS lower than the pixel driving voltage EVDD is applied to the cathode electrode of the light emitting element EL. The capacitor Cst is connected between the gate electrode and the source electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0039] The light-emitting element EL may be realized as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, an emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. When a voltage is applied to the anode electrode and the cathode electrode of the OLED, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL are transferred to the emitting layer EML to form excitons, and visible light is emitted from the emitting layer EML. The OLED used for the light-emitting element may have a tandem structure in which multiple emitting layers are stacked. The OLED with the tandem structure can improve the brightness and life of a pixel.

[0040] Due to process variations and element characteristic variations caused in the manufacturing process of the display panel, there may be differences in the electrical characteristics of the driving elements DT between pixels. Such differences in the electrical characteristics of the driving elements DT may become greater as the driving time of the pixels increases. In order to compensate for the variations in the electrical characteristics of the driving elements between pixels, an internal compensation circuit may be included in the pixel circuit of each subpixel, or an external compensation circuit may be connected thereto.

[0041] A touch screen may be configured by disposing a touch sensor on the display panel 100. Touch input may be sensed using a separate touch sensor or through a pixel. The touch sensor may be an on-cell type or add-on type that is disposed on the screen of the display panel, or an in-cell type touch sensor that is built into the pixel array.

[0042] 1, the display panel driving circuit writes input image data to pixels of a display panel 100 under the control of a timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120. The display device further includes a timing controller 130 that controls operation timings of the data driver 110 and the gate driver 120 and transmits pixel data of an input image to the data driver 110, a level shifter 140 connected between the timing controller 130 and the gate driver 120, a power supply unit 400, etc.

[0043] The data driver 110 converts pixel data of an input image received as a digital signal from the timing controller 130 for each frame into analog gamma compensation voltages and outputs data signals Vdata1 to Vdata3. As shown in circles in FIG. 1, the data signals (Vdata1 to Vdata3) output from the data driver 110 are provided to corresponding data lines DL1 to DL3. The data driver 110 outputs the data signals Vdata1 to Vdata3 using a digital to analog converter (hereinafter referred to as "DAC") that converts the pixel data input as a digital signal into an analog gamma compensation voltage. The data driver 110 may be integrated into a source driver IC 110a shown in FIGS. 3a to 3c. The source driver IC 110a may be mounted on a flexible film 110b and connected between the source PCBs 152 and 153 and the display panel 100 in a COF (Chip on Film) bonding process. Each of the source drive ICs 110a may include a built-in touch sensor driver for driving a touch sensor.

[0044] The display panel driving circuit may further include a demultiplexer array 112 disposed between the data driving unit 110 and the data lines DL.

[0045] The demultiplexer array 112 sequentially connects one channel of the data driver 110 to a number of data lines DL and distributes the data signal output from one channel of the data driver 110 to the data lines DL in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer array 112 is optional.

[0046] The gate driver 120 may be formed in a bezel region BZ where no image is displayed in the display panel 100, or at least a portion of the gate driver 120 may be disposed in the pixel array AA. The gate driver 120 outputs gate pulses GATE1, GATE2, and GATE3 in response to a shift clock received from the level shifter 140. The gate pulses GATE1, GATE2, and GATE3 are sequentially supplied to the gate lines GL1, GL2, and GL3.

[0047] The gate pulses GATE1 to GATE3 applied to the gate lines GL1 to GL3 turn on the switch elements ST of the sub-pixels 101 to select the pixels to be charged with the voltages of the data signals Vdata1 to Vdata3. The switch elements ST of the sub-pixels 101 can be turned on in response to the gate high voltages VGH of the corresponding gate pulses GATE1 to GATE3 and turned off in response to the gate low voltages VGL. The gate pulses GATE1 to GATE3 swing between the gate high voltages VGH and the gate low voltages VGL. The gate driver 120 shifts the gate pulses using a shift register.

[0048] The timing controller 130 can multiply the input frame frequency by i to control the operation timing of the display panel drivers 110 and 120 at a frame frequency of the input frame frequency×i Hz (i is a positive integer greater than 0). The input frame frequency is 60 Hz for the NTSC (National Television Standards Committee) system and 50 Hz for the PAL (Phase-Alternating Line) system.

[0049] The timing controller 130 receives pixel data of an input image and a timing signal synchronized therewith from the host system 200. The pixel data of the input image received by the timing controller 130 is a digital signal. The timing controller 130 transmits the pixel data to the data driver 110. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted because the vertical period and the horizontal period can be determined from the method of counting the data enable signal DE. The data enable signal DE has a period of one horizontal period 1H.

[0050] The timing controller 130 may generate a data timing control signal for controlling the data driver 110, a gate timing control signal for controlling the gate driver 120, a MUX control signal for controlling the switch elements of the demultiplexer array 112, etc. based on a timing signal received from the host system 200. The control signal output from the timing controller 130 may include a clock of a digital signal voltage level.

[0051] The host system 200 may include any one of the main boards of a television, a set-top box, a navigation system, a personal computer (PC), a home theater, a vehicle system, a mobile system, and a wearable system. The processor of the host system may scale a video signal from a video source according to the resolution of the display panel 100 and transmit the scaled video signal together with a timing signal to the timing controller 130. The processor of the host system may execute an application program corresponding to the touch input in response to touch data input from the touch sensor driver. In the mobile device and the wearable device, the data driver 110, the timing controller 130, the level shifter 140, etc. may be integrated into one drive IC (not shown).

[0052] The shift clocks output from the level shifters 140 to 142 swing between a gate high voltage VGH and a gate low voltage VGL, and are supplied to the gate driver 120 through clock lines CL1 to CLn. The clocks output from the level shifters 140 to 142 may be applied to at least one of the demultiplexer array 112, the gate driver 120, the data driver 110, and the touch sensor driver.

[0053] The power supply unit 400 generates a voltage required for driving the pixel array of the display panel 100 and the display panel driving circuit using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, a buck-boost converter, etc. The power supply unit 400 adjusts a DC input voltage from the host system 200 to generate DC voltages such as a gamma reference voltage VGMA, a gate high voltage VGH, a gate low voltage VGL, a positive power supply voltage AVDD, and a pixel common voltage. The gate high voltage VGH is a voltage higher than the gate low voltage VGL. The positive power supply voltage AVDD is a voltage lower than the gate high voltage VGH and higher than the gate low voltage VGL. Hereinafter, the "gate high voltage" will be referred to as a first gate voltage, the "gate low voltage" as a second gate voltage, and the "positive power supply voltage AVDD" as a third gate voltage. It should be noted that the third gate voltage AVDD is not limited to a half voltage between the first gate voltage VGH and the second gate voltage VGL, but is a voltage lower than the first gate voltage VGH and lower than the second gate voltage VGL. For example, it may be set to, but is not limited to, VGH=25[V], VGL=-15[V], and AVDD=12[V]. The first gate voltage VGH, the second gate voltage VGL, and the third gate voltage AVDD are supplied to the level shifter 140.

[0054] The gamma reference voltage VGMA is supplied to the data driver 110. The gamma reference voltage VGMA is divided by a voltage divider circuit of the data driver 110 for each gray scale and supplied to a DAC of the data driver 110. The power supply unit 400 may generate constant voltages commonly applied to the pixels, for example, a pixel driving voltage EVDD and a pixel base voltage EVSS.

[0055] 3a to 3c are diagrams showing various embodiments of a level shifter in a display device according to an embodiment of the present invention.

[0056] 3a to 3c, the control board 150 may be connected to first and second source PCBs 152 and 153 through a flexible circuit board 151, such as a flexible flat cable (FFC) or a flexible printed circuit board (FPCB), and connectors 151a and 151b. The source drive IC 110a is connected between the source PCBs 152 and 153 and the display panel 100.

[0057] 3a, the timing controller 130 and the level shifter 140 may be mounted on a control board 150. In this case, an input terminal of the level shifter 140 may be connected to the timing controller 130 through a wiring formed on the control board 150. An output terminal of the level shifter 140 may be connected to the gate driver 120 through a wiring connecting the flexible circuit board 151, the source PCB 152, the COF (Chip on film) 110b, and the gate driver 120 on the display panel 100.

[0058] As shown in FIG. 3b, the level shifters 141 and 142 can be implemented on each of the source PCBs 152 and 153. The first level shifter 141 can be implemented on the first source PCB 152, and the second level shifter 142 can be implemented on the second source PCB 153. The input terminals of the level shifters 141 and 142 are connected to the timing controller 130 through the wirings connecting the control board 150, the flexible circuit board 151, and the source PCBs 152 and 153. The output terminals of the level shifters 141 and 142 can be connected to the gate driver unit 120 through the wirings connecting the source PCBs 152 and 153, the COF 110b, and the gate driver unit 120 on the display panel 100.

[0059] As shown in FIG. 3c, the level shifters 141 and 142 can be connected to the source drive IC 110a. The timing controller 130 can transfer a video data packet including pixel data of an input video and a control packet including various control information to the source drive IC 110a. The timing controller 130 can encode gate timing control information in the control packet and transfer it to the source drive IC 110a. The source drive IC 110a can generate a gate timing control signal from the gate timing control information and provide it to the level shifters 141 and 142.

[0060] FIG. 4 is a block diagram showing the configuration of the level shifters 140, 141, and 142. FIG. 5 is a waveform diagram showing the input and output signals of the level shifters 140, 141, and 142.

[0061] Referring to FIG. 4, each of the level shifters 140, 141, and 142 can include a control unit 300 and a plurality of clock output units 311 to 31N.

[0062] When the level shifters 140, 141, and 142 include N channels (N is a positive integer equal to or greater than 2), the shift clocks GCLK1 to GCLKN are sequentially output from the N clock output units 311 to 31N. The first to Nth shift clocks GCLK1 to GCLKN are sequentially phase-shifted, and their pulse periods may overlap each other. For example, as shown in FIG. 5, when the first shift clock GCLK1, the second shift clock GCLK2, and the third shift clock GLCK3 are sequentially output, the second shift clock GCLK2 overlaps with a partial period of the pulse of the first shift clock GCLK1 and overlaps with a partial period of the pulse of the third shift clock GCLK3. The shift clocks GCLK1 to GCLKN swing between the second gate voltage VGL and the first gate voltage VGH. At the rising edge of the shift clocks GCLK1 to GCLKN, the voltages of the shift clocks GCLK1 to GCLKN increase at a first slew rate from the second gate voltage VGL to the third gate voltage AVDD, and then increase at a second slew rate to the first gate voltage VGH. At the falling edge of the shift clocks GCLK1 to GCLKN, the voltages of the shift clocks GCLK1 to GCLKN decrease at a third slew rate from the first gate voltage VGH to the third gate voltage AVDD, and then decrease at a fourth slew rate from the third gate voltage AVDD to the second gate voltage VGL.

[0063] The slew rate is the amount of voltage change per unit time. When the slew rate is high, the voltage reaches the target voltage quickly, whereas when the slew rate is low, the voltage reaches the target voltage slowly. The controller 300 can reduce the slew rate at each of the rising and falling edges of the clocks output from the level shifters 140, 141, and 142 to reduce EMI generated in the level shifters 140, 141, and 142.

[0064] The control unit 300 receives the first and second input clocks ONCLK and OFFCLK from the timing controller 130. The first and second input clocks ONCLK and OFFCLK have the same frequency and a phase difference. The second input clock OFFCLK may be delayed in phase by 180 degrees compared to the first input clock ONCLK, but is not limited to this. The first input clock ONCLK defines the rising timing of the shift clocks GCLK1 to GCLKN. The second input clock OFFCLK defines the falling timing of the shift clocks GCLK1 to GCLKN.

[0065] The control unit 300 outputs first and second control signals SWH, SWL synchronized with the first and second input clocks ONCLK, OFFCLK. The control unit 300 outputs a third control signal SWG having a frequency obtained by multiplying the first and second input clocks ONCLK, OFFCLK together. The first to third control signals SWH, SWL, SWG separated by channel are phase shifted on a channel-by-channel basis. The first to third control signals SWH, SWL, SWG are separated by channel and input to the clock output units 311 to 31N.

[0066] The control unit 300 overlaps a part of the pulse of the third control signal SWG with the pulses of the first and second control signals SWH, SWL in order to reduce EMI of the shift clocks GCLK1-GCLKN output to the gate driver 120. A part of the pulse period (or pulse width) of the third control signal SWG overlapping with the first and second control signals SWH, SWL may include a falling edge of the pulse of the third control signal SWG. A rising edge of the pulse of the third control signal SWG may not overlap with the first and second control signals SWH, SWL.

[0067] The first to third control signals SWH, SWL, SWG separated by channel are input to the clock output units 311 to 31N. For example, the first channel control signals SWH1, SWL1, SWG1 are input to the first clock output unit 311. The second channel control signals SWH2, SWL2, SWG2, which are delayed in phase from the first channel control signals SWH1, SWL1, SWG1, are input to the second clock output unit 312. The Nth channel control signals SWHN, SWLN, SWGN, which are delayed in phase from the N-1th channel control signals, are input to the Nth clock output unit 31N.

[0068] Each of the clock output units 311-31N outputs a first gate voltage VGH during a pulse period of the first control signal SWH, and outputs a second gate voltage VGL during a pulse period of the second control signal SWL. Each of the clock output units 311-31N can reduce EMI by lowering the slew rate of the shift clocks GCLK1-GCLKN during a period in which the pulse of the first control signal SWH and the pulse of the third control signal SWG overlap. Each of the clock output units 311-31N can reduce EMI by lowering the slew rate of the shift clocks GCLK1-GCLKN during a period in which the pulse of the second control signal SWL and the pulse of the third control signal SWG overlap. Therefore, the slew rate can be reduced during the time in which the pulses overlap each other.

[0069] FIG. 6 is a circuit diagram showing a schematic shift register of the gate driver 120. As shown in FIG.

[0070] 6, the shift register of the gate driver 120 includes cascaded signal transmission units ST1 to ST4. A start pulse VST received from the outside or a carry signal CAR from a previous signal transmission unit is input to the signal transmission units ST1 to ST4, and shift clocks GCLK1 to GLKN are input. The start pulse VST can be generated independently of the first pulse of the first shift clock GCLK1 input to the first signal transmission unit ST1 or the shift clocks GCLK1 to GCLKN.

[0071] The driving unit 60 of each of the signal transmission units ST1 to ST4 charges and discharges the first control node Q and the second control node QB. The output buffer of each of the signal transmission units ST1 to ST4 includes a pull-up transistor Tu and a pull-down transistor Td. The pull-up transistor Tu is turned on when the shift clocks GCLK1 to GCLKN are input while the first control node Q is charged, and charges the output node with the first gate voltage VGH, thereby increasing the voltage of the gate pulses GATE1 to GATE4. The pull-down transistor Td is turned on when the second control node QB is charged, and discharges the output node to the second gate voltage VGL, thereby decreasing the voltage of the gate pulses GATE1 to GATE4. Therefore, the shift register of the gate driving unit 120 sequentially shifts the gate pulses GATE1 to GATE4 in response to the shift clocks GCLK1 to GCLKN, and outputs them to the gate lines.

[0072] FIG. 7 is a circuit diagram showing the clock output sections of the level shifters 140, 141, and 142 in detail.

[0073] 7, the clock output unit 310 includes a first transistor M1 connected between a first power input terminal n1 and an output terminal n3, a second transistor M2 connected between a second power input terminal n2 and the output terminal n3, and a third transistor M3 connected between a third power input terminal n4 and the output terminal n3. A first gate voltage VGH is supplied to the first power input terminal n1. A second gate voltage VGL is supplied to the second power input terminal n2. A third gate voltage AVDD is supplied to the third power input terminal n4.

[0074] The shift clock GCLK output from the clock output unit 310 is supplied to the gate driver 120 through an output terminal n3. A low pass filter (LPF) may be connected to a clock line between the clock output unit 310 and the gate driver 120, but is not limited thereto. The low pass filter (LPF) may include a resistor R connected in series to the clock line, and a capacitor C connected between the clock line and a ground voltage source GND.

[0075] The first transistor M1 is turned on in response to a voltage during an on-period of the first control signal SWH to electrically connect the first power supply input terminal n1 to the output terminal n3, and is turned off in response to a voltage during an off-period of the first control signal SWH. When the first transistor M1 is turned on, a first gate voltage VGH is provided to the output terminal n3. The first transistor M1 includes a first electrode connected to the first power supply input terminal n1, a gate electrode to which the first control signal SWH is applied, and a second electrode connected to the output terminal n3.

[0076] The second transistor M2 is turned on in response to a voltage during an on-period of the second control signal SWL to electrically connect the second power supply input terminal n2 to the output terminal n3, and is turned off in response to a voltage during an off-period of the second control signal SWL. When the second transistor M2 is turned on, a second gate voltage VGL is supplied to the output terminal n3. The second transistor M2 includes a first electrode connected to the second power supply input terminal n2, a gate electrode to which the second control signal SWL is applied, and a second electrode connected to the output terminal n3.

[0077] The third transistor M3 is turned on in response to a voltage during an on-period of the third control signal SWG to electrically connect the third power supply input terminal n4 to the output terminal n3, and is turned off in response to a voltage during an off-period of the third control signal SWG. When the third transistor M3 is turned on, a third gate voltage AVDD is supplied to the output terminal n3. The third transistor M3 includes a first electrode connected to the third power supply input terminal n4, a gate electrode to which the third control signal SWG is applied, and a second electrode connected to the output terminal n3.

[0078] The first and third transistors M1 and M3 may be implemented as N-channel MOSFETs (NMOS), and the second transistor M2 may be implemented as a P-channel MOSFET (PMOS). In this case, in Fig. 8, the second control signal SWL may be a signal with an inverted phase and may be applied to the gate electrode of the second transistor M2. In Fig. 8, during the on-period ON of the control signals SWH, SWL, and SWG, the corresponding transistors M1, M2, and M3 are turned on.

[0079] FIG. 8 is a waveform diagram showing a method of driving a level shifter according to an embodiment of the present invention.

[0080] 8, each of the pulse periods ON1, ON2 of the third control signal SWG is greater than each of the pulse periods of the first and second input clocks ONCLK, OFFCLK.

[0081] The first on-period ON1 of the third control signal SWG includes a first non-overlapping period T1 and a first overlapping period t01. The first on-period ON1 of the third control signal SWG may be, but is not limited to, an odd-numbered pulse period of the third control signal SWG.

[0082] The first non-overlapping period T1 does not overlap with the on-period ON of the first and second control signals SWH and SWL. The first overlapping period t01 overlaps with a portion of the on-period ON of the first control signal SWH, including the rising edge. The first overlapping period t01 does not overlap with the input clocks ONCLK and OFFCLK. During the first overlapping period t01, a current Ira flows through the power supply wiring to which the third gate voltage AVDD is applied and the pull-up resistor Ra, and pulses of the input clocks ONCLK and OFFCLK are not input to the level shifters 140, 141, and 142.

[0083] During the first non-overlapping period T1, the third transistor M3 is in an on state, while the first and second transistors M1 and M2 are in an off state. During the first non-overlapping period T1, the voltage of the shift clock GCLK increases from the second gate voltage VGL to the third gate voltage AVDD at a first slew rate.

[0084] During the first superimposition period t01, the first and third transistors M1 and M3 are in an ON state, while the second transistor M2 is in an OFF state. During the first superimposition period t01, a current flows from the first power supply input terminal n1 to the output terminal n3, and a current Ira flows through the pull-up resistor Ra connected to the wiring to which the third gate voltage AVDD is applied via the third power supply input terminal n4. At this time, the pulses of the input clocks ONCLK and OFFCLK are not input to the level shifters 140, 141, and 142. During the first superimposition period t01, the voltage of the shift clock GCLK increases at a second slew rate from the third gate voltage AVDD to the first gate voltage VGH. The second slew rate may be higher than the first slew rate, but is not limited to this. The second slew rate may be controlled according to the first superimposition period t01. Since the second slew rate is low only during the first superimposition period t01, EMI that occurs when the voltage of the shift clock GCLK increases to the first gate voltage VGH can be reduced.

[0085] The second on-period ON2 of the third control signal SWG includes a second non-overlapping period T2 and a second overlapping period t02. The second on-period ON2 of the third control signal SWG may be, but is not limited to, an even-numbered pulse period of the third control signal SWG.

[0086] The second non-overlapping period T2 does not overlap with the on-period ON of the first and second control signals SWH and SWL. The second overlapping period t02 overlaps with a portion of the on-period ON of the second control signal SWL, including the rising edge. The second overlapping period t02 does not overlap with the input clocks ONCLK and OFFCLK. During the second overlapping period t02, a current Ira flows through the power supply wiring to which the third gate voltage AVDD is applied and the pull-up resistor Ra, and pulses of the input clocks ONCLK and OFFCLK are not input to the level shifters 140, 141, and 142.

[0087] During the second non-overlapping period T2, the third transistor M3 is in an on state, while the first and second transistors M1 and M2 are in an off state. During the second non-overlapping period T2, the voltage of the shift clock GCLK decreases from the first gate voltage VGH to the third gate voltage AVDD at a third slew rate.

[0088] During the second superimposition period t02, the second and third transistors M2 and M3 are in an ON state, while the first transistor M1 is in an OFF state. During the second superimposition period t02, a current flows from the output terminal n3 to the second power supply input terminal n2, and a current Ira flows through the pull-up resistor Ra connected to the wiring to which the third gate voltage AVDD is applied via the third power supply input terminal n4. At this time, the pulses of the input clocks ONCLK and OFFCLK are not input to the level shifters 140, 141, and 142. During the second superimposition period t02, the voltage of the shift clock GCLK decreases at a fourth slew rate from the third gate voltage AVDD to the second gate voltage VGL. The fourth slew rate may be higher than the third slew rate, but is not limited thereto. The fourth slew rate may be controlled according to the second superimposition period t02. Since the fourth slew rate is low only during the second overlapping period t02, EMI that occurs when the voltage of the shift clock GCLK is lowered to the second gate voltage VGL can be reduced.

[0089] The on-period ON of the first control signal SWH includes a first overlapping period t01 and a third non-overlapping period T3. During the first overlapping period t01, the first and third transistors M1 and M3 are simultaneously in an on-state. The third non-overlapping period T3 does not overlap with the on-periods ON, ON1, and ON2 of the second and third control signals SWL and SWG. During the third non-overlapping period T3, the first transistor M1 is in an on-state, while the second and third transistors M2 and M3 are in an off-state. Therefore, during the third non-overlapping period T3, the voltage of the shift clock GCLK maintains the first gate voltage VGH.

[0090] The on-period ON of the second control signal SWL includes a second overlapping period t02 and a fourth non-overlapping period T4. During the second overlapping period t02, the second and third transistors M2 and M3 are simultaneously in the on-state. The fourth non-overlapping period T4 does not overlap with the on-periods ON, ON1, and ON2 of the first and third control signals SWH and SWG. During the fourth non-overlapping period T4, the second transistor M2 is in the on-state, while the first and third transistors M1 and M3 are in the off-state. Therefore, during the fourth non-overlapping period T4, the voltage of the shift clock GCLK maintains the second gate voltage VGL.

[0091] The off period of the first control signal SWH overlaps with the second non-overlapping period T2, the second overlapping period t02, the fourth non-overlapping period T4, and the first non-overlapping period T1. The off period of the second control signal SWL overlaps with the first non-overlapping period T1, the first overlapping period t01, the third non-overlapping period T3, and the second non-overlapping period T2. Therefore, the first transistor M1 and the second transistor M2 are not turned on at the same time, but are turned on alternately.

[0092] Fig. 9 is a circuit diagram showing a clock generating circuit for generating the third control signal shown in Fig. 8. Fig. 10 is a waveform diagram showing input and output signals of the third control signal generating circuit shown in Fig. 9.

[0093] 9 and 10, the clock generation circuit includes an input circuit 92, a clock modulation circuit 94, and an output buffer 96.

[0094] The input circuit 92 can include an OR gate that receives the first and second input clock signals ONCLK and OFFCLK and outputs their logical sum. The output signal of the input circuit 92 is input to the clock modulation circuit 94. The clock modulation circuit 94 further modulates the pulse width of the clock input from the input circuit 92 to be longer by the overlapping periods t01 and t02 as shown in FIG. 8 and outputs the modulated clock. The output buffer 96 receives the output signal of the clock modulation circuit 94 and outputs a third control signal SWG that swings between the third gate voltage AVDD and the boosted third gate voltage AVDD + 5V. The output buffer 96 can include a voltage follower.

[0095] The level shifters 140, 141, and 142 can generate the boosted third gate voltage AVDD + 5V using a power supply circuit, such as a charge pump, that boosts the third gate voltage AVDD. The boosted third gate voltage AVDD + 5V is set to a voltage that is higher than the threshold voltage of the third transistor M3. The voltage during the ON period of the third control signal SWG can be the boosted third gate voltage AVDD + 5V.

[0096] FIG. 11 is a waveform diagram showing a method of driving a level shifter according to another embodiment of the present invention. In FIG. 11, the same reference numerals are given to substantially the same components as those in the embodiment described above in connection with FIG. 8, and detailed description thereof will be omitted.

[0097] Referring to FIG. 11, the first ON period ON1 of the third control signal SWG includes a first non-overlapping period T1 and a first overlapping period t01. The first overlapping period t01 overlaps with a partial period including the rising edge within the ON period ON of the first control signal SWH. The first overlapping period t01 does not overlap with the input clocks ONCLK and OFFCLK. During the first overlapping period t01, the voltage of the third control signal SWG gradually decreases. A part of the first overlapping period t01 can overlap with the period during which the voltage of the shift clock GCLK is maintained at the first gate voltage VGH.

[0098] During the first superimposition period t01, a current flows from the first power supply input terminal n1 to the output terminal n3, and a current flows from the first power supply input terminal n1 to the third power supply input terminal n4. Therefore, during the first superimposition period t01, a current Ira flows through the power supply wiring to which the third gate voltage AVDD is applied and the pull-up resistor Ra. At this time, the pulses of the input clocks ONCLK and OFFCLK are not input to the level shifters 140, 141, and 142.

[0099] The second on-period ON2 of the third control signal SWG includes a second non-overlapping period T2 and a second overlapping period t02. The second overlapping period t02 overlaps with a portion of the on-period ON of the second control signal SWL, including the rising edge. The second overlapping period t02 does not overlap with the input clocks ONCLK and OFFCLK. During the second overlapping period t02, the voltage of the third control signal SWG gradually decreases. A portion of the second overlapping period t02 may overlap with a period in which the voltage of the shift clock GCLK is maintained at the first gate voltage VGH.

[0100] During the second superimposition period t02, a current flows from the output terminal n3 to the second power supply input terminal n2, and a current flows from the third power supply input terminal n4 to the second power supply input terminal n2. Therefore, during the second superimposition period t02, a current Ira flows through the power supply wiring to which the third gate voltage AVDD is applied and the pull-up resistor Ra. At this time, the pulses of the input clocks ONCLK and OFFCLK are not input to the level shifters 140, 141, and 142.

[0101] Fig. 12 is a circuit diagram showing a clock generating circuit for generating the third control signal shown in Fig. 11. Fig. 13 is a waveform diagram showing input and output signals of the third control signal generating circuit shown in Fig. 12.

[0102] 12 and 13, the clock generating circuit includes an input circuit 92, an output buffer 96, an edge detecting circuit 97, first and second switch elements M01, M02, and a delay circuit 98.

[0103] The input circuit 92 may include an OR gate that receives the first and second input clocks ONCLK and OFFCLK and outputs their logical sum. The output buffer 96 receives the output signal of the input circuit 92 and outputs a third control signal SWG that swings between the third gate voltage AVDD and the boosted third gate voltage AVDD+5V.

[0104] The first switch element M01 is coupled between the output terminal of the output buffer 96 and the output terminal of the delay circuit 98, and can be turned on / off under the control of the edge detection circuit 97. The second switch element M02 is coupled between the output terminal of the output buffer 96 and the input terminal of the delay circuit 98, and can be turned on / off under the control of the edge detection circuit 97. Each of the first and second switch elements M01 and M02 can be composed of a transistor.

[0105] The edge detection circuit 97 detects rising and falling edges from the pulse of the third control signal SWG input from the output buffer 96. When a rising edge is detected from the third control signal SWG, the edge detection circuit 97 applies a gate signal of a gate-on voltage to the gate electrode of the first switch element M01 to turn on the first switch element M01. Therefore, when a rising edge is detected from the third control signal SWG, the third control signal SWG is applied to the gate electrode of the third switch element M3 without delay.

[0106] When a falling edge is detected from the third control signal SWG, the edge detection circuit 97 applies a gate signal having an inverted gate-on voltage to the gate electrode of the second switch element M02 to turn on the second switch element M02. Therefore, when a falling edge is detected from the third control signal SWG, the falling edge voltage of the third control signal SWG is delayed through the delay circuit 98 and applied to the gate electrode of the third switch element M3.

[0107] The delay circuit 98 delays the falling edge of the third control signal SWG input through the second switch element M02. The delay circuit 98 may be embodied as an RC delay circuit, but is not limited to this.

[0108] In view of the above, the contents of the specification describing the problem to be solved by the invention, the means for solving the problem, and the effects of the invention do not specify the essential features of the claims, and therefore the scope of the claims is not limited by the matters described in the specification.

[0109] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and can be modified in various ways without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the present invention are for illustration purposes, not for limiting the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative and non-limiting in all respects. The scope of protection of the present invention should be interpreted by the scope of the claims, and all technical ideas within the equivalent range should be interpreted as being included in the scope of the present invention.

Claims

1. a first power supply input terminal to which a first gate voltage is applied; a second power supply input terminal to which a second gate voltage lower than the first gate voltage is applied; a third power supply input terminal to which a third gate voltage lower than the first gate voltage and higher than the second gate voltage is applied; an output terminal from which a shift clock is output; a first switch element that electrically connects the first power supply input terminal to the output terminal in response to a voltage during an on-period of a first control signal; a second switch element that electrically connects the second power supply input terminal to the output terminal in response to a voltage during an on-period of a second control signal; a third switch element that electrically connects the third power supply input terminal to the output terminal in response to a voltage during an on-period of a third control signal; a control unit that receives a first input clock and a second input clock having the same frequency and phase difference with respect to the first input clock, and outputs the first control signal, the second control signal, and the third control signal; Including, a portion of a first ON period of the third control signal overlaps with a portion of an ON period of the first control signal; A portion of a second ON period of the third control signal overlaps with a portion of an ON period of the second control signal; The first on-period of the third control signal is a first non-overlapping period that does not overlap with an on-period of the first control signal and an on-period of the second control signal; a first overlapping period that overlaps with a portion of a period including a rising edge of a pulse during an on-period of the first control signal; The second on-period of the third control signal is a second non-overlapping period that does not overlap with the on-period of the first control signal and the on-period of the second control signal; a second overlapping period that overlaps a portion of the ON period of the second control signal that includes a rising edge of the pulse; 4. A level shifter comprising:

2. During the first overlap period, a current flows between the first power supply input terminal and the output terminal, and a current flows between the third power supply input terminal and the output terminal; During the second overlap period, a current flows between the second power supply input terminal and the output terminal, and a current flows between the third power supply input terminal and the second power supply input terminal; 2. The level shifter according to claim 1.

3. The level shifter of claim 1 , wherein the first overlap period and the second overlap period do not overlap with the first input clock and the second input clock, respectively.

4. 2. The level shifter according to claim 1, wherein, during the first superimposition period and the second superimposition period, a current flows through a power supply wiring to which the third gate voltage is applied, and pulses of the first input clock and the second input clock are not input.

5. 2 . The level shifter according to claim 1 , wherein the first non-overlapping period and the second non-overlapping period do not overlap with an ON period of the first control signal and an ON period of the second control signal, respectively.

6. The on-period of the first control signal is the first overlap period; a third non-overlapping period that does not overlap with an on-period of the second control signal and the first and second on-periods of the third control signal; Including, The on-period of the second control signal is the second overlap period; a fourth non-overlapping period that does not overlap with an on-period of the second control signal and the first and second on-periods of the first control signal; The level shifter of claim 1 , comprising:

7. a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of pixels arranged thereon; a data driver for outputting a data signal applied to the data line; a gate driver that receives a shift clock and supplies a gate pulse to the gate line; a level shifter which receives as input a first input clock, a second input clock having the same frequency and a different phase from that of the first input clock, a first gate voltage, a second gate voltage lower than the first gate voltage, and a third gate voltage having a voltage level between the first gate voltage and the second gate voltage, and outputs the shift clock; Including, The level shifter includes: a first power supply input terminal to which the first gate voltage is applied; a second power supply input terminal to which the second gate voltage is applied; a third power supply input terminal to which the third gate voltage is applied; an output terminal from which the shift clock is output; a control unit that receives the first input clock and the second input clock and outputs a first control signal, a second control signal, and a third control signal; a first switch element that electrically connects the first power supply input terminal to the output terminal in response to a voltage during an on-period of the first control signal; a second switch element that electrically connects the second power supply input terminal to the output terminal in response to a voltage during an on-period of the second control signal; a third switch element that electrically connects the third power supply input terminal to the output terminal in response to a voltage during an on-period of the third control signal; a control unit that receives the first input clock and the second input clock having the same frequency and the different phase with respect to the first input clock, and outputs the first control signal, the second control signal, and the third control signal; Including, a portion of a first ON period of the third control signal overlaps with a portion of an ON period of the first control signal; A portion of a second ON period of the third control signal overlaps with a portion of an ON period of the second control signal; The first on-period of the third control signal is a first non-overlapping period that does not overlap with an on-period of the first control signal and an on-period of the second control signal; a first overlapping period that overlaps with a portion of a period including a rising edge of a pulse during an on-period of the first control signal; The second on-period of the third control signal is a second non-overlapping period that does not overlap with the on-period of the first control signal and the on-period of the second control signal; a second overlapping period that overlaps a portion of the ON period of the second control signal that includes a rising edge of the pulse; Including, Display device.

8. During the first overlap period, a current flows between the first power supply input terminal and the output terminal, and a current flows between the third power supply input terminal and the output terminal; During the second overlap period, 8. The display device according to claim 7, wherein a current flows between the second power supply input terminal and the output terminal, and a current flows between the third power supply input terminal and the second power supply input terminal.

9. a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of pixels arranged thereon; a data driver for outputting a data signal applied to the data line; a gate driver that receives a shift clock and supplies a gate pulse to the gate line; a power supply unit that outputs a first gate voltage, a second gate voltage lower than the first gate voltage, and a third gate voltage having a voltage level between the first gate voltage and the second gate voltage; a level shifter which receives a first input clock, a second input clock having the same frequency and a different phase from that of the first input clock, the first gate voltage, the second gate voltage, and the third gate voltage, and outputs the shift clock; A display device, wherein, during at least a portion of a time when there is no pulse of the first input clock and no pulse of the second input clock, a current flows through a power supply wiring connected between the power supply unit and the level shifter, to which the third gate voltage is applied.

10. The level shifter includes: a first power supply input terminal to which the first gate voltage is applied; a second power supply input terminal to which the second gate voltage is applied; a third power supply input terminal to which the third gate voltage is applied; an output terminal from which the shift clock is output; a control unit that receives the first input clock and the second input clock and outputs a first control signal, a second control signal, and a third control signal; a first switch element that electrically connects the first power supply input terminal to the output terminal in response to a voltage during an on-period of the first control signal; a second switch element that electrically connects the second power supply input terminal to the output terminal in response to a voltage during an on-period of the second control signal; a third switch element that electrically connects the third power supply input terminal to the output terminal in response to a voltage during an on-period of the third control signal; The display device of claim 9 .

11. The first on-period of the third control signal is a first non-overlapping period that does not overlap with an on-period of the first control signal and an on-period of the second control signal; a first overlapping period that overlaps with a part of a period including a rising edge of a pulse during an on-period of the first control signal and does not overlap with pulses of the first input clock and the second input clock; Including, The second on-period of the third control signal is a second non-overlapping period that does not overlap with the on-period of the first control signal and the on-period of the second control signal; a second overlapping period that overlaps with a portion of the on-period of the second control signal including a rising edge of a pulse and does not overlap with pulses of the first input clock and the second input clock; The display device of claim 10 .

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