Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device in which the occurrence of an electrical short circuit between a conductive film to which a low voltage is applied and a conductive film to which a high voltage is applied, is suppressed, and a method of manufacturing the semiconductor device.SOLUTION: In a semiconductor device, a multilayer wiring structure MLS in which a plurality of conductive films CDL and a plurality of interlayer dielectric films ILL are laminated is formed so as to cover a main surface of a first semiconductor chip SCP1. The conductive films CDL include conductive films ML1, ML2, ML3 to which a low voltage is applied and conductive films ML4 to which a high voltage is applied. The conductive films ML1, ML2, ML3 to which the low voltage is applied are located below the conductive films ML4 to which the high voltage is applied and closer to the main surface of a semiconductor substrate SUB. The conductive films ML3 are arranged as conductive films CDL of at least one layer between a first inductor CL1a to which the low voltage is applied and a second inductor CL2a to which the high voltage is applied.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device provided with a micro isolator.

Background Art

[0002] In recent years, for environmental protection, in the field of automobiles, a conversion from a gasoline engine to a motor as power has been attempted. The rotational speed of the motor is controlled by a power semiconductor device equipped with a power semiconductor element for electricity. The power semiconductor device is controlled by a semiconductor device equipped with a microcomputer.

[0003] In a semiconductor device equipped with a power semiconductor element for electricity, a voltage of about several hundred (V) to about one thousand several hundred (V) is handled. On the other hand, a semiconductor device equipped with a microcomputer is driven by a voltage of about several (V). In order to control a semiconductor device equipped with a power semiconductor element for electricity by a microcomputer, a micro isolator (digital isolator) is applied to transmit and receive an electrical signal between a circuit including the power semiconductor element and a circuit including the microcomputer.

[0004] In a micro isolator, electromagnetic induction is used to transmit an electrical signal between an inductor (one inductor) electrically connected to a circuit including a microcomputer and an inductor (the other inductor) electrically connected to a circuit including a power semiconductor element.

[0005] As a structure for transmitting this electrical signal, there is a structure in which one inductor is disposed on a semiconductor substrate, and the other inductor is disposed with an interlayer insulating film interposed therebetween on the one inductor. As patent documents disclosing a semiconductor device having such a structure, for example, there are Patent Document 1 and Patent Document 2.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-82212 [Patent Document 2] International Publication No. 2015 / 114758 [Summary of the Invention] [Problems to be Solved by the Invention]

[0007] In the multilayer wiring structure in the semiconductor device described above, a plurality of conductive films constituting a circuit including a microcomputer are laminated. The plurality of conductive films include a conductive film formed in the same layer as the other inductor. For this reason, it is assumed that current flows along the insulating interface between the conductive film to which a low voltage is applied and the conductive film including the other inductor to which a high voltage is applied, resulting in an electrical short circuit.

[0008] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems]

[0009] A semiconductor device according to an embodiment is a semiconductor device including a first semiconductor chip on which a first semiconductor circuit, a first inductor, and a second inductor are formed. The first semiconductor chip has a semiconductor substrate having a main surface and a multilayer wiring structure. The multilayer wiring structure is on the main It is formed to cover a surface, and a plurality of conductive films and a plurality of interlayer insulating films are laminated. The plurality of conductive films in the multilayer wiring structure include a first conductive film group and a second conductive film group. The first conductive film group includes a first inductor to which a first voltage is applied and constitutes a first semiconductor circuit. The second conductive film group includes a second inductor to which a second voltage different from the first voltage is applied. The first conductive film group is disposed in a layer closer to the main surface and below the layer in which the second conductive film group is disposed. Assuming that i and j are natural numbers representing the order of the layers of the plurality of conductive films sequentially laminated from the main surface side of the semiconductor substrate, the first inductor is disposed in the i-th layer and the second inductor is disposed in the j-th layer. At least one layer of conductive film is disposed between the i-th layer and the j-th layer. Let \(k\) be a natural number representing the order of a plurality of conductive film layers sequentially stacked from the main surface side of the semiconductor substrate. The first conductive film group includes a first electrode pad disposed in the \(k\)th layer. The \(k\)th layer is below the \(j\)th layer and is either the \(i\)th layer or a layer above the \(i\)th layer. Among the plurality of interlayer insulating films, in the interlayer insulating film located between the \(k\)th layer and the \(j\)th layer, the film thickness of the interlayer insulating film in a region other than the region where the second inductor is disposed is thinner than the film thickness of the interlayer insulating film in the region where the second inductor is disposed. Among the plurality of interlayer insulating films, the interlayer insulating film located between the \(k\)th layer and the \(j\)th layer has a first interlayer insulating film covering the first electrode pad and a second interlayer insulating film formed on the first interlayer insulating film. In the second interlayer insulating film in a region other than the region where the second inductor is disposed, a groove is formed that surrounds the second inductor and reaches the first interlayer insulating film in a plan view seen from the main surface side.

[0010] A method for manufacturing a semiconductor device according to another embodiment is a method for manufacturing a semiconductor device including a manufacturing process of a semiconductor circuit including semiconductor elements, a first semiconductor chip having a first inductor and a second inductor. The manufacturing process of the first semiconductor chip has the following processes. Prepare a semiconductor substrate having a main surface. Form semiconductor elements on the main surface of the semiconductor substrate. A multilayer wiring structure is formed by laminating a plurality of conductive films and a plurality of interlayer insulating films that are electrically connected to the semiconductor elements and constitute a semiconductor circuit so as to cover the main surface of the semiconductor substrate. The process of forming the multilayer wiring structure includes the following processes. Form a first conductive film group including a first inductor to which a first voltage is applied and constituting a semiconductor circuit. Form an interlayer insulating film so as to cover the first conductive film group. Form a second conductive film group including a second inductor to which a second voltage different from the first voltage is applied so as to cover the interlayer insulating film. Assuming that i and j are natural numbers representing the order of the layers of the plurality of conductive films sequentially laminated from the main surface side of the semiconductor substrate, the process of forming the first conductive film group includes the process of forming the first inductor in the i-th layer, and the process of forming the second conductive film group includes the process of forming the second inductor in the j-th layer. The process of forming the multilayer wiring structure includes the process of forming at least one layer of conductive film between the i-th layer and the j-th layer. Let \(k\) be a natural number representing the order of a plurality of conductive film layers sequentially stacked from the main surface side of the semiconductor substrate. The step of forming the first conductive film group includes the step of forming a first electrode pad in a \(k\)th layer that is below the \(j\)th layer and is either the \(i\)th layer or a layer above the \(i\)th layer. The step of forming the multilayer wiring structure includes the step of making the film thickness of the interlayer insulating film in a region other than the region where the second inductor is formed thinner than the film thickness of the interlayer insulating film in the region where the second inductor is formed among the interlayer insulating films formed between the first electrode pad and the second inductor. After the step of forming the multilayer wiring structure, the method further includes a step of performing a grinding process on the back surface of the semiconductor substrate opposite to the main surface, and a step of transporting the semiconductor substrate having the back surface ground and performing a desired process on the semiconductor substrate. The step of forming an interlayer insulating film between the first electrode pad and the second inductor includes the step of forming a first interlayer insulating film so as to cover the first electrode pad, the step of forming a second interlayer insulating film that is thicker than the first interlayer insulating film and has different etching characteristics from the first interlayer insulating film so as to cover the first interlayer insulating film, and the step of removing the second interlayer insulating film in a region other than the region where the second inductor is formed. In the step of removing the second interlayer insulating film, a groove is formed in the second interlayer insulating film that surrounds the second inductor and reaches the first interlayer insulating film in a plan view seen from the main surface side.

Advantages of the Invention

[0011] According to the semiconductor device according to one embodiment, current can flow along the insulating interface, and it is possible to suppress electrical short - circuiting.

[0012] According to the method for manufacturing a semiconductor device according to another embodiment, it is possible to manufacture a semiconductor device in which current flows along the insulating interface and electrical short - circuiting is suppressed.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] First, an example of a circuit of a semiconductor device including a micro isolator according to each embodiment will be described.

[0015] As shown in FIG. 1, the semiconductor device SDV includes a first semiconductor chip SCP1 and a second semiconductor chip SCP2 as semiconductor chips SCP. A first semiconductor circuit SC1 including a semiconductor element or the like that controls driving of the load LOD is formed on the first semiconductor chip SCP1. A second semiconductor circuit SC2 including a semiconductor element or the like that drives a load LOD such as a motor is formed on the second semiconductor chip SCP2.

[0016] The first semiconductor circuit SC1 includes a control circuit CC, a reception circuit RX2, and a transmission circuit TX1. The reception circuit RX2 and the transmission circuit TX1 are electrically connected to the control circuit CC. A first inductor CL1a is electrically connected to the transmission circuit TX1. A third inductor CL1b is electrically connected to the reception circuit RX2. The first semiconductor circuit SC1 operates (drives) at about several (V).

[0017] The second semiconductor circuit SC2 includes a drive circuit DR, a reception circuit RX1, and a transmission circuit TX2. The drive circuit DR is electrically connected to the load LOD. The reception circuit RX1 and the transmission circuit TX2 are electrically connected to the drive circuit DR. A second inductor CL2a is electrically connected to the reception circuit RX1. A fourth inductor CL2b is electrically connected to the transmission circuit TX2. The second semiconductor circuit SC2 operates (drives) at about several hundreds (V) to about one thousand several hundreds (V).

[0018] The first inductor CL1a and the second inductor CL2a are arranged to face each other. The first inductor CL1a and the second inductor CL2a are magnetically coupled. The third inductor CL1b and the fourth inductor CL2b are arranged to face each other. The third inductor CL1b and the fourth inductor CL2b are magnetically coupled.

[0019] A signal is sent from the control circuit CC to the transmission circuit TX1. The signal sent to the transmission circuit TX1 flows as a current through the first inductor CL1a. When a current flows through the first inductor CL1a as a coil, an induced current flows through the second inductor CL2a as a coil by electromagnetic induction. The induced current flowing through the second inductor CL2a is sent as a signal to the drive circuit DR via the receiving circuit RX1. In this way, the signal of the control circuit CC is transmitted to the drive circuit DR.

[0020] On the other hand, a signal is sent from the drive circuit DR to the transmission circuit TX2. The signal sent to the transmission circuit TX2 flows as a current through the fourth inductor CL2b. When a current flows through the fourth inductor CL2b as a coil, an induced current flows through the third inductor CL1b as a coil by electromagnetic induction. The induced current flowing through the third inductor CL1b is sent as a signal to the control circuit CC via the receiving circuit RX2. In this way, the signal of the drive circuit DR is transmitted to the control circuit CC. By this series of operations, the driving of the load LOD is controlled. Hereinafter, the structure of the semiconductor device SDV will be specifically described.

[0021] Embodiment 1 The semiconductor device SDV according to Embodiment 1 will be described. First, an example of the overall structure of the semiconductor device SDV will be described. As shown in FIG. 2, in the semiconductor device SDV, the semiconductor chip SCP is mounted on the lead frame LFM. The first semiconductor chip SCP1 is mounted on the lead frame LFM1. The second semiconductor chip SCP2 is mounted on the lead frame LFM2.

[0022] The first semiconductor chip SCP1 is electrically connected to the corresponding lead frame LFM1, for example, by a wire (not shown). The second semiconductor chip SCP2 is electrically connected to the corresponding lead frame LFM2, for example, by a wire (not shown).

[0023] The semiconductor chip SCP mounted on the lead frame LFM is encapsulated by the encapsulating resin REN. The lead terminals LFT project from the encapsulating resin REN. The lead terminals LFT include a lead terminal LFT1 and a lead terminal LFT2. The lead terminal LFT1 is connected to the lead frame LFM1. The lead terminal LFT2 is connected to the lead frame LFM2.

[0024] A first electrode pad PEL1 is formed on the first semiconductor chip SCP1. The first electrode pad PEL1 and the corresponding lead frame LFM1 are electrically connected by a wire (not shown). Also, a first inductor CL1a and a second inductor CL2a are arranged on the first semiconductor chip SCP1. The first inductor CL1a is arranged below the second inductor CL2a so as to face the second inductor CL2a.

[0025] The second inductor CL2a is formed in a spiral shape. The first inductor CL1a is also formed in a spiral shape (not shown). One end of the second inductor CL2a is connected to the second electrode pad PEL 2a. The other end of the second inductor CL2a is connected to the second electrode pad PEL 2b. The second electrode pad PEL 2a, PEL 2b and the second semiconductor chip SCP2 are electrically connected by a wire WIR. In addition, in order to stabilize the operation of the second inductor CL2a, two second inductors CL2a may be arranged in parallel so that the winding directions are the same.

[0026] On the other hand, a fourth inductor CL2b (see FIG. 1) and a third inductor CL1b (see FIG. 1) are arranged on the second semiconductor chip SCP2 (both are not shown). The fourth inductor CL2b is arranged below the third inductor CL1b so as to face the third inductor CL1b. The third inductor CL1b is electrically connected to the first semiconductor chip SCP1 by a wire (not shown).

[0027] The first semiconductor chip SCP1 will be described in detail. As shown in FIG. 3, in the first semiconductor chip SCP1, for example, an n-channel transistor NTR and a p-channel transistor PTR are formed in a predetermined region on the main surface of the semiconductor substrate SUB. The n-channel transistor NTR and the p-channel transistor PTR form part of the first semiconductor circuit SC1.

[0028] The n-channel transistor NTR is formed in the p-type well PTW. A pair of n-type impurity regions NIR serving as source and drain are formed in the p-type well PTW. A gate electrode NGE is formed on the surface of the portion of the p-type well PTW sandwiched by the pair of n-type impurity regions NIR with a gate insulating film interposed therebetween.

[0029] The p-channel transistor PTR is formed in the n-type well NTW. A pair of p-type impurity regions PIR serving as source and drain are formed in the n-type well NTW. A gate electrode PGE is formed on the surface of the portion of the n-type well NTW sandwiched by the pair of p-type impurity regions PIR with a gate insulating film interposed therebetween.

[0030] A multilayer wiring structure MLS is formed so as to cover the main surface of the semiconductor substrate SUB. In the multilayer wiring structure MLS, a plurality of conductive films CDL and a plurality of interlayer insulating films ILL are laminated. The conductive film CDL as wiring is electrically connected to the n-channel transistor NTR, the p-channel transistor PTR, etc. The conductive film CDL forms part of the first semiconductor circuit SC1.

[0031] An interlayer insulating film IL1 is formed on the main surface of the semiconductor substrate SUB so as to cover the n-channel transistor NTR and the p-channel transistor PTR. A contact plug PG is formed so as to penetrate the interlayer insulating film IL1. An interlayer insulating film IL2 is formed so as to cover the interlayer insulating film IL1. A conductive film ML1 is formed in the groove of the interlayer insulating film IL2. The conductive film ML1 includes the first-layer wiring and the first-layer first inductor CL1a.

[0032] An interlayer insulating film IL3 is formed so as to cover the interlayer insulating film IL2. A via VA1 is formed so as to penetrate the interlayer insulating film IL3. An interlayer insulating film IL4 is formed so as to cover the interlayer insulating film IL3. A conductive film ML2 is formed in a groove of the interlayer insulating film IL4. The conductive film ML2 includes a second-layer wiring and a second-layer first inductor CL1a. The second-layer first inductor CL1a and the first-layer first inductor CL1a are electrically connected by the via VA1.

[0033] An interlayer insulating film IL5 is formed so as to cover the interlayer insulating film IL4. A via VA2 is formed so as to penetrate the interlayer insulating film IL5. A conductive film ML3 is formed on the surface of the interlayer insulating film IL5. The conductive film ML3 includes a third-layer wiring and a first electrode pad PEL1.

[0034] An interlayer insulating film IL6 is formed so as to cover the conductive film ML3. An interlayer insulating film IL7 is formed so as to cover the interlayer insulating film IL6. An interlayer insulating film IL8 is formed so as to cover the interlayer insulating film IL7. The interlayer insulating film IL8 is formed in a region where a second inductor CL2a, a second electrode pad PEL2a, etc. are arranged. The interlayer insulating film IL8 is not formed in a region where the second inductor CL2a, etc. are not arranged.

[0035] A second inductor CL2a and a second electrode pad PEL2a are formed on the surface of the interlayer insulating film IL8. An interlayer insulating film IL9 is formed so as to cover the second inductor CL2a and the interlayer insulating film IL7, etc. A polyimide film PIL is formed so as to cover the interlayer insulating film IL9. An opening KP1 for exposing the surface of the first electrode pad PEL1 is formed. An opening KP2 for exposing the surface of the second electrode pad PEL2a is formed. The second electrode pad PEL2a is electrically connected to a second semiconductor chip SCP2 by a wire WIR.

[0036] In the first semiconductor chip SCP1 of the semiconductor device SDV described above, the first inductor CL1a is formed by the conductive film ML1 and the conductive film ML2 (the i-th layer). The second inductor CL2a is formed by the conductive film ML4 (the j-th layer). That is, a conductive film ML3 is disposed as at least one layer of conductive film CDL between the first inductor CL1a to which a low voltage is applied and the second inductor CL2a to which a high voltage is applied. In other words, the first inductor CL1a to which a low voltage is applied is formed two layers (the layers of the conductive film CDL) below the second inductor CL2a to which a high voltage is applied.

[0037] The plurality of conductive films CDL in the multilayer wiring structure MLS include a conductive film CDL (the first conductive film group) that constitutes a first semiconductor circuit including the first electrode pad PEL1 and the first inductor CL1a, and a conductive film CDL (the second conductive film group) that constitutes the second inductor CL2a and the second electrode pad PEL2a and the like.

[0038] That is, the conductive film CDL includes the conductive films ML1, ML2, and ML3 (the first conductive film group) to which a low voltage is applied and the conductive film ML4 (the second conductive film group) to which a high voltage is applied. The conductive films ML1, ML2, and ML3 to which a low voltage is applied are located on the side (layer) closer to the main surface of the semiconductor substrate SUB, which is below the conductive film ML4 to which a high voltage is applied.

[0039] Next, an example of a method for manufacturing the first semiconductor chip SCP1 in the semiconductor device SDV described above will be described.

[0040] First, as shown in FIG. 4, a semiconductor substrate SUB having a main surface is prepared. Next, the semiconductor substrate SUB is subjected to a photolithography process, and p-type impurities and n-type impurities are respectively implanted. Thereby, a p-type well PTW and an n-type well NTW are formed. Next, the semiconductor substrate SUB is subjected to a photolithography process, and an n-type impurity is implanted, whereby an n-type impurity region NIR is formed in the p-type well PTW. The semiconductor substrate SUB is subjected to a photolithography process, and a p-type impurity is implanted, whereby a p-type impurity region PIR is formed in the n-type well NTW.

[0041] Next, a gate electrode NGE is formed on the p-type well PTW with a gate insulating film interposed therebetween. A gate electrode PGE is formed on the n-type well NTW with a gate insulating film interposed therebetween. Next, an interlayer insulating film IL1 is formed so as to cover the gate electrode NGE and the gate electrode PGE. Next, a contact plug PG is formed to penetrate the interlayer insulating film IL1. Next, an interlayer insulating film IL2 is formed so as to cover the interlayer insulating film IL1.

[0042] Next, a groove is formed in the interlayer insulating film IL2, and a conductive film ML1 is formed in the groove. At this time, a first inductor CL1a (conductive film ML1) is formed simultaneously. Next, an interlayer insulating film IL3 is formed so as to cover the interlayer insulating film IL2. Next, a via VA1 is formed to penetrate the interlayer insulating film IL3. Next, an interlayer insulating film IL4 is formed so as to cover the interlayer insulating film IL3.

[0043] Next, a groove is formed in the interlayer insulating film IL4, and a conductive film ML2 is formed in the groove. At this time, a first inductor CL1a (conductive film ML2) is formed simultaneously. The first inductor CL1a (conductive film ML2) and the first inductor CL1a (conductive film ML1) are electrically connected by the via VA1. Next, an interlayer insulating film IL5 is formed so as to cover the interlayer insulating film IL4.

[0044] Next, a via VA2 is formed to penetrate the interlayer insulating film IL5. Next, a conductive film ML3 is patterned on the surface of the interlayer insulating film IL5. At this time, a first electrode pad PEL1 (conductive film ML3) is formed simultaneously. As a result, a conductive film CDL serving as a first conductive film group is formed. Next, an interlayer insulating film IL6 is formed so as to cover the conductive film ML3. Next, an interlayer insulating film IL7 is formed so as to cover the interlayer insulating film IL6.

[0045] Next, as shown in FIG. 5, an interlayer insulating film IL8 is formed so as to cover the interlayer insulating film IL7. The thickness of the interlayer insulating film IL8 is made thicker than the film thicknesses of other interlayer insulating films such as the interlayer insulating film IL7, and is, for example, about 4 μm. By making the film thickness of the interlayer insulating film IL8 thick, the withstand voltage between the first inductor CL1a and the second inductor CL2a (see FIG. 6 etc.) formed in the next step is ensured.

[0046] Next, as shown in FIG. 6, a conductive film ML4 is patterned on the surface of the interlayer insulating film IL8. At this time, the second inductor CL2a, the second electrode pad PEL2a, etc. are formed simultaneously. As a result, a conductive film CDL that becomes the second conductive film group is formed. Note that by patterning the conductive film ML4 before the partial removal of the interlayer insulating film IL8 performed in the next step, defocus in the photolithography process can be suppressed. Also, the conductive film CDL that becomes the first conductive film group is formed on the side (layer) closer to the main surface of the semiconductor substrate SUB than the conductive film CDL that becomes the second conductive film group, thereby preventing an electrical short circuit along the insulating interface.

[0047] Next, the relatively thick interlayer insulating film IL8 is partially removed. As shown in FIG. 7, by subjecting the interlayer insulating film IL8 to photolithography and etching processes, the portion of the interlayer insulating film IL8 located in the region where the second inductor CL2a, the second electrode pad PEL2a, etc. are arranged is left, and the portions of the interlayer insulating film IL8 located in other regions are removed.

[0048] Next, as shown in FIG. 8, an interlayer insulating film IL9 is formed so as to cover the second inductor CL2a and the interlayer insulating film IL7 etc. Next, by subjecting the interlayer insulating film IL9 to photolithography and etching processes, an opening KP1a for exposing the first electrode pad PEL1 is formed. An opening KP2a for exposing the second electrode pad PEL2a is formed.

[0049] Next, as shown in FIG. 9, a polyimide film PIL is formed so as to cover the interlayer insulating film IL9. Next, by performing photolithography and etching processes on the polyimide film PIL, an opening KP1b and an opening KP2b are formed. An opening KP1 that exposes the first electrode pad PEL1 is formed by the opening KP1a and the opening KP1b. An opening KP2 that exposes the second electrode pad PEL2a is formed by the opening KP2a and the opening KP2b. Next, as shown in FIG. 10, by performing a grinding process on the back surface of the semiconductor substrate SUB, the thickness of the semiconductor substrate SUB is reduced (back surface grinding process).

[0050] Next, for example, an electrical test (wafer test) of the semiconductor device is performed. Next, by dicing the semiconductor substrate SUB, it is taken out as the first semiconductor chip SCP1. Next, the first semiconductor chip SCP1 is mounted on a lead frame LFM1 (see FIG. 2). A second semiconductor chip SCP2 formed in the same manner as the first semiconductor chip SCP1 is mounted on a lead frame LFM2 (see FIG. 2).

[0051] Next, the first semiconductor chip SCP1 and the second semiconductor chip SCP2 mounted on the lead frame LFM are placed in a mold (not shown). By filling the mold with a molding resin, the first semiconductor chip SCP1 and the second semiconductor chip SCP2 are encapsulated. Thereafter, the semiconductor device SDV encapsulated with the encapsulating resin REN is taken out of the mold (see FIG. 2). By performing a desired bending process on the lead terminals LFT protruding from the encapsulating resin REN, the semiconductor device SDV is completed.

[0052] In the semiconductor device SDV described above, an electrical short circuit along the insulating interface can be prevented. Also, warping of the semiconductor substrate SUB due to back surface grinding of the semiconductor substrate SUB can be reduced. These will be described in comparison with the semiconductor device according to the comparative example.

[0053] As shown in FIG. 11, in the first semiconductor chip CSP1 of the semiconductor device CSDV according to the comparative example, an n-channel transistor NTR and a p-channel transistor PTR are formed in a predetermined region on the main surface of the semiconductor substrate SUB. The n-channel transistor NTR and the p-channel transistor PTR constitute a part of the first semiconductor circuit SC1.

[0054] An interlayer insulating film ZL1 is formed on the main surface of the semiconductor substrate SUB so as to cover the n-channel transistor NTR and the p-channel transistor PTR. A contact plug PG is formed so as to penetrate the interlayer insulating film ZL1. An interlayer insulating film ZL2 is formed so as to cover the interlayer insulating film ZL1. A conductive film ML1 is formed in a groove of the interlayer insulating film ZL2. The conductive film ML1 includes a first-layer wiring and a first-layer first inductor CL1a.

[0055] An interlayer insulating film ZL3 is formed so as to cover the interlayer insulating film ZL2. A via VA1 is formed so as to penetrate the interlayer insulating film ZL3. An interlayer insulating film ZL4 is formed so as to cover the interlayer insulating film ZL3. A conductive film ML2 is formed in a groove of the interlayer insulating film ZL4. The conductive film ML2 includes a second-layer wiring and a second-layer first inductor CL1a. An interlayer insulating film ZL5 is formed so as to cover the interlayer insulating film ZL4.

[0056] A via VA2 is formed so as to penetrate the interlayer insulating film ZL5. An interlayer insulating film ZL6 is formed so as to cover the interlayer insulating film ZL5. A conductive film ML3 is formed in a groove of the interlayer insulating film ZL6. An interlayer insulating film ZL7 is formed so as to cover the interlayer insulating film ZL6. An interlayer insulating film ZL8 is formed so as to cover the interlayer insulating film ZL8. A via VA3 is formed so as to penetrate the interlayer insulating film ZL7 and the interlayer insulating film ZL8.

[0057] A conductive film ML4 is formed on the surface of the interlayer insulating film ZL8. The conductive film ML4 includes a first electrode pad PEL1, a second inductor CL2a, and a second electrode pad PEL2a in addition to the wiring of the fourth layer. The first electrode pad PEL1 is electrically connected to the conductive film ML3 of the third layer. An interlayer insulating film ZL9 is formed so as to cover the conductive film ML4. A polyimide film PIL is formed so as to cover the interlayer insulating film ZL9. An opening KP1 for exposing the first electrode pad PEL1 is formed. An opening KP2 for exposing the second electrode pad PEL2a is formed.

[0058] In the semiconductor device SDV according to the comparative example, among the conductive films ML4 arranged in the fourth layer, high voltages are applied to the conductive films ML4 constituting the second inductor CL2a and the second electrode pad PEL2a, respectively. On the other hand, low voltages are applied to the conductive films ML4 other than the conductive films ML4 constituting the second inductor CL2a and the second electrode pad PEL2a, respectively.

[0059] That is, in the first semiconductor chip CSCP1 according to the comparative example, a conductive film ML4 to which a low voltage is applied and a conductive film ML4 to which a high voltage is applied are formed on the surface of the interlayer insulating film ZL8. For this reason, there is a possibility that an electrical short circuit ES may occur due to current flowing along the insulating interface between the conductive film ML4 to which a low voltage is applied and the conductive film ML4 to which a high voltage is applied.

[0060] In addition, it is necessary to ensure the breakdown voltage between the first inductor CL1a to which a low voltage is applied and the second inductor CL2a to which a high voltage is applied. For this reason, in the first semiconductor chip CSCP1 according to the comparative example, an interlayer insulating film ZLL including an interlayer insulating film ZL8 having a relatively thick film thickness (about several μm) is formed between the first inductor CL1a and the second inductor CL2a.

[0061] In the process of manufacturing the first semiconductor chip CSCP1, the interlayer insulating film ZLL including the interlayer insulating film ZL8 is formed on the entire surface of the semiconductor substrate SUB. When a series of wafer processes for the semiconductor substrate SUB are completed, the semiconductor substrate SUB is then sent to an assembly process (assembly process) through a back grinding process.

[0062] In the back grinding process, a grinding process is performed on the back surface of the semiconductor substrate SUB so that the thickness of the semiconductor substrate SUB becomes thinner than the original thickness (refer to the two-dot chain line in FIG. 11). Moreover, on the entire surface of the semiconductor substrate SUB, the interlayer insulating film ZLL including the interlayer insulating film ZL8 having a relatively thick film thickness is in a formed state. The interlayer insulating film ZL8 and the like having a relatively thick film thickness have film stress (compressive stress).

[0063] Therefore, due to the film stress of the interlayer insulating film ZLL, there is a risk that the semiconductor substrate SUB, which has become thinner than the original thickness, will be prone to warping. Specifically, as shown in FIG. 12, it is assumed that due to the compressive stress of the interlayer insulating film ZLL (the interlayer insulating film ZL8 and the like), the semiconductor substrate SUB will warp so as to be convex upward.

[0064] In the processes after back grinding and the assembly process, there is a process of transporting the semiconductor substrate SUB by a transport arm TAM (refer to FIG. 13 etc.). At this time, as shown in FIGS. 13 and 14, when the semiconductor substrate SUB is warped, it is assumed that the semiconductor substrate SUB will not be well adsorbed by the transport arm TAM and a transport error will occur.

[0065] Also, in the processes after back grinding and the assembly process, there is a process of performing a desired process on the semiconductor substrate SUB in a state where the semiconductor substrate SUB is placed on a wafer stage WSG (refer to FIG. 15). At this time, as shown in FIG. 15, when the semiconductor substrate SUB is warped, it is assumed that the semiconductor substrate SUB will not be well adsorbed by the wafer stage WSG and an adsorption error will occur.

[0066] For the semiconductor device CSDV (first semiconductor chip CSCP1) according to the comparative example, the semiconductor device SDV (first semiconductor chip SCP1) according to Embodiment 1 has the following effects.

[0067] First, in the first semiconductor chip SCP1 according to Embodiment 1, the conductive film CDL includes conductive films ML1, ML2, ML3 (first conductive film group) to which a low voltage is applied and a conductive film ML4 (second conductive film group) to which a high voltage is applied. Only the conductive film ML4 is formed on the surface of the interlayer insulating film IL8 on which the conductive film ML4 to which a high voltage is applied is formed.

[0068] Among the conductive films ML1, ML2, ML3 to which a low voltage is applied, the uppermost conductive film ML3 is formed on the surface of the interlayer insulating film IL5. That is, the conductive films ML1, ML2, ML3 to which a low voltage is applied are located on the side (layer) closer to the main surface of the semiconductor substrate SUB, below the conductive film ML4 to which a high voltage is applied.

[0069] Thereby, the flow of current along the insulating interface between the conductive film ML3 etc. to which a low voltage is applied and the conductive film ML4 to which a high voltage is applied is suppressed, and the occurrence of an electrical short circuit can be prevented.

[0070] Also, in the first semiconductor chip SCP1, an interlayer insulating film ILL including an interlayer insulating film IL8 having a relatively thick film thickness (about several μm) is formed between the first inductor CL1a and the second inductor CL2a. Thereby, a withstand voltage can be ensured between the first inductor CL1a to which a low voltage is applied and the second inductor CL2a to which a high voltage is applied.

[0071] Furthermore, the interlayer insulating film IL8 having a relatively thick film thickness, which is interposed between the first inductor CL1a and the second inductor CL2a, is not formed in a region other than the region where the second inductor CL2a is disposed. The interlayer insulating film IL8 located in a region other than the region where the second inductor CL2a is disposed will be removed after the second inductor CL2a is formed (see FIG. 7).

[0072] Therefore, in the interlayer insulating film ILL, the film stress (compressive stress) of the interlayer insulating film IL8 having a relatively large film thickness is reduced. As a result, as shown in FIG. 16, the semiconductor substrate SUB that has become thinner than the original thickness is suppressed from warping upward so as to be convex, and becomes flatter than in the comparative example.

[0073] As a result, in the processes after back grinding and the assembly process, as shown in FIG. 17, the semiconductor substrate SUB can be satisfactorily adsorbed by the transfer arm TAM, preventing the occurrence of transfer errors. Further, as shown in FIG. 18, the semiconductor substrate SUB can be satisfactorily adsorbed by the wafer stage WSG, preventing the occurrence of adsorption errors.

[0074] Embodiment 2 Here, the film type of the interlayer insulating film ILL interposed between the first inductor CL1a and the second inductor CL2a is specified.

[0075] As shown in FIG. 19, an interlayer insulating film ILL including an interlayer insulating film IL7 (first interlayer insulating film) and an interlayer insulating film IL8 (second interlayer insulating film) is formed between the first inductor CL1a and the second inductor CL2a. The interlayer insulating film IL8 has a relatively large film thickness (about several μm). On the other hand, the interlayer insulating film IL7 is formed in a region other than the region where the second inductor CL2a is arranged, such as a region where the first electrode pad PEL1 is arranged, but the interlayer insulating film IL8 is not formed.

[0076] That is, the interlayer insulating film IL7 is formed across the region where the second inductor CL2a is arranged and the region other than the region where the second inductor CL2a is arranged. Note that the interlayer insulating film IL7 may be partially formed, for example, in a region that functions as an etching stopper, in a region other than the region where the second inductor CL2a is arranged. The interlayer insulating film IL8 is formed in the region where the second inductor CL2a is arranged and is not formed in the region other than the region where the second inductor CL2a is arranged.

[0077] Therefore, the film thickness TKA of the interlayer insulating film IL7 located in a region other than the region where the second inductor CL2a is disposed is smaller than the film thicknesses TKB of the interlayer insulating films IL7 and IL8 interposed between the first inductor CL1a and the second inductor CL2a.

[0078] In the semiconductor device SDV (first semiconductor chip SCP1) according to Embodiment 2, films having different etching characteristics from each other are applied as the film types of the interlayer insulating film IL7 and the interlayer insulating film IL8. Here, a silicon nitride film is applied as an example of the interlayer insulating film IL7. A silicon oxide film is applied as an example of the interlayer insulating film IL8. Note that for other configurations, since they are the same as the configuration of the semiconductor device SDV shown in FIG. 3, the same reference numerals are given to the same members, and the description thereof will not be repeated unless necessary.

[0079] In the semiconductor device SDV described above, in addition to the effects described for the semiconductor device SDV described above, the following effects can be obtained.

[0080] That is, in the process of manufacturing the first semiconductor chip SCP1, when removing the interlayer insulating film IL8 located in a region other than the region where the second inductor CL2a is disposed, the interlayer insulating film IL8 can be removed using the interlayer insulating film IL7 as an etching stopper. In this case, the silicon nitride film (interlayer insulating film IL7) can be left, and the silicon oxide film (interlayer insulating film IL8) can be surely removed.

[0081] Thereby, for example, compared with the case where the interlayer insulating film IL7 and the interlayer insulating film IL8 are formed by a single interlayer insulating film ILL, the thickness of the interlayer insulating film ILL located in a region other than the region where the second inductor CL2a is disposed can be accurately controlled.

[0082] In the semiconductor device SDV (first semiconductor chip SCP1) described above, the case where a silicon nitride film is applied as the interlayer insulating film IL7 and a silicon oxide film is applied as the interlayer insulating film IL8 has been described. The film types are not limited to these, and other film types with different etching characteristics may be applied as long as the interlayer insulating film IL8 can be removed while leaving the interlayer insulating film IL7.

[0083] Embodiment 3 Here, a modified example of the structure for reducing the film stress of the interlayer insulating film will be described. As shown in FIGS. 20 and 21, in the first semiconductor chip SCP1 (semiconductor device SDV), a groove LGS is formed in the interlayer insulating film IL8 located in a region other than the region where the second inductor CL2a is arranged. The groove LGS is formed, for example, in a lattice pattern. Note that for other configurations, since they are the same as the configuration of the semiconductor device SDV shown in FIG. 3, the same reference numerals are assigned to the same members, and the description thereof will not be repeated unless necessary.

[0084] Next, an example of the manufacturing method of the first semiconductor chip SCP1 (semiconductor device SDV) described above will be described. After going through the same processes as those shown in FIGS. 4 to 6, as shown in FIG. 22, the groove LGS is formed by performing photolithography and etching on the interlayer insulating film IL8. The groove LGS is formed so as to penetrate the interlayer insulating film IL8 and reach the interlayer insulating film IL7. The groove LGS is formed, for example, in a lattice pattern in a plan view of the semiconductor substrate SUB.

[0085] As described above, by applying film types with different etching characteristics as the interlayer insulating film IL7 and the interlayer insulating film IL8, the interlayer insulating film IL8 can be etched while leaving the interlayer insulating film IL7.

[0086] Next, in the same manner as the process shown in FIG. 8, as shown in FIG. 23, an interlayer insulating film IL9 is formed so as to cover the second inductor CL2a and the interlayer insulating film IL7 and the like. Also, an opening KP1a for exposing the first electrode pad PEL1 is formed. An opening KP2a for exposing the second electrode pad PEL2a is formed.

[0087] Next, in the same manner as the process shown in FIG. 9, as shown in FIG. 24, a polyimide film PIL is formed so as to cover the interlayer insulating film IL9. Also, an opening KP1b and an opening KP2b are formed. Next, in the same manner as the process shown in FIG. 10, as shown in FIG. 25, by performing a grinding process on the back surface of the semiconductor substrate SUB, the thickness of the semiconductor substrate SUB is reduced (back surface grinding process). Thereafter, through an assembly process, a semiconductor device SDV (see, for example, FIG. 2) is completed.

[0088] In the above-described first semiconductor chip SCP1 (semiconductor device SDV), lattice-shaped grooves LGS are formed in the interlayer insulating film IL8 located in a region other than the region where the second inductor CL2a is disposed. As a result, in the interlayer insulating film ILL, the film stress (compressive stress) of the interlayer insulating film IL8 having a relatively large film thickness is reduced, and it is possible to suppress the semiconductor substrate SUB, which has become thinner than the original thickness, from warping upward so as to be convex.

[0089] As a result, in the same manner as described in Embodiment 1, for example, it is possible to prevent a transfer error of the semiconductor substrate SUB by a transfer arm. Also, it is possible to prevent an adsorption error of the semiconductor substrate SUB on the wafer stage.

[0090] Note that, in the above-described semiconductor device SDV, the first inductor CL1a to which a low voltage is applied is disposed on the lower side (the side closer to the main surface), and the first semiconductor chip SCP1 in which the second inductor CL2a to which a high voltage is applied is disposed on the upper side has been described as an example. In the second semiconductor chip SCP2, the high-low relationship of the voltages is reversed, and the inductor to which a high voltage is applied is disposed on the lower side, and the inductor to which a low voltage is applied is disposed on the upper side (not shown). Such a structure can also be applied.

[0091] Regarding the semiconductor devices described in each embodiment, various combinations can be made as necessary.

[0092] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0093] SDV semiconductor device, SCP semiconductor chip, SCP1 first semiconductor chip, SC1 first semiconductor circuit, TX1 transmission circuit, RX2 reception circuit, CC control circuit, PEL1 first electrode pad, PEL2a, PEL2b second electrode pads, SCP2 second semiconductor chip, SC2 second semiconductor circuit, RX1 reception circuit, TX2 transmission circuit, DRC drive circuit, LOD load, CL inductor, CL1a first inductor, CL2a second inductor, CL1b third inductor, CL2b fourth inductor, LFM, LFM1, LFM2 lead frame, LFT, LFT1, LFT2 lead terminal, WIR wire, REN encapsulating resin, SUB semiconductor substrate, PTW p-type well, NGE gate electrode, NIR n-type impurity region, NTR n-channel transistor, NTW n-type well, PGE gate electrode, PIR p-type impurity region, PTR p-channel transistor, MLS multilayer wiring structure, ILL, IL1, IL2, IL3, IL4, IL5, IL6, IL7, IL8, IL9 interlayer insulating film, PIL polyimide film, CDL, ML1, ML2, ML3, ML4 conductive film, PG contact plug, VA1, VA2 via, KP1, KP1a, KP1b, KP2, KP2a, KP2b opening, LGS groove.

Claims

1. A semiconductor device including a first semiconductor chip on which a first semiconductor circuit, a first inductor, and a second inductor are formed, wherein the first semiconductor chip includes a semiconductor substrate having a main surface, and a multilayer wiring structure formed to cover the main surface of the semiconductor substrate and including a plurality of conductive films and a plurality of interlayer insulating films stacked thereon, and the plurality of conductive films in the multilayer wiring structure include a first conductive film group that includes the first inductor to which a first voltage is applied and constitutes the first semiconductor circuit, and a second conductive film group that includes the second inductor to which a second voltage different from the first voltage is applied, and the first conductive film group is disposed in a layer closer to the main surface than the layer in which the second conductive film group is disposed, where i and j are natural numbers representing the order of the layers of the plurality of conductive films sequentially stacked from the main surface side of the semiconductor substrate, the first inductor is disposed in the i-th layer, the second inductor is disposed in the j-th layer, at least one layer of the conductive film is disposed between the i-th layer and the j-th layer, where k is a natural number representing the order of the layers of the plurality of conductive films sequentially stacked from the main surface side of the semiconductor substrate, the first conductive film group includes a first electrode pad disposed in the k-th layer, the k-th layer is below the j-th layer and is either the i-th layer or a layer above the i-th layer, in the interlayer insulating film located between the k-th layer and the j-th layer among the plurality of interlayer insulating films, the film thickness of the interlayer insulating film located in a region other than the region where the second inductor is disposed is thinner than the film thickness of the interlayer insulating film located in the region where the second inductor is disposed, among the plurality of interlayer insulating films, the interlayer insulating film located between the k-th layer and the j-th layer includes a first interlayer insulating film covering the first electrode pad, and a second interlayer insulating film formed on the first interlayer insulating film, and in the second interlayer insulating film located in a region other than the region where the second inductor is disposed, a groove is formed that surrounds the second inductor and reaches the first interlayer insulating film in a plan view seen from the main surface side, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the first interlayer insulating film includes a silicon nitride film, and the second interlayer insulating film includes a silicon oxide film.

3. The semiconductor device according to claim 1 or 2, wherein the second conductive film group is electrically connected to the second inductor and includes second electrode pads formed on the j-th layer.

4. A semiconductor device comprising a second semiconductor chip disposed at a distance from the first semiconductor chip and supplied with the second voltage, wherein the second semiconductor chip is electrically connected to the second inductor via the second electrode pad, according to claim 3.

5. A method of manufacturing a semiconductor device including a manufacturing process of a semiconductor circuit including semiconductor elements, a first semiconductor chip having a first inductor and a second inductor, wherein the manufacturing process of the first semiconductor chip includes: preparing a semiconductor substrate having a main surface; forming the semiconductor elements on the main surface of the semiconductor substrate; forming a multilayer wiring structure by laminating a plurality of conductive films and a plurality of interlayer insulating films that are electrically connected to the semiconductor elements so as to cover the main surface of the semiconductor substrate; and the step of forming the multilayer wiring structure includes: forming a first conductive film group including the first inductor to which a first voltage is applied and constituting the semiconductor circuit; forming the interlayer insulating film so as to cover the first conductive film group; forming a second conductive film group including the second inductor to which a second voltage different from the first voltage is applied so as to cover the interlayer insulating film; and assuming that i and j are natural numbers representing the order of layers of the plurality of conductive films sequentially laminated from the main surface side of the semiconductor substrate, the step of forming the first conductive film group includes forming the first inductor in the i-th layer; the step of forming the second conductive film group includes forming the second inductor in the j-th layer; the step of forming the multilayer wiring structure includes forming at least one layer of the conductive film between the i-th layer and the j-th layer; assuming that k is a natural number representing the order of layers of the plurality of conductive films sequentially laminated from the main surface side of the semiconductor substrate, the step of forming the first conductive film group includes forming a first electrode pad in a k-th layer below the j-th layer and either the i-th layer or above the i-th layer. The step of forming the multilayer wiring structure includes a step of making the film thickness of the interlayer insulating film located in a region other than the region where the second inductor is formed, among the interlayer insulating films formed between the first electrode pad and the second inductor, thinner than the film thickness of the interlayer insulating film located in the region where the second inductor is formed. After the step of forming the multilayer wiring structure, a step of performing a grinding process on the back surface of the semiconductor substrate opposite to the main surface; a step of transporting the semiconductor substrate having the grinding process performed on the back surface and performing a desired process on the semiconductor substrate; further comprising: The step of forming the interlayer insulating film between the first electrode pad and the second inductor includes: a step of forming a first interlayer insulating film so as to cover the first electrode pad; a step of forming a second interlayer insulating film thicker than the first interlayer insulating film and having different etching characteristics from the first interlayer insulating film so as to cover the first interlayer insulating film; a step of removing the second interlayer insulating film located in a region other than the region where the second inductor is formed; comprising: In the step of removing the second interlayer insulating film, a groove is formed in the second interlayer insulating film so as to surround the second inductor and reach the first interlayer insulating film in a plan view seen from the main surface side. A method of manufacturing a semiconductor device.

6. In the step of forming the first interlayer insulating film, a silicon nitride film is formed. In the step of forming the second interlayer insulating film, a silicon oxide film is formed. The method of manufacturing a semiconductor device according to claim 5.

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