Storage Device and Control Method of Storage Controller

Abstract

To make it possible to, when a processor of a controller stops, continuously respond to an I / O request from a host apparatus without including a special control functional unit as in a local router.SOLUTION: A front-end interface of a controller includes a plurality of corresponding queueing interfaces for each processor of the controller, and an enqueueing destination of a host I / O command can be switched in response to an instruction from a processor. When a controller OS restarts, the controller waits for completion of a host I / O and executes controller blocking and restarting during setup. Therefore, to determine whether this process is possible, the processor gives an instruction to switch a queue and waits until a switch source queue is empty.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a storage device including a front-end interface and a processor.

Background Art

[0002] In a storage device, in order to improve reliability, a plurality of storage controllers (hereinafter simply referred to as controllers) that control the storage device are provided so that even if a failure occurs in one of the controllers and the operation stops, the remaining controllers can continue the operation. A typical number of such controllers is 2.

[0003] For example, Patent Document 1 discloses an example in which a controller unit of a storage device is configured by two controllers. In this case, each controller is equipped with a processor for controlling the system, and a non-transparent bridge (NTB) is provided in a switch connected to each processor.

[0004] One of the roles played by this NTB is an address conversion function between the addresses used by the processors connected to each switch and other addresses. In particular, when connecting two controllers, the addresses used by each processor need to be converted from the address used by the processor of one controller to the address used by the processor of the other controller because each processor controls and manages them. For example, since each processor assigns independent addresses to the connected memory, protocol chips, etc., they cannot be directly connected and use the same address. The two processors are connected by an NTB between them, and by converting the destination address of the packet passing through the NTB, data transfer between them becomes possible.

[0005] Also, when each processor stops, the addresses used by each processor become unavailable because the controlling processor is no longer present. For example, it becomes unclear which memory was assigned which address, and thus the addresses cannot be used.

[0006] In a storage device, in addition to failures, the processor of the controller may need to be stopped due to, for example, an update of the OS (OPERATING SYSTEM) of the controller. In the storage device, I / O (Input / Output) communication is performed for data input / output with a host device. The protocol used for this I / O communication with the host device is, for example, FIBRE CHANNEL.

[0007] The controller is equipped with a front-end interface that includes a protocol chip for controlling the protocol used for such I / O communication, together with a processor. In such a situation, when the processor of the controller stops, the processor connected to the front-end interface becomes unavailable, and the controller does not respond to I / O requests from the host device. From the perspective of the host device, it appears that the storage device has temporarily shut down. To recover, it is necessary to reconnect the host device to the remaining controller that is still operating.

[0008] To solve this problem, in the controller, it is conceivable to automatically connect the I / O requests from the host device to a controller that has a processor not stopped by, for example, an OS update.

[0009] For example, in the configuration described in Patent Document 1, since two processors for controlling the system are installed, when the processor of one controller stops, it is conceivable to transmit the I / O requests from the host device to the processor of the other controller.

[0010] In addition, Patent Document 2 discloses an example of a storage device including a local router having a function capable of automatically switching I / O communication even when the processor of the controller stops by automatically distributing access destinations from the front-end interface to each controller.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0012] In the technology described in Patent Document 1, at most one NTB is mounted on each controller, and each front-end interface uses the address controlled by the processor of its own controller and does not use the address controlled by the other processor. Therefore, when the processor of the controller stops, the address becomes unusable, so there is no available address, and each front-end interface cannot transmit a request from the host device to the other processor.

[0013] In addition, in the technology described in Patent Document 2, since the local router requires complex control, it may be necessary to mount some processor to perform program control. In that case, when updating the OS of the local router itself, it is necessary to stop and restart the local router. In such a case, the function of automatically switching I / O communication between the local router and the host device cannot be used, and the I / O communication with the host device is disconnected.

[0014] Therefore, a technology is desired that enables continuous response to I / O requests from a host device without providing a special control function unit such as a local router when the processor of the controller stops.

Means for Solving the Problem

[0015] One embodiment of the present invention is a storage device that processes requests from a host device, includes a plurality of storage controllers, and a first storage controller among the plurality of storage controllers includes a first front-end interface that controls a protocol for communication with the host device and a first processor that controls the storage device. A second storage controller among the plurality of storage controllers includes a second processor that controls the storage device. The first storage controller further includes a first address conversion unit that converts a first address used by the first processor and a second address used by the first front-end interface, a second address conversion unit that converts a third address used by the second processor and the second address used by the first front-end interface, a first outbound queue that controls data transfer from the first front-end interface to the first processor through the first address conversion unit, and a first inbound queue that controls data transfer from the first processor to the first front-end interface through the first address conversion unit. The second storage controller further includes a second outbound queue that controls data transfer from the first front-end interface to the second processor through the second address conversion unit and a second inbound queue that controls data transfer from the second processor to the first front-end interface through the second address conversion unit. After receiving a first enqueue destination switching instruction that designates the second outbound queue as an enqueue destination for a request from the host device, the first front-end interface switches the enqueue destination to the second outbound queue from a request from the host device to which an identifier of a series of operations related to a new host request to be received next is assigned.

Advantages of the Invention

[0016] According to one aspect of the present invention, even if the processor of one of the controllers constituting the dual controller stops processing, the processor of the other controller can take over the I / O request from the host device and continue to respond. Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0017]

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Figure 15

Modes for Carrying Out the Invention

[0018] Hereinafter, several embodiments of the present invention will be described with reference to the drawings. In all the embodiments, it is assumed that the components denoted by the same reference numerals are substantially the same. Also, since the processing executed by the processor is performed using appropriate storage resources (e.g., memory) and communication interface devices (e.g., communication ports), the subject of the processing may be the processor. The processor may have dedicated hardware in addition to the CPU (Central Processing Unit).

Embodiment

[0019] With reference to FIGS. 1 to 9, the storage device according to Embodiment 1 will be described.

[0020] FIG. 1 is a diagram showing the storage device according to Embodiment 1.

[0021] The storage device 100 includes controllers 110 and 120, and a drive box 130 having a plurality of hard disk drives or a plurality of solid state drives.

[0022] The controller 110 includes a processor 111, a memory 112, a front-end interface 113, a back-end interface 114, a PCIe (PCI Express) switch 115, and a management processor 116. Similarly, the controller 120 includes a processor 121, a memory 122, a front-end interface 123, a back-end interface 124, a PCIe switch 125, and a management processor 126. The processors 111 and 121 each have a plurality of processor cores (not shown) inside.

[0023] A host device (not shown) that accesses the storage device 100 is connected to the storage device 100 via the front-end interfaces 113 and 123. The host device and the front-end interfaces 113 and 123 are connected by a transmission line such as a fiber channel cable or an Ethernet cable.

[0024] Alternatively, the host device and the front-end interfaces 113 and 123 may be connected via a storage area network composed of a plurality of transmission lines and a plurality of switches. The front-end interfaces 113 and 123 convert the data transfer protocol between the host device and the storage device 100 and the data transfer protocol within the controllers 110 and 120. The front-end interfaces 113 and 123 include protocol chips.

[0025] The drive box 130 is connected to the controllers 110 and 120 via the back-end interfaces 114 and 124. The back-end interfaces 114 and 124 convert the data transfer protocol within the controllers 110 and 120 and the data transfer protocol between the controllers 110 and 120 and the drive box 130. When the drives in the drive box are NVMeSSDs with PCIe connections, the back-end interfaces 114 and 124 are PCIe switches that do not perform protocol conversion.

[0026] The processors 111 and 121 control data transfer between a host device connected via the front-end interfaces 113 and 123 and a drive box 130 connected via the back-end interfaces 114 and 124. Further, the processors 111 and 121 control data transfer between the controllers.

[0027] The memories 112 and 122 are the main memories of the processors 111 and 121 respectively, and store programs (such as a storage control program) executed by the processors 111 and 121, management tables referred to by the processors 111 and 121, etc. Also, the memories 112 and 122 are also used as cache memories of the controllers 110 and 120 respectively.

[0028] FIG. 2 is a diagram showing the configuration of the controllers 110 and 120 according to the first embodiment.

[0029] In FIG. 2, for simplicity of explanation, the back-end interfaces 114 and 124 in FIG. 1 are omitted.

[0030] The processors 111 and 121 each have NTBs 211 and 231. The NTB 211 and the NTB 231 are connected by a link 140. The processor 111 and the processor 121 can communicate with each other via the link 140. In this way, within the storage device 100, a dual controller is configured by two controllers 110 and 120. The processors 111 and 121 transfer user data and controller control data that are duplicated between the two controllers on the link 140.

[0031] The front-end interface 113 has interrupt setting registers 217 and 218. The front-end interface 113 can send an interrupt such as MSI (Message Signaled Interrupt) to the addresses set in the interrupt setting registers 217 and 218. For example, an address to an interrupt controller (not shown) built into the processor 111 is set in the interrupt setting register 217, and an address to an interrupt controller (not shown) built into the processor 121 is set in the interrupt setting register 218. By doing so, the front-end interface 113 can send an interrupt to the processor 111 or 121. These interrupts are used for error notifications from the front-end interface to the processor and for operations related to the control queue for data transfer described later.

[0032] Similarly, the front-end interface 123 has interrupt setting registers 237 and 238. The front-end interface 123 can send an interrupt such as MSI to the addresses set in the interrupt setting registers 237 and 238. For example, an address to an interrupt controller built into the processor 121 is set in the interrupt setting register 237, and an address to an interrupt controller built into the processor 111 is set in the interrupt setting register 238. By doing so, the front-end interface 123 can send an interrupt to the processor 111 or 121.

[0033] Also, the interrupts sent by the front-end interfaces 113 and 123 to the processors 111 and 121 use only MSI or MSI-X that can pass through the NTB as a PCIe Write request, and do not use legacy interrupts (INTx).

[0034] The PCIe switch 115 has NTBs 214 and 215. The NTB 214 is connected to the port 212 of the processor 111 via the link 117. The NTB 215 is connected to the port 233 of the processor 121 via the link 128.

[0035] Similarly, the PCIe switch 125 has NTBs 234 and 235. NTB 234 is connected to the port 232 of the processor 121 via the link 127. NTB 235 is connected to the port 213 of the processor 111 via the link 118.

[0036] The port 213 of the processor 111 and the port 233 of the processor 121 have the PCIe DPC (Downstream Port Containment) function enabled. Thus, for example, when removing the controller 110 from the storage device 100, even if the links 118 and 128 go down, the controller 120 remaining in the storage device 100 does not need to handle the link down as an error, so the operation can continue.

[0037] Similarly, for example, when removing the controller 120 from the storage device 100, even if the links 118 and 128 go down, the controller 110 remaining in the storage device 100 does not need to handle the link down as an error, so the operation can continue.

[0038] The management processor 116 connects its root port 216 to the PCIe switch 115 and functions as a root complex for the front - end interface 113 and the PCIe switch 115.

[0039] Similarly, the management processor 126 connects its root port 236 to the PCIe switch 125 and functions as a root complex for the front - end interface 123 and the PCIe switch 125.

[0040] Note that the management processor 116 is not involved in the data transfer control between the host device and the storage device 100, and performs initial settings and the like for the other front - end interface 113 and the PCIe switch 115 including NTBs 214 and 215. Also, the alternative function of the management processor 116 may be incorporated in the PCIe switch 115.

[0041] Similarly, the management processor 126 is not involved in controlling data transfer between the host device and the storage device 100, and performs initial settings and the like for the other front-end interfaces 123 and the PCIe switch 125 including the NTBs 234 and 235. Further, the alternative function of the management processor 126 may be incorporated in the PCIe switch 125.

[0042] The memories 112 and 122 have Outbound Queues (OQs) and Inbound Queues (IQs) which are queues for controlling data transfer between the processors 111 and 121 and the front-end interfaces 113 and 123. The OQ is a queue for controlling data transfer from the front-end interface to the processor, and the IQ is a queue for controlling data transfer from the processor to the front-end interface.

[0043] The memory 112 has an OQ201 and an IQ202 for controlling data transfer between the processor 111 and the front-end interface 113. The memory 112 also has an OQ203 and an IQ204 for controlling data transfer between the processor 111 and the front-end interface 123.

[0044] Similarly, the memory 122 has an OQ221 and an IQ222 for controlling data transfer between the processor 121 and the front-end interface 123. The memory 122 also has an OQ223 and an IQ224 for controlling data transfer between the processor 121 and the front-end interface 113. Thus, in the storage device according to the first embodiment, the control queues of the front-end interface are arranged across two controllers.

[0045] In FIG. 2, OQ201 is denoted as "OQ00", IQ202 as "IQ00", OQ203 as "OQ01", IQ204 as "IQ01", OQ221 as "OQ11", IQ222 as "IQ11", OQ223 as "OQ10", and IQ224 as "IQ10".

[0046] Also, the front - end interface 113 can switch between using OQ201 and IQ202 or using OQ223 and IQ224 according to an instruction from the processor 111. Similarly, the front - end interface 123 can switch between using OQ221 and IQ222 or using OQ203 and IQ204 according to an instruction from the processor 121.

[0047] The instruction of the above - mentioned processor is executed, for example, by the processor writing a predetermined value to the PCIe register of the front - end interface in a PCIe Write request.

[0048] Also, the above - mentioned switching setting status is stored in the registers of the front - end interfaces 113 and 123 that can be accessed via PCIe, and can be read by the processors 111 and 121.

[0049] The front - end interfaces 113 and 123 are respectively connected to either of the processors 111 and 121 via the NTB. Thus, even when the processor 111 or 121 stops and the links 117, 118 go link - down, or the links 127, 128 go link - down, the links between the front - end interfaces 113, 123 and the PCIe switches 115, 125 do not go down. That is, the state of the links connecting the front - end interfaces 113, 123 and the PCIe switches 115, 125 is not affected by the stop of the processors 111 and 121.

[0050] FIG. 3 is a diagram for explaining the configuration of OQ and IQ according to Embodiment 1.

[0051] Both OQ201 and IQ202 store entries in a total of N elements numbered from 0 to N-1. In OQ201, the content of an entry is, for example, a host I / O command received from a host device. In IQ202, the content of an entry is, for example, a response corresponding to a completed host I / O command or a data transfer list that the processor instructs the front-end interface. Also, each entry contains identification information of an exchange (i.e., exchange ID) indicating which exchange of host I / O the entry is related to. An exchange indicates a series of operations related to read operations, write operations, etc. between the host and the storage.

[0052] In OQ201 of Figure 3, as an example, entries are stored in the elements from the (i-1)-th to the (i+5)-th. The other entries in OQ201 are empty. OQ_PI (Producer Index) 301 indicates the location of the element where the front-end interface will next store an entry. OQ_CI (Consumer Index) 302 indicates the location of the element where the entry that the processor will next read is stored. When OQ_PI 301 and OQ_CI 302 indicate the same element, it means that there are no unprocessed entries stored in OQ201 and it is in an empty state. Also, the latest entry that has been processed is stored in the (i-1)-th element. The processor can determine which exchange the entry related to has been completed by examining the exchange ID of this entry.

[0053] In IQ202 of FIG. 3, as an example, entries are stored in elements from the (j - 1)-th to the (i + 4)-th. The other entries in IQ202 are empty. IQ_PI311 indicates the location of the element where the processor will next store an entry. IQ_CI312 indicates the location of the element where the entry that the front-end interface will next read is stored. When IQ_PI311 and IQ_CI312 indicate the same element, it means that there are no unprocessed entries stored in IQ202 and it is in an empty state. Also, the latest entry that has been processed is stored in the (j - 1)-th element. The processor can determine which exchange the entry related to has been processed by examining the exchange ID of this entry.

[0054] FIG. 4 is a diagram for explaining the normal data transfer path between the front-end interface and the memory in the storage device 100 according to the first embodiment.

[0055] Here, it is assumed that the front-end interface 113 and the processor 111 use OQ201 and IQ202 of FIG. 2, and the front-end interface 123 and the processor 121 use OQ221 and IQ222 of FIG. 2.

[0056] The front-end interface 113 accesses the memory 112 via the data transfer path 400 passing through the PCIe switch 115, NTB214, link 117, and processor 111. The front-end interface 123 accesses the memory 122 via the data transfer path 401 passing through the PCIe switch 125, NTB234, link 127, and processor 121. Also, data is transferred between the memory 112 and the memory 122 via the data transfer path 402 passing through the link 140 by the processors 111 and 121.

[0057] The front-end interface 113 sends an interrupt to the processor 111 via the PCIe switch 115, NTB214, and link 117. The front-end interface 123 sends an interrupt to the processor 121 via the PCIe switch 125, NTB234, and link 127.

[0058] FIG. 5 is a diagram for explaining a data transfer path after the queue destination queue of the front-end interface in the storage device 100 according to the first embodiment is switched.

[0059] Here, it is assumed that the front-end interface 113 and the processor 121 use OQ223 and IQ224 in FIG. 2, and the front-end interface 123 and the processor 121 use OQ221 and IQ222 in FIG. 2.

[0060] The front-end interface 113 accesses the memory 122 via the data transfer path 500 passing through the PCIe switch 115, NTB215, link 128, and processor 121. The front-end interface 123 accesses the memory 122 via the data transfer path 401 passing through the PCIe switch 125, NTB234, link 127, and processor 121. Also, data is transferred between the memory 112 and the memory 122 via the data transfer path 402 through which the processors 111 and 121 pass through the link 140.

[0061] The front-end interface 113 sends an interrupt to the processor 121 via the PCIe switch 115, NTB215, and link 128. The front-end interface 123 sends an interrupt to the processor 121 via the PCIe switch 125, NTB234, and link 127.

[0062] FIG. 6 is a diagram for explaining a data transfer path after the queue destination queue of the front-end interface in the storage device 100 according to the first embodiment is switched.

[0063] Here, it is assumed that the front-end interface 113 and the processor 111 use OQ201 and IQ202 in FIG. 2, and the front-end interface 123 and the processor 111 use OQ203 and IQ204 in FIG. 2.

[0064] The front-end interface 113 accesses the memory 112 via the data transfer path 400 passing through the PCIe switch 115, NTB214, link 117, and processor 111. The front-end interface 123 accesses the memory 112 via the data transfer path 600 passing through the PCIe switch 125, NTB235, link 118, and processor 111. Also, data is transferred between the memory 112 and the memory 122 via the data transfer path 402 through which the processors 111 and 121 pass through the link 140.

[0065] The front-end interface 113 sends an interrupt to the processor 111 via the PCIe switch 115, NTB214, and link 117. The front-end interface 123 sends an interrupt to the processor 111 via the PCIe switch 125, NTB235, and link 118.

[0066] FIG. 7 is a diagram for explaining a normal data transfer sequence in the storage device 100 according to the first embodiment.

[0067] Here, as an example, the case where the front-end interface 113 and the processor 111 use OQ201 and IQ202 will be described.

[0068] First, the host device 700 sends a host I / O command 701 to the front-end interface 113.

[0069] The front-end interface 113 that has received the host I / O command 701 enqueues an entry 702 including the command content into OQ201 (step 703).

[0070] Next, the front-end interface 113 sends an interrupt to the address set in the interrupt setting register 217 to notify the processor 111 that an entry has been queued in the OQ (step 704). Further, the front-end interface 113 updates the OQ_PI of the OQ 201 in the memory 112 (step 705).

[0071] The processor 111 that has received the interrupt reads out the entry in which the content of the host I / O command is stored from the OQ 201 (step 706). Further, the processor 111 updates the OQ_CI of the OQ 201 in the front-end interface 113 (step 707).

[0072] Next, the processor 111 queues an entry including a data transfer list corresponding to the host I / O command 701 in the IQ 202 (step 708). Further, the processor 111 updates the IQ_PI of the IQ 202 in the front-end interface 113 (step 709).

[0073] The front-end interface 113 with the updated IQ_PI reads out the entry including the data transfer list from the IQ 202 (step 710).

[0074] Subsequently, between the host device 700 and the memory 112, the front-end interface 113 performs data transfer according to the data transfer list included in the entry read from the IQ 202 (step 711).

[0075] When the data transfer is completed, the front-end interface 113 updates the IQ_CI of the IQ 202 in the memory 112 (step 712).

[0076] In this way, the processor 111 can process the host I / O command 701 received by the front-end interface 113.

[0077] FIG. 8 is a diagram for explaining a data transfer sequence after queue switching of an enqueue destination of a front-end interface in the storage device 100 according to Embodiment 1.

[0078] Here, as an example, a case where the front-end interface 113 and the processor 121 use the OQ223 and the IQ224 will be described.

[0079] First, the host device 700 transmits a host I / O command 801 to the front-end interface 113.

[0080] The front-end interface 113 that has received the host I / O command 801 enqueues an entry 802 including the command content into the OQ223 (step 803).

[0081] Next, the front-end interface 113 transmits an interrupt to the address set in the interrupt setting register 218 in order to notify the processor 121 that an entry has been enqueued in the OQ (step 804). Further, the front-end interface 113 updates the OQ_PI of the OQ223 in the memory 122 (step 805).

[0082] The processor 121 that has received the interrupt reads out an entry in which the content of the host I / O command is stored from the OQ223 (step 806). Further, the processor 121 updates the OQ_CI of the OQ223 in the front-end interface 113 (step 807).

[0083] Next, the processor 121 enqueues an entry including a data transfer list corresponding to the host I / O command 801 into the IQ224 (step 808). Further, the processor 121 updates the IQ_PI of the IQ224 in the front-end interface 113 (step 809).

[0084] The updated front-end interface 113 for IQ_PI reads an entry including a data transfer list from IQ224 (step 810).

[0085] Subsequently, between the host device 700 and the memory 122, the front-end interface 113 performs data transfer according to the data transfer list included in the entry read from IQ224 (step 811).

[0086] When the data transfer is completed, the front-end interface 113 updates the IQ_CI of IQ224 in the memory 122 (step 812).

[0087] In this way, the processor 121 can process the host I / O command 801 received by the front-end interface 113.

[0088] FIG. 9 is a diagram for explaining a flowchart when one of the controllers is restarted in the storage device 100 according to the first embodiment.

[0089] Here, as an example, when the controller 110 is restarted, the processing flow when the processor 121 of the controller 120 takes over the processing of the host I / O received by the front-end interface 113 will be described.

[0090] First, the processor 111 checks whether the controller 120 is in the process of restarting (step 901).

[0091] Next, in step 902, if the controller 120 is in the process of restarting, the process returns to step 901. If it is not in the process of restarting, the process proceeds to step 903.

[0092] Next, the processor 111 notifies the processor 121 of the start of the restart process of the controller 110 (step 903).

[0093] Next, the processor 111 transmits a queue switching command to the front-end interface 113 to switch the operation target queues from OQ201 and IQ202 to OQ223 and IQ224 (step 904).

[0094] Upon receiving the queue switching command, the front-end interface 113 then enqueues the subsequently received host I / O commands to OQ223 (step 905). In other words, the front-end interface 113 switches the enqueue destination OQ from the newly received exchange. Whether a new exchange has started can be determined by examining the exchange ID included in the host I / O command.

[0095] That is, the front-end interface 113 enqueues the host I / O commands received from the host device 700 after receiving the queue switching command from the processor 111, where the exchange ID has switched for the first time among the host I / O commands (i.e., the first host I / O command with a new exchange ID assigned) and the host I / O commands after that to OQ223.

[0096] Next, the processor 111 waits for OQ201 and IQ202 to become empty (step 906). The processor 111 can determine that OQ201 is empty when OQ_PI and OQ_CI of OQ201 are equal. Similarly, the processor 111 can determine that IQ202 is empty when IQ_PI and IQ_CI of IQ202 are equal. If OQ201 and IQ202 are empty, it can be seen that there is no outstanding host I / O related to OQ201 among the host I / O received by the front-end interface 113 that the processor 111 should process.

[0097] Furthermore, to ensure that there is no outstanding host I / O related to OQ201, the processor 111 may check whether the exchange IDs included in the entry corresponding to the host I / O command most recently processed in OQ201 and the entry corresponding to the response most recently processed in IQ202 match. If OQ201 and IQ202 are empty and the two exchange IDs match, it can be seen that there is no outstanding host I / O received by the front-end interface 113 that the processor 111 should process.

[0098] Next, the storage device 100 blocks the controller 110 and performs necessary processes such as updating the OS. Then, the storage device 100 continues to operate with only one of the controllers 120. After that, the storage device 100 restarts the controller 110. Accordingly, the processor 111 stops and restarts (step 907).

[0099] After restarting the controller 110, the processor 111 checks the queue switching setting status of the front-end interface 113 (step 908).

[0100] Next, in step 909, if the host I / O command enqueue destination is OQ223, the process proceeds to step 910. Otherwise, the process ends.

[0101] Next, the processor 111 notifies the processor 121 of the restart of the controller 110 with the operation target queue of the front-end interface 113 switched (step 910).

[0102] Next, the processor 111 sends a queue switching command to the front-end interface 113 to switch the operation target queue from OQ223 and IQ224 to OQ201 and IQ202 (step 911).

[0103] Upon receiving the queue switching command, the front-end interface 113 will then queue the host I / O commands received with the new exchange ID to OQ201 (step 912).

[0104] Next, the processor 111 waits for OQ223 and IQ224 to become empty (step 913). The processor 111 can determine that OQ223 is empty when OQ_PI and OQ_CI of OQ223 are equal. Similarly, the processor 111 can determine that IQ224 is empty when IQ_PI and IQ_CI of IQ224 are equal. The fact that OQ223 and IQ224 are empty means that there is no outstanding host I / O received by the front-end interface 113 to be processed by the processor 121.

[0105] Furthermore, to ensure that there is no outstanding host I / O related to OQ223, the processor 111 may check whether the exchange IDs contained in the entry corresponding to the host I / O command most recently processed in OQ223 and the entry corresponding to the response most recently processed in IQ224 match.

[0106] Finally, the processor 111 notifies the processor 121 of the completion of the restart process of the controller 110 (step 914).

[0107] As described above, the storage device 100 according to the first embodiment restarts the controller after the queue switching process by the front-end interface to the target OQ is completed and the host I / O being processed before the switching is completed, so that the host I / O is not interrupted even when one of the controllers is restarted.

[0108] In the storage device 100 according to the first embodiment, an example in which a pair of OQ and IQ are arranged for each controller in each front-end interface has been described. However, the storage device 100 may arrange two or more pairs of OQ and IQ. For example, when two pairs of OQ and IQ are arranged for each controller in each front-end interface, the two pairs are used as units of switching processing.

[0109] Also, for example, it may be assumed that a failure occurs in the processor 111, memory 112, etc. of the controller 110. Even in such a case, the influence is not transmitted to the front-end interface 113 and the controller 120 by the NTBs 211, 214, and 215. However, when a failure occurs in the processor 111, the processor 111 cannot send a queue switching command to the front-end interface 113. In that case, the processor 121 that has detected the occurrence of a failure in the processor 111 via a heartbeat or the like through the link 140 sends an instruction to switch the enqueue destination of the host I / O command to the normal controller 120 side to the front-end interface 113 via the links 128, NTB 215, and the PCIe switch 115. Thereby, the storage device 100 according to the first embodiment can continue to operate. However, in this case, it is necessary to resend the unfinished I / O being processed by the failed controller 110 by the host device.

Embodiment

[0110] Next, with reference to FIGS. 10 to 11, a storage device according to the second embodiment will be described. The configuration of the storage device according to the second embodiment is the same as that of the storage device according to the first embodiment shown in FIGS. 1 to 9 except for the differences described below, and thus the description thereof will be omitted.

[0111] The storage device 100 according to Embodiment 2 controls data transfer between the front-end interface 113 and the processors 111 and 121 using both the pair of OQ201 and IQ202 and the pair of OQ223 and IQ224 during normal operation. In this case, the host I / O command received by the front-end interface 113 is received by either of the processors 111 and 121 via OQ201 or OQ223. Then, according to an instruction from the processor 111, it is possible to switch whether to use the pair of OQ201 and IQ202 or the pair of OQ223 and IQ224 for data transfer.

[0112] Similarly, the storage device 100 according to Embodiment 2 controls data transfer between the front-end interface 123 and the processors 111 and 121 using both the pair of OQ221 and IQ222 and the pair of OQ203 and IQ204 during normal operation. In this case, the host I / O command received by the front-end interface 123 is received by either of the processors 111 and 121 via OQ221 or OQ203. Then, according to an instruction from the processor 121, it is possible to switch whether to use the pair of OQ221 and IQ222 or the pair of OQ203 and IQ204 for data transfer.

[0113] Note that the switching process in the storage device according to Embodiment 2 will be referred to as "queue skew" processing.

[0114] FIG. 10 is a diagram for explaining a normal data transfer path between the front-end interface and the memory in the storage device according to Embodiment 2.

[0115] Here, it is assumed that the front-end interface 113 and the processor 111 use OQ201 and IQ202 in FIG. 2, and the front-end interface 113 and the processor 121 use OQ223 and IQ224 in FIG. 2.

[0116] Also, it is assumed that the front-end interface 123 and the processor 121 use OQ221 and IQ222 in FIG. 2, and the front-end interface 123 and the processor 111 use OQ203 and IQ204 in FIG. 2.

[0117] The front-end interface 113 accesses the memory 112 via the data transfer path 400 passing through the PCIe switch 115, NTB214, link 117, and processor 111. Also, the front-end interface 113 accesses the memory 122 via the data transfer path 1000 passing through the PCIe switch 115, NTB215, link 128, and processor 121.

[0118] The front-end interface 123 accesses the memory 122 via the data transfer path 401 passing through the PCIe switch 125, NTB234, link 127, and processor 121. Also, the front-end interface 123 accesses the memory 112 via the data transfer path 1001 passing through the PCIe switch 125, NTB235, link 118, and processor 111.

[0119] Also, data is transferred between the memory 112 and the memory 122 via the data transfer path 402 passing through the processors 111 and 121 and the link 140.

[0120] The front-end interface 113 sends an interrupt to the processor 111 via the PCIe switch 115, NTB214, and link 117. The front-end interface 113 sends an interrupt to the processor 121 via the PCIe switch 115, NTB215, and link 128. The front-end interface 123 sends an interrupt to the processor 111 via the PCIe switch 125, NTB235, and link 118. The front-end interface 123 sends an interrupt to the processor 121 via the PCIe switch 125, NTB234, and link 127.

[0121] FIG. 11 is a diagram for explaining a flowchart when restarting one of the controllers in the storage device according to the second embodiment.

[0122] Here, as an example, when restarting the controller 110, the processing flow when the processor 121 of the controller 120 takes over the processing of the host I / O received by the front-end interface 113 will be described.

[0123] First, the processor 111 checks whether the controller 120 is in the process of restarting (step 1101).

[0124] Next, in step 1102, if the controller 120 is in the process of restarting, the process returns to step 1101. If it is not in the process of restarting, the process proceeds to step 1103.

[0125] Next, the processor 111 notifies the processor 121 of the start of the restart process of the controller 110 (step 1103).

[0126] Next, the processor 111 sends a queue skew command to the front-end interface 113 to switch the operation target queue to only OQ223 and IQ224. The processor 121 sends a queue skew command to the front-end interface 123 to switch the operation target queue to only OQ221 and IQ223 (step 1104).

[0127] The front-end interface 113 that has received the queue skew command then enqueues the host I / O commands received with the new exchange ID only to OQ223. The front-end interface 123 that has received the queue skew command then enqueues the host I / O commands received with the new exchange ID only to OQ221 (step 1105).

[0128] Next, the processor 111 waits for OQ201, IQ202, OQ203, and IQ204 to become empty (step 1106). The processor 111 can determine that OQ201 is empty when the OQ_PI and OQ_CI of OQ201 are equal. Similarly, the processor 111 can determine that IQ202 is empty when the IQ_PI and IQ_CI of IQ202 are equal. If OQ201 and IQ202 are empty, it can be seen that there is no outstanding host I / O received by the front-end interface 113 that the processor 111 should process in relation to OQ201.

[0129] Furthermore, to ensure that there is no outstanding host I / O related to OQ201, the processor 111 may check whether the exchange IDs contained in the entry corresponding to the host I / O command most recently processed in OQ201 and the entry corresponding to the response most recently processed in IQ202 match. If OQ201 and IQ202 are empty and the two exchange IDs match, it can be seen that there is no outstanding host I / O received by the front-end interface 113 that the processor 111 should process in relation to OQ201 and IQ202.

[0130] Also, the processor 111 can determine that OQ203 is empty when the OQ_PI and OQ_CI of OQ203 are equal. Similarly, the processor 111 can determine that IQ204 is empty when the IQ_PI and IQ_CI of IQ204 are equal. If OQ203 and IQ204 are empty, it can be seen that there is no outstanding host I / O received by the front-end interface 123 that the processor 111 should process in relation to OQ203.

[0131] Furthermore, to ensure that there is no outstanding host I / O related to OQ203, the processor 111 may check whether the exchange IDs included in the entry corresponding to the host I / O command most recently processed in OQ203 match the exchange IDs included in the entry corresponding to the response most recently processed in IQ204. If OQ203 and IQ204 are empty and the two exchange IDs match, it can be seen that there is no outstanding host I / O received by the front-end interface 123 that the processor 111 should process in relation to OQ203 and IQ204.

[0132] Next, the storage device 100 according to the second embodiment blocks the controller 110 and performs necessary processes such as updating the OS. Then, the storage device 100 according to the second embodiment continues to operate with only one of the controllers 120. Along with this blocking process, the processor 111 stops. After that, the storage device 100 restarts the controller 110. Accordingly, the processor 111 stops and then restarts (step 1107).

[0133] After the restart of the controller 110, the processor 111 checks the offset setting status of the front-end interface 113 (step 1108).

[0134] Next, in step 1109, if the host I / O command enqueue destination is only OQ223, the process proceeds to step 1110. Otherwise, the process ends.

[0135] Next, the processor 111 notifies the processor 121 of the restart of the controller 110 with the operation target queue of the front-end interface 113 offset (step 1110).

[0136] Next, the processor 111 transmits a command to cancel the queue concentration state to the front-end interface 113. The processor 121 transmits a command to cancel the queue concentration state to the front-end interface 123 (step 1111).

[0137] The front-end interface 113 that receives the queue unloading command will then enqueue host I / O commands received with the new exchange ID to OQ 201 or OQ 223. The front-end interface 123 that receives the queue unloading command will then enqueue host I / O commands received with the new exchange ID to OQ 221 or OQ 203 (step 1112).

[0138] Finally, the processor 111 notifies the processor 121 of the completion of the restart process of the controller 110 (step 1113).

[0139] As described above, the storage device 100 of the second embodiment restarts the controller after the front-end interface has completed the consolidation process of the enqueue destination OQ and the host I / O that was being processed before the enqueue destination OQ was switched by the consolidation process has been completed, so that host I / O is not interrupted even when the controller is restarted.

[0140] In the storage device 100 according to the second embodiment, an example has been described in which each front-end interface allocates a pair of OQ and IQ for each controller, but the storage device 100 may allocate two or more pairs of OQ and IQ. For example, when each front-end interface allocates two pairs of OQ and IQ for each controller, the two pairs are used as a unit of the load balancing process. EXAMPLES

[0141] Next, with reference to FIGS. 12 to 15, a description will be given of the storage device according to Example 3. The configuration of the storage device according to Example 3 is the same as that of the storage device according to Example 1 shown in FIGS. 1 to 9, except for the differences described below, and thus the description thereof will be omitted.

[0142] FIG. 12 is a diagram for explaining the configuration of a controller in the storage device according to Example 3.

[0143] In FIG. 12, for simplicity of explanation, the back-end interface is omitted as in FIG. 2. The storage device according to Example 3 is characterized in that there is no link (link 140 in FIG. 2) connecting between processors corresponding to link 140 in FIG. 2. Instead, processors 111 and 121 perform data transfer between processors through paths passing through links 118, 128 and PCIe switches 115, 125.

[0144] FIG. 13 is a diagram for explaining a normal data transfer path between the front-end interface and the memory in the storage device according to Example 3.

[0145] Normally, the front-end interface 113 and the processor 111 use OQ201 and IQ202 in FIG. 12, and the front-end interface 113 and the processor 121 use OQ223 and IQ224 in FIG. 12 to control data transfer.

[0146] The front-end interface 113 accesses the memory 112 via a data transfer path 1300 passing through the PCIe switch 115, NTB214, link 117, and processor 111. The front-end interface 123 accesses the memory 122 via a data transfer path 1301 passing through the PCIe switch 125, NTB234, link 127, and processor 121. Also, between the memory 112 and the memory 122, the processors 111 and 121 transfer data via a data transfer path 1302 passing through the processor 111, link 117, NTB214, PCIe switch 115, NTB215, link 128, and processor 121. Also, between the memory 112 and the memory 122, the processors 111 and 121 transfer data via a data transfer path 1303 passing through the processor 121, link 127, NTB234, PCIe switch 125, NTB235, link 118, and processor 111. For example, the usage of the two data transfer paths 1302 and 1303 between the processors can be such that one is used for user data transfer with a large amount of transferred data, and the other is used for control data transfer with a small amount of transferred data in the storage device. Thereby, an effect of shortening the control data transfer time can be expected.

[0147] The front-end interface 113 sends an interrupt to the processor 111 via the PCIe switch 115, NTB214, and link 117. The front-end interface 123 sends an interrupt to the processor 121 via the PCIe switch 125, NTB234, and link 127.

[0148] FIG. 14 is a diagram for explaining a data transfer path after queue switching of the enqueue destination of the front-end interface in the storage device according to Embodiment 3.

[0149] Here, it is assumed that the front - end interface 113 and the processor 121 use OQ223 and IQ224 in FIG. 12, and the front - end interface 123 and the processor 121 use OQ221 and IQ222 in FIG. 12.

[0150] The front - end interface 113 accesses the memory 122 via the data transfer path through the PCIe switch 115, NTB215, link 128, and processor 121. 1400 The front - end interface 123 accesses the memory 122 via the data transfer path 1301 through the PCIe switch 125, NTB234, link 127, and processor 121. Also, between the memory 112 and the memory 122, the processors 111 and 121 transfer data via the data transfer path 1303 through the processor 121, link 127, NTB234, PCIe switch 125, NTB235, link 118, and processor 111. Also, between the memory 112 and the memory 122, the processors 111 and 121 may transfer data via the data transfer path 1302 (FIG. 13) through the processor 111, link 117, NTB214, PCIe switch 115, NTB215, link 128, and processor 121.

[0151] The front - end interface 113 sends an interrupt to the processor 121 via the PCIe switch 115, NTB215, and link 128. The front - end interface 123 sends an interrupt to the processor 121 via the PCIe switch 125, NTB234, and link 127.

[0152] FIG. 15 is a diagram for explaining the data transfer path after the queue destination queue switching of the front - end interface in the storage device according to Example 3.

[0153] Here, it is assumed that the front-end interface 113 and the processor 111 use OQ201 and IQ202 in FIG. 12, and the front-end interface 123 and the processor 111 use OQ203 and IQ204 in FIG. 12.

[0154] The front-end interface 113 accesses the memory 112 via a data transfer path 1300 passing through the PCIe switch 115, NTB214, link 117, and processor 111. The front-end interface 123 accesses the memory 112 via a data transfer path 1500 passing through the PCIe switch 125, NTB235, link 118, and processor 111. Also, between the memory 112 and the memory 122, data is transferred between the processor 111 and the processor 121 via a data transfer path 1302 passing through the processor 111, link 117, NTB214, PCIe switch 115, NTB215, link 128, and processor 121. Also, between the memory 112 and the memory 122, data may be transferred between the processor 111 and the processor 121 via a data transfer path 1303 (FIG. 13) passing through the processor 121, link 127, NTB234, PCIe switch 125, NTB235, link 118, and processor 111.

[0155] The front-end interface 113 sends an interrupt to the processor 111 via the PCIe switch 115, NTB214, and link 117. The front-end interface 123 sends an interrupt to the processor 111 via the PCIe switch 125, NTB235, and link 118.

[0156] Similar to the storage device 100 according to the first embodiment, the storage device 100 according to the third embodiment restarts the controller after the switching process of the enqueue destination OQ by the front-end interface is completed and the host I / O that was being processed before the switching is completed. In this way, even if one of the controllers is restarted, the host I / O will not be interrupted. Also, since the storage device 100 according to the third embodiment has fewer links connecting between the controllers than the storage device 100 according to the first embodiment, the implementation becomes easier.

[0157] Also, the system according to the embodiment of the present invention may be configured as follows.

[0158] (1) A storage device (e.g., storage device 100) that processes requests from a host device, including a plurality of storage controllers. The first storage controller (e.g., controller 110) among the plurality of storage controllers includes a first front-end interface (e.g., front-end interface 113) that controls the protocol for communication with the host device, and a first processor (e.g., processor 111) that controls the storage device. The second storage controller (e.g., controller 120) among the plurality of storage controllers includes a second processor (e.g., processor 121) that controls the storage device. The first storage controller further includes a first address conversion unit (e.g., NTB214) that converts a first address used by the first processor and a second address used by the first front-end interface, a second address conversion unit (e.g., NTB215) that converts a third address used by the second processor and the second address used by the first front-end interface, a first outbound queue (e.g., OQ201) that controls data transfer from the first front-end interface to the first processor through the first address conversion unit, and a first inbound queue (e.g., IQ202) that controls data transfer from the first processor to the first front-end interface through the first address conversion unit. The second storage controller further includes a second outbound queue (e.g., OQ223) that controls data transfer from the first front-end interface to the second processor through the second address conversion unit, and a second inbound queue (e.g., IQ224) that controls data transfer from the second processor to the first front-end interface through the second address conversion unit. After the first front-end interface receives a first queue destination switching instruction that designates the second outbound queue as the queue destination for requests from the host device,Switch the enqueue destination to the second outbound queue (e.g., steps 904, 905, or steps 1104, 1105) from the request from the host device with an identifier (e.g., exchange ID) of a series of operations related to a newly received host request.

[0159] Thus, even if the processor of one of the controllers constituting the dual controller stops processing, the processor of the other controller can take over the I / O request from the host device and continue to respond.

[0160] (2) In (1) above, before stopping processing, the first processor transmits the first enqueue destination switching instruction to the first front-end interface (e.g., step 904 or step 1104), and stops processing after the first outbound queue and the first inbound queue become empty (e.g., steps 906, 907, or steps 1106, 1107).

[0161] Thus, when the processor of one of the controllers is planned to be stopped for the purpose of OS update or the like, the processor of the other controller can take over the I / O request from the host device and continue to respond.

[0162] (3) In (2) above, when an identifier of a series of operations related to the request from the host device that was most recently processed in the first outbound queue is the same as an identifier of a series of operations related to the host request of the response that was most recently processed in the first inbound queue among the responses to the request from the host device, the first processor stops processing (e.g., steps 906, 907, or steps 1106, 1107).

[0163] Thus, it is possible to reliably determine that there is no outstanding host I / O and stop the processor at an appropriate timing.

[0164] (4) In the above (1), the first front-end interface separately sets the destination address of the first interrupt related to the first outbound queue and the destination address of the second interrupt related to the second outbound queue, and transmits the first interrupt to the first processor through the first address conversion unit (for example, via data transfer path 400), and transmits the second interrupt to the second processor through the second address conversion unit (for example, via data transfer path 500).

[0165] Thereby, when the processor of one controller stops processing, the processor of the other controller can take over the I / O requests from the host device.

[0166] (5) In the above (1), the first processor can read the queue destination setting of the first front-end interface.

[0167] Thereby, the current queue destination can be confirmed.

[0168] (6) In the above (1), after restart, if the result of reading the queue destination setting of the request from the host device from the first front-end interface by the first processor shows that the queue destination is the second outbound queue, the first processor switches the queue destination to the first outbound queue (for example, step 909: Yes~step 912, or step 1109: Yes~step 1112).

[0169] Thereby, the restarted processor can resume I / O.

[0170] (7) In the above (1), further, a third address conversion unit (for example, NTB235) that converts the first address used by the first processor and the fourth address used by the second front-end interface, and the third address used by the second processor and the fourth address used by the second front-end interface, and a fourth address conversion unit (for example, NTB234) that converts the fourth address used by the second front-end interface, and the first processor and the second processor communicate with each other through the third address conversion unit and the fourth address conversion unit (for example, via the data transfer path 1303).

[0171] This can reduce the number of links connecting the controllers, making the implementation easier.

[0172] (8) In the above (1), further, a switch (for example, switch 115) including the first address conversion unit and the second address conversion unit is included, and the first processor and the second processor communicate with each other through the switch (for example, via the data transfer path 1302).

[0173] This can reduce the number of links connecting the controllers, making the implementation easier.

[0174] (9) In the above (1), before receiving the first front-end interface queue switching instruction, the first front-end interface queues a request from the host device to the first outbound queue or the second outbound queue (for example, transfer via data transfer path 400 or 1000), and before stopping processing, the first processor sends the first queue switching instruction to the first front-end interface (for example, step 1104). When the first front-end interface receives the first queue switching instruction from the first processor, it queues a request from the host device with an identifier for a series of operations related to the next new host request received only to the second outbound queue (for example, step 1105). The first processor stops processing after the first outbound queue and the first inbound queue become empty (for example, steps 1106 and 1107).

[0175] Thus, when one front-end interface queues to queues related to multiple processors during normal operation, in order to shift to the queue related to the other processor before stopping one processor, even if the processor of the one controller stops processing, the processor of the other controller can take over the I / O request from the host device and continue to respond.

[0176] (10) In the above (9), the second storage controller further includes a second front-end interface (for example, front-end interface 123) that controls the protocol of communication with the host device, a third address conversion unit (for example, NTB235) that converts the first address used by the first processor and the fourth address used by the second front-end interface, a fourth address conversion unit (for example, NTB234) that converts the third address used by the second processor and the fourth address used by the second front-end interface, a third outbound queue (for example, OQ221) that controls data transfer from the second front-end interface to the second processor through the fourth address conversion unit, and a third inbound queue (for example, IQ222) that controls data transfer from the second processor to the second front-end interface through the fourth address conversion unit. The first storage controller further includes a fourth outbound queue (for example, OQ203) that controls data transfer from the second front-end interface to the first processor through the third address conversion unit, and a fourth inbound queue (for example, IQ204) that controls data transfer from the first processor to the second front-end interface through the third address conversion unit. The second front-end interface queues requests from the host device to the third outbound queue or the fourth outbound queue. The second processor sends a second queue destination switching instruction (for example, step 1104) to the second front-end interface to specify the third outbound queue as the queue destination for requests from the host device before the first processor stops processing. When the second front-end interface receives the second queue destination switching instruction, it queues requests from the host device, to which an identifier for a series of operations related to the next new host request is assigned, only to the third outbound queue (for example, step 1105). The first processorAfter the first outbound queue, the first inbound queue, the fourth outbound queue, and the fourth inbound queue become empty, the process is stopped (for example, steps 1106 and 1107).

[0177] Accordingly, when one front-end interface is enqueuing to queues related to a plurality of processors during normal operation, in order to shift to the queue related to the other processor before stopping one processor, even if the processor of the one controller stops processing, the processor of the other controller can take over the I / O request from the host device and continue to respond.

[0178] (11) In the above (10), when the identifier of a series of operations related to the request from the host device that was most recently processed in the first outbound queue and the identifier of a series of operations related to the host request of the response that was most recently processed in the first inbound queue among the responses to the request from the host device indicate the same host request, and the identifier of a series of operations related to the request from the host device that was most recently processed in the fourth outbound queue and the identifier of a series of operations related to the host request of the response that was most recently processed in the fourth inbound queue among the responses to the request from the host device indicate the same host request, the first processor stops processing (for example, steps 1106 and 1107).

[0179] Accordingly, it is possible to surely determine that there is no unfinished host I / O and stop the processor at an appropriate timing.

[0180] (12) In the above (1), when a failure occurs in the first storage controller, the second processor that detected the failure transmits the first queueing destination switching instruction to the first front-end interface.

[0181] Accordingly, even when a failure occurs in the processor of one of the controllers, the processor of the other controller can take over the I / O requests from the host device and continue to respond.

[0182] Note that the present invention is not limited to the above-described embodiments, and various modifications are included. For example, the above-described embodiments have been described in detail for better understanding of the present invention, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is possible.

[0183] In addition, each of the above configurations, functions, processing units, processing means, etc. may be realized in hardware by designing a part or all of them, for example, by using an integrated circuit. Also, each of the above configurations, functions, etc. may be realized in software by a processor interpreting and executing a program for realizing each function. Information such as a program, table, file, etc. for realizing each function can be stored in a storage device such as a non-volatile semiconductor memory, a hard disk drive, an SSD (Solid State Drive), or a computer-readable non-transitory data storage medium such as an IC card, an SD card, or a DVD.

[0184] Also, the control lines and information lines show those considered necessary for explanation, and not necessarily all the control lines and information lines are shown on the product. In practice, it may be considered that almost all the components are interconnected.

Description of Reference Numerals

[0185] 100: Storage device 110, 120: Controller 111, 121: Processor 112, 122: Memory 113, 123: Front-end interface 114, 124: Back-end interface 115, 125: PCIe switch 116, 126: Management processor 130: Drive box 217, 218, 237, 218: Interrupt setting register 211, 214, 215, 231, 234, 235: Non-transparent bridge 201, 203, 221, 223: Outbound queue 202, 204, 222, 224: Inbound queue

Claims

1. A storage device that processes requests from a host device, including a plurality of storage controllers, wherein a first storage controller among the plurality of storage controllers includes a first front-end interface that controls a protocol for communication with the host device, and a first processor that controls the storage device, wherein a second storage controller among the plurality of storage controllers includes a second processor that controls the storage device, wherein the first storage controller further includes a first address conversion unit that converts a first address used by the first processor and a second address used by the first front-end interface, and a second address conversion unit that converts a third address used by the second processor and the second address used by the first front-end interface, a first outbound queue that controls data transfer from the first front-end interface to the first processor through the first address conversion unit, and a first inbound queue that controls data transfer from the first processor to the first front-end interface through the first address conversion unit, wherein the second storage controller further includes a second outbound queue that controls data transfer from the first front-end interface to the second processor through the second address conversion unit, and a second inbound queue that controls data transfer from the second processor to the first front-end interface through the second address conversion unit, wherein the first front-end interface switches the enqueue destination to the second outbound queue from a request from the host device to which an identifier of a series of operations related to a new host request to be received next is assigned, after receiving a first enqueue destination switching instruction that designates the second outbound queue as an enqueue destination for requests from the host device. A storage device.

2. The storage device according to claim 1, wherein the first processor transmits the first enqueue destination switching instruction to the first front-end interface before stopping processing. A storage device that stops processing after the first outbound queue and the first inbound queue become empty.

3. The storage device according to claim 2, wherein when an identifier of a series of operations related to a request from the host device that was most recently processed in the first outbound queue and an identifier of a series of operations related to the host request of the response that was most recently processed in the first inbound queue among the responses to the request from the host device indicate the same host request, the first processor stops processing. A storage device.

4. The storage device according to claim 1, wherein the first front-end interface individually sets a transmission destination address of a first interrupt related to the first outbound queue and a transmission destination address of a second interrupt related to the second outbound queue, transmits the first interrupt to the first processor through the first address conversion unit, and transmits the second interrupt to the second processor through the second address conversion unit. A storage device.

5. The storage device according to claim 1, wherein the first processor can read the queue destination setting of the first front-end interface. A storage device.

6. The storage device according to claim 5, wherein after restart, when the first processor reads the queue destination setting of a request from the host device from the first front-end interface and the queue destination is the second outbound queue, the first processor switches the queue destination to the first outbound queue. A storage device.

7. The storage device according to claim 1, further comprising a third address conversion unit that converts the first address used by the first processor and a fourth address used by the second front-end interface, and a fourth address conversion unit that converts the third address used by the second processor and the fourth address used by the second front-end interface, and the first processor and the second processor communicate with each other through the third address conversion unit and the fourth address conversion unit. A storage device.

8. The storage device according to claim 1, further comprising a switch including the first address conversion unit and the second address conversion unit, wherein the first processor and the second processor communicate with each other through the switch. A storage device.

9. The storage device according to claim 1, before receiving the first queue destination switching instruction, the first front-end interface queues requests from the host device to the first outbound queue or the second outbound queue, before stopping processing, the first processor transmits the first queue destination switching instruction to the first front-end interface, when the first front-end interface receives the first queue destination switching instruction from the first processor, the first front-end interface queues requests from the host device, which are associated with a series of operations for the next new host request and are assigned identifiers, only to the second outbound queue, the first processor stops processing after the first outbound queue and the first inbound queue become empty. A storage device.

10. The storage device according to claim 9, the second storage controller further includes, a second front-end interface for controlling a protocol for communication with the host device, a third address conversion unit for converting the first address used by the first processor and the fourth address used by the second front-end interface, a fourth address conversion unit for converting the third address used by the second processor and the fourth address used by the second front-end interface, a third outbound queue for controlling data transfer from the second front-end interface to the second processor through the fourth address conversion unit, a third inbound queue for controlling data transfer from the second processor to the second front-end interface through the fourth address conversion unit, the first storage controller further includes, a fourth outbound queue for controlling data transfer from the second front-end interface to the first processor through the third address conversion unit, A fourth inbound queue that controls data transfer from the first processor to the second front-end interface through the third address translation unit, The second front-end interface queues requests from the host device into the third outbound queue or the fourth outbound queue, Before the first processor stops processing, the second processor sends a second queue destination switching instruction to the second front-end interface to specify the third outbound queue as the queue destination for requests from the host device, Upon receiving the second queue destination switching instruction, the second front-end interface queues requests from the host device, which are associated with an identifier for a series of operations related to the next new host request received, only into the third outbound queue, The first processor is a storage device that stops processing after the first outbound queue, the first inbound queue, the fourth outbound queue, and the fourth inbound queue become empty.

11. A storage device according to claim 10, wherein an identifier for a series of operations related to the request from the host device that was most recently processed in the first outbound queue and an identifier for a series of operations related to the host request of the response that was most recently processed in the first inbound queue among the responses to the request from the host device indicate the same host request, and when an identifier for a series of operations related to the request from the host device that was most recently processed in the fourth outbound queue and an identifier for a series of operations related to the host request of the response that was most recently processed in the fourth inbound queue among the responses to the request from the host device indicate the same host request, the first processor stops processing.

12. A storage device according to claim 1, wherein when a failure occurs in the first storage controller, the second processor that detected the failure sends a first queue destination switching instruction to the first front-end interface.

13. A control method for a storage controller of a storage device that processes requests from a host device, wherein the storage device includes a plurality of storage controllers, and a first storage controller among the plurality of storage controllers includes a first front-end interface that controls a protocol for communication with the host device, and a first processor that controls the storage device, a second storage controller among the plurality of storage controllers includes a second processor that controls the storage device, the first storage controller further includes a first address conversion unit that converts a first address used by the first processor and a second address used by the first front-end interface, and a second address conversion unit that converts a third address used by the second processor and the second address used by the first front-end interface, a first outbound queue that controls data transfer from the first front-end interface to the first processor through the first address conversion unit, and a first inbound queue that controls data transfer from the first processor to the first front-end interface through the first address conversion unit, the second storage controller further includes a second outbound queue that controls data transfer from the first front-end interface to the second processor through the second address conversion unit, and a second inbound queue that controls data transfer from the second processor to the first front-end interface through the second address conversion unit, the control method for the storage controller includes the step of the first front-end interface receiving a first queue destination switching instruction that designates the second outbound queue as a queue destination for requests from the host device, and the step of the first front-end interface switching the queue destination to the second outbound queue from a request from the host device to which an identifier for a series of operations related to a new host request to be received next is assigned after receiving the first queue destination switching instruction. A control method for a storage controller.

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