Performance Evaluation Apparatus for Nonvolatile Semiconductor Memory

Abstract

To highly accurately evaluate access performance of a non-volatile semiconductor memory.SOLUTION: In a performance evaluation device (20) of a non-volatile semiconductor memory (10) including a NAND flash memory (11) and a controller (12), a command execution unit (21) issues a descending order write command instructing data write in an access pattern accessed in an address descending order to all regions of the non-volatile semiconductor memory (10). A host controller (22) acquires a command response time to a write command. The command execution unit (21) issues the descending order write command a set number of times or more. The host controller (22) generates performance evaluation data of the non-volatile semiconductor memory (10) on the basis of a command response time of the set number of times or more for descending order write command of the set number of times or more.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a performance evaluation apparatus for non-volatile semiconductor memories such as SD memory cards.

Background Art

[0002] An SD memory card (see, for example, Patent Document 1) is used as a recording device such as in-vehicle equipment. The conventional evaluation of the access performance of an SD memory card only measures the command response time when the accessed address position is changed continuously or randomly through the SD memory card interface. Even for the same individual, the measurement results vary, and high-precision evaluation has not been achieved.

[0003] The main purpose of evaluating the access performance of an SD memory card is to find the limits of the performance inherent to the SD memory card. Thereby, from the perspective of a system using the SD memory card, it is to clarify that no abnormality occurs in data reading and writing. For example, when an operating system (hereinafter referred to as OS) is installed on the SD memory card, when the SD memory card is used as a temporary storage destination for the system resources of the OS, or when multiple applications are executed in parallel to read and write data on the SD memory card, etc., reading and writing of data to random address positions occur frequently, so high-precision evaluation of random access performance has become more important.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the conventional evaluation of random access performance, the internal processing of the SD memory card could not be quantified, and variations occurred in the results of performance evaluation even when the same pattern of random access was performed on the same type of SD memory card from the same manufacturer. Also, in the evaluation using a conventional PC, due to the influence of the overhead of the PC's OS, similarly, variations occurred in the results of performance evaluation even when the same pattern was written to the same type of SD memory card from the same manufacturer.

[0006] Thus, with the conventional evaluation method, the maximum processing time when writing to a specific SD memory card could not be clarified, and the limit of access performance based on this processing time could not be clearly grasped. Therefore, when using an SD memory card in a system, a command response time longer than expected by the system might occur. As a result, unexpected troubles such as write errors and processing delays might occur. Similar phenomena might also occur in non-volatile semiconductor memories other than SD memory cards including NAND flash memory.

[0007] This embodiment has been made in view of such a situation, and its purpose is to provide a technique for highly accurately evaluating the access performance of non-volatile semiconductor memories.

Means for Solving the Problem

[0008] To solve the above problems, a performance evaluation apparatus for a non-volatile semiconductor memory according to an aspect of this embodiment is a performance evaluation apparatus for a non-volatile semiconductor memory including a NAND flash memory and a controller, and issues a descending write command for instructing writing of data in an access pattern that accesses all areas of the non-volatile semiconductor memory in descending order of addresses Issue it, and before or after that, issue an ascending write command that instructs writing of data in an access pattern that accesses all areas of the non-volatile semiconductor in ascending address order A command execution unit to be acquired, and a host controller for the command response time for the write command and generate performance evaluation data of the non-volatile semiconductor memory based on the command response time is provided. The command execution unit issues the descending write command Issue the ascending write command more than the first set number of times to be The second issued more than the set number of times, and the host controller Extract the difference between the command response time for the first descending write command after switching from the ascending write command to the descending write command and the command response time for the next descending write command as the switching processing time in the access direction, or extract the difference between the command response time for the first ascending write command after switching from the descending write command to the ascending write command and the command response time for the next ascending write command as the switching processing time in the access direction, and generate performance evaluation data of the non-volatile semiconductor memory further based on the extracted switching processing time in the access direction .

[0009] Another aspect of this embodiment is a method for evaluating the performance of a non-volatile semiconductor memory. This method is a method for evaluating the performance of a non-volatile semiconductor memory including a NAND flash memory and a controller, and includes a first step of issuing a descending write command for instructing writing of data in an access pattern that accesses all areas of the non-volatile semiconductor memory in descending address order, and a second step of acquiring a command response time for the write command. The first step issues the descending write command a set number of times or more, and the second step generates performance evaluation data of the non-volatile semiconductor memory based on the set number of command response times for the set number of descending write commands.

[0010] Note that any combination of the above components, and those obtained by converting the expression of this embodiment among a method, an apparatus, a system, a recording medium, a computer program, etc., are also effective as aspects of this embodiment.

Advantages of the Invention

[0011] According to this embodiment, the access performance of a non-volatile semiconductor memory can be evaluated with high accuracy.

Brief Description of the Drawings

[0012]

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[0013] The present embodiment relates to an SD memory card (including a micro SD card) generally distributed on the market, and a performance evaluation apparatus and a performance evaluation method for evaluating the limit of access performance of an SD memory card by measuring the access time from an external interface based on the SD memory card standard.

[0014] FIG. 1 is a diagram showing the configuration of an evaluation system for an SD memory card 10 using a performance evaluation apparatus 20 according to an embodiment. The SD memory card 10 includes a NAND flash memory 11 and a controller 12. The NAND flash memory 11 is a memory that stores information according to the state of charges in the floating gates of transistors.

[0015] In the NAND flash memory 11, since the source line is shared by a plurality of cells, data writing / reading is performed in page units. Erasing is performed in block units including a plurality of pages. Erasing is performed by extracting electrons from the floating gate, and writing is performed by injecting electrons into the floating gate. The NAND flash memory 11 realizes higher integration than the NOR flash memory in which a source line is provided for each cell by sharing the source line among a plurality of cells.

[0016] The controller 12 controls data writing, reading, erasing, conversion between logical addresses and physical addresses, wear leveling, error correction, management of defective blocks, interface with the host, etc.

[0017] In the NAND flash memory 11, data cannot be overwritten, and it is necessary to erase it once and then write. As described above, erasing needs to be performed in block units. Therefore, it is necessary to read the data of the entire block including the writing area into the buffer once, erase the entire block, and write the data in the buffer and the new data to the block.

[0018] In the case of an SSD, in addition to the NAND flash memory, it is equipped with a volatile internal cache memory that can be used as a buffer during writing. Usually, DRAM is used for this internal cache memory. By using the DRAM in the SSD, high-speed writing becomes possible. On the other hand, in the case of an SD memory card, generally due to space constraints, in addition to the NAND flash memory 11, it does not have a volatile internal cache memory.

[0019] Therefore, in the SD memory card 10, writing is performed by utilizing the surplus capacity of the NAND flash memory 11. The NAND flash memory 11 actually has a larger storage capacity than the recording capacity described in the specifications. The difference between the storage capacity in the specifications and the actual storage capacity becomes the surplus capacity. The surplus capacity is often set to about 10 - 25% of the actual storage capacity.

[0020] The SD memory card 10 utilizes this surplus capacity for writing and wear leveling. When rewriting data, the controller 12 saves the data of the block containing the page to be written (hereinafter referred to as the target block) to a surplus block, and erases the data of the target block. The controller 12 writes the saved data (excluding the data of the page to be written) and the new data to the target block.

[0021] When writing data larger than the block size, the controller 12 may write the new data to a surplus block and change the status of the surplus block to a normal block, and change the status of the block where the old data exists to a surplus block.

[0022] Basically, the NAND flash memory 11 does not have a physical performance difference due to the position of the write address like an HDD. Therefore, when the same data is written in a state where the surplus capacity used as the internal cache is full, the command response time should be the same regardless of the write address.

[0023] However, generally, a difference occurs between the command response time when data is continuously written in the forward direction within a predetermined address range of the SD memory card 10 and the command response time when data is randomly written in the same address range in a state where the surplus capacity used as the internal cache is full. This is because in the NAND flash memory 11, multiple pages within a block can be continuously written in the ascending address direction (hereinafter also referred to as forward access), but cannot be continuously written in the descending address direction (hereinafter also referred to as reverse access). That is, in the NAND flash memory 11, it is necessary to write multiple pages within a block in ascending address order.

[0024] FIG. 2 is a diagram schematically showing an operation of continuously writing in pages 3 - 5 in block 1 of a NAND flash memory by forward access. FIG. 3 is a diagram schematically showing an operation of continuously writing in pages 3 - 5 in block 1 of a NAND flash memory by reverse access. In forward access, data can be written in pages 3 - 5 in one write operation, but in reverse access, three write operations are required, such as in page 5, page 4, and page 3. Thus, more processing is required for continuous writing by reverse access compared to continuous writing by forward access.

[0025] The above-described processing and the like are performed by the controller 12 as internal processing in the SD memory card 10. The physical address of the NAND flash memory 11 is converted into a logical address by the controller 12, and data is written into the NAND flash memory 11 based on the converted address.

[0026] Writing to the NAND flash memory 11 is generally performed in page units as shown in FIG. 2. However, since writing pages in descending order is prohibited, if an attempt is made to write pages in descending order as reverse access, the writing man-hours increase as shown in FIG. 3. The writing method in FIG. 3 is a conceptual diagram and a simple example. The method of internal processing of the controller 12 when continuously writing data to the SD memory card 10 by reverse access through the actual SD memory card interface varies depending on the manufacturer of the SD memory card 10, and ultimately appears as a difference in the access performance of the SD memory card 10. In previous performance evaluations, there was no method to clearly grasp the internal processing time that varies for each manufacturer.

[0027] Here, if the command response times when continuously writing the same data to the SD memory card 10 in forward access and when continuously writing in reverse access are summed based on the amount of data written, it should be the command response time per amount of data written. However, in reality, it may take a longer command response time.

[0028] This is due to the occurrence of switching processing of the access direction of the NAND flash memory 11 inside the SD memory card 10, such as when changing from continuous writing in forward access shown in FIG. 2 to continuous writing in reverse access shown in FIG. 3. There are also differences in this access direction switching process for each manufacturer of the SD memory card 10, which ultimately appears as a difference in the access performance of the SD memory card 10. In previous performance evaluations, there was no way to clearly grasp the time of this process.

[0029] As described above, the command response time during writing by each actual access includes, as components, the writing processing time of forward access, the writing processing time of reverse access, and the access direction switching processing time. In this embodiment, a method for highly accurately evaluating the access performance of the SD memory card 10 is provided by quantitatively measuring and summing each of these components.

[0030] The performance evaluation device 20 is a dedicated tester for measuring the pure performance of the SD memory card 10. The performance evaluation device 20 includes a command execution unit 21 and a host controller 22. The host controller 22 designates an arbitrary address range and issues write commands / read commands in a forward access or reverse access pattern. The host controller 22 can also specify the power supply voltage and transfer speed during data transfer.

[0031] Generally, in the benchmark test of storage devices using a PC or a smartphone, repeated access is made to a predetermined LBA of an SD memory card 10, which is one of the storage devices, from the PC or the smartphone under the intervention of the OS of the PC or the smartphone, and the access time is measured. Such a benchmark test has limitations such that the access pattern is not unified, the transfer frequency varies for each hardware configuration, and the overhead of the OS intervenes. Due to these limitations, it was common to plot the command response time for each measurement system environment and perform relative evaluation. Therefore, even if it was possible to confirm that the SD memory card 10 to be evaluated could be used in the measurement system without problems in the normal usage method, it was not possible to accurately grasp what access performance each individual of the SD memory card 10 had.

[0032] In contrast, in the present embodiment, a dedicated tester environment in which the overhead of the OS and the like does not intervene is configured, and data of a specific access pattern is directly written to the entire area of the SD memory card 10 at the maximum transfer amount and the maximum transfer frequency.

[0033] The command execution unit 21 outputs a write command / read command issued by the host controller 22 and executes data transfer processing with the SD memory card 10. The data transfer processing by the write command / read command is completed with a response output from the SD memory card 10.

[0034] The host controller 22 determines the command response time and the processing time of each component based on the response to the write command / read command. The host controller 22 registers the obtained command response time and the processing time of each component in the database 30 as performance evaluation data. It is preferable to register the performance evaluation data in a distinguishable manner for each individual SD memory card. The database 30 may be composed of information devices such as a PC, a server, a tablet, etc., not shown in the figure. For example, the performance evaluation device 20 and the information device are connected by a USB cable, and the performance evaluation data is output from the performance evaluation device 20 to the database 30.

[0035] FIG. 4 is a diagram showing an example of an access pattern when continuously writing data to an SD memory card by forward access. The vertical axis represents the LBA (Logical Block Address) consisting of logical addresses, and the horizontal axis represents the command issue number (a number indicating the order of command issuance). Each write command is issued in ascending order of the command issue number. In the forward access shown in FIG. 4, data is written to the entire area of the SD memory card 10 in units of 256 blocks from 0 LBA to the maximum LBA. The data to be written may be arbitrary data. When the command execution unit 21 issues, for example, the nth write command, as soon as it receives the response to the nth write command from the controller 12, it issues the (n + 1)th write command. Here, the time from the issuance of the nth command to the reception of the response is the nth command response time. Note that the write in units of 256 blocks is just an example, and it may be written in other block units such as 512 block units.

[0036] FIG. 5 is a diagram showing an example of an access pattern when continuously writing data to an SD memory card by reverse access. Each write command is issued in ascending order of the command issue number. In the reverse access shown in FIG. 5, data is written to the entire area of the SD memory card 11 in units of 256 blocks from the maximum LBA to 0 LBA. The data to be written may be arbitrary data.

[0037] FIG. 6 is a diagram showing an example of a table in which the command response time is plotted for each command issue number n. The table in which the command response time is plotted is generated for each of forward access and reverse access.

[0038] The write processing time for each access will be described in detail. The write processing time for forward access is obtained as the processing time per unit of capacity from the write time required when writing to the entire area of the SD memory card 10 in a determined access pattern as shown in FIG. 4, for example. The write processing time in the reverse direction is obtained as the processing time per unit of capacity from the write time required when writing to the entire area of the SD memory card 10 in a determined access pattern as shown in FIG. 5, for example.

[0039] Since the controller 12 of the SD memory card 10 only repeats the same internal processing when continuously writing to the entire area in units of capacity determined by a single-direction access pattern, the time required for writing will be approximately the same time for each. However, generally, the write time involving the access direction switching process is longer than the normal access processing time.

[0040] The access direction switching processing time is included in the write time required when writing to the entire area in the first reverse access after writing to the entire area in the write processing of forward access to the SD memory card 10, for example. Therefore, the processing time for switching the access direction can be obtained by taking the difference between the write time required when performing writing to the entire area in the second reverse access subsequently and the previous write time.

[0041] FIG. 7 is a flowchart showing the flow of an evaluation method of the SD memory card 10 using the performance evaluation device 20 according to the embodiment. The example shown in FIG. 7 is an example in which forward access is performed 5 times and reverse access is performed 5 times.

[0042] The host controller 22 resets the evaluation count parameter n of the forward access to 1 (S10). The command execution unit 21 continuously writes data to the SD memory card 10 in the forward direction in the access pattern shown in FIG. 4. The host controller 22 acquires the command response time and the write time of the entire area of the SD memory card 10 (S11). The data written to the SD memory card 10 can be of any kind, and the purpose is to acquire the command response time of each access pattern as shown in FIG. 6.

[0043] In each evaluation of the forward access, the host controller 22 executes data processing for acquiring the maximum command response time m and the entire area write time k (S12).

[0044] FIG. 8 is a diagram showing a subroutine of the data processing of the forward access. When the evaluation count parameter n is 1 (YES in S120), since there is no data in the maximum value parameter m of the command response time, the host controller 22 stores the value of the command response time [n] as it is in the maximum value parameter m (S122).

[0045] When the evaluation count parameter n is other than 1 (NO in S120), the host controller 22 compares the value of the maximum value parameter m with the value of the command response time [n] (S121). When the value of the command response time [n] is larger (YES in S121), the host controller 22 updates the maximum value parameter m to the value of the command response time [n] (S122). When the value of the command response time [n] is not larger (NO in S121), the process of step S122 is skipped.

[0046] When the evaluation count parameter n is 1 (YES in S123), since there is no data in the maximum value parameter k of the entire area write time, the host controller 22 stores the value of the entire area write time [n] as it is in the maximum value parameter k (S125).

[0047] When the evaluation count parameter n is other than 1 (NO in S123), the host controller 22 compares the value of the maximum value parameter k with the value of the full area write time [n] (S124). When the value of the full area write time [n] is larger (YES in S124), the host controller 22 updates the maximum value parameter k to the value of the full area write time [n] (S125). When the value of the full area write time [n] is not larger (NO in S124), the process of step S125 is skipped. Return to FIG. 7.

[0048] When the evaluation count parameter n is less than 5 (YES in S13), the host controller 22 increments the evaluation count parameter n by 1 (S14). Transition to step S11.

[0049] When the evaluation count parameter n reaches 5 (NO in S13), the host controller 22 records the maximum value m of the command response time in the forward direction and the maximum value k of the full area write time, obtained by performing five forward accesses, in the database 30 (S15). The maximum value k of the full area write time, when converted to the access time per unit transfer amount, becomes the write processing time of the forward access.

[0050] Performing five forward accesses is to fill up the surplus capacity used as the internal cache. Therefore, if it is possible to ensure that the surplus capacity used as the internal cache is filled up, it is not necessary to be limited to five times, and other setting times may be used.

[0051] The host controller 22 resets the evaluation count parameter n of the forward access to 1 (S16). The command execution unit 21 continuously writes data to the SD memory card 10 in the reverse direction in the access pattern as shown in FIG. 5. The host controller 22 acquires the command response time and the write time of the entire area of the SD memory card 10 (S17). The data written to the SD memory card 10 can be anything, and the purpose is to acquire the command response time of each access pattern as shown in FIG. 6.

[0052] In each evaluation of reverse access, the host controller 22 executes data processing for obtaining the maximum command response time p, the full-area write time q, and the write time t during access direction switching processing (S18).

[0053] FIG. 9 is a diagram showing a subroutine of data processing for reverse access. When the evaluation count parameter n is 1 (YES in S180), since no data is entered in the maximum value parameter p of the command response time, the host controller 22 stores the value of the command response time [n] as it is in the maximum value parameter p (S182).

[0054] When the evaluation count parameter n is other than 1 (NO in S180), the host controller 22 compares the value of the maximum value parameter p with the value of the command response time [n] (S181). When the value of the command response time [n] is larger (YES in S181), the host controller 22 updates the maximum value parameter p to the value of the command response time [n] (S182). When the value of the command response time [n] is not larger (NO in S181), the process of step S182 is skipped.

[0055] When the evaluation count parameter n is 1 (YES in S183), since no data is entered in the maximum value parameter q of the full-area write time, the host controller 22 stores the value of the full-area write time [n] as it is in the maximum value parameter q (S187).

[0056] When the evaluation count parameter n is 2 (NO in S183, YES in S184), the host controller 22 subtracts the value of the full area write time [2] from the maximum value parameter q (the value of the full area write time [1]) to calculate the write time t during the access direction switching process (S185). The write time during the access direction switching process is included in the first full area write time but not in the second full area write time. Therefore, by calculating the difference between the two, the write time during the access direction switching process can be calculated. When the evaluation count parameter n is other than 2 (NO in S184), the process of step S185 is skipped.

[0057] The host controller 22 compares the value of the maximum value parameter q with the value of the full area write time [n] (S186). When the value of the full area write time [n] is larger (YES in S186), the host controller 22 updates the maximum value parameter q to the value of the full area write time [n] (S187). When the value of the full area write time [n] is not larger (NO in S186), the process of step S187 is skipped. Return to FIG. 7.

[0058] When the evaluation count parameter n is less than 5 (YES in S19), the host controller 22 increments the evaluation count parameter n by 1 (S20). Transition to step S17. When reverse access is performed, since 5 forward accesses have already been performed, the surplus capacity used as the internal cache is full. Therefore, the number of times of reverse access may be less than 5. Since the surplus capacity used as the internal cache uses a part of the non-volatile NAND flash memory 11, some data remains in the surplus capacity used as the internal cache without being erased.

[0059] When the evaluation count parameter n reaches 5 (NO in S19), the host controller 22 records in the database 30 the maximum value p of the command response time in the reverse direction and the maximum value q of the full area write time obtained by performing 5 reverse accesses (S21). The maximum value q of the full area write time is the access time per unit transfer amount converted into the write processing time of the reverse access.

[0060] The host controller 22 records the write time t at the time of access direction switching processing in the database 30 (S22).

[0061] Furthermore, as the random access performance of the SD memory card 10, the host controller 22 may calculate the write time per unit transfer amount of the SD memory card 10 by adding the write processing time of the forward access, the write processing time of the reverse access, and the write time t at the time of access direction switching processing.

[0062] Furthermore, as the command response performance of the SD memory card 10, the host controller 22 may determine the maximum command response time of the SD memory card 10 based on the maximum value m of the command response time during forward direction writing and the maximum value p of the command response time during reverse direction writing including the access direction switching processing time.

[0063] Designers of a system using the SD memory card 10 require, as random access performance, the write time per unit transfer amount and the maximum command response time of the SD memory card 10 in order to determine the system timeout during writing. The maximum command response time may be the maximum value of the command response times for all accesses. The command response time during reverse access writing may include the access direction switching processing time. The host controller 22 compares the maximum value m of the command response time during forward access writing with the maximum value p of the command response time during reverse access writing including the access direction switching processing time, and registers the larger value as the maximum command response time of the SD memory card 10 in the database 30.

[0064] FIG. 10 is a diagram showing an example of a table in which evaluation data of a plurality of SD memory cards 10 are plotted. In the table shown in FIG. 10, the maximum command response time, the write time of forward access, the write time of reverse access, and the access direction switching processing time are recorded for each individual SD memory card 10.

[0065] According to the recording of the evaluation data of such processing times, based on the data transfer amount during random access and the forward access write time or the reverse access write time, the time required to write the data in each access direction can be obtained. By adding the access direction switching processing time corresponding to the number of times of switching the access direction to this time, the random access performance during actual use in a system using the SD memory card 10 can be estimated. Also, the maximum command response time at this time can be calculated.

[0066] According to this embodiment, the access processing time in a state where the surplus capacity of the internal cache is full is obtained. In the same-type SD memory cards 10 where the configurations of the controller 12 and the NAND flash memory 11 are the same, when the surplus capacity of the internal cache is full, the internal processing of the controller 12 has the same operation. Therefore, the maximum command response time and the maximum value of the time required for writing to the entire area show the same results, and the random access performance obtained from these is also the same. In this embodiment, the various access performances of the same-type SD memory cards 10 can be inferred more accurately.

[0067] Conventionally, when evaluating the random access performance of the SD memory card 10, a write process is performed multiple times with an unspecified data capacity to an unspecified address based on pseudo-random numbers or the like, and the total of the processing times is used as the evaluation result. According to this embodiment, without using an unspecified method as in the prior art, and by continuously performing the evaluation for a specified number of times for each access pattern, the processing time for each access with less variation can be obtained. Also, by recording the processing time, the performance unique to the SD memory card 10 in a loaded state can be clarified.

[0068] As described above, according to this embodiment, the access performance of the SD memory card 10 can be evaluated with high accuracy. The designer of the system using the SD memory card 10 can appropriately determine the threshold setting of the time-out time of the system processing based on the evaluation data as shown in FIG. 10. Also, in a system where the threshold of the time-out time has already been determined, an SD memory card 10 with sufficient margin in the specifications can be selected.

[0069] The performance evaluation of the SD memory card 10 according to this embodiment is effective for pre-evaluation in applications that require reliability, such as in-vehicle devices (for example, drive recorders). An SD memory card 10 that satisfies the required write speed can be accurately extracted. Also, the performance evaluation of the SD memory card 10 according to this embodiment can also be used for the performance evaluation of second-hand SD memory cards 10 with unclear backgrounds.

[0070] As described above, the present invention has been described based on embodiments. It should be understood by those skilled in the art that these embodiments are illustrative, and various modifications are possible for each of the constituent elements and combinations of the processing processes, and such modifications are also within the scope of the present invention. Also, replacements of the expression of the present invention among a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as aspects of the present invention.

[0071] In the above embodiment, after performing the forward access n times, the reverse access was performed n times. In this regard, the reverse access may be performed n times first, and then the forward access may be performed n times. In that case, the writing time during the access direction switching process is included in the first full-area writing time of the forward access. The writing time during the access direction switching process is calculated from the difference between the first full-area writing time of the forward access and the second full-area writing time.

[0072] In the above embodiment, the performance evaluation of the SD memory card 10 was described as an example. In this regard, the SD memory card 10 is an example of a non-volatile semiconductor memory that does not include a volatile cache memory inside. It is also applicable to the performance evaluation of other non-volatile semiconductor memories that do not include a volatile cache memory inside. For example, it is also applicable to the performance evaluation of eMMC and USB memories.

Description of Reference Numerals

[0073] 10 SD memory card, 11 NAND flash memory, 12 controller, 20 performance evaluation device, 21 command execution unit, 22 host controller, 30 database.

Claims

1. A performance evaluation apparatus for a non-volatile semiconductor memory including a NAND flash memory and a controller, a command execution unit that issues a descending write command for instructing writing of data in an access pattern that accesses all areas of the non-volatile semiconductor memory in descending address order, and before or after that, issues an ascending write command for instructing writing of data in an access pattern that accesses all areas of the non-volatile semiconductor in ascending address order; a host controller that acquires a command response time for the write command and generates performance evaluation data for the non-volatile semiconductor memory based on the command response time, and the command execution unit issues the descending write command a first set number of times or more and issues the ascending write command a second set number of times or more, wherein the host controller extracts a difference between a command response time for the first descending write command after switching from the ascending write command to the descending write command and a command response time for the next descending write command as a switching processing time in the access direction, or extracts a difference between a command response time for the first ascending write command after switching from the descending write command to the ascending write command and a command response time for the next ascending write command as a switching processing time in the access direction, and generates performance evaluation data for the non-volatile semiconductor memory further based on the extracted switching processing time in the access direction. A performance evaluation apparatus for a non-volatile semiconductor memory.

2. The host controller adds together a maximum value of command response times for the ascending write command including the switching processing time in the access direction and a maximum value of command response times for the descending write command to estimate a maximum command response time for the non-volatile semiconductor memory. The performance evaluation apparatus for a non-volatile semiconductor memory according to Claim 1.

3. The non-volatile semiconductor memory is an SD memory card. The performance evaluation apparatus for a non-volatile semiconductor memory according to Claim 1 or 2.

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