Semiconductor memory device and control method thereof

Abstract

To provide a semiconductor memory device and a control method thereof capable of operating a sense amplifier of each bank at high speed even when an overdrive voltage is shared among a plurality of banks. 【Solution means】The semiconductor memory device includes a plurality of banks 20 each having at least one sense amplifier 10, and when an amplification operation of the voltages of bit lines BLT and TLC connected to the sense amplifier 10 of each of the plurality of banks 10 is performed, a first voltage supply unit 30 that supplies an overdrive voltage VOD higher than the operating voltage VBLH of the sense amplifier 10 to the sense amplifier 10 of each of the plurality of banks 20, and when an amplification operation is performed in any one of the plurality of banks 20, the overdrive voltage VOD is supplied to the sense amplifier 10 of any one of the banks 20 in a state where the overdrive voltage VOD has not dropped, and a control unit 40 that controls the supply of a charging voltage for charging the overdrive voltage VOD.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a control method thereof.

Background Art

[0002] For example, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) generates a weak potential difference in a pair of complementary bit lines (hereinafter referred to as "a pair of bit lines") based on data held in a memory cell, and reads the data by amplifying this potential difference with a sense amplifier. Further, in order to speed up the data read operation of the sense amplifier by speeding up the amplification operation of the voltage of the bit line, a semiconductor memory device configured to supply an overdrive voltage higher than the operating voltage of the sense amplifier to the sense amplifier at the start of the amplification operation is known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in a conventional semiconductor memory device, in order to meet requirements such as reduction of chip size and improvement of design efficiency, as shown in FIG. 1(a), a VOD supply unit that supplies an overdrive voltage (VOD) is provided so as to be shareable between a plurality (two in the example of the figure) of banks (bank 0, bank 1) each including a plurality of memory cells and a plurality of sense amplifiers. In such a configuration, when the amplification operation of the voltage of the bit lines connected to the sense amplifiers of each of the plurality of banks (bank 0, bank 1) is performed, the VOD supply unit supplies the overdrive voltage to the sense amplifiers of each bank.

[0005] FIG. 1(b) shows an example of voltage changes of respective signals when sense amplifiers of each of a plurality of banks (bank 0, bank 1) are operated. In the example shown in FIG. 1(b), at time t1, data stored in any memory cell in bank 0 (BK0) is sent to bit line BLT (BK0), whereby the voltage level of bit line BLT (BK0) slightly changes. Next, when the amplification operation of the voltage of the bit line is started at time t2, the voltage levels of a pair of bit lines BLT (BK0), BLC (BK0) are amplified by a sense amplifier connected to the pair of bit lines BLT (BK0), BLC (BK0). At this time, since an overdrive voltage is supplied from the VOD supply unit to the sense amplifier of bank 0 (BK0), the voltage of node VOD_BK01 between the VOD supply unit and each bank (bank 0, bank 1) drops.

[0006] Next, at time t3, when the voltage levels of the pair of bit lines BLT (BK0), BLC (BK0) of bank 0 (BK0) are amplified to voltages substantially the same as the operating voltage VBLH and the ground voltage VSS, the VOD supply unit stops supplying the overdrive voltage to the sense amplifier of bank 0 (BK0). At this time, the voltage of node VOD_BK01 starts to rise so as to recover to the initial state (the state where the voltage has not dropped).

[0007] However, at time t4, when the voltage amplification operation of a pair of bit lines BLT(BK1) and BLC(BK1) of another bank 1 (BK1) starts while the voltage of node VOD_BK01 has not recovered to its initial state, an overdrive voltage is supplied from the VOD supply unit to the sense amplifier of bank 1 (BK1). As a result, the voltage of node VOD_BK01 (i.e., the overdrive voltage) drops further below the voltage at time t2. Thereby, the voltage of bit line BLT(BK1) is amplified using the further-dropped overdrive voltage. In this case, the time until the voltage of bit line BLT(BK1) reaches the operating voltage VBLH becomes longer (i.e., the amplification operation becomes longer), and the data read operation of the sense amplifier of bank 1 is delayed. Therefore, in the prior art, when the overdrive voltage is shared among a plurality of banks (bank 0, bank 1), there is a risk that it becomes difficult to operate the sense amplifier of each bank (here, bank 1) at high speed.

[0008] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor memory device and a control method thereof capable of operating the sense amplifier of each bank at high speed even when an overdrive voltage is shared among a plurality of banks.

Means for Solving the Problems

[0009] In order to solve the above problems, the present invention provides a semiconductor memory device including: a plurality of banks each including at least one sense amplifier; a first voltage supply unit that supplies an overdrive voltage higher than the operating voltage of the sense amplifier to each of the sense amplifiers of the plurality of banks when a voltage amplification operation of a bit line connected to each of the sense amplifiers of the plurality of banks is performed; and a control unit that controls the supply of a charging voltage for charging the overdrive voltage so that the overdrive voltage is supplied to the sense amplifier of any one of the plurality of banks in a state where the overdrive voltage has not dropped when the amplification operation is performed in any one of the plurality of banks.

[0010] According to such an invention, when an amplification operation is performed in any one of the banks, an overdrive voltage that has not been voltage - dropped can be supplied to the sense amplifier of the any one of the banks. Therefore, for example, compared with the case of supplying an overdrive voltage in a voltage - dropped state to the sense amplifier of the any one of the banks, the amplification operation in the any one of the banks can be speeded up, and as a result, the operation of the sense amplifier of the any one of the banks can be speeded up. Thereby, even when the overdrive voltage is shared among a plurality of banks, the sense amplifiers of each bank can be operated at high speed.

[0011] Further, the present invention is a control method for a semiconductor memory device, the semiconductor memory device including: a plurality of banks each including at least one sense amplifier; and a first voltage supply unit that supplies an overdrive voltage higher than the operating voltage of the sense amplifier to the sense amplifier of each of the plurality of banks when an amplification operation of the voltage of a bit line connected to the sense amplifier of each of the plurality of banks is performed, and a control unit. The control unit executes a step of controlling the supply of a charging voltage for charging the overdrive voltage so that the overdrive voltage is supplied to the sense amplifier of the any one of the banks in a state where the overdrive voltage has not been voltage - dropped when the amplification operation is performed in any one of the plurality of banks, thereby providing a control method for a semiconductor memory device.

Effects of the Invention

[0012] According to the semiconductor memory device and its control method of the present invention, even when the overdrive voltage is shared among a plurality of banks, the sense amplifiers of each bank can be operated at high speed.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0014] FIG. 2 is a diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 2(a), the semiconductor memory device includes a plurality of sense amplifiers 10 connected to a plurality of memory cells MC. Note that in the example shown in FIG. 2(a), it should be noted that one memory cell MC and one sense amplifier 10 are shown in order to avoid making the figure unclear. Also, each of the memory cell MC and the sense amplifier 10 may have a configuration similar to a well-known configuration.

[0015] As shown in FIG. 2(a), the sense amplifier 10 is connected to a pair of bit lines BLT and BLC, and a memory cell MC is connected to the bit line BLT. The node on the high-voltage power supply side of the sense amplifier 10 is connected to the operating voltage VBLH via the switch 11 and to the overdrive voltage VOD via the switch 12. Also, the node on the high-voltage power supply side of the sense amplifier 10 is connected to the operating voltage VBLH or the overdrive voltage VOD by controlling the on / off of the switches 11 and 12 by a control unit 40 described later. Further, the node on the low-voltage power supply side of the sense amplifier 10 is connected to the ground voltage VSS. In FIG. 2(a), the case where each of the switches 11 and 12 is constituted by an N-channel type field effect transistor (nMOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)) is shown as an example, but each of the switches 11 and 12 may be constituted by other circuits or the like.

[0016] Also, as shown in FIG. 2(b), the semiconductor memory device according to the present embodiment includes a plurality (two in the example of the figure) of banks 20, a first voltage supply unit 30, and a control unit 40. Each of the plurality of banks 20 includes at least one memory cell MC and at least one sense amplifier 10. That is, each of the plurality of banks 20 includes at least one of the configurations shown in FIG. 2(a). Further, the first voltage supply unit 30 is connected to each of the plurality of banks 20 via the node VOD_BK01, and supplies the overdrive voltage VOD, which is higher than the operating voltage VBLH of the sense amplifier 10, to the sense amplifier 10 of each of the plurality of banks 20 when the amplification operation of the voltages of the pair of bit lines BLT and BLC connected to the sense amplifier 10 of each of the plurality of banks 20 is performed. Note that the first voltage supply unit 30 may be configured to generate the overdrive voltage VOD based on a power supply supplied from the outside.

[0017] When an amplification operation is performed in any one of the plurality of banks 20, the control unit 40 controls the supply of a charging voltage for charging the overdrive voltage VOD so that the overdrive voltage VOD is supplied to the sense amplifier 10 of any one of the banks 20 without the voltage drop.

[0018] Further, the control unit 40 may be configured to stop the supply of the charging voltage when an amplification operation is started in any one of the plurality of banks 20. Thereby, it is possible to suppress the consumption of the charging voltage when an amplification operation is started in any one of the banks 20 (that is, when the overdrive voltage VOD is supplied to the sense amplifier 10 of any one of the banks 20).

[0019] Furthermore, the control unit 40 may be configured to start the supply of the charging voltage when the voltage of the bit line BLT reaches a voltage substantially the same as the operating voltage VBLH of the sense amplifier 10 in the amplification operation. Here, the "substantially the same voltage" is not limited to the state where the voltage of the bit line BLT and the operating voltage VBLH are exactly equal. For example, it may include a state where the difference in voltage between the voltage of the bit line BLT and the operating voltage VBLH is sufficiently small so that the voltage of the bit line BLT and the operating voltage VBLH can be regarded as equal. Thereby, when the voltage of the bit line BLT reaches a voltage substantially the same as the operating voltage VBLH of the sense amplifier 10 (that is, when the supply of the overdrive voltage VOD to the sense amplifier 10 of any one of the banks 20 is stopped), the charging voltage can be supplied to the overdrive voltage VOD whose voltage has dropped.

[0020] Furthermore, when an amplification operation is performed in any one of the banks 20 and then an amplification operation is performed in another bank 20 other than the any one of the banks 20, the control unit 40 may be configured to supply a charging voltage so that the overdrive voltage VOD recovers to a state where it has not substantially dropped until the amplification operation starts in the other bank 20. Here, the "state where the overdrive voltage VOD has not substantially dropped" is not limited to a state where the overdrive voltage VOD has not dropped at all. For example, it may include a state where the voltage has dropped only by a sufficiently low voltage value from the voltage value when the overdrive voltage VOD has not dropped at all (that is, a state that can be regarded as the same value as the value of the overdrive voltage VOD when it has not dropped). Thereby, when the amplification operation starts in the other bank 20, the overdrive voltage VOD that has not substantially dropped can be supplied to the sense amplifier 10 of the other bank 20.

[0021] As shown in FIG. 2(b), the control unit 40 includes a switch 41 for controlling the supply of the charging voltage and a circuit (here, a capacitor 42) for charging the overdrive voltage VOD. The switch 41 is provided between the node VOD_BK01 and the capacitor 42. The switch 41 includes an nMOSFET. For example, when a high-level signal EN_VODR is input to the gate terminal of the nMOSFET, the switch 41 is configured to connect the capacitor 42 to the node VOD_BK01 (that is, supply the charging voltage charged in the capacitor 42). Further, the capacitance of the capacitor 42 may be set so that the charging voltage charged in the capacitor 42 becomes a voltage higher than the overdrive voltage VOD. In the present embodiment, the case where the switch 41 includes an nMOSFET is described as an example, but the switch 41 may include, for example, a P-channel type field effect transistor (pMOSFET), or may include another switch circuit or the like other than the MOSFET. Also, in the present embodiment, the case where the circuit for charging the overdrive voltage VOD includes the capacitor 42 is described as an example, but the circuit may have other configurations.

[0022] Referring to FIG. 3, an example of the operation of the control unit 40 when operating each sense amplifier 10 of each of the plurality of banks 20 will be described. Here, the case where data stored in the memory cell MC of each bank 20 is read out will be described. First, in the standby state, the voltages of a pair of bit lines BLT(BK0), BLC(BK0), BLT(BK1), BLC(BK1) connected to each sense amplifier 10 of each bank (bank 0, bank 1) 20 are set to the equalizer voltage VBLEQ. Here, the height of the equalizer voltage VBLEQ may be, for example, half of the operating voltage VBLH.

[0023] At time t11, data stored in any memory cell MC in bank 0 (BK0) is sent to the bit line BLT(BK0) connected to the memory cell MC, causing the voltage level of the bit line BLT(BK0) to change slightly. Also, between time t11 and time 12, data stored in any memory cell MC in bank 1 (BK1) is sent to the bit line BLT(BK1) connected to the memory cell MC, causing the voltage level of the bit line BLT(BK1) to change slightly.

[0024] Next, when the amplification operation of the voltage of the bit line of bank 0 (BK0) is started at time t12, the control unit 40 stops supplying the charging voltage charged in the capacitor 42 to the overdrive voltage VOD. Specifically, the control unit 40 turns off the switch 41 by inputting a low-level signal EN_VODR to the gate terminal of the nMOSFET of the switch 41. As a result, the connection between the capacitor 42 and the node VOD_BK01 is cut off, and the charging of the overdrive voltage VOD is stopped. Also, the control unit 40 turns on the switch 12 connected to the sense amplifier 10 that performs the amplification operation of the voltage of the bit line (that is, inputs a high-level signal to the gate terminal of the nMOSFET of the switch 12). As a result, the overdrive voltage VOD is supplied from the first voltage supply unit 30 to the sense amplifier 10.

[0025] Next, at time t13, when the voltage levels of a pair of bit lines BLT(BK0) and BLC(BK0) of bank 0 (BK0) are amplified to voltages approximately the same as the operating voltage VBLH and the ground voltage VSS, the control unit 40 starts supplying the charging voltage. Note that the timing at which the voltage levels of the pair of bit lines BLT(BK0) and BLC(BK0) of bank 0 (BK0) are amplified to voltages approximately the same as the operating voltage VBLH and the ground voltage VSS may be determined, for example, by being measured in advance, or may be determined by a predetermined voltage detection circuit (not shown) detecting that the voltage levels of the pair of bit lines BLT(BK0) and BLC(BK0) have reached voltages approximately the same as the operating voltage VBLH and the ground voltage VSS.

[0026] Here, the control unit 40 turns on the switch 41 by inputting a high-level signal EN_VODR to the gate terminal of the nMOSFET of the switch 41. As a result, the capacitor 42 and the node VOD_BK01 are connected, and the charging of the overdrive voltage VOD is started. Also, the control unit 40 turns off the switch 12 connected to the sense amplifier 10 that performs the voltage amplification operation of the bit line (that is, inputs a low-level signal to the gate terminal of the nMOSFET of the switch 12), and turns on the switch 11 connected to the sense amplifier 10 (that is, inputs a high-level signal to the gate terminal of the nMOSFET of the switch 11). As a result, the supply of the overdrive voltage VOD from the first voltage supply unit 30 to the sense amplifier 10 is stopped, and the operating voltage VBLH is supplied to the sense amplifier 10. Furthermore, the voltage of the node VOD_BK01 (overdrive voltage VOD) rises as the charging voltage is supplied.

[0027] Next, when the voltage of node VOD_BK01 (overdrive voltage VOD) substantially recovers to the initial state (the state where the voltage has not dropped), the control unit 40 stops supplying the charging voltage to the overdrive voltage VOD. Note that the timing at which the voltage of node VOD_BK01 substantially recovers to the initial state may be determined, for example, by being measured in advance, or may be determined by a predetermined voltage detection circuit (not shown) detecting that the voltage of node VOD_BK01 has substantially recovered to the initial state. In this way, when the amplification operation is performed in bank 1 (BK1) after the amplification operation is performed in bank 0 (BK0), the charging voltage is supplied so that the overdrive voltage VOD substantially recovers to the state where the voltage has not dropped until the amplification operation is started in bank 1 (BK1).

[0028] Then, when the amplification operation of the voltage of the bit line of bank 1 (BK1) starts at time t14, the control unit 40 stops supplying the charging voltage charged in the capacitor 42 to the overdrive voltage VOD, similar to the operation at time t12. Further, the control unit 40 supplies the overdrive voltage VOD from the first voltage supply unit 30 to the sense amplifier 10 of bank 1 (BK1). At this time, since the overdrive voltage VOD has already substantially recovered to the initial state (the state where the voltage has not dropped), when the amplification operation is performed in the sense amplifier 10 of bank 1 (BK1), the overdrive voltage VOD is supplied to the sense amplifier 10 of bank 1 (BK1) in the state where the voltage has not dropped.

[0029] In the example shown in FIG. 3, the timing at which the voltage of node VOD_BK01 (overdrive voltage VOD) substantially recovers to the initial state (a state where the voltage has not dropped) and the timing at which the amplification operation of the voltage of the bit lines of bank 1 (BK1) starts are shown to occur simultaneously. Here, the control unit 40 may control to wait for the amplification operation of the voltage of the bit lines of bank 1 (BK1) to start so that, for example, after the voltage of node VOD_BK01 (overdrive voltage VOD) substantially recovers to the initial state (a state where the voltage has not dropped), the amplification operation of the voltage of the bit lines of bank 1 (BK1) starts. Thereby, it is possible to surely supply the overdrive voltage VOD in a state where the voltage has not dropped to the sense amplifier 10 of bank 1 (BK1).

[0030] At time t15, when the voltage levels of the pair of bit lines BLT(BK1) and BLC(BK1) of bank 1 (BK1) are amplified to substantially the same voltages as the operating voltage VBLH and the ground voltage VSS, the control unit 40 starts supplying the charging voltage in the same manner as the operation at time t13.

[0031] In this way, when an amplification operation is performed in any of the banks 20, it becomes possible to supply the overdrive voltage VOD that has not dropped in voltage to the sense amplifier 10 of any of the banks 20.

[0032] As described above, according to the semiconductor memory device and its control method of the present embodiment, when an amplification operation is performed in any of the banks 20, it is possible to supply the overdrive voltage VOD that has not dropped in voltage to the sense amplifier 10 of any of the banks 20. Therefore, for example, compared with the case of supplying the overdrive voltage VOD whose voltage has dropped to the sense amplifier 10 of any of the banks 20, the amplification operation in any of the banks 20 can be speeded up, and as a result, the operation of the sense amplifier 10 of any of the banks 20 can be speeded up. Thereby, even when the overdrive voltage VOD is shared among a plurality of banks 20, the sense amplifier 10 of each bank 20 can be operated at high speed.

[0033] In the above-described embodiment, the case where the amplification operation of the bit line voltage of bank 1 (BK1) is started after the amplification operation of the bit line voltage of bank 0 (BK0) is started has been described as an example. However, the present invention is not limited to this case. For example, as shown in FIG. 4, the amplification operations of the bit line voltages of a plurality of banks 20 (bank 0, bank 1) may be performed simultaneously. In this case, the control unit 40 may be configured to always supply the charging voltage (that is, always set the signal EN_VODR to the high level) when performing the amplification operations simultaneously in at least two of the plurality of banks 20. Thereby, since the charging voltage is always supplied to the overdrive voltage VOD, it is possible to reduce the amount of drop in the overdrive voltage VOD due to the simultaneous performance of the amplification operations of the bit line voltages of the plurality of banks 20 (bank 0, bank 1).

[0034] Note that the operation of the control unit 40 at times t21, t22, and t23 in FIG. 4 may be the same as the operation at times t11, t12, and t13 described above, except that the amplification operations of the bit line voltages of the plurality of banks 20 (bank 0, bank 1) are performed simultaneously and the signal EN_VODR is always set to the high level.

[0035] In the above-described embodiment, the case where the control unit 40 includes one switch 41 and one capacitor 42 has been described as an example. However, the present invention is not limited to this case. For example, as shown in FIG. 5, the control unit 40 may include the same number of control units as the number of banks 20 (in the example of the figure, the first control unit 40a and the second control unit 40b), and each of the control units 40a, 40b may include one switch 41a, 41b and one capacitor 42a, 42b. Here, each of the control units 40a, 40b may be associated with any one of the plurality of banks 20. For example, the control unit 40a may be associated with bank 0 (BK0), and the control unit 40b may be associated with bank 1 (BK1).

[0036] Also, the charging voltages charged to the capacitors 42a and 42b may be different from each other. This makes it possible to associate different charging voltages with each of the plurality of banks 20. Furthermore, since it is considered that the amount of drop in the overdrive voltage VOD during the amplification operation in any one of the banks 20 increases as the position of that bank 20 relative to the first voltage supply unit 30 becomes farther, the charging voltages charged to the capacitors 42a and 42b may be set to increase as the position of the corresponding bank 20 becomes farther from the first voltage supply unit 30.

[0037] Furthermore, the control unit 40 may be configured to supply the charging voltage corresponding to any one of the plurality of banks 20 when an amplification operation is performed in that bank 20. This makes it possible to charge the charging voltage corresponding to the bank 20 in which the amplification operation is performed to the overdrive voltage VOD. Here, when an amplification operation is performed in bank 0 (BK0), the first control unit 40a of the control unit 40 may supply the charging voltage of the capacitor 42a to the overdrive voltage VOD by inputting a high-level signal EN_A to the gate terminal of the nMOSFET of the switch 41a. Also, when the overdrive voltage VOD has recovered to a state where it has hardly dropped in voltage, the first control unit 40a of the control unit 40 may stop the supply of the charging voltage by inputting a low-level signal EN_A to the gate terminal of the nMOSFET of the switch 41a. Furthermore, when an amplification operation is performed in bank 1 (BK1), the second control unit 40b of the control unit 40 may supply the charging voltage of the capacitor 42b to the overdrive voltage VOD by inputting a high-level signal EN_B to the gate terminal of the nMOSFET of the switch 41b. Additionally, when the overdrive voltage VOD has recovered to a state where it has hardly dropped in voltage, the second control unit 40b of the control unit 40 may stop the supply of the charging voltage by inputting a low-level signal EN_B to the gate terminal of the nMOSFET of the switch 41b.

[0038] FIG. 6 shows a configuration example of the control unit 40 according to another modification of the present invention. As shown in FIG. 6, the control unit 40 may include a second voltage supply unit 43. Here, the second voltage supply unit 43 may be configured to charge the capacitor 42 with a plurality of different charging voltages. Also, each of the plurality of different charging voltages may be associated with any one of the plurality of banks 20, similar to the modification shown in FIG. 5. For example, the charging voltage charged to the capacitor 42 may be set such that the position of the bank 20 corresponding to the charging voltage becomes higher as it is farther from the first voltage supply unit 30.

[0039] In this modification, the control unit 40 is configured to supply any one of the plurality of charging voltages to the overdrive voltage VOD. Thereby, it becomes possible to charge the overdrive voltage VOD using different charging voltages. For example, when the amplification operation is performed in bank 0 (BK0), the control unit 40 supplies the charging voltage associated with bank 0 (BK0) from the second voltage supply unit 43 to the capacitor 42, and when the amplification operation is performed in bank 1 (BK1), the charging voltage associated with bank 1 (BK1) may be supplied from the second voltage supply unit 43 to the capacitor 42.

[0040] In the above-described embodiments and modifications, the case where the control unit 40 includes at least one switch 41, 41a, 41b and at least one capacitor 42, 42a, 42b has been described as an example, but the present invention is not limited to this case. For example, the control unit 40 may be configured by other circuits having the same effects as those of the above-described embodiments and modifications.

Description of Reference Numerals

[0041] 10…Sense amplifier 20…Bank 30…First voltage supply unit 40…Control unit 40a…First control unit 40b…Second control unit 41, 41a, 41b…Switch 42, 42a, 42b…Capacitor 43…Second voltage supply unit EN_A, EN_B, EN_VODR... signals VBLEQ…Equalizer voltage VBLH…Operating voltage VOD…Overdrive voltage VSS…Ground voltage

Claims

1. a plurality of banks each including at least one sense amplifier; a first voltage supply unit that supplies an overdrive voltage higher than an operating voltage of the sense amplifier to each of the plurality of banks when an amplification operation of a voltage of a bit line connected to the sense amplifier of each of the plurality of banks is performed; a control unit that controls supply of a charging voltage for charging the overdrive voltage so that the overdrive voltage is supplied to the sense amplifier of the bank without being dropped when the amplification operation is performed in the bank among the plurality of banks; the control unit is configured to constantly supply the charging voltage when the amplifying operation is performed simultaneously in at least two of the plurality of banks. Semiconductor memory device.

2. the control unit is configured to stop supplying the charging voltage when the amplifying operation is started in any one of the plurality of banks.

2. The semiconductor memory device according to claim 1.

3. the control unit is configured to start supplying the charging voltage when the voltage of the bit line reaches substantially the same voltage as an operating voltage of the sense amplifier in the amplifying operation.

2. The semiconductor memory device according to claim 1.

4. the control unit is configured to supply the charging voltage when the amplification operation is performed in another bank other than the one of the banks after the amplification operation is performed in the one of the banks, such that the overdrive voltage is restored to a state in which there is almost no voltage drop until the amplification operation is started in the other bank.

2. The semiconductor memory device according to claim 1.

5. The control unit includes a circuit for charging the overdrive voltage.

2. The semiconductor memory device according to claim 1.

6. the circuit includes a capacitor for charging the overdrive voltage; 6. The semiconductor memory device according to claim 5.

7. The control unit includes a switch for controlling the supply of the charging voltage.

2. The semiconductor memory device according to claim 1.

8. The switch includes a MOS transistor.

8. The semiconductor memory device according to claim 7.

9. A different charging voltage is associated with each of the plurality of banks, the control unit is configured to supply the charging voltage corresponding to any one of the plurality of banks when the amplifying operation is performed in the any one of the plurality of banks.

2. The semiconductor memory device according to claim 1.

10. The control unit is configured to supply any one of a plurality of charging voltages.

2. The semiconductor memory device according to claim 1.

11. The control unit includes a second voltage supply unit that supplies the plurality of charging voltages. The semiconductor memory device according to claim 10.

12. A method for controlling a semiconductor memory device, comprising: The semiconductor memory device includes: a plurality of banks each including at least one sense amplifier; a first voltage supply unit that supplies an overdrive voltage higher than an operating voltage of the sense amplifier to each of the plurality of banks when an amplification operation of a voltage of a bit line connected to the sense amplifier of each of the plurality of banks is performed; A control unit, the control unit is configured to always supply a charging voltage for charging the overdrive voltage when the amplifying operation is performed simultaneously in at least two banks among the plurality of banks; The control unit: executing a step of controlling the supply of the charging voltage so that, when the amplifying operation is performed in any one of the plurality of banks, the overdrive voltage is supplied to the sense amplifier of the any one of the banks without being dropped in voltage; A method for controlling a semiconductor memory device.

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