Electronic control unit

Abstract

To provide an electronic control device capable of appropriately controlling a power supply voltage and a clock frequency in accordance with a load in a system which controls a vehicle.SOLUTION: An electronic control device comprises: a master IP 4 and a bus master 5 which access an SRAM 6, a DDR 7, etc., via a bus 2; a bus monitor 3 which is disposed between the master IP 4 and the bus 2 and measures a traffic volume based on access states of the master IP 4 and the bus master 5 to the bus 2; a power source supply IC 10 which supplies a power source VDD for operation to the master IP 4; and a clock frequency control section 9 which supplies a clock for operation to the master IP 4. A plurality of applications each executed by the master IP 4, an average throughput corresponding to each application and a target transfer amount per unit time are set in a bus load target table. The bus monitor 3 controls the voltage VDD of the power source supply IC 10 and the clock frequency of the clock frequency control section 9 so as to be balanced with the target transfer amount of an application being executed by the master IP 4 in accordance with the measured traffic volume.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an electronic control unit mounted on a vehicle.

Background Art

[0002] DVFS (Dynamic Voltage Frequency Scaling) is a technology related to power control of, for example, a multi-core processor. When there are many tasks to be processed and the load is heavy, the power supply voltage and the operating clock frequency of the system are increased. When the load is light, the power supply voltage and the operating clock frequency are decreased.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, for in - vehicle electronic control units, DVFS control has not yet been applied. In DVFS control, it is important how to control the power supply voltage and the clock frequency according to the load of the system.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic control unit that can appropriately control the power supply voltage and the clock frequency according to the load in a system for controlling a vehicle.

Means for Solving the Problems

[0006] According to the electronic control device described in claim 1, it is mounted on a vehicle and is one of a plurality of bus masters that access a plurality of resources via a system bus. It includes a main master, a bus monitor disposed at least between the main master and the system bus for measuring the traffic volume based on the access states of the plurality of bus masters to the system bus, a power supply circuit that supplies operating power to the main master and is configured with a variable voltage, and a clock generation circuit that supplies an operating clock to the main master and is configured with a variable clock frequency.

[0007] In the bus load target table included in the bus monitor, a plurality of applications executed by the main master, and the average throughput and the target transfer amount per unit time corresponding to each application are set. Then, the bus monitor controls the voltage of the power supply circuit and the clock frequency of the clock generation circuit so as to balance with the target transfer amount of the application being executed by the main master according to the measured traffic volume. With this configuration, in the electronic control device mounted on the vehicle, DVFS control can be applied to optimize the target transfer amount of the application being executed by the main master according to the traffic volume measured by the bus monitor.

[0008] Specifically, like the electronic control device described in claim 2, when the bus monitor determines that the access of the main master will be in a standby state based on the measured traffic volume, the bus monitor reduces the voltage of the power supply circuit and the clock frequency of the clock generation circuit.

[0009] Also, like the electronic control device described in claim 3, when the bus monitor determines that it cannot achieve the corresponding target transfer amount in the bus load target table based on the measured traffic volume, the bus monitor increases the voltage of the power supply circuit and the clock frequency of the clock generation circuit. By controlling in these ways, DVFS control can be applied.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] (First Embodiment) Hereinafter, the first embodiment will be described. As shown in FIG. 1, the electronic control device 1 of this embodiment includes a master IP (Intellectual Property) 4 connected to a system bus 2 via a bus monitor 3, bus masters 5a, 5b, 5c directly connected to the system bus 2, an SRAM 6, and a DDR (Double Data Rate) 7, and is configured as a SoC (System on Chip). The electronic control device 1 is, for example, an ECU (Electronic Control Unit) mounted on a vehicle. The master IP 4, which is one of the bus masters and also the main master, is, for example, a CPU or a DSP (Digital Signal Processor). The RAM 6 and the DDR 7 are examples of resources. The master IP 4 and the bus masters 5a to 5c access the RAM 6, the DDR 7, etc. via the system bus 2 and execute processing according to their respective control programs.

[0012] As shown in FIG. 2, there are a voltage control unit 8 and a clock frequency control unit 9 around the bus monitor 3 and the master IP 4. The clock frequency control unit 9 corresponding to a clock generation circuit supplies a clock signal to the master IP 4, and the frequency of the clock signal is configured to be variable. Also, outside the electronic control device 1, there is a power supply IC 10 corresponding to a power supply circuit, and the IC 10 supplies an operating power supply VDD to the master IP 4. The voltage of the power supply VDD is also configured to be variable. The voltage control unit 8 and the clock frequency control unit 9 are controlled by the bus monitor 3.

[0013] As shown in FIG. 3, the bus monitor 3 includes a bus traffic measurement unit 11, a traffic determination unit 12, a bus load target table unit 13, and a change instruction unit 14. The bus traffic measurement unit 11 is, for example, a counter that counts the number of bus requests output to a bus arbiter (not shown) as the number of accesses because the master IP 4 and the bus masters 5a to 5c acquire the access right to the system bus 2. The traffic determination unit 12 determines the congestion state of the system bus 2, that is, the traffic situation, according to the above-mentioned number of accesses.

[0014] The bus load target table unit 13 is provided with a bus load target table shown in FIG. 4. The bus load target table is a table showing the average throughput [GB / s] and the target transfer amount [GB] per second for each of the functions and application programs A to D that are targets executed by the master IP4. Note that functions are also included in the concept of applications. These are obtained in advance by performing simulations or the like beforehand. The master IP4 performs processing related to the NPU (Neural network Processing Unit) as, for example, an AI (Artificial Intelligence) engine.

[0015] The traffic determination unit 12 refers to the bus load target table and determines the traffic situation of the system bus 2 as described above, and issues an instruction to the change instruction unit 14. The change instruction unit 14 outputs a voltage change instruction to the voltage control unit 8 and a frequency change instruction to the clock frequency control unit 9 in response to the input instruction.

[0016] Next, the operation of this embodiment will be described. As shown in FIG. 5, when the bus traffic measurement unit 11 of the bus monitor 3 starts measurement, it waits until bus access by the master IP4 and the bus master 5 occurs (S1), and when bus access occurs, it increments the access counter (S2). In the subsequent step S3, when the predetermined interval measurement period ends, the throughput SP is calculated by the following formula based on the count value of the access counter at that time (S4). SP = (access count value) × (transfer byte amount [Byte] per access) / (interval measurement period [s])

[0017] As shown in FIG. 6, when the bus monitor 3 is activated, it performs initial settings (S11), and when the interval time has elapsed (S12), it makes a determination in step S13. In step S13, it refers to the bus load target table and determines whether the current throughput is insufficient to achieve the target transfer amount corresponding to the type of function / application currently being executed by the master IP4. If it is insufficient (Yes), it outputs a change instruction to the voltage control unit 8 and the clock frequency control unit 9 to increase the power supply voltage VDD and the frequency of the clock signal (S15).

[0018] FIGS. 7 and 8 show images corresponding to this case. Assume that the range of the clock frequency that can be changed by the clock frequency control unit 9 is, for example, 0.8 GHz to 1.2 GHz, and the throughput of the master IP4 at a frequency of 0.8 GHz is 50 GB / s. If this throughput does not reach the target transfer amount corresponding to the currently executed function / application, the throughput is increased to 75 GB / s by increasing the clock frequency to 1.2 GHz. When the clock frequency is increased to the maximum value of 1.2 GHz, the frequency is fixed at that value. Incidentally, accordingly, the power supply voltage VDD is also increased from 0.8 V to 1.2 V, for example.

[0019] On the other hand, in step S13, if it is determined that the current throughput is sufficient (No), a determination in step S14 is made. In step S14, it determines whether the NPU processing executed by the master IP4 is in a state of being waited for because the traffic on the system bus 2 is congested. If the NPU processing is in a state of being waited for (Yes), a change instruction is output to the voltage control unit 8 and the clock frequency control unit 9 to decrease the power supply voltage VDD and the frequency of the clock signal (S16).

[0020] Figures 9 and 10 show the corresponding images for this case. Assume that the throughput of master IP4 at a frequency of 1.0 GHz is 50 GB / s and the Wait rate for waiting for processing is 80%. In this case, the congestion state of system bus 2 becomes the bottleneck and the Wait rate is increasing, and it can be said that master IP4 is operating at an unnecessarily high frequency. Therefore, the throughput is reduced to 25 GB / s by reducing the clock frequency to 0.5 GHz. Incidentally, in conjunction with this, the power supply voltage VDD is also reduced, for example, from 1.0 V to 0.5 V.

[0021] On the other hand, in step S14, if the NPU process is not in a waiting state (No), the determination in step S17 is made. In step S17, the current throughput of master IP4 is compared with the corresponding target throughput in the bus load target table. If the current throughput matches the target throughput, the process proceeds to step S12. If the current throughput exceeds the target throughput, the same process as in step S16 is performed (S18), and if the current throughput is lower than the target throughput, the same process as in step S15 is performed (S19).

[0022] As described above, according to the present embodiment, in the electronic control unit 1 mounted on the vehicle, a master IP4 and a bus master 5 that access SRAM6, DDR7, etc. via the system bus 2, and a bus monitor 3 that is disposed between the master IP4 and the system bus 2 and measures the traffic volume based on the access states of the master IP4 and the bus master 5 to the system bus 2, a power supply IC 10 that supplies the operating power supply VDD to the master IP4 and is configured to have a variable voltage, and a clock frequency control unit 9 that supplies the operating clock to the master IP4 and is configured to have a variable clock frequency are provided.

[0023] In the bus load target table included in the bus monitor 3, a plurality of applications executed by the master IP4, the average throughput corresponding to each application, and the target transfer amount per unit time are set. Then, the bus monitor 3 controls the voltage VDD of the power supply IC 10 and the clock frequency of the clock frequency control unit 9 so as to balance with the target transfer amount of the application being executed by the master IP4 according to the measured traffic volume. With this configuration, in the electronic control unit 1 mounted on the vehicle, DVFS control can be applied so as to optimize the target transfer amount of the application being executed by the master IP4 according to the traffic volume measured by the bus monitor 3.

[0024] Specifically, when the bus monitor 3 determines that the access of the master IP4 is in a standby state based on the measured traffic volume, the bus monitor 3 decreases the voltage VDD of the power supply IC 10 and the clock frequency of the clock frequency control unit 9. Also, when the bus monitor 3 determines that the corresponding target transfer amount in the bus load target table cannot be achieved based on the measured traffic volume, the bus monitor 3 increases the voltage VDD of the power supply IC 10 and the clock frequency of the clock frequency control unit 9. By controlling in these ways, DVFS control can be applied.

[0025] (Second Embodiment) Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted, and the different parts will be described. As shown in FIG. 11, the electronic control unit 21 of the second embodiment includes a bus monitor 22 having a data compression / expansion function instead of the bus monitor 3. As shown in FIG. 12, in the bus monitor 22, a data compression / decompression circuit unit 23 is arranged between the master IP4 and the system bus 2, and the bus traffic measurement unit 11 accesses the system bus 2 via the data compression / decompression circuit unit 23.

[0026] As shown in FIG. 13, the data compression / decompression circuit unit 23 waits until a bus access by the master IP4 occurs (S21), and when a bus access occurs, determines whether it is a write access or a read access (S22). If it is a write access, the write data of the master IP4 is compressed and written to the SRAM 6 or the DDR 7 (S23). On the other hand, if it is a read access, the read data read from the SRAM 6 or the DDR 7 is decompressed and read by the master IP4 (S24).

[0027] As described above, according to the second embodiment, the bus monitor 22 compresses the data for which the master IP4 performs a write access to the system bus 2 and decompresses the data for which the master IP4 performs a read access. With this configuration, the amount of data on the system bus 2 can be reduced, and the congestion of the bus traffic can be alleviated.

[0028] (Third Embodiment) In the third embodiment, while the electronic control device 1A is actually operating, the bus monitor 3A dynamically generates and updates the bus load target table. The update is performed at regular intervals, for example, every 10 seconds. As shown in FIG. 14, when the above-described regular period elapses in step S31, it waits until a bus access by the master IP4 occurs (S32). When a bus access occurs, the bus traffic volume is measured (S33), and the average throughput is calculated (S34). In the subsequent step S35, until the calibration period for update ends, it returns to step 32. When the calibration period ends, the bus load target table is updated to the result of calibration (S36). The above processing is performed for each type of function / application executed by the master IP4.

[0029] As described above, according to the third embodiment, the bus monitor 3A measures the average throughput when the master IP4 executes each application, and dynamically generates the bus load target table according to the measured result. Thereby, a bus load target table according to the actual processing situation can be generated.

[0030] (Fourth Embodiment) In the fourth embodiment, as shown in FIG. 15, while the electronic control unit 1 is actually operating, for example, if machine learning or the like is applied to predict a period during which burst traffic becomes congested as the processing time elapses, the voltage VDD and the clock frequency are maximized before the predicted time to enter that period. Thereby, processing can be executed quickly before the period during which burst traffic becomes congested.

[0031] (Fifth Embodiment) The fifth embodiment shows a case where the configuration such as the electronic control unit 1 is applied to a configuration closer to that actually mounted on a vehicle and performing AI processing or the like. As shown in FIG. 16, in the electronic control unit 31, the system bus 2 is connected to a CPU 32, a DSP 33, a DNN (Deep Neural Network) 34, an extended specification accelerator IP 35, a GPU (Graphic Processing Unit) 36, an ISP (Image Signal Processor) 37, a bus master 5, an SRAM 6, a DDR 7, and the like. Note that the arrows connecting to the system bus 2 that are painted black indicate access via the bus monitor 3.

[0032] The CPU 32, the DSP 33, and the DNN 34 have a multi-core configuration, and the CPU 32 includes a primary cache and a secondary cache (not shown). The CPU 32 is actually equipped with two types of CPUs, one for OS management and application execution and the other for real-time processing, and is responsible for all software processing. The DSP 33 mainly executes fixed / floating-point multiply-accumulate operations at high speed. The DNN 34 can execute 4- or 8-bit low-bit integer multiply-accumulate operations at high speed.

[0033] Generally, in terms of general-purpose complexity, it is CPU > DSP > DNN. However, in AI processing and other scenarios, for processing that requires high-speed simple operations, it is DNN > DSP > CPU. Therefore, each performs the operations they are good at and shares the processing. In recent years, the in-vehicle autonomous driving control SoC has become more complex in control, and the amount of operations has also tended to increase enormously. Therefore, without the CPU, DSP, and DNN cooperating with each other and sharing the operations they are good at, advanced control cannot be achieved. Also, if the three macros of CPU, DSP, and DNN keep moving simultaneously, not only will the bus bandwidth saturate and the performance cannot be fully utilized, but the power consumption will also increase, and the heat generation problem must also be considered. Therefore, the present invention is required to realize the optimal cooperative operation of the CPU, DSP, and DNN.

[0034] (Other Embodiments) The resources are not limited to SRAM6 and DDR7. The specific numerical values of the power supply voltage and the clock frequency may be appropriately changed according to individual designs. Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to these embodiments and structures. The present disclosure also includes various modifications and modifications within the equivalent scope. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, are also within the scope and spirit of the present disclosure.

Description of Reference Numerals

[0035] In the drawings, 1 represents an electronic control unit, 2 represents a system bus, 3 represents a bus monitor, 4 represents a master IP, 5 represents a bus master, 6 represents SRAM, 7 represents DDR, 8 represents a voltage control unit, 9 represents a clock frequency control unit, and 10 represents a power supply IC.

Claims

1. It is mounted on a vehicle and a plurality of bus masters (4, 5a to 5c) that access a plurality of resources via a system bus (2), a main master (4) that is one of the plurality of bus masters, a bus monitor (3, 3A, 22) that is disposed at least between the main master and the system bus and measures the traffic volume based on the access states of the plurality of bus masters to the system bus, a power supply circuit (10) that supplies operating power to the main master and is configured such that the voltage is variable, a clock generation circuit (9) that supplies an operating clock to the main master and is configured such that the clock frequency is variable, and the bus monitor includes a bus load target table, in the bus load target table, a plurality of applications executed by the main master, and an average throughput and a target transfer amount per unit time corresponding to each application are set, an electronic control unit that controls the voltage of the power supply circuit and the clock frequency of the clock generation circuit so as to balance with the target transfer amount of the application being executed by the main master according to the measured traffic volume.

2. The electronic control unit according to claim 1, wherein when the bus monitor determines, based on the measured traffic volume, that the access of the main master has entered a standby state, the bus monitor controls to decrease the voltage of the power supply circuit and the clock frequency of the clock generation circuit.

3. The electronic control unit according to claim 1 or 2, wherein when the bus monitor determines, based on the measured traffic volume, that the corresponding target transfer amount in the bus load target table cannot be achieved, the bus monitor controls to increase the voltage of the power supply circuit and the clock frequency of the clock generation circuit.

4. The electronic control unit according to claim 1 or 2, wherein the bus monitor (22) compresses data that the main master writes to the system bus and decompresses data that the main master reads from the system bus.

5. The electronic control unit according to claim 1 or 2, wherein the bus monitor (3A) measures the average throughput when the main master executes each application and dynamically generates the bus load target table according to the measured result.

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