Method of manufacturing a semiconductor device

Abstract

To provide a semiconductor device capable of suitably forming a resin layer on a semiconductor chip and a method for manufacturing the same.SOLUTION: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of laminates on a substrate. Each laminate is formed so as to include a plurality of semiconductor chips laminated on the substrate. The method also includes arranging a plurality of first wires connecting the laminates to each other on the laminates. The method further includes forming a resin layer on the laminates and the first wires. In addition, the method includes lowering an upper surface of the resin layer until the first wires are exposed on the upper surface of the resin layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] When forming a resin layer on a semiconductor chip, how to form the resin layer becomes a problem. For example, when polishing or grinding the resin layer on the semiconductor chip, how to detect the end point of polishing or grinding becomes a problem.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a semiconductor device and a method for manufacturing the same that can suitably form a resin layer on a semiconductor chip.

Means for Solving the Problems

[0005] According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies being formed to include a plurality of semiconductor chips stacked on the substrate. The method further includes disposing a plurality of first wires on the stacked body to connect the stacked bodies to each other. The method further includes forming a resin layer on the stacked body and the first wires. The method further includes lowering the upper surface of the resin layer until the first wires are exposed on the upper surface of the resin layer.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 35, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment.

[0009] The semiconductor device in FIG. 1 includes a substrate 1 and a stacked body S. The stacked body S includes a plurality of memory chips 3, a control chip 5, and a metal piece 7. FIG. 1 further shows an adhesive layer 2 provided on the lower surface of each memory chip 3, an adhesive layer 4 provided on the lower surface of the control chip 5, and an adhesive layer 6 provided on the lower surface of the metal piece 7. Each memory chip 3 and the control chip 5 are examples of semiconductor chips. Each memory chip 3 is an example of a first semiconductor chip, and the control chip 5 is an example of a second semiconductor chip.

[0010] The semiconductor device in FIG. 1 further includes a plurality of metal pads 11, a plurality of vertical wires 12, a plurality of metal pads 13, a plurality of bonding wires 14, a plurality of metal pads 15, a plurality of metal pillars 16, a plurality of metal pads 17, a bonding wire 18, a resin layer 21, a redistribution layer (RDL) 22, a shield layer 23, a plurality of metal pads 24, and a plurality of metal bumps 25. The bonding wire 18 is an example of a first wire, and the vertical wire 12 is an example of a second wire. The redistribution layer 22 is an example of a first redistribution layer, and the shield layer 23 is an example of a metal layer.

[0011] FIG. 1 shows the X direction, Y direction, and Z direction that are perpendicular to each other. In FIG. 1, the X direction and the Y direction are parallel to the surface of the substrate 1, and the Z direction is perpendicular to the surface of the substrate 1. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may coincide with the direction of gravity or may not coincide with the direction of gravity. The X direction is an example of a first direction, and the Y direction is an example of a second direction. The Z direction is an example of the stacking direction of the stacked body S.

[0012] The substrate 1 is, for example, a semiconductor substrate such as a silicon substrate or an insulating substrate such as a glass substrate. In FIG. 1, the plurality of memory chips 3 are sequentially stacked on the substrate 1, and the control chip 5 and the metal piece 7 are stacked on the uppermost memory chip 3. Each memory chip 3 is adhered to the substrate 1 or another memory chip 3 by an adhesive layer 2. The control chip 5 is adhered to the uppermost memory chip 3 by an adhesive layer 4. The metal piece 7 is adhered to the uppermost memory chip 3 by an adhesive layer 6. These adhesive layers 2, 4, and 6 are, for example, DAF (Die Attachment Film). Note that the metal piece 7 may be disposed on the uppermost memory chip 3 without using the adhesive layer 6.

[0013] Each memory chip 3 includes a memory cell array including a plurality of memory cells. These memory cells may be formed by a charge storage layer or a channel semiconductor layer extending in the Z direction. That is, these memory cells may form a memory cell array of a three-dimensional semiconductor memory. The plurality of memory chips 3 of the present embodiment generally have the same shape. Therefore, these memory chips 3 of the present embodiment generally have the same area in plan view, that is, generally have the same area when viewed from above. Further, these memory chips 3 are stacked so as to be shifted from each other in the X direction in plan view. Therefore, it is possible to dispose the metal pads 11 on these memory chips 3.

[0014] The control chip 5 functions as a controller that controls the operation of each memory chip 3. This controller is formed by, for example, a CMOS circuit. The control chip 5 of the present embodiment has an area smaller than the area of each memory chip 3 in plan view. Further, the thickness (length in the Z direction) of the control chip 5 of the present embodiment is set to be thinner than the thickness of each memory chip 3.

[0015] The metal piece 7 is used as a metal pad for the bonding wire 18. The metal piece 7 is formed of a metal such as Al (aluminum) or Cu (copper), for example. The metal piece 7 of the present embodiment has an area smaller than the area of each memory chip 3 in plan view. Further, the thickness of the metal piece 7 of the present embodiment is set to, for example, 1 μm or more, and specifically, is set to about 30 μm.

[0016] Each metal pad 11 is provided on one of the memory chips 3. In FIG. 1, one vertical wire 12 is provided on one metal pad 11, and one metal pad 13 is provided on one vertical wire 12. Thus, each vertical wire 12 has a lower end electrically connected to the metal pad 11 and an upper end electrically connected to the metal pad 13. Each vertical wire 12 is electrically connected to the memory chip 3 via the metal pad 11 and is electrically connected to the rewiring layer 22 via the metal pad 13. Each vertical wire 12 extends in the Z direction from the metal pad 11 to the metal pad 13, that is, extends perpendicular to the surface of the substrate 1. Each vertical wire 12 is formed of a metal such as Au (gold), Ag (silver), or Cu (copper), for example.

[0017] Each bonding wire 14 is provided on two metal pads 11 and electrically connects these metal pads 11. Each bonding wire 14 electrically connects, for example, one memory chip 3 in the laminate S and another memory chip 3 in the laminate S. Each bonding wire 14 is formed of a metal such as Au (gold), Ag (silver), or Cu (copper), for example. The semiconductor device of the present embodiment may include not only the bonding wires 14 included in the XZ cross section shown in FIG. 1 but also bonding wires 14 not included in the XZ cross section shown in FIG. 1.

[0018] Each metal pad 15 is provided on the control chip 5. In FIG. 1, one metal pillar 16 is provided on one metal pad 15, and one metal pad 17 is provided on one metal pillar 16. Therefore, each metal pillar 16 has a lower end electrically connected to the metal pad 15 and an upper end electrically connected to the metal pad 17. Each metal pillar 16 is electrically connected to the control chip 5 via the metal pad 15 and is electrically connected to the rewiring layer 22 via the metal pad 17. Each metal pillar 16 extends in the Z direction from the metal pad 15 to the metal pad 17. Each metal pillar 16 is formed of a metal such as Cu (copper), Sn (tin), SnAg (tin-silver alloy), for example. Each metal pillar 16 is formed by plating with such a metal, for example. Each metal pillar 16 may be formed of a single metal layer or may be formed of a plurality of metal layers. The metal pillar 16 may be formed in the same manner as the vertical wire 12. In plan view, the plurality of metal pillars 16 may be provided at a higher density than the plurality of vertical wires 12.

[0019] The bonding wire 18 is provided on the metal piece 7 and extends from the upper surface of the metal piece 7 to the upper surface of the resin layer 21. Therefore, the bonding wire 18 shown in FIG. 1 has a lower end electrically connected to the metal piece 7 and an upper end in contact with the rewiring layer 22. The bonding wire 18 is formed of a metal such as Au (gold), Ag (silver), Cu (copper), for example. The bonding wire 18 of the present embodiment extends in the Z direction in the same manner as the vertical wire 12, but is used for a different purpose from the vertical wire 12. Therefore, the bonding wire 18 may have different shape properties and material properties from the vertical wire 12. For example, it may have a diameter thicker than the diameter of the vertical wire 12 or may be formed of a material different from the material of the vertical wire 12.

[0020] As described below, when manufacturing the semiconductor device of the present embodiment, a plurality of stacked bodies S are formed on a substrate 11, and a plurality of bonding wires 18 for connecting these stacked bodies S to each other are arranged on these stacked bodies S. Further, a resin layer 21 is formed on these stacked bodies S and the bonding wires 18, and then the upper surface of the resin layer 21 is polished or ground. At this time, the bonding wire 18 is used to detect the end point of polishing or grinding. FIG. 1 shows the bonding wire 18 remaining after polishing or grinding.

[0021] In the present embodiment, the vertical wire 12 is provided to electrically connect the memory chip 3 and the redistribution layer 22, while the bonding wire 18 is used to detect the end point of polishing or grinding of the resin layer 21. In order to facilitate detection of the end point of polishing or grinding, the bonding wire 18 may have different shape properties and material properties from those of the vertical wire 12. Details of the end point detection method using the bonding wire 18 will be described later.

[0022] The resin layer 21 is formed on the substrate 1 and the stacked body S. The vertical wire 12, the bonding wire 14, the metal pillar 16, the bonding wire 18, etc. are also provided in the resin layer 21. The resin layer 21 may be formed of any resin. The resin forming the resin layer 21 is also called a mold resin. The resin layer 21 of the present embodiment is formed of an insulator.

[0023] The redistribution layer 22 is provided on the resin layer 21. The redistribution layer 22 includes a plurality of insulating films and a plurality of wiring layers, and these wiring layers form a multilayer wiring structure. On the other hand, at least a part of these insulating films is formed of, for example, resin. FIG. 1 schematically shows a plurality of wirings L1, L2 in the redistribution layer 22. Each wiring L1 electrically connects the vertical wire 12 and the metal pillar 16. Each wiring L2 electrically connects the metal pillar 16 and the metal bump 25.

[0024] The shield layer 23 is formed on the lower surface of the substrate 1 and the side surfaces of the substrate 1, the resin layer 21, and the rewiring layer 22. The shield layer 23 functions, for example, as an electromagnetic shield of the semiconductor device of the present embodiment. The shield layer 23 is formed of, for example, a plurality of metal layers.

[0025] Each metal pad 24 is provided on the rewiring layer 22. In FIG. 1, one metal bump 25 is provided on one metal pad 24. Each metal bump 25 is electrically connected to the control chip 5 via, for example, the metal pad 24, the wiring L2, and the metal pillar 16. Each metal bump 25 is used to electrically connect the semiconductor device of the present embodiment to another device.

[0026] FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment.

[0027] First, the substrate 1 is prepared, and a plurality of stacked bodies S are formed on the substrate 1 (FIG. 2(a)). The substrate 1 shown in FIG. 2(a) is, for example, a semiconductor substrate or an insulating substrate having the shape of a wafer. Each stacked body S is formed by stacking a plurality of memory chips 3 on the substrate 1 and stacking the control chip 5 and the metal piece 7 on the uppermost memory chip 3. Each memory chip 3 is disposed on the substrate 1 or another memory chip 3 via the adhesive layer 2. The control chip 5 is disposed on the uppermost memory chip 3 via the adhesive layer 4. The metal piece 7 is disposed on the uppermost memory chip 3 via the adhesive layer 6. FIG. 2(a) shows two of the plurality of stacked bodies S.

[0028] Next, a plurality of metal pads 11, a plurality of vertical wires 12, a plurality of bonding wires 14, a plurality of metal pads 15, a plurality of metal pillars 16, and a plurality of bonding wires 18 are arranged on these laminates S (FIG. 2(a)). However, in FIG. 2(a), the illustration of the metal pads 11 and 15 is omitted. Also, FIG. 2(a) shows one bonding wire 18 out of the plurality of bonding wires 18. The bonding wire 18 shown in FIG. 2(a) has one end portion disposed on the metal piece 7 of one laminate S and the other end portion disposed on the metal piece 7 of the other laminate S. In this way, the bonding wire 18 shown in FIG. 2(a) connects these two laminates S to each other. This bonding wire 18 extends generally in the X direction. On the other hand, the vertical wire 12 extends in the Z direction due to the rigidity of the vertical wire 12 itself.

[0029] Note that in FIG. 2(a), for the sake of clarity of the positional relationship between the vertical wire 12 and the bonding wire 18, the vertical wire 12 and the bonding wire 18 are illustrated so as to overlap each other. However, the vertical wire 12 and the bonding wire 18 of the present embodiment are arranged on the laminate S so as not to contact each other. Also, the metal pillar 16 and the bonding wire 18 of the present embodiment are arranged on the laminate S so as not to contact each other.

[0030] Next, a resin layer 21 is formed on the substrate 1 and the laminate S (FIG. 2(a)). As a result, the laminate S is covered with the resin layer 21. Similarly, the metal pads 11, the vertical wire 12, the bonding wire 14, the metal pads 15, the metal pillar 16, and the bonding wire 18 are also covered with the resin layer 21.

[0031] Next, the upper surface of the resin layer 21 is polished or ground (FIG. 2(b)). As a result, the resin layer 21 is gradually removed from the upper surface, and the upper surface of the resin layer 21 descends. The polishing or grinding of the resin layer 21 is performed until the vertical wire 12, the metal pillar 16, and the bonding wire 18 are exposed on the upper surface of the resin layer 21. FIG. 2(b) shows the vertical wire 12, the metal pillar 16, and the bonding wire 18 remaining after polishing or grinding. The polishing or grinding of the resin layer 21 is performed, for example, using a CMP (Chemical Mechanical Polishing) apparatus or a grind apparatus. The polishing or grinding in this embodiment is performed until the bonding wire 18 is cut, and ends before the control chip 5 and the metal piece 7 are exposed on the upper surface of the resin layer 21.

[0032] In the process of FIG. 2(b), the end point of the polishing or grinding of the resin layer 21 is detected using the bonding wire 18. For example, by detecting that a component of the CMP apparatus or the grind apparatus has reached the bonding wire 18, that the bonding wire 18 has been cut by polishing or grinding, or that the state of the bonding wire 18 has changed due to polishing or grinding, it is possible to detect the end point of the polishing or grinding. Hereinafter, three examples of the end point detection method using the bonding wire 18 will be described.

[0033] In the first example, the motor current flowing in the motor of the CMP apparatus or the grind apparatus is measured. In the second example, the eddy current flowing in the bonding wire 18 is measured by an eddy current sensor. In the third example, the reflectance of light on the upper surface of the resin layer 21 is measured by an optical sensor. The values of the motor current, the eddy current, and the reflectance change due to the influence of the polishing or grinding of the bonding wire 18. For example, when the bonding wire 18 is exposed on the upper surface of the resin layer 21, the friction characteristics, the electrical characteristics, and the optical characteristics of the upper surface of the resin layer 21 change, which changes the values of the motor current, the eddy current, and the reflectance. Therefore, according to this embodiment, by detecting a change in the motor current, the eddy current, or the reflectance, the end point of the polishing or grinding of the resin layer 21 can be detected.

[0034] In the end point detection of this embodiment, a second example is adopted. That is, the end point of the polishing or grinding of the resin layer 21 is detected by detecting the change in eddy current. In this case, generally, the larger the size of the bonding wire 18 or the metal piece 7, the larger the value of the eddy current. As a result, the end point of the polishing or grinding can be detected with higher accuracy. Therefore, it is desirable that the bonding wire 18 and the metal piece 7 of this embodiment have a size capable of generating a sufficient eddy current. Also, it is desirable that the bonding wire 18 and the metal piece 7 of this embodiment are formed of a material capable of generating a sufficient eddy current. In this embodiment, the end point of the polishing or grinding is detected by detecting that the value of the eddy current significantly decreases.

[0035] FIG. 2(a) and FIG. 2(b) show a plurality of device regions R1 on the substrate 1 and a scribe region R2 on the substrate 1. Each of these device regions R1 has a rectangular planar shape. The scribe region R2 has a mesh-like planar shape that individually surrounds these device regions R1. Each device region R1 corresponds to one semiconductor device shown in FIG. 1 and includes one laminate S.

[0036] After performing the process of FIG. 2(b), a metal pad 13, a metal pad 17, and a redistribution layer 22 are arranged on the resin layer 21 (see FIG. 1). Next, the substrate 1, the resin layer 21, and the redistribution layer 22 are cut along the scribe region R2. As a result, the substrate 1, the resin layer 21, and the redistribution layer 22 are divided into individual device regions R1. Next, a shield layer 23 is formed on the lower surface of the substrate 1 and on the side surfaces of the substrate 1, the resin layer 21, and the redistribution layer 22 for each device region R1. Next, a metal pad 24 and a metal bump 25 are formed on the redistribution layer 22 for each device region R1. In this way, the semiconductor device of this embodiment is manufactured.

[0037] FIG. 3 is a perspective view showing a method of manufacturing the semiconductor device of the first embodiment.

[0038] FIG. 3 shows a plurality of stacked bodies S formed in the process of FIG. 2(a). These stacked bodies S are arranged in the shape of a two-dimensional array (square lattice) adjacent to each other in the X direction and the Y direction. In other words, these stacked bodies S are arranged at the intersections of a plurality of straight lines extending in the X direction and a plurality of straight lines extending in the Y direction.

[0039] FIG. 3 further shows a plurality of bonding wires 18 formed in the process of FIG. 2(a). Each bonding wire 18 shown in FIG. 3 is disposed on two metal pieces 7 of two stacked bodies S, connecting these stacked bodies S to each other. Also, each bonding wire 18 shown in FIG. 3 extends parallel to the X direction or the Y direction in a plan view. In FIG. 3, four bonding wires 18 are disposed on each metal piece 7.

[0040] In FIG. 3, four metal pieces 7 are electrically connected to each other by four bonding wires 18. Therefore, these metal pieces 7 are at the same potential, and eddy currents flow between these metal pieces 7. However, as the polishing or grinding of the resin layer 21 progresses, these bonding wires 18 are cut, and the eddy currents disappear or decrease. Thereby, it becomes possible to detect the end point of polishing or grinding.

[0041] FIG. 4 is a plan view showing a method of manufacturing a semiconductor device according to the first embodiment.

[0042] FIG. 4(a) shows the substrate 1 after the bonding wires 18 are disposed in the process of FIG. 2(a). In FIG. 4(a), a plurality of stacked bodies S are arranged on the substrate 1 in the shape of a two-dimensional array, and a plurality of bonding wires 18 are disposed on these stacked bodies S. Each bonding wire 18 extends parallel to the X direction or the Y direction in the plan view of FIG. 4(a). FIG. 4(a) shows the uppermost memory chip 3 of each stacked body S and the metal piece 7 of each stacked body S, but the illustration of the control chip 5 of each stacked body S is omitted.

[0043] FIG. 4(b) shows the substrate 1 after the bonding wire 18 is cut in the process of FIG. 2(b). Note that although a part of each bonding wire 18 remains on each metal piece 7 even after being cut in the process of FIG. 2(b), FIG. 4(b) omits its illustration.

[0044] FIGS. 5 to 10 are cross-sectional views showing a method of manufacturing the semiconductor device of the first embodiment. Specifically, FIGS. 5 to 10 show the details of the processes of FIGS. 2(a) and 2(b). Further, FIGS. 5 to 10 show the process of processing one device region R1 out of the plurality of device regions R1.

[0045] First, the substrate 1 is prepared, and the laminate S is formed on the substrate 1 (FIG. 5). The laminate S is formed by laminating a plurality of memory chips 3 on the substrate 1 and laminating the control chip 5 and the metal pieces 7 on the uppermost memory chip 3.

[0046] Next, a plurality of metal pads 11, a plurality of vertical wires 12, a plurality of bonding wires 14, a plurality of metal pads 15, a plurality of metal pillars 16, and bonding wires 18 are arranged on the laminate S (FIG. 6). Each vertical wire 12 is arranged on any one of the memory chips 3 via the metal pad 11. Each bonding wire 14 is arranged on two metal pads 11. Each metal pillar 16 is arranged on the control chip 5 via the metal pad 11. The bonding wires 18 are arranged on the metal pieces 7 of the laminate S shown in FIG. 6 and on the metal pieces 7 of another laminate S (not shown). As a result, these laminates S are connected to each other by the bonding wires 18.

[0047] Next, a resin layer 21 is formed on the substrate 1 and the laminate S (FIG. 7). As a result, the laminate S is covered with the resin layer 21. Similarly, the metal pads 11, the vertical wires 12, the bonding wires 14, the metal pads 15, the metal pillars 16, and the bonding wires 18 are also covered with the resin layer 21.

[0048] Next, the upper surface of the resin layer 21 is polished or ground (FIG. 8). As a result, the resin layer 21 is gradually removed from the upper surface, and the upper surface of the resin layer 21 drops. The polishing or grinding of the resin layer 21 is performed until the vertical wire 12, the metal pillar 16, and the bonding wire 18 are exposed on the upper surface of the resin layer 21. The polishing or grinding in the present embodiment is performed until the bonding wire 18 is cut, and ends before the control chip 5 and the metal piece 7 are exposed on the upper surface of the resin layer 21.

[0049] Next, a plurality of metal pads 13, a plurality of metal pads 17, and a redistribution layer 22 are arranged on the resin layer 21 (FIG. 9). As a result, the vertical wire 12 and the metal pillar 16 are electrically connected by the wiring L1. Next, the substrate 1, the resin layer 21, and the redistribution layer 22 are cut along the scribe region R2 (FIG. 9). As a result, the substrate 1, the resin layer 21, and the redistribution layer 22 are divided into individual device regions R1.

[0050] Next, a shield layer 23 is formed on the lower surface of the substrate 1 and on the side surfaces of the substrate 1, the resin layer 21, and the redistribution layer 22 for each device region R1 (FIG. 10). Next, a plurality of metal pads 24 and a plurality of metal bumps 25 are formed on the redistribution layer 22 for each device region R1 (FIG. 10). As a result, the metal pillar 16 and the metal bump 25 are electrically connected by the wiring L2. Note that the bonding wire 18 in the present embodiment is not electrically connected to the wiring in the redistribution layer 22 and is electrically insulated from the wiring in the redistribution layer 22. In this way, the semiconductor device of the present embodiment is manufactured.

[0051] As described above, when manufacturing the semiconductor device of the present embodiment, a plurality of stacked bodies S are formed on the substrate 11, and a plurality of bonding wires 18 for connecting these stacked bodies S to each other are arranged on these stacked bodies S. Further, a resin layer 21 is formed on these stacked bodies S and the bonding wires 18, and then the upper surface of the resin layer 21 is polished or ground. Therefore, according to the present embodiment, it becomes possible to suitably form the resin layer 21. For example, by using the bonding wire 18 to detect the end point of polishing or grinding, it becomes possible to form the resin layer 21 polished or ground to a desired thickness.

[0052] In addition, each memory chip 3 of the present embodiment may include any type of memory cell array. For example, each memory chip 3 may include a memory cell array of a NAND memory, or may include a memory cell array of a DRAM. Further, each stacked body S of the present embodiment may include a semiconductor chip other than the memory chip 3, or may include a semiconductor chip other than the control chip 5. Further, the semiconductor device of the present embodiment may include a wire other than the bonding wire 18 on the metal piece 7, or may include a wire other than the vertical wire 12 on the metal pad 11. The same applies to the second to sixth embodiments described later.

[0053] (Second Embodiment) FIG. 11 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0054] The semiconductor device of the present embodiment shown in FIG. 11 includes the same components as the semiconductor device of the first embodiment shown in FIG. 1. However, the metal piece 7 of the present embodiment has the same area as the area of each memory chip 3 in plan view. Further, in the stacked body S of the present embodiment, the metal piece 7 is stacked on the uppermost memory chip 3, and the control chip 5 is stacked on the metal piece 7.

[0055] According to this embodiment, by increasing the size of the metal piece 7, it becomes possible to generate a large eddy current. On the other hand, according to the first embodiment, by laminating the metal piece 7 and the control chip 5 on the topmost memory chip 3, it becomes possible to reduce the height of the laminate S.

[0056] FIG. 12 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the second embodiment.

[0057] First, a substrate 1 is prepared, and a plurality of laminates S are formed on the substrate 1 (FIG. 12(a)). Each laminate S is formed by laminating a plurality of memory chips 3 on the substrate 1, laminating a metal piece 7 on the topmost memory chip 3, and laminating a control chip 5 on the metal piece 7. FIG. 12(a) shows two of the plurality of laminates S.

[0058] Next, a plurality of metal pads 11, a plurality of vertical wires 12, a plurality of bonding wires 14, a plurality of metal pads 15, a plurality of metal pillars 16, and a plurality of bonding wires 18 are arranged on these laminates S (FIG. 12(a)). However, FIG. 12(a) omits the illustration of the metal pads 11 and 15. Also, FIG. 12(a) shows one of the plurality of bonding wires 18.

[0059] Next, a resin layer 21 is formed on the substrate 1 and the laminate S (FIG. 12(a)). As a result, the laminate S is covered by the resin layer 21.

[0060] Next, the upper surface of the resin layer 21 is polished or ground (FIG. 12(b)). As a result, the resin layer 21 is gradually removed from the upper surface, and the upper surface of the resin layer 21 drops. The end point of the polishing or grinding in this embodiment is detected using the bonding wire 18, similar to the first embodiment.

[0061] After performing the process of FIG. 12(b), a metal pad 13, a metal pad 17, and a rewiring layer 22 are disposed on the resin layer 21 (see FIG. 11). Next, the substrate 1, the resin layer 21, and the rewiring layer 22 are cut along the scribe region R2. As a result, the substrate 1, the resin layer 21, and the rewiring layer 22 are divided into individual device regions R1. Next, a shield layer 23 is formed on the lower surface of the substrate 1 and on the side surfaces of the substrate 1, the resin layer 21, and the rewiring layer 22 for each device region R1. Next, a metal pad 24 and a metal bump 25 are formed on the rewiring layer 22 for each device region R1. In this way, the semiconductor device of the present embodiment is manufactured.

[0062] FIG. 13 is a perspective view showing a method of manufacturing a semiconductor device according to the second embodiment.

[0063] FIG. 13 shows a plurality of stacked bodies S and a plurality of bonding wires 18 formed in the process of FIG. 12(a). Each bonding wire 18 shown in FIG. 13 is disposed on two metal pieces 7 of two stacked bodies S, and connects these stacked bodies S to each other. The metal piece 7 of the present embodiment is disposed between the uppermost memory chip 3 and the control chip 5.

[0064] FIGS. 14 to 18 are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment. Specifically, FIGS. 14 to 18 show the details of the processes of FIGS. 12(a) and 12(b). Further, FIGS. 14 to 18 show the process of processing one device region R1 out of the plurality of device regions R1.

[0065] First, a substrate 1 is prepared, and a stacked body S is formed on the substrate 1 (FIG. 14). The stacked body S is formed by stacking a plurality of memory chips 3 on the substrate 1, stacking a metal piece 7 on the uppermost memory chip 3, and stacking a control chip 5 on the metal piece 7.

[0066] Next, a plurality of metal pads 11, a plurality of vertical wires 12, a plurality of bonding wires 14, a plurality of metal pads 15, a plurality of metal pillars 16, and a bonding wire 18 are arranged on the laminate S (FIG. 15). Next, a resin layer 21 is formed on the substrate 1 and the laminate S (FIG. 16). Next, the upper surface of the resin layer 21 is polished or ground (FIG. 17).

[0067] Next, a plurality of metal pads 13, a plurality of metal pads 17, and a redistribution layer 22 are arranged on the resin layer 21 (FIG. 18). Next, the substrate 1, the resin layer 21, and the redistribution layer 22 are cut along the scribe region R2 (FIG. 18). Next, a shield layer 23 is formed on the lower surface of the substrate 1 and on the side surfaces of the substrate 1, the resin layer 21, and the redistribution layer 22 for each device region R1 (FIG. 18). Next, a plurality of metal pads 24 and a plurality of metal bumps 25 are formed on the redistribution layer 22 for each device region R1 (FIG. 18). In this way, the semiconductor device of the present embodiment is manufactured.

[0068] FIG. 19 is a cross-sectional view showing a first example of the end point detection method according to the second embodiment.

[0069] FIG. 19 shows a step of polishing the upper surface of the resin layer 21 of the present embodiment by the CMP apparatus 31. When polishing the upper surface of the resin layer 21 by the CMP apparatus 31, the upper surface of the resin layer 21 is brought into contact with the CMP apparatus 31 by facing the upper surface of the resin layer 21 downward. Therefore, the upper surface of the resin layer 21 shown in FIG. 19 faces the -Z direction.

[0070] In FIG. 19, the CMP apparatus 31 includes a polishing table 31a, a polishing pad 31b, and a sensor 31c. The polishing pad 31b is placed on the polishing table 31b and rotated by the polishing table 31b. The CMP apparatus 31 can polish the upper surface of the resin layer 21 by pressing the upper surface of the resin layer 21 against the upper surface of the rotating polishing pad 31b.

[0071] Sensor 31c is inserted into the holes provided in polishing table 31a and polishing pad 31b. Sensor 31c is, for example, a distance sensor using eddy current. FIG. 19 shows the distance between sensor 31c and metal piece 7 with an arrow. In this case, CMP apparatus 31 can measure the above distance or detect the end point of polishing of resin layer 21 by measuring the eddy current flowing in bonding wire 18 with sensor 31c. Note that the first method shown in FIG. 19 is applicable to each embodiment other than the second embodiment.

[0072] FIG. 20 is a cross-sectional view showing a second example of the end point detection method of the second embodiment.

[0073] FIG. 20 shows the step of grinding the upper surface of resin layer 21 of the present embodiment with grinding apparatus 32. When grinding the upper surface of resin layer 21 with grinding apparatus 32, grinding apparatus 32 is brought into contact with the upper surface of resin layer 21 with the upper surface of resin layer 21 facing upward. Therefore, the upper surface of resin layer 21 shown in FIG. 20 faces the +Z direction.

[0074] In FIG. 20, grinding apparatus 32 includes wheel 32a, a plurality of convex portions 32b, and sensor 32c. These convex portions 32b are provided on the outer peripheral surface of wheel 32a and rotate together with wheel 32a. Grinding apparatus 32 can grind the upper surface of resin layer 21 by pressing these rotating convex portions 32b against the upper surface of resin layer 21.

[0075] Sensor 32c is provided at a position away from wheel 32a and convex portions 32b. Sensor 32c is, for example, a distance sensor using eddy current. FIG. 20 shows the distance between sensor 32c and metal piece 7 with an arrow. In this case, grinding apparatus 32 can measure the above distance or detect the end point of polishing of resin layer 21 by measuring the eddy current flowing in bonding wire 18 with sensor 32c. Note that the second method shown in FIG. 20 is applicable to each embodiment other than the second embodiment.

[0076] As described above, when manufacturing the semiconductor device of the present embodiment, a plurality of stacked bodies S are formed on the substrate 11, and a plurality of bonding wires 18 for connecting these stacked bodies S to each other are arranged on these stacked bodies S. Further, a resin layer 21 is formed on these stacked bodies S and the bonding wires 18, and then the upper surface of the resin layer 21 is polished or ground. Therefore, according to the present embodiment, similarly to the first embodiment, the resin layer 21 can be preferably formed. For example, by using the bonding wire 18 to detect the end point of polishing or grinding, it is possible to form the resin layer 21 polished or ground to a desired thickness.

[0077] (Third Embodiment) FIG. 21 is a perspective view showing a method of manufacturing a semiconductor device according to the third embodiment.

[0078] Similar to FIG. 3, FIG. 21 shows a plurality of stacked bodies S and a plurality of bonding wires 18 formed in the process of FIG. 2(a). These stacked bodies S are arranged in a two-dimensional array (square lattice) adjacent to each other in the X direction and the Y direction. Each bonding wire 18 shown in FIG. 21 is arranged on two metal pieces 7 of two stacked bodies S, connecting these stacked bodies S to each other. However, each bonding wire 18 shown in FIG. 21 extends non-parallel to the X direction and the Y direction in a plan view. According to the present embodiment, compared with the first embodiment, eddy currents are more likely to flow in the bonding wire 18.

[0079] FIG. 22 is a plan view showing a method of manufacturing a semiconductor device according to the third embodiment.

[0080] FIG. 22(a) shows the substrate 1 after the bonding wires 18 are arranged in the process of FIG. 2(a), similar to FIG. 4(a). Each bonding wire 18 extends non-parallel to the X direction and the Y direction in a plan view of FIG. 22(a).

[0081] FIG. 22(b) shows the substrate 1 after the bonding wire 18 is cut in the process of FIG. 2(b), similar to FIG. 4(b). Note that although a part of each bonding wire 18 remains on each metal piece 7 even after being cut in the process of FIG. 2(b), FIG. 22(b) omits the illustration thereof.

[0082] According to the present embodiment, similarly to the first and second embodiments, the resin layer 21 can be preferably formed. For example, by using the bonding wire 18 to detect the end point of polishing or grinding, it becomes possible to form the resin layer 21 polished or ground to a desired thickness.

[0083] (Fourth Embodiment) FIG. 23 is a perspective view showing a method of manufacturing a semiconductor device according to the fourth embodiment.

[0084] FIG. 23 shows a plurality of laminates S and a plurality of bonding wires 18 formed in the process of FIG. 12(a), similar to FIG. 13. These laminates S are arranged in a two-dimensional array (square lattice) shape adjacent to each other in the X direction and the Y direction. Further, each bonding wire 18 shown in FIG. 23 is arranged on two metal pieces 7 of two laminates S, connecting these laminates S to each other. However, each bonding wire 18 shown in FIG. 23 extends non-parallel to the X direction and the Y direction in a plan view. According to the present embodiment, eddy currents are more likely to flow in the bonding wire 18 than in the third embodiment.

[0085] According to the present embodiment, similarly to the first to third embodiments, the resin layer 21 can be preferably formed. For example, by using the bonding wire 18 to detect the end point of polishing or grinding, it becomes possible to form the resin layer 21 polished or ground to a desired thickness.

[0086] (Fifth Embodiment) FIG. 24 is a cross-sectional view showing the structure of a semiconductor device according to the fifth embodiment.

[0087] The semiconductor device of the present embodiment shown in FIG. 24 includes, in addition to the components of the semiconductor device of the first embodiment shown in FIG. 1, a laminate S', a resin layer 41, a redistribution layer 42, a plurality of metal pads 43, a plurality of vertical wires 44, and a plurality of metal pads 45. The laminate S' is an example of a second laminate, and the redistribution layer 42 is an example of a second redistribution layer.

[0088] The laminate S' includes a plurality of memory chips 3. These memory chips 3 are sequentially stacked on the substrate 1. Each of these memory chips 3 is disposed via an adhesive layer 2 on the substrate 1 or on another memory chip 3. The properties of the adhesive layer 2 and the memory chips 3 within the laminate S' are the same as those of the adhesive layer 2 and the memory chips 3 within the laminate S.

[0089] The resin layer 41 is formed on the substrate 1 and the laminate S'. The properties of the resin layer 41 are the same as those of the resin layer 21. The redistribution layer 42 is provided on the resin layer 41. The properties of the redistribution layer 42 are the same as those of the redistribution layer 22. The laminate S' is provided within the resin layer 41 between the substrate 1 and the redistribution layer 42.

[0090] On the other hand, the laminate S of the present embodiment is provided on the redistribution layer 42. That is, the laminate S of the present embodiment is not provided directly on the substrate 1, but is provided on the substrate 1 via the resin layer 41 and the redistribution layer 42. And the resin layer 21 is formed on the redistribution layer 42 and the laminate S. The redistribution layer 22 is provided on the resin layer 21. The shield layer 23 is formed on the lower surface of the substrate 1 and on the side surfaces of the substrate 1, the resin layer 41, and the redistribution layer 42, the resin layer 21, and the redistribution layer 22.

[0091] The semiconductor device of the present embodiment includes metal pads 11, vertical wires 12, metal pads 13, and bonding wires 14 not only on the laminate S but also on the laminate S'. Each metal pad 11 is provided on any one of the memory chips 3 in the laminate S or the laminate S'. In FIG. 24, one vertical wire 12 is provided on one metal pad 11, and one metal pad 13 is provided on one vertical wire 12. Each bonding wire 14 is provided on two metal pads 11 in the laminate S or on two metal pads 11 in the laminate S'. Note that the metal pads 11, vertical wires 12, metal pads 13, and bonding wires 14 on the laminate S' are provided in the resin layer 41. Further, each vertical wire 12 on the laminate S' is electrically connected to the memory chip 3 via the metal pad 11 and is electrically connected to the redistribution layer 42 via the metal pad 13.

[0092] Each metal pad 43 is provided on the redistribution layer 42. In FIG. 24, one vertical wire 44 is provided on one metal pad 43, and one metal pad 45 is provided on one vertical wire 44. Therefore, each vertical wire 44 has a lower end electrically connected to the metal pad 43 and an upper end electrically connected to the metal pad 45. Each vertical wire 44 is electrically connected to the redistribution layer 42 via the metal pad 43 and is electrically connected to the redistribution layer 22 via the metal pad 45. Each vertical wire 44 extends in the Z direction from the metal pad 11 to the metal pad 13, that is, extends perpendicular to the surface of the substrate 1. Each vertical wire 44 is formed of a metal such as Au (gold), Ag (silver), or Cu (copper), for example.

[0093] Similar to FIG. 1, FIG. 24 schematically shows a plurality of wirings L1 and L2 in the redistribution layer 22. Each wiring L1 electrically connects the vertical wire 12 and the metal pillar 16. Each wiring L2 electrically connects the metal pillar 16 and the metal bump 25.

[0094] FIG. 24 further schematically shows a plurality of wirings L3 in the rewiring layer 22 and a plurality of wirings L4 in the rewiring layer 42. Each wiring L3 electrically connects the vertical wire 44 and the metal pillar 16. Each wiring L4 electrically connects the vertical wire 12 and the vertical wire 44.

[0095] According to the present embodiment, by providing the rewiring layer 42 between the substrate 1 and the rewiring layer 22, it becomes possible to shorten the length of each vertical wire 12. In FIG. 1, four memory chips 3 are stacked on the substrate 1. On the other hand, in FIG. 24, eight memory chips 3 are stacked on the substrate 1. However, the average length of the vertical wires 12 shown in FIG. 24 is approximately the same as the average length of the vertical wires 12 shown in FIG. 1. Therefore, according to the present embodiment, it becomes possible to suppress the distortion of the shape of the vertical wires 12.

[0096] The stacked body S includes a plurality of memory chips 3, and these memory chips 3 are stacked with each other shifted in the X direction in a plan view. Similarly, the stacked body S' includes a plurality of memory chips 3, and these memory chips 3 are stacked with each other shifted in the X direction in a plan view. However, each memory chip 3 in the stacked body S is shifted in the +X direction with respect to the lower memory chip 3, while each memory chip 3 in the stacked body S' is shifted in the -X direction with respect to the lower memory chip 3. Thereby, it becomes possible to reduce the area occupied by the stacked bodies S and S' in a plan view, and it becomes possible to miniaturize the semiconductor device of the present embodiment.

[0097] Note that the stacked body S of the present embodiment has the same structure as the stacked body S of the first embodiment, but may alternatively have the same structure as the stacked body S of the second, third, or fourth embodiment.

[0098] FIGS. 25 to 29 are cross-sectional views showing a method of manufacturing a semiconductor device according to the fifth embodiment.

[0099] First, prepare a substrate 1 and form a laminate S' on the substrate 1 (Fig. 25). The laminate S' is formed by laminating a plurality of memory chips 3 on the substrate 1.

[0100] Next, arrange a plurality of metal pads 11, a plurality of vertical wires 12, and a plurality of bonding wires 14 on the laminate S' (Fig. 25). Each vertical wire 14 is arranged on any one of the memory chips 3 via a metal pad 11. Each bonding wire 14 is arranged on two metal pads 11.

[0101] Next, form a resin layer 41 on the substrate 1 and the laminate S' (Fig. 25). As a result, the laminate S' is covered by the resin layer 41. Similarly, the metal pads 11, the vertical wires 12, and the bonding wires 14 are also covered by the resin layer 41.

[0102] Next, polish or grind the upper surface of the resin layer 41 (Fig. 26). As a result, the resin layer 41 is gradually removed from the upper surface, and the upper surface of the resin layer 41 drops. The polishing or grinding of the resin layer 41 is performed until the vertical wire 12 is exposed on the upper surface of the resin layer 41. The polishing or grinding of the resin layer 41 in this embodiment ends before the memory chip 3 is exposed on the upper surface of the resin layer 41.

[0103] Next, arrange a plurality of metal pads 13 and a redistribution layer 42 on the resin layer 41, and form a laminate S on the redistribution layer 42 (Fig. 27). The laminate S is formed by laminating a plurality of memory chips 3 on the redistribution layer 42 and laminating a control chip 5 and a metal piece 7 on the uppermost memory chip 3.

[0104] Next, a plurality of metal pads 11, a plurality of vertical wires 12, a plurality of bonding wires 14, a plurality of metal pads 15, a plurality of metal pillars 16, and a bonding wire 18 are arranged on the laminate S (FIG. 27). Each vertical wire 12 is arranged via a metal pad 11 on any one of the memory chips 3 in the laminate S. Each bonding wire 14 is arranged on two metal pads 11 on the laminate S. Each metal pillar 16 is arranged via a metal pad 11 on the control chip 5. The bonding wire 18 is arranged on the metal piece 7 of the laminate S shown in FIG. 27 and on the metal piece 7 of another laminate S (not shown). As a result, these laminates S are connected to each other by the bonding wire 18.

[0105] Next, a plurality of metal pads 43 and a plurality of vertical wires 44 are arranged on the redistribution layer 42 (FIG. 27). Each vertical wire 44 is arranged via a metal pad 43 on the redistribution layer 42. As a result, the vertical wire 12 and the vertical pillar 44 are electrically connected by the wiring L4.

[0106] Next, a resin layer 21 is formed on the redistribution layer 42 and the laminate S (FIG. 27). As a result, the laminate S is covered with the resin layer 21. Similarly, the metal pad 11, the vertical wire 12, the bonding wire 14, the metal pad 15, the metal pillar 16, the bonding wire 18, the metal pad 43, and the vertical wire 44 are also covered with the resin layer 21.

[0107] Note that in FIG. 27, for the sake of clarity of the positional relationship between the vertical wire 44 and the bonding wire 18, the vertical wire 44 and the bonding wire 18 are shown overlapping each other. However, the vertical wire 44 and the bonding wire 18 of the present embodiment are arranged so as not to contact each other.

[0108] Next, the upper surface of the resin layer 21 is polished or ground (FIG. 28). As a result, the resin layer 21 is gradually removed from the upper surface, and the upper surface of the resin layer 21 descends. The polishing or grinding of the resin layer 21 is performed until the vertical wire 12, the metal pillar 16, the bonding wire 18, and the vertical wire 44 are exposed on the upper surface of the resin layer 21. The polishing or grinding of the resin layer 21 in the present embodiment is performed until the bonding wire 18 is cut, and ends before the control chip 5 and the metal piece 7 are exposed on the upper surface of the resin layer 21.

[0109] Next, a plurality of metal pads 13, a plurality of metal pads 17, and a rewiring layer 22 are arranged on the resin layer 21 (FIG. 29). As a result, the vertical wire 12 and the metal pillar 16 are electrically connected by the wiring L1, and the vertical wire 44 and the metal pillar 16 are electrically connected by the wiring L3. Next, the substrate 1, the resin layer 41, the rewiring layer 42, the resin layer 21, and the rewiring layer 22 are cut along the above-described scribe region R2 (FIG. 29). As a result, the substrate 1, the resin layer 41, the rewiring layer 42, the resin layer 21, and the rewiring layer 22 are divided into the above-described individual device regions R1.

[0110] Next, a shield layer 23 is formed on the lower surface of the substrate 1 and on the side surfaces of the substrate 1, the resin layer 41, the rewiring layer 42, the resin layer 21, and the rewiring layer 22 for each device region R1 (FIG. 29). Next, a plurality of metal pads 24 and a plurality of metal bumps 25 are formed on the rewiring layer 22 for each device region R1 (FIG. 29). As a result, the metal pillar 16 and the metal bump 25 are electrically connected by the wiring L2. Note that the bonding wire 18 in the present embodiment is not electrically connected to the wiring in the rewiring layer 22 and is electrically insulated from the wiring in the rewiring layer 22. In this way, the semiconductor device of the present embodiment is manufactured.

[0111] According to the present embodiment, as in the first to fourth embodiments, the resin layer 21 can be suitably formed. For example, by using the bonding wire 18 to detect the end point of polishing or grinding, it is possible to form the resin layer 21 polished or ground to a desired thickness.

[0112] In this embodiment, the metal piece 7 and the bonding wire 18 may also be arranged on the laminate S'. As a result, it becomes possible to suitably form the resin layer 41 in the same manner as the resin layer 21. In this case, the metal piece 7 and the bonding wire 18 on the laminate S' can be arranged in the same manner as the metal piece 7 and the bonding wire 18 on the laminate S of any one of the first to fourth embodiments, for example.

[0113] (Sixth Embodiment) FIG. 30 is a perspective view showing a method of manufacturing a semiconductor device according to the sixth embodiment.

[0114] Similar to FIG. 3, FIG. 30 shows the laminate S formed in the process of FIG. 2(a) and a plurality of bonding wires 18. Specifically, FIG. 30 shows one laminate S out of the plurality of laminates S formed in the process of FIG. 2(a). These laminates S are arranged in a two-dimensional array (square lattice) shape adjacent to each other in the X direction and the Y direction. Further, each bonding wire 18 shown in FIG. 30 is arranged on the metal piece 7 of the laminate S shown in FIG. 30 and on the metal piece 7 of another laminate S (not shown), connecting these laminates S to each other.

[0115] The laminate S shown in FIG. 30 includes a lower laminate S1 provided on the substrate 1 and an upper laminate S2 provided on the lower laminate S1. The lower laminate S1 includes a plurality of memory chips 3 sequentially laminated on the substrate 1. The upper laminate S2 includes a plurality of memory chips 3 sequentially laminated on the lower laminate S1, a control chip 5 laminated on the uppermost memory chip 3 in the upper laminate S2, and a metal piece 7 laminated on the uppermost memory chip 3 in the upper laminate S2.

[0116] In this embodiment, the positions of the plurality of semiconductor chips 3 included in the lower laminate S1 are shifted from each other in the X direction in a plan view. On the other hand, the positions of the plurality of semiconductor chips included in the upper laminate S2 are shifted from each other in the Y direction in a plan view. As a result, it becomes possible to configure the shape of the laminate S in a well-balanced manner.

[0117] Note that the upper laminate S2 of the present embodiment has the same structure as the laminate S of the first embodiment, but may alternatively have the same structure as the laminate S of the second, third, fourth, or fifth embodiment.

[0118] According to the present embodiment, as in the first to fifth embodiments, the resin layer 21 can be preferably formed. For example, by using the bonding wire 18 to detect the end point of polishing or grinding, it is possible to form the resin layer 21 polished or ground to a desired thickness.

[0119] (Modification of the First Embodiment) FIG. 31 is a plan view showing a method of manufacturing a semiconductor device according to a modification of the first embodiment.

[0120] FIG. 31(a) shows the substrate 1 after the bonding wire 18 is disposed in the step of FIG. 2(a), similar to FIG. 4(a). In FIG. 31(a), the bonding wire 18 is disposed only on a part of the laminate S on the substrate 1. Thereby, the number of the bonding wires 18 disposed on the substrate 1 can be reduced. In this case, the metal piece 7 may not be disposed on the laminate S where the bonding wire 18 is not disposed.

[0121] FIG. 31(b) also shows the substrate 1 after the bonding wire 18 is disposed in the step of FIG. 2(a). Also in FIG. 31(b), the bonding wire 18 is disposed only on a part of the laminate S on the substrate 1. Thus, the laminate S where the bonding wire 18 is not disposed may be selected in any manner.

[0122] FIG. 32 is a cross-sectional view showing the structure of a semiconductor device according to another modification of the first embodiment.

[0123] The semiconductor device of this modified example shown in FIG. 32 includes the same components as the semiconductor device of the first embodiment shown in FIG. 1. However, the metal piece 7 of this modified example is disposed between the two memory chips 3. Thus, the metal piece 7 may be disposed on a memory chip 3 other than the uppermost memory chip 3.

[0124] FIG. 33 is a cross-sectional view showing the structure of a semiconductor device according to another modified example of the first embodiment.

[0125] The semiconductor device of this modified example shown in FIG. 33 has a structure in which the metal piece 7 is removed from the semiconductor device of the first embodiment shown in FIG. 1. Therefore, the bonding wire 18 of this modified example is directly disposed on the uppermost memory chip 3. Note that the bonding wire 18 of this modified example may be directly disposed on a memory chip 3 other than the uppermost memory chip 3.

[0126] FIG. 34 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 33.

[0127] FIG. 34(a) shows a first example of the structure of the uppermost memory chip 3. The uppermost memory chip 3 in this example includes a wiring 51 formed in the memory chip 3. The wiring 51 is, for example, a bonding pad formed of a metal such as Al (aluminum) or Cu (copper). In this example, a plurality of bonding wires 18 are disposed on the wiring 51. Thereby, it becomes possible to polish or grind the resin layer 21 in the same manner as when these bonding wires 18 are disposed on the metal piece 7.

[0128] Figure 34(b) shows a second example of the structure of the top memory chip 3. The top memory chip 3 in this example includes wiring 52 formed within this memory chip 3. The wiring 52 is formed by two wirings in wiring layer 52a, two via plugs 52b, and one wiring in wiring layer 52c. Each of wiring layer 52a, via plug 52b, and wiring layer 52c is formed of a metal such as Al (aluminum), Cu (copper), or W (tungsten), for example. In this example, a plurality of bonding wires 18 are arranged on the wiring 52. Thereby, it becomes possible to polish or grind the resin layer 21 in the same manner as when these bonding wires 18 are arranged on the metal piece 7.

[0129] Figure 35 is a cross-sectional view showing the structure of a semiconductor device according to another modification of the first embodiment.

[0130] The semiconductor device of this modification shown in Figure 35 includes the same components as the semiconductor device of the first embodiment shown in Figure 1. However, the rewiring layer 22 of this modification includes a wiring L5 that electrically connects the bonding wire 18 and the shield layer 23. In this case, by electrically connecting the memory chip 3 in the laminate S to the metal piece 7, it becomes possible to supply the potential of the shield layer 23 into the memory chip 3 via the bonding wire 18. That is, it becomes possible to supply the ground potential into the memory chip 3 via the bonding wire 18.

[0131] Thus, the bonding wire 18 may be effectively utilized as wiring within the semiconductor device. In Figure 35, the bonding wire 18 functions as ground wiring within the semiconductor device. The bonding wire 18 may be used as wiring for other purposes within the semiconductor device.

[0132] Note that the structures and methods of these modifications are also applicable to each embodiment other than the first embodiment.

[0133] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices and methods described in this specification can be implemented in various other forms. Also, various omissions, substitutions, and changes can be made to the forms of the devices and methods described in this specification without departing from the gist of the invention. The scope of the appended claims and equivalents thereto are intended to include such forms and modifications within the scope and gist of the invention.

Explanation of Reference Numerals

[0134] 1: Substrate, 2: Adhesive layer, 3: Memory chip, 4: Adhesive layer, 5: Control chip, 6: Adhesive layer, 7: Metal piece, 11: Metal pad, 12: Vertical wire, 13: Metal pad, 14: Bonding wire, 15: Metal pad, 16: Metal pillar, 17: Metal pad, 18: Bonding wire, 21: Resin layer, 22: Redistribution layer, 23: Shield layer, 24: Metal pad, 25: Metal bump, 31: CMP device, 31a: Polishing table, 31b: Polishing pad, 31c: Sensor, 32: Grinding device, 32a: Wheel, 32b: Protrusion, 32c: Sensor, 41: Resin layer, 42: Redistribution layer, 43: Metal pad, 44: Vertical wire, 45: Metal pad, 51: Wiring, 52: Wiring, 52a: Wiring layer, 52b: Via plug, 52c: Wiring layer

Claims

1. Form a plurality of stacked bodies on a substrate, each of the stacked bodies being formed to include a plurality of semiconductor chips stacked on the substrate, Dispose a plurality of first wires on the stacked body to connect the stacked bodies to each other, Form a resin layer on the stacked body and the first wires, Lower the upper surface of the resin layer until the first wires are exposed on the upper surface of the resin layer. A method for manufacturing a semiconductor device including this.

2. Further including disposing a plurality of second wires extending in the stacking direction of the stacked body on the stacked body, The resin layer is formed on the stacked body, the first wires, and the second wires. The method for manufacturing a semiconductor device according to claim 1.

3. At least one of the stacked bodies further includes a metal piece disposed on the semiconductor chip, At least one of the first wires is disposed on the metal piece. The method for manufacturing a semiconductor device according to claim 1 or 2.

4. At least one of the stacked bodies includes, as the semiconductor chip, a first semiconductor chip and a second semiconductor chip having an area smaller than the area of the first semiconductor chip in plan view, The metal piece is disposed on the first semiconductor chip. The method for manufacturing a semiconductor device according to claim 3.

5. The second semiconductor chip controls the operation of the first semiconductor chip. The method for manufacturing a semiconductor device according to claim 4.

6. In plan view, the area of the metal piece is smaller than the area of the first semiconductor chip. The method for manufacturing a semiconductor device according to claim 4 or 5.

7. The second semiconductor chip and the metal piece are disposed on the first semiconductor chip. The method for manufacturing a semiconductor device according to claim 4 or 5. Claim 8 The method of manufacturing a semiconductor device according to claim 4 or 5, wherein in plan view, the area of the metal piece is the same as the area of the first semiconductor chip. Claim 9 The method of manufacturing a semiconductor device according to claim 4 or 5, wherein the metal piece is disposed on the first semiconductor chip, and the second semiconductor chip is disposed on the metal piece. Claim 10 The plurality of stacked bodies are disposed at intersections of a plurality of straight lines extending in a first direction and a plurality of straight lines extending in a second direction, The method of manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the first wire extends parallel to the first direction or the second direction in plan view. Claim 11 The plurality of stacked bodies are disposed at intersections of a plurality of straight lines extending in a first direction and a plurality of straight lines extending in a second direction, The method of manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the first wire extends non-parallel to the first direction and the second direction in plan view. Claim 12 At least one of the stacked bodies further includes wiring formed in the semiconductor chip, The method of manufacturing a semiconductor device according to claim 1 or 2, wherein at least one of the first wires is disposed on the wiring.

Images