Semiconductor device, and method of manufacturing the same

Abstract

To provide a semiconductor device capable of improving adhesion.SOLUTION: A semiconductor device 1A includes a resin layer 10, a mounting wiring layer 30, a semiconductor element 50, and sealing resin 60. The resin layer 10 has a resin principal surface 101. The mounting wiring layer 30 is arranged on the resin principal surface 101 and has a mounting wiring principal surface 301 and a mounting wiring rear surface 302 directed to the opposite side of the mounting wiring principal surface 301. The semiconductor element 50 is mounted on the mounting wiring principal surface 301, has an element wiring principal surface 541 directed to the resin layer 10 side and includes an element wiring layer 54 connected to the mounting wiring layer 30. The sealing resin 60 seals the mounting wiring layer 30 and the semiconductor element 50. The mounting wiring principal surface 301 is contacted with the sealing resin 60. The mounting wiring principal surface 301 of the mounting wiring layer 30 has a rough surface with surface roughness lager than that of the mounting wiring rear surface 302 of the mounting wiring layer 30.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] Conventionally, semiconductor devices have been miniaturized as electronic devices are miniaturized. Patent Document 1 shows an example of a semiconductor device. This semiconductor device includes a rectangular die pad, a plurality of leads arranged around the die pad, a semiconductor chip mounted on the die pad, and a sealing resin for sealing the semiconductor chip. The plurality of leads serve as wirings for electrically connecting the semiconductor chip and the outside of the semiconductor device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, the adhesion between the lead and the sealing resin can be a cause of peeling that occurs between the lead and the sealing resin. Therefore, there is room for improvement in terms of adhesion.

Means for Solving the Problems

[0005] A semiconductor device according to one aspect of the present disclosure includes a resin layer having a resin main surface, a mounting wiring layer having a mounting wiring main surface disposed on the resin main surface and facing the same side as the resin main surface, and a mounting wiring back surface facing the side of the resin main surface, a semiconductor element mounted on the mounting wiring main surface and having an element wiring main surface facing the side of the resin layer and connected to the mounting wiring, and a sealing resin for sealing the mounting wiring layer and the semiconductor element. The mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface.

[0006] A method for manufacturing a semiconductor device according to an aspect of the present disclosure includes a step of forming a resin layer having a resin main surface, a step of forming a mounting wiring layer on the resin main surface, the mounting wiring layer having a mounting wiring main surface facing the same direction as the resin main surface and a mounting wiring back surface facing the side of the resin main surface, a step of mounting a semiconductor element having an element wiring main surface facing the side of the resin main surface on the mounting wiring layer, a step of making the mounting wiring main surface a rough surface having a surface roughness greater than that of the mounting wiring back surface, a step of making the element wiring main surface a rough surface having a surface roughness greater than that of the mounting wiring back surface, and a step of forming a sealing resin that contacts the resin main surface and seals the mounting wiring and the semiconductor element.

Advantages of the Invention

[0007] According to an aspect of the present disclosure, it is possible to provide a semiconductor device with improved adhesion and a method for manufacturing the semiconductor device.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments and modification examples will be described with reference to the drawings. The embodiments and modification examples shown below illustrate the configurations and methods for embodying the technical idea, and do not limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to those described below. Various modifications can be made to the following embodiments and modification examples. Further, the following embodiments and modification examples can be implemented in combination with each other within a technically consistent range.

[0010] In this specification, the state where "member A is connected to member B" includes the case where member A and member B are physically directly connected, and the case where member A and member B are indirectly connected via other members that do not affect the electrical connection state.

[0011] Similarly, the state where "member C is provided between member A and member B" includes the case where member A and member C, or member B and member C are directly connected, and the case where member A and member C, or member B and member C are indirectly connected via other members that do not affect the electrical connection state.

[0012] (First Embodiment) Hereinafter, the first embodiment will be described. FIG. 1 is a perspective view showing the appearance of the semiconductor device 1A of the present embodiment. FIG. 2 is a cross-sectional view of the semiconductor device 1A of the present embodiment. FIGS. 3 and 4 are partially enlarged cross-sectional views of the semiconductor device 1A. FIG. 5 is a cross-sectional view showing the surface state of the element wiring layer 54 and the encapsulating resin 60 of the semiconductor element 50. FIG. 6 is a cross-sectional view showing the surface state of the mounting wiring layer 30 and the encapsulating resin 60 of the semiconductor device 1A. FIGS. 7 to 20 are cross-sectional views showing an exemplary manufacturing process of the semiconductor device 1A.

[0013] [Configuration of Semiconductor Device] The semiconductor device 1A shown in these figures is a device that is surface-mounted on a circuit board of various electronic devices. As shown in FIG. 1, the semiconductor device 1A is in the shape of a rectangular plate. Here, for convenience of explanation, the thickness direction of the semiconductor device 1A is defined as the Z direction. Also, the direction along one side of the semiconductor device 1A orthogonal to the Z direction is defined as the X direction. Further, the direction orthogonal to both the Z direction and the X direction of the semiconductor device 1A is defined as the Y direction.

[0014] As shown in FIGS. 1 to 4, the semiconductor device 1A includes a resin layer 10, a terminal portion 20, a mounting wiring layer 30, a bonding portion 40, a semiconductor element 50, an encapsulating resin 60, and an external conductive film 70. [Resin Layer] As shown in FIG. 2, the resin layer 10 is a support member that serves as the basis of the semiconductor device 1A and is used as a substrate made of resin. The resin layer 10 is plate-shaped.

[0015] The resin layer 10 has a resin front surface 101, a resin back surface 102, and a plurality of resin side surfaces 103. The resin front surface 101 and the resin back surface 102 face opposite sides in the Z direction. The resin front surface 101 is flat. The resin back surface 102 is flat. Each resin side surface 103 intersects the resin front surface 101 and the resin back surface 102. The resin side surface 103 faces either the X direction or the Y direction. Each resin side surface 103 is flat. Each resin side surface 103 intersects, and in this embodiment, is orthogonal to, the resin front surface 101 and the resin back surface 102. The resin side surface 103 is connected to the resin front surface 101 and the resin back surface 102.

[0016] The resin layer 10 is made of a material having, for example, electrical insulation properties. As this material, for example, a synthetic resin with an epoxy resin or the like as the main component can be used. The synthetic resin according to the present embodiment is an epoxy resin containing a filler. The filler is composed of, for example, SiO2 (silica). The material constituting the resin layer 10 is colored, for example, black. Cutting marks are formed on the resin front surface 101, the resin back surface 102, and the resin side surface 103, which are the surfaces of the resin layer 10. And on the resin front surface 101, the resin back surface 102, and the resin side surface 103, which are the surfaces of the resin layer 10, the filler contained in the material of the resin layer 10 is exposed.

[0017] The resin layer 10 has a plurality of through holes 11 penetrating the resin layer 10 from the resin front surface 101 to the resin back surface 102 in the Z direction. In the present embodiment, the resin layer 10 has a plurality of through holes 11 on each side of the resin side surface 103 of the resin layer 10. The through holes 11 are, for example, rectangular when viewed from the Z direction. Note that the shape of the through holes 11 may be circular or polygonal. Each through hole 11 extends to the resin side surface 103. That is, each through hole 11 opens on the resin side surface 103.

[0018] [Terminal portion] The terminal portion 20 is disposed in each through hole 11. The terminal portion 20 has a terminal front surface 201, a terminal back surface 202, and terminal side surfaces 203, 204. The terminal front surface 201 and the terminal back surface 202 face opposite sides in the Z direction. The terminal side surfaces 203, 204 intersect the terminal front surface 201 and the terminal back surface 202. The terminal side surfaces 203, 204 are connected to the terminal front surface 201 and the terminal back surface 202.

[0019] In the first embodiment, the back surface 202 of the terminal portion 20 is flush with the back surface 102 of the resin layer 10. This back surface 202 of the terminal portion is an exposed surface that is exposed from the back surface 102 of the resin layer 10. Note that the back surface 202 of the terminal portion 20 may not be flush with the back surface 102 of the resin layer 10. The side surface 203 of the terminal portion 20 is in contact with the inner wall surface 113 of the through hole 11. The side surface 204 of the terminal portion 20 is exposed from the side surface 103 of the resin layer 10. The terminal portion 20 is made of a material having electrical conductivity. As the material of the terminal portion 20, for example, Cu (copper), Cu alloy, etc. can be used.

[0020] [Actual assembly line] The actual assembly line layer 30 is formed on the main surface 101 of the resin layer 10. The actual assembly line layer 30 is made of a material having electrical conductivity and is electrically connected to the terminal portion 20. The actual assembly line layer 30 has an actual assembly line main surface 301, an actual assembly line back surface 302, and actual assembly line side surfaces 303, 304. The actual assembly line main surface 301 and the actual assembly line back surface 302 face opposite sides in the Z direction. The actual assembly line side surfaces 303, 304 face a direction orthogonal to the Z direction. The actual assembly line main surface 301 of the actual assembly line layer 30 faces the same direction as the main surface 101 of the resin layer 10. The actual assembly line back surface 302 of the actual assembly line layer 30 faces the same direction as the back surface 102 of the resin layer 10. The actual assembly line side surfaces 303, 304 are connected to the actual assembly line main surface 301 and the actual assembly line back surface 302.

[0021] A part of the actual assembly line back surface 302 is in contact with the main surface 101 of the resin layer 10, and another part of the actual assembly line back surface 302 is connected to the main surface 201 of the terminal portion 20. The plurality of actual assembly line side surfaces 303 are in contact with the sealing resin 60. The actual assembly line side surface 304 facing the X direction is an exposed side surface that is exposed from the resin side surface 603 of the sealing resin 60.

[0022] [Joint portion] The joint portion 40 is provided on the actual assembly line layer 30. The joint portion 40 is electrically connected to the actual assembly line layer 30. The joint portion 40 joins the semiconductor element 50 to the actual assembly line layer 30. By the joint portion 40, the semiconductor element 50 is supported away from the actual assembly line main surface 301 of the actual assembly line layer 30.

[0023] [Semiconductor element] The semiconductor element 50 has an element substrate 51, electrode pads 52, an insulating film 53, an element wiring layer 54, and element electrodes 55.

[0024] The element substrate 51 has a substrate front surface 511, a substrate back surface 512, and a plurality of substrate side surfaces 513. The substrate front surface 511 and the substrate back surface 512 face opposite sides in the Z direction. Each substrate side surface 513 faces either the X direction or the Y direction. The substrate front surface 511 faces the actual mounting wiring main surface 301 of the actual mounting wiring layer 30. The substrate back surface 512 faces the same direction as the actual mounting wiring main surface 301 of the actual mounting wiring layer 30. The substrate side surfaces 513 are connected to the substrate front surface 511 and the substrate back surface 512.

[0025] The semiconductor element 50 is an integrated circuit (IC) such as an LSI (Large Scale Integration), for example. Also, the semiconductor element 50 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, a transistor such as a MOSFET, or a discrete semiconductor element such as a diode or various sensors. For example, in the case of an LSI, the substrate front surface 511 is the surface on which the components for the functions of the semiconductor element 50 are formed. Note that the semiconductor element 50 is not limited to one having a plurality of components formed thereon, and may be an element having a single component formed thereon, such as a chip capacitor or a chip inductor, or an element having components formed on a substrate other than a semiconductor.

[0026] The electrode pads 52 are provided on the substrate front surface 511 of the element substrate 51. The insulating film 53 is formed so as to contact the main surface 511 of the substrate. The insulating film 53 contacts the peripheral portion of the electrode pad 52 and is formed so as to expose the central portion of the electrode pad 52. A part of the electrode pad 52 is exposed from the insulating film 53. The insulating film 53 is composed of, for example, SiN (silicon nitride). The main surface 531 of the insulating film 53 constitutes the element main surface of the semiconductor element 50. The back surface 532 of the insulating film 53 contacts the main surface 511 of the element substrate 51. The back surface 512 of the element substrate 51 constitutes the element back surface of the semiconductor element 50. The side surface 513 of the element substrate 51 constitutes the element side surface of the semiconductor element 50.

[0027] The element wiring layer 54 is connected to the electrode pad 52. The element wiring layer 54 extends from the electrode pad 52 to the insulating film 53 and contacts the main surface 531 of the insulating film 53. The element wiring layer 54 is composed of, for example, Cu, Cu alloy, etc.

[0028] The element electrode 55 is arranged at a position that does not overlap the electrode pad 52 when viewed from the Z direction. That is, the electrode pad 52 and the element electrode 55 are displaced in a direction intersecting the Z direction. The element electrode 55 is connected to the element wiring layer 54. The element electrode 55 is connected to the joint portion 40. In this way, the semiconductor element 50 is mounted on the main surface 301 of the mounting wiring layer 30.

[0029] [Sealing resin] The sealing resin 60 contacts the resin main surface 101 of the resin layer 10 and seals the mounting wiring layer 30, the joint portion 40, and the semiconductor element 50. The sealing resin 60 is filled between the resin layer 10 and the semiconductor element 50. When viewed from the Z direction, the sealing resin 60 overlaps the resin layer 10.

[0030] The sealing resin 60 has a resin main surface 601, a resin back surface 602, and a resin side surface 603. The resin main surface 601 faces the same direction as the resin main surface 101 of the resin layer 10. The resin back surface 602 faces the opposite side of the resin main surface 601. The resin back surface 602 contacts the resin main surface 101 of the resin layer 10. The resin side surface 603 intersects the resin main surface 601 and the resin back surface 602.

[0031] The sealing resin 60 has, in the Z direction, a first resin portion 60A which is a portion on the resin layer 10 side, and a second resin portion 60B which is on the resin main surface 601 side. The first resin portion 60A has a first resin side surface 603a which forms part of the resin side surface 603, and the second resin portion 60B has a second resin side surface 603b which forms part of the resin side surface 603. When viewed from the Z direction, the first resin portion 60A is the same size as the resin layer 10. Also, when viewed from the Z direction, the second resin portion 60B is formed to be larger than the first resin portion 60A. The second resin side surface 603b is located outside the first resin side surface 603a. Thus, the sealing resin 60 has a step 61 which is recessed inside the sealing resin 60 due to the difference in size between the first resin portion 60A and the second resin portion 60B. The step 61 is provided over the entire circumferential direction of the sealing resin 60.

[0032] The sealing resin 60 is made of, for example, a resin having electrical insulation properties. As this resin, for example, a synthetic resin with an epoxy resin as the main component can be used. Also, the sealing resin 60 is, for example, colored black. Note that the material and shape of the sealing resin 60 are not limited.

[0033] [External conductive film] The external conductive film 70 has a first conductive film 71 and a second conductive film 72. The first conductive film 71 contacts the terminal back surface 202 of the terminal portion 20. The second conductive film 72 contacts the terminal side surface 204 of the terminal portion 20 and the actual mounting wiring side surface 304 of the actual mounting wiring layer 30. The external conductive film 70 having the first conductive film 71 and the second conductive film 72 serves as an external connection terminal of the semiconductor device 1A. The external conductive film 70 is composed of, for example, a plurality of metal layers laminated on each other. As the metal layers, for example, a Ni (nickel) layer and an Au (gold) layer. Note that the material of the external conductive film 70 is not limited, but for example, a Ni layer, a Pd (palladium) layer, and an Au layer may be laminated and formed, or it may be Sn (tin).

[0034] [Detailed description of semiconductor device] Next, the details of the actual mounting wiring layer 30 and the semiconductor element 50 of the semiconductor device 1A of the present embodiment will be described.

[0035] As shown in FIG. 3, the terminal side surface 203 of the terminal portion 20 is a rough surface with a larger surface roughness than the terminal main surface 201 of the terminal portion 20. The surface roughness of the terminal side surface 203 is indicated by, for example, the arithmetic mean roughness Ra. The arithmetic mean roughness Ra of the terminal side surface 203 is, for example, 0.3 μm or more.

[0036] The terminal portion 20 is formed in the through hole 11 of the resin layer 10, and the terminal side surface 203 of the terminal portion 20 is in contact with the resin layer 10. The terminal side surface 203 is a rough surface and is formed, for example, by a roughening process. The terminal main surface 201 is a flat surface and is formed, for example, by polishing. The terminal side surface 203 is a rough surface. Thereby, the adhesion between the terminal side surface 203 and the resin layer 10 in contact with the terminal side surface 203 can be improved.

[0037] As shown in FIGS. 3 and 4, the actual mounting line main surface 301 and the actual mounting line side surface 303 of the actual mounting line layer 30 are in contact with the sealing resin 60. The back surface 302 of the actual mounting line layer 30 is in contact with the terminal portion 20 or the resin layer 10. The actual mounting line main surface 301 of the actual mounting line layer 30 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting line layer 30. In the present embodiment, the actual mounting line side surface 303 of the actual mounting line layer 30 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting line layer 30, similar to the actual mounting line main surface 301.

[0038] In the present embodiment, the joint portion 40 is disposed on the actual mounting line main surface 301. That is, the actual mounting line main surface 301 includes a covered portion 3011 covered by the joint portion 40 and an exposed portion 3012 exposed from the joint portion 40. The exposed portion 3012 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting line as described above. The covered portion 3011 is a flat surface with a smaller surface roughness than the exposed surface.

[0039] As shown in FIGS. 3 and 4, the actual mounting line layer 30 has a metal layer 31 and a conductive layer 32. The metal layer 31 and the conductive layer 32 are laminated on the resin main surface 101 of the resin layer 10 in this order.

[0040] The metal layer 31 is a conductive layer mainly composed of, for example, Ti (titanium). The metal layer 31 is in contact with the resin main surface 101 of the resin layer 10 and the terminal main surface 201 of the terminal portion 20. The metal layer 31 is formed as a seed layer for forming the conductive layer 32. The conductive layer 32 is mainly composed of, for example, Cu.

[0041] The metal layer 31 has a main surface 311, a back surface 312, and side surfaces 313. The main surface 311 and the back surface 312 face opposite sides in the Z direction. The plurality of side surfaces 313 face a direction intersecting the Z direction. The surfaces of the metal layer 31, that is, the main surface 311, the back surface 312, and the side surfaces 313, are smooth surfaces.

[0042] The conductive layer 32 is formed on the main surface 311 of the metal layer 31. The conductive layer 32 has a main surface 321, a back surface 322, and side surfaces 323. The main surface 321 and the back surface 322 face opposite sides in the Z direction. The plurality of side surfaces 323 face a direction intersecting the Z direction. Among the plurality of side surfaces 323, the side surfaces constituting the actual mounting line side surface 303 of the actual mounting line layer 30 are in contact with the sealing resin 60. Among the plurality of side surfaces 323, the side surfaces constituting the actual mounting line side surface 304 (see FIG. 2) of the actual mounting line layer 30 are exposed from the sealing resin 60.

[0043] In the present embodiment, the main surface 321 of the conductive layer 32 mainly composed of Cu constitutes the actual mounting line main surface 301 of the actual mounting line layer 30. That is, the main surface 321 of the conductive layer 32 is a rough surface with a larger surface roughness than the actual mounting line back surface 302. Among the side surfaces 323 of the conductive layer 32, the side surfaces covered by the sealing resin 60 are rough surfaces with a larger surface roughness than the actual mounting line back surface 302, similar to the main surface 321 of the conductive layer 32. Among the side surfaces 323 of the conductive layer 32, the side surfaces exposed from the sealing resin 60 are flat surfaces.

[0044] The main surface 321 of the conductive layer 32 constitutes the main surface 301 of the actual mounting wiring layer 30. The back surface 312 of the metal layer 31 constitutes the back surface 302 of the actual mounting wiring layer 30. The thickness of the metal layer 31 is thinner than that of the conductive layer 32. It can be said that the actual mounting wiring layer 30 is substantially composed of the conductive layer 32. Therefore, it can be said that the side surface 303 of the actual mounting wiring layer 30 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting wiring layer 30.

[0045] The joint 40 includes a plating layer 41 formed on the main surface 301 of the actual mounting wiring layer 30 and a solder layer 42 between the plating layer 41 and the element electrode 55 of the semiconductor element 50. The plating layer 41 is made of a conductive metal material. For example, the plating layer 41 is made of Ni. The solder layer 42 is made of Sn or an alloy containing Sn. This alloy is, for example, an Sn-Ag (silver) -based alloy, an Sn-Sb (antimony) -based alloy, etc.

[0046] The semiconductor element 50 has an element wiring layer 54 and an element electrode 55. The element wiring layer 54 is formed on the main surface 531 of the insulating film 53. The element wiring layer 54 has an element wiring main surface 541, an element wiring back surface 542, and an element wiring side surface 543. The element wiring main surface 541 faces the same direction as the main surface 531 of the insulating film 53. That is, the element wiring main surface 541 faces the element wiring main surface 541 of the actual mounting wiring layer 30. The element wiring back surface 542 faces the opposite side of the element wiring main surface 541. The element wiring back surface 542 is in contact with the main surface 531 of the insulating film 53.

[0047] The main element wiring surface 541 of the element wiring layer 54 is a rough surface with a larger surface roughness than the back element wiring surface 542. The surface roughness of the main element wiring surface 541 is equal to the surface roughness of the main mounting wiring surface 301 of the mounting wiring layer 30. That is, the main element wiring surface 541 of the element wiring layer 54 is a rough surface with a larger surface roughness than the back mounting wiring surface 302 of the mounting wiring layer 30. In this specification, "equal" includes cases where the difference between two measured values is within a predetermined percentage, for example, within 5% of one of the measured values, when the two measured values are the same value. In this embodiment, if the difference in surface roughness between the main mounting wiring surface 301 and the main element wiring surface 541 is within 5% of the surface roughness of the main mounting wiring surface 301, it can be said that they are equal.

[0048] The side element wiring surface 543 of the element wiring layer 54 is a rough surface with a larger surface roughness than the back element wiring surface 542. The surface roughness of the wiring side surface is equal to the surface roughness of the main element wiring surface 541. That is, the side element wiring surface 543 of the element wiring layer 54 is a rough surface with a larger surface roughness than the back mounting wiring surface 302 of the mounting wiring layer 30.

[0049] The element electrode 55 is provided on the main element wiring surface 541 of the element wiring layer 54. Therefore, the main element wiring surface 541 of the element wiring layer 54 is partially covered by the element electrode 55. That is, the main element wiring surface 541 includes a covered portion 5411 covered by the element electrode 55 and an exposed portion 5412 that is not covered by the element electrode 55, that is, exposed from the element electrode 55. As described above, the exposed portion 5412 is a rough surface with a larger surface roughness than the back mounting wiring surface 302 of the mounting wiring layer 30. The covered portion 5411 is a flat surface with a smaller surface roughness than the exposed portion 5412.

[0050] The exposed portion 5412 of the main element wiring surface 541 of the element wiring layer 54 and the side element wiring surface 543 are the surface of the element wiring layer 54. That is, the surface of the element wiring layer 54 is a rough surface with a larger surface roughness than the back mounting wiring surface 302 of the mounting wiring layer 30. The surface of the element wiring layer 54, that is, the main element wiring surface 541 (exposed portion 5412) and the side element wiring surface 543, are in contact with the sealing resin 60.

[0051] The element electrode 55 includes a conductive layer 56 and a barrier layer 57. The conductive layer 56 is connected to the element wiring main surface 541 of the element wiring layer 54. The conductive layer 56 is composed of, for example, Cu or a Cu alloy. The conductive layer 56 may include a seed layer. The seed layer is composed of, for example, titanium (Ti) / Cu. The barrier layer 57 is composed of Ni, an alloy containing Ni, or a plurality of metal layers containing Ni. As the barrier layer 57, for example, Ni, Pd, Au, an alloy containing two or more of these metals, etc. can be used.

[0052] The conductive layer 56 has a main surface 561, a back surface 562, and side surfaces 563. The main surface 561 and the back surface 562 face opposite sides in the Z direction. The main surface 561 faces the same direction as the element wiring main surface 541 of the element wiring layer 54. The back surface 562 faces the element wiring main surface 541. The side surfaces 563 intersect the main surface 561 and the back surface 562. The side surfaces 563 are connected to the main surface 561 and the back surface 562.

[0053] The back surface 562 of the conductive layer 56 is in contact with the element wiring main surface 541 of the element wiring layer 54. Also, the main surface 561 of the conductive layer 56 is in contact with the barrier layer 57. The side surfaces 563 of the conductive layer 56 are rough surfaces with a larger surface roughness than the main surface 561 and the back surface 562. In the present embodiment, the surface roughness of the side surfaces 563 of the conductive layer 56 is equal to the surface roughness of the element wiring main surface 541 of the element wiring layer 54. Therefore, the side surfaces 563 of the conductive layer 56 are rough surfaces with a larger surface roughness than the actual mounting wiring back surface 302 of the actual mounting wiring layer 30. The side surfaces 563 of the conductive layer 56 are in contact with the sealing resin 60.

[0054] The barrier layer 57 has a main surface 571, a back surface 572, and side surfaces 573. The main surface 571 and the back surface 572 face opposite sides in the Z direction. The main surface 571 faces the same direction as the main surface 561 of the conductive layer 56. The back surface 572 faces the main surface 561 of the conductive layer 56. The side surfaces 573 intersect the main surface 571 and the back surface 572. The side surfaces 573 are connected to the main surface 571 and the back surface 572.

[0055] The back surface 572 of the barrier layer 57 is in contact with the main surface 561 of the conductive layer 56. Also, the main surface 571 of the barrier layer 57 is in contact with the solder layer 42 of the joint portion 40. The side surface 573 of the barrier layer 57 is a flat surface. The side surface 573 of the barrier layer 57 is in contact with the encapsulating resin 60.

[0056] [Method for manufacturing a semiconductor device] With reference to FIGS. 7 to 20, an example of a method for manufacturing a semiconductor device 1A according to the first embodiment will be described. Each of the figures to be referred to shows a range in which one semiconductor device 1A is formed. For ease of understanding, in FIGS. 7 to 20, the same reference numerals are given to the components similar to those in FIGS. 1 to 6. Also, the definition of each direction shown in each figure is the same as the definition of the direction shown in FIGS. 1 to 6. The two broken lines DL1 shown in FIGS. 7 to 20 indicate the range in which one semiconductor device 1A is formed.

[0057] As shown in FIG. 7, the method for manufacturing the semiconductor device 1A includes a step of preparing a support substrate 900. The support substrate 900 is made of, for example, a single crystal material of Si (silicon). The support substrate 900 has a main surface 9001 and a back surface 9002 that face opposite sides in the Z direction. Note that, as the support substrate 900, a substrate made of a synthetic resin material such as an epoxy resin may be used.

[0058] Also, the method for manufacturing the semiconductor device 1A includes a step of forming a seed layer 901. For example, the seed layer 901 is formed on the main surface 9001 of the support substrate 900 by a sputtering method. The seed layer 901 includes, for example, a first layer mainly composed of Ti and a second layer mainly composed of Cu. The first layer is formed on the entire main surface 9001 of the support substrate 900, and the second layer in contact with the first layer is formed.

[0059] As shown in FIG. 8, the manufacturing method of the semiconductor device 1A includes a step of forming a terminal portion 920. The step of forming the terminal portion 920 includes a step of forming a mask, a step of forming the terminal portion 920, a step of removing the mask, a step of roughening the surface of the terminal portion 920, and a step of removing the seed layer 901. The terminal portion 920 is made of, for example, Cu or an alloy mainly composed of Cu. The terminal portion 920 is formed, for example, by an electrolytic plating method. In the semiconductor device 1A described above, the terminal portion 920 becomes the terminal portion 20.

[0060] In the step of forming a mask, a mask (not shown) is formed on the seed layer 901 shown in FIG. 7, for example, by photolithography. For example, a photosensitive resist layer is brought into contact with the seed layer 901, and the resist layer is exposed and developed to form a mask having an opening. In the step of forming the terminal portion 920, the terminal portion 920 is formed, for example, by an electrolytic plating method. The plating metal is deposited on the surface of the seed layer exposed from the mask by the electrolytic plating method using the seed layer as a conductive path to form the terminal portion 920. In the step of removing the mask, the mask is removed using, for example, a stripping solution. In the step of roughening the surface of the terminal portion 920, the support substrate 900 on which the terminal portion 920 is formed is immersed in a roughening solution. As the roughening solution, for example, an alkaline solution can be used. The surface of the terminal portion 920 is roughened by the roughening solution. In the step of removing the seed layer 901, the seed layer 901 exposed from the terminal portion 920 is removed by etching, for example, wet etching.

[0061] As shown in FIG. 9, the manufacturing method of the semiconductor device 1A includes a step of forming a resin layer 910. The resin layer 910 is formed so as to contact the side surface and the main surface of the terminal portion 920. As the material of the resin layer 910, the material constituting the resin layer 910 shown in FIG. 2 can be used. In the present embodiment, as the material of the resin layer 910, a synthetic resin mainly composed of an epoxy resin or the like can be used.

[0062] As shown in FIG. 10, the manufacturing method of the semiconductor device 1A has a step of removing a part of the resin layer 910 and the terminal portion 920. The resin layer 910 is formed thicker than the thickness of the resin layer 10 shown in FIG. 2. For example, the resin layer 910 and the terminal portion 920 are ground up to the broken line DL2 shown in FIG. 9. By this grinding, the main surface 9201 of the terminal portion 920 is exposed on the resin main surface 9101 of 910. Then, burrs generated in the terminal portion 920 by grinding are removed from the resin main surface 9101 of the resin layer 910 by etching, for example, wet etching.

[0063] As shown in FIG. 11, the manufacturing method of the semiconductor device 1A has a step of forming the actual wiring layer 930. The step of forming the actual wiring layer 930 includes a step of forming the seed layer 931, a step of forming the mask 902, a step of forming the plating layer 932, and a step of removing the mask 902.

[0064] In the step of forming the seed layer 931, for example, the seed layer 931 is formed by a sputtering method. The seed layer 931 includes a first layer mainly composed of Ti and a second layer mainly composed of Cu. The second layer is in contact with the main surface of the first layer. This seed layer 931 includes the metal layer 31 shown in FIGS. 3 and 4 and a part of the conductive layer 32. The seed layer 931 is formed so as to be in contact with the resin main surface 9101 of the resin layer 91- and the main surface 9201 of the terminal portion 920. In the step of forming the mask 902, for example, the mask 902 is formed by photolithography. The mask 902 has an opening 9021 corresponding to the actual mounting wiring layer 30 shown in FIG. 2. First, for example, a photosensitive resist layer is formed on the main surface of the seed layer 931. As the resist layer, for example, a dry film resist can be used. The resist layer may be composed of a plurality of dry film resists. Next, by performing exposure and development on the resist layer, a mask 902 having an opening 9021 is formed. In the step of forming the plating layer 932, for example, the plating layer 932 is formed by an electrolytic plating method. The plating layer 932 corresponds to the conductive layer 32 shown in FIGS. 3 and 4. The plating layer 932 is formed by growing a plating metal on the main surface of the seed layer 931 exposed from the mask 902. The plating metal constituting the plating layer 932 contains Cu. In the step of removing the mask 902, for example, the mask 902 is removed using a stripping solution.

[0065] As shown in FIG. 12, the method for manufacturing the semiconductor device 1A includes a step of forming a joint portion 40. The step of forming the joint portion 40 includes a step of forming a mask 903 and a step of forming a plating layer 41 and a solder layer 42.

[0066] In the step of forming the mask 903, for example, similar to the mask 902 shown in FIG. 11, for example, by photolithography, a mask 903 having an opening 9031 is formed. In the step of forming the plating layer 41 and the solder layer 42, similar to the plating layer 932 shown in FIG. 11, for example, by an electrolytic plating method, the plating layer 41 and the solder layer 42 are formed in this order. The plating layer 41 contains Ni and Ni alloys. The solder layer 42 contains an alloy containing Sn and Ag.

[0067] Also, the method for manufacturing the semiconductor device 1A includes a step of removing the mask 903. The step of removing the mask 903 removes the mask 903 using, for example, a stripping solution. Also, the method for manufacturing the semiconductor device 1A includes a step of removing the seed layer 931. The step of removing the seed layer 931 removes the seed layer 931 exposed from the plating layer 932 by etching, for example, wet etching. The remaining seed layer 931 and plating layer 932 constitute the actual wiring layer 30 shown in FIG. 13.

[0068] As shown in FIG. 13, the method for manufacturing the semiconductor device 1A includes a step of mounting the semiconductor element 50. The step of mounting the semiconductor element 50 includes a step of flip-chip mounting the semiconductor element 50 and a step of performing a reflow process. For example, using a flip-chip bonder, flux is applied to the element electrodes 55, and the semiconductor element 50 is flip-chip mounted. The reflow process cools the solder layer 42 shown in FIG. 12 to a liquid state by heating and then cools it. Through these processes, the semiconductor element 50 is mounted on the actual wiring layer 30 by the joint 40.

[0069] As shown in FIG. 14, the method for manufacturing the semiconductor device 1A includes a step of performing a roughening process. In FIG. 14, the locations to be roughened are indicated by thick lines. The step of performing the roughening treatment is a process of roughening the surfaces of the actual mounting wiring layer 30 and the element wiring layer 54. In this step, an alkaline solution is used as the roughening solution. The support substrate 900 on which the semiconductor element 50 is mounted is immersed in the roughening solution. The roughening solution (alkaline solution) used here reacts well with the Cu that constitutes the actual mounting wiring layer 30 (the conductive layer 32 shown in FIGS. 3 and 4) and the element wiring layer 54. Also, this roughening solution hardly reacts with metals other than Cu such as Ti, Ni, Sn, and Ag. Therefore, the surfaces of the actual mounting wiring layer 30 (conductive layer 32) and the element wiring layer 54 made of a material containing Cu become rough surfaces. In the semiconductor element 50 of the present embodiment, the element electrode 55 includes a conductive layer 56 formed of a material containing Cu. Therefore, the side surface 563 (see FIGS. 3 and 4) of the conductive layer 56 becomes a rough surface in this step, similar to the actual mounting wiring layer 30 (conductive layer 32) and the element wiring layer 54.

[0070] As shown in FIG. 15, the manufacturing method of the semiconductor device 1A includes a step of forming a resin layer 960. The resin layer 960 is a member that becomes the encapsulating resin 60 shown in FIG. 2. The resin layer 960 is a synthetic resin mainly composed of, for example, an epoxy resin. The resin layer 960 is formed, for example, by compression molding. The resin layer 960 is formed in contact with the resin main surface 9101 of the resin layer 910 so as to encapsulate the semiconductor element 50, the joint portion 40, and the actual mounting wiring layer 30. That is, the resin layer 960 is filled between the resin layer 910 and the semiconductor element 50.

[0071] As shown in FIGS. 16 and 17, the manufacturing method of the semiconductor device 1A includes a step of removing the support substrate 900. Attach a dicing tape (not shown) to the main surface 9601 of the resin layer 960. Note that Fig. 17 shows an upside-down view compared to Fig. 16. Then, by grinding, remove a part of the support substrate 900, the seed layer 901, a part of the resin layer 910, and a part of the terminal portion 920. At this time, grind from the side of the support substrate 900 toward the resin layer 960 up to the dashed line DL3 shown in Fig. 16. As a result, as shown in Fig. 19, the resin back surface 9102 of the resin layer 910 and the back surface 9202 of the terminal portion 920 are formed. Note that after peeling the support substrate 900 from the resin layer 910, a part of the resin layer 910, the seed layer 901, and a part of the terminal portion 920 may be ground.

[0072] As shown in Fig. 18, the method for manufacturing the semiconductor device 1A includes a step of forming a separation groove 904. In this step, while cutting the resin layer 910, a part of the resin layer 960 in the Z direction is cut (half-cut). When cutting the resin layer 910 and half-cutting the resin layer 960 in this way, for example, cut from the resin back surface 9102 of the resin layer 910 toward the main surface 9601 of the resin layer 960 along the dashed line (cutting line) DL1 shown in Fig. 18 using a dicing blade. In this way, by half-cutting the resin layer 960, a separation groove 904 is formed in the resin layer 960. Then, by cutting the resin layer 910 with a dicing blade and half-cutting the resin layer 960, the terminal portion 20 is formed. More specifically, the terminal side surface 204 of the terminal portion 20 and the actual mounting wiring side surface 304 of the actual mounting wiring layer 30 are formed. The terminal side surface 204 of the terminal portion 20 and the actual mounting wiring side surface 304 of the actual mounting wiring layer 30 are exposed in the separation groove 904.

[0073] As shown in FIG. 19, the manufacturing method of the semiconductor device 1A includes a step of forming an external conductive film 70. The external conductive film 70 includes a first conductive film 71 that contacts the terminal back surface 202 of the terminal portion 20, and a second conductive film 72 that contacts the terminal side surface 204 of the terminal portion 20 and the actual mounting line side surface 304 of the actual mounting line layer 30. The second conductive film 72 is formed in the separation groove 904. The external conductive film 70 is composed of a plating metal. For example, the external conductive film 70 is formed by depositing a plating metal, such as Ni, Pd, Au, in this order by an electroless plating method. Note that the configuration and formation method of the external conductive film 70 are not limited to the above method.

[0074] As shown in FIG. 20, the manufacturing method of the semiconductor device 1A includes a step of singulating. The resin layer 960 is cut, and the semiconductor element 50 is divided into individual pieces with one unit. At the time of division, for example, a dicing blade narrower than the dicing blade that half-cuts the resin layer 960 along the broken line (cutting line) DL1 cuts from the separation groove 904 of the resin layer 960 to the main surface 9601 of the resin layer 960, and the resin layer 960 is cut. The individual piece is the semiconductor device 1A including the encapsulation resin 60. Thereby, the encapsulation resin 60 is formed. The semiconductor device 1A is manufactured through the above steps.

[0075] (Operation) Next, the operation of the semiconductor device 1A of the present embodiment will be described. The semiconductor device 1A includes a resin layer 10, an actual mounting line layer 30, a semiconductor element 50, and an encapsulation resin 60. The resin layer 10 has a resin main surface 101. The actual mounting line layer 30 is disposed on the resin main surface 101 and has an actual mounting line main surface 301 and an actual mounting line back surface 302 facing the side opposite to the actual mounting line main surface 301. The semiconductor element 50 is mounted on the actual mounting line main surface 301, has an element wiring main surface 541 facing the resin layer 10 side, and includes an element wiring layer 54 connected to the actual mounting line layer 30. The encapsulation resin 60 encapsulates the actual mounting line layer 30 and the semiconductor element 50.

[0076] The main surface 301 of the actual mounting line layer is in contact with the encapsulating resin 60. The main surface 301 of the actual mounting line layer 30 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting line layer 30. Therefore, due to the anchor effect of the encapsulating resin 60 in contact with the main surface 301 of the actual mounting line layer 30, the adhesion of the encapsulating resin 60 to the actual mounting line layer 30 can be improved. And the peeling of the encapsulating resin 60 from the actual mounting line layer 30 can be suppressed.

[0077] The element wiring layer 54 has an element wiring main surface 541 and an element wiring back surface 542 facing the side opposite to the element wiring main surface 541. The element wiring main surface 541 is in contact with the encapsulating resin 60. The element wiring main surface 541 of the element wiring layer 54 is a rough surface with a larger surface roughness than the element wiring back surface 542 of the element wiring layer 54. Therefore, due to the anchor effect of the encapsulating resin 60 in contact with the element wiring main surface 541 of the element wiring layer 54, the adhesion of the encapsulating resin 60 to the element wiring layer 54 can be improved. And the peeling of the encapsulating resin 60 from the element wiring layer 54 can be suppressed.

[0078] The side surface 303 of the actual mounting line layer 30 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting line layer 30, similar to the main surface 301 of the actual mounting line layer 30. Therefore, the adhesion of the encapsulating resin 60 to the side surface 303 of the actual mounting line layer 30 can be improved. And the peeling of the encapsulating resin 60 from the side surface 303 of the actual mounting line layer 30 can be suppressed.

[0079] The element electrode 55 of the semiconductor element 50 includes a conductive layer 56 and a barrier layer 57. The conductive layer 56 is composed of, for example, Cu or a Cu alloy. The side surface 563 of the conductive layer 56 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting line layer 30. Therefore, the adhesion of the encapsulating resin 60 to the conductive layer 56 can be improved. And the peeling of the encapsulating resin 60 from the conductive layer 56 can be suppressed.

[0080] The terminal side surface 203 of the terminal portion 20 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting wiring layer 30. Thereby, the adhesion between the terminal side surface 203 of the terminal portion 20 and the resin layer 10 can be improved. And peeling of the terminal portion 20 from the resin layer 10 can be suppressed.

[0081] The semiconductor device 1A has an external conductive film 70 that contacts the exposed surface of the terminal portion 20. With the external conductive film 70, the semiconductor device 1A can be easily mounted on a circuit board. The external conductive film 70 has a first conductive film 71 that contacts the back surface 202 of the terminal portion 20 and a second conductive film 72 that contacts the terminal side surface 204 of the terminal portion 20. The first conductive film 71 and the second conductive film 72 increase the connection area to the circuit board and can be firmly fixed. Also, since a fillet of solder for connecting to the circuit board is formed on the second conductive film 72, the connection state to the circuit board can be easily confirmed.

[0082] The manufacturing method of the semiconductor device 1A has a step of making the main surface 301 of the actual mounting wiring layer 30 and the main surface 541 of the element wiring layer 54 into rough surfaces after the semiconductor element 50 is mounted on the actual mounting wiring layer 30. Thereby, compared with the case where the actual mounting wiring layer 30 and the element wiring layer 54 have separate side surfaces, the number of steps is small, and the actual mounting wiring layer 30 and the element wiring layer 54 can be easily made into rough surfaces.

[0083] The manufacturing method of the semiconductor device 1A has a step of roughening the surface of the terminal portion 920 that constitutes the terminal portion 920. The surface of the terminal portion 920 becomes the terminal side surface 203 of the terminal portion 20 of the semiconductor device 1A. Thereby, the adhesion between the terminal side surface 203 of the terminal portion 20 and the resin layer 10 can be improved. And peeling of the terminal portion 20 from the resin layer 10 can be suppressed.

[0084] (Effect) As described above, according to the present embodiment, the following effects are obtained. (1-1) The semiconductor device 1A includes a resin layer 10, a mounting wiring layer 30, a semiconductor element 50, and a sealing resin 60. The resin layer 10 has a resin main surface 101. The mounting wiring layer 30 is disposed on the resin main surface 101 and has a mounting wiring main surface 301 and a mounting wiring back surface 302 facing the side opposite to the mounting wiring main surface 301. The semiconductor element 50 is mounted on the mounting wiring main surface 301, has an element wiring main surface 541 facing the resin layer 10 side, and includes an element wiring layer 54 connected to the mounting wiring layer 30. The sealing resin 60 seals the mounting wiring layer 30 and the semiconductor element 50.

[0085] The mounting wiring main surface 301 is in contact with the sealing resin 60. The mounting wiring main surface 301 of the mounting wiring layer 30 is a rough surface with a larger surface roughness than the mounting wiring back surface 302 of the mounting wiring layer 30. Therefore, due to the anchor effect of the sealing resin 60 in contact with the mounting wiring main surface 301 with respect to the mounting wiring main surface 301 of the mounting wiring layer 30, the adhesion of the sealing resin 60 to the mounting wiring layer 30 can be improved. And the peeling of the sealing resin 60 from the mounting wiring layer 30 can be suppressed.

[0086] (1-2) The element wiring layer 54 has an element wiring main surface 541 and an element wiring back surface 542 facing the side opposite to the element wiring main surface 541. The element wiring main surface 541 is in contact with the sealing resin 60. The element wiring main surface 541 of the element wiring layer 54 is a rough surface with a larger surface roughness than the element wiring back surface 542 of the element wiring layer 54. Therefore, due to the anchor effect of the sealing resin 60 in contact with the element wiring main surface 541 with respect to the element wiring main surface 541 of the element wiring layer 54, the adhesion of the sealing resin 60 to the element wiring layer 54 can be improved. And the peeling of the sealing resin 60 from the element wiring layer 54 can be suppressed.

[0087] (1-3) The mounting wiring side surface 303 of the mounting wiring layer 30 is a rough surface with a larger surface roughness than the mounting wiring back surface 302 of the mounting wiring layer 30, similar to the mounting wiring main surface 301. Therefore, the adhesion of the sealing resin 60 to the mounting wiring side surface 303 can be improved. And the peeling of the sealing resin 60 from the mounting wiring side surface 303 can be suppressed.

[0088] (1-4) The device electrode 55 of the semiconductor device 50 includes a conductive layer 56 and a barrier layer 57. The conductive layer 56 is composed of, for example, Cu or a Cu alloy. The side surface 563 of the conductive layer 56 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting wiring layer 30 of the actual mounting wiring layer 30. Therefore, the adhesion of the encapsulating resin 60 to the conductive layer 56 can be improved. And the peeling of the encapsulating resin 60 from the conductive layer 56 can be suppressed.

[0089] (1-5) The terminal side surface 203 of the terminal portion 20 is a rough surface with a larger surface roughness than the back surface 302 of the actual mounting wiring layer 30 of the actual mounting wiring layer 30. Thereby, the adhesion between the terminal side surface 203 of the terminal portion 20 and the resin layer 10 can be improved. And the peeling of the terminal portion 20 from the resin layer 10 can be suppressed.

[0090] (1-6) The semiconductor device 1A has an external conductive film 70 that contacts the exposed surface of the terminal portion 20. With the external conductive film 70, the semiconductor device 1A can be easily mounted on a circuit board. The external conductive film 70 has a first conductive film 71 that contacts the back surface 202 of the terminal of the terminal portion 20 and a second conductive film 72 that contacts the terminal side surface 204 of the terminal portion 20. The first conductive film 71 and the second conductive film 72 increase the connection area to the circuit board and can be firmly fixed. Also, since a fillet of solder for connecting to the circuit board is formed with respect to the second conductive film 72, the connection state to the circuit board can be easily confirmed.

[0091] (1-7) The manufacturing method of the semiconductor device 1A includes a step of making the main surface 301 of the actual mounting wiring layer 30 and the main surface 541 of the device wiring layer 54 into rough surfaces after the semiconductor device 50 is mounted on the actual mounting wiring layer 30. Thereby, compared with the case where the actual mounting wiring layer 30 and the device wiring layer 54 have separate side surfaces, the number of steps is small, and the actual mounting wiring layer 30 and the device wiring layer 54 can be easily made into rough surfaces.

[0092] (1-8) The manufacturing method of the semiconductor device 1A has a step of roughening the surface of the terminal portion 920 that constitutes the terminal portion 920. The surface of the terminal portion 920 becomes the terminal side surface 203 of the terminal portion 20 of the semiconductor device 1A. Thereby, the adhesion between the terminal side surface 203 of the terminal portion 20 and the resin layer 10 can be improved. And it is possible to suppress the terminal portion 20 from peeling off from the resin layer 10.

[0093] (Second Embodiment) Hereinafter, the second embodiment will be described. The semiconductor device 1B of the present embodiment is mainly different from the semiconductor device 1A of the first embodiment in that it includes a first adhesion layer 81 and a second adhesion layer 82. In the following description, the same reference numerals are given to the constituent members similar to those in the first embodiment, and part or all of the description thereof is omitted.

[0094] [Schematic Configuration of Semiconductor Device] FIG. 21 is a cross-sectional view of the semiconductor device 1B of the present embodiment. FIGS. 22 and 23 are enlarged cross-sectional views of a part of the semiconductor device 1B. FIG. 24 is an enlarged cross-sectional view showing the element wiring layer 54, the second adhesion layer 82, and the sealing resin 60. FIG. 25 is an enlarged cross-sectional view showing the mounting wiring layer 30, the first adhesion layer 81, and the sealing resin 60.

[0095] The semiconductor device 1B has a first adhesion layer 81 and a second adhesion layer 82. The first adhesion layer 81 covers the surface of the mounting wiring layer 30. In other words, the semiconductor device 1B has a first adhesion layer 81 in contact with the surface of the mounting wiring layer 30.

[0096] As shown in FIGS. 22 and 23, the mounting wiring layer 30 has a mounting wiring main surface 301, a mounting wiring back surface 302, and a mounting wiring side surface 303. The mounting wiring back surface 302 is in contact with the resin main surface 101 of the resin layer 10. The mounting wiring main surface 301 and the mounting wiring side surface 303 are rough surfaces having a larger surface roughness than the mounting wiring back surface 302. The first adhesion layer 81 is in contact with the rough mounting wiring main surface 301 and the mounting wiring side surface 303.

[0097] The joint portion 40 for mounting the semiconductor element 50 on the actual mounting wiring layer 30 is provided on the actual mounting wiring main surface 301 of the actual mounting wiring layer 30. The covered portion 3011 of the actual mounting wiring main surface 301 covered by the joint portion 40 is a flat surface. The actual mounting wiring main surface 301 (exposed portion 3012) exposed from the joint portion 40 is a rough surface with a larger surface roughness than the actual mounting wiring back surface 302. The first adhesion layer 81 is in contact with the actual mounting wiring main surface 301 (exposed portion 3012) exposed from the joint portion 40.

[0098] The first adhesion layer 81 is an organic film. The first adhesion layer 81 contains an adhesion improver. With this first adhesion layer 81, the adhesion between the actual mounting wiring layer 30 and the sealing resin 60 in contact with the actual mounting wiring layer 30 can be further improved.

[0099] In the present embodiment, the surface roughness (arithmetic mean roughness Ra) of the actual mounting wiring main surface 301 of the actual mounting wiring layer 30 is 0.16 μm or more. The film thickness of the coated film of the first adhesion layer 81 is 40 nm or more and 120 nm or less. Thereby, peeling between the actual mounting wiring main surface 301 of the actual mounting wiring layer 30 and the sealing resin 60 can be suppressed.

[0100] FIG. 30 shows the evaluation results of the presence or absence of peeling with respect to the rough surface roughness and the film thickness of the coated film. In FIG. 30, the surface roughness is the arithmetic mean roughness Ra. The film thickness of the coated film is the film thickness of the first adhesion layer 81. In the hatched area in FIG. 30, no peeling occurred.

[0101] Note that the film thickness of the coated film of the first adhesion layer 81 can also be adjusted according to the surface roughness of the actual mounting wiring main surface 301. As shown in FIG. 30, when the surface roughness is 0.30 μm or more, in the first adhesion layer 81 with a film thickness of the coated film smaller than 40 nm, generation of peeling can be suppressed in the same manner as in the above embodiment. Furthermore, by setting the surface roughness to 0.30 μm or more, the first adhesion layer 81 can be omitted, that is, the configuration of the semiconductor device 1A of the first embodiment can be adopted.

[0102] The actual mounting line layer 30 has a metal layer 31 and a conductive layer 32. The metal layer 31 is composed of a material containing Ti. The conductive layer 32 is composed of a material containing Cu. And the side surface 313 of the metal layer 31 is a flat surface. The main surface 321 and the side surface 323 of the conductive layer 32 are rough surfaces. The adhesion layer is in contact with the main surface 321 and the side surface 323 of the rough conductive layer 32. That is, the first adhesion layer 81 is in contact with the surface (main surface 321 and side surface 323) of the conductive layer 32 and is not in contact with the surface (side surface 313) of the metal layer 31.

[0103] The element wiring layer 54 has an element wiring main surface 541, an element wiring back surface 542, and an element wiring side surface 543. The element wiring back surface 542 is in contact with the main surface 531 of the insulating film 53. The element wiring main surface 541 and the element wiring side surface 543 are rough surfaces with a surface roughness greater than that of the actual mounting line back surface 302 of the actual mounting line layer 30. The second adhesion layer 82 is in contact with the rough element wiring main surface 541 and the element wiring side surface 543.

[0104] The second adhesion layer 82 is an organic film. The second adhesion layer 82 contains an adhesion improver. With this second adhesion layer 82, the adhesion between the element wiring layer 54 and the sealing resin 60 in contact with the element wiring layer 54 can be further improved.

[0105] In this embodiment, the surface roughness (arithmetic mean roughness Ra) of the element wiring main surface 541 of the element wiring layer 54 is 0.16 μm or more. The coating film thickness of the second adhesion layer 82 is 40 nm or more and 120 nm or less. Thereby, peeling between the element wiring main surface 541 of the element wiring layer 54 and the sealing resin 60 can be suppressed.

[0106] FIG. 30 shows the evaluation results of the presence or absence of peeling with respect to the rough surface roughness and the coating film thickness. In FIG. 30, the surface roughness is the arithmetic mean roughness Ra. The coating film thickness is the film thickness of the second adhesion layer 82. In FIG. 30, peeling was not observed in the hatched area.

[0107] Note that the film thickness of the second adhesion layer 82 can also be adjusted according to the surface roughness of the main surface 541 of the element wiring. As shown in FIG. 30, when the surface roughness is 0.30 μm or more, in the second adhesion layer 82 with a film thickness smaller than 40 nm, generation of peeling can be suppressed in the same manner as in the above embodiment. Furthermore, by setting the surface roughness to 0.30 μm or more, the second adhesion layer 82 can be omitted, that is, the semiconductor device 1A of the first embodiment can be configured.

[0108] The semiconductor element 50 has an element electrode 55. The element electrode 55 is provided on the main surface 541 of the element wiring layer 54. The covered portion 5411 of the main surface 541 of the element wiring layer 54 covered by the element electrode 55 is a flat surface. The main surface 541 of the element wiring layer 54 exposed from the element electrode 55 is a rough surface with a larger surface roughness than the back surface 302 of the mounting wiring layer 30. The second adhesion layer 82 covers the main surface 541 (exposed portion 5412) of the element wiring layer 54 exposed from the element electrode 55.

[0109] The element electrode 55 includes a conductive layer 56 connected to the element wiring layer 54 and a barrier layer 57 continued from the conductive layer 56. The conductive layer 56 is made of a material containing Cu. The side surface 563 of the conductive layer 56 is a rough surface with a larger surface roughness than the back surface 302 of the mounting wiring layer 30. The barrier layer 57 is made of a material containing Ni. The side surface 573 of the barrier layer 57 is a flat surface. The second adhesion layer 82 is in contact with the surface (side surface 563) of the conductive layer 56 and is not in contact with the surface (side surface 573) of the barrier layer 57.

[0110] Therefore, the second adhesion layer 82 of the present embodiment has a wiring covering portion 821 in contact with the surface of the element wiring layer 54 and an electrode covering portion 822 in contact with the conductive layer 56 of the element electrode 55. The second adhesion layer 82 covers the surface of the element wiring layer 54 of the semiconductor element 50. In other words, the semiconductor device 1B has a second adhesion layer 82 (wiring covering portion 821) that contacts the surface of the element wiring layer 54 of the semiconductor element 50. Further, the second adhesion layer 82 covers the surface of the conductive layer 56 that constitutes the element electrode 55 of the semiconductor element 50. In other words, the semiconductor device 1B has a second adhesion layer 82 (electrode covering portion 822) that contacts the surface of the conductive layer 56 of the element electrode 55.

[0111] The second adhesion layer 82 is an organic film. The second adhesion layer 82 contains an adhesion improver. With this second adhesion layer 82, the adhesion between the element wiring layer 54 and the sealing resin 60 in contact with the element wiring layer 54 can be further improved. Thereby, peeling of the sealing resin 60 from the element wiring layer 54 can be suppressed. Also, with the second adhesion layer 82, the adhesion between the element electrode 55 and the sealing resin 60 in contact with the element electrode 55 can be further improved. Thereby, peeling of the sealing resin 60 from the element electrode 55 can be suppressed.

[0112] [Method for manufacturing a semiconductor device] Next, a method for manufacturing the semiconductor device 1B of the present embodiment will be described. FIG. 26 shows a state in which the semiconductor element 50 is mounted. FIG. 27 shows a state in which a roughening process is performed. That is, the method for manufacturing the semiconductor device 1B of the present embodiment includes the steps from FIGS. 7 to 14 shown in the method for manufacturing the semiconductor device 1A of the first embodiment.

[0113] As shown in FIG. 28, the method for manufacturing the semiconductor device 1B includes a step of forming the first adhesion layer 81 and the second adhesion layer 82. The first adhesion layer 81 and the second adhesion layer 82 are formed by applying a liquid resin material, for example, by a spin coating method. The resin material (organic solution) for forming the first adhesion layer 81 and the second adhesion layer 82 easily adheres to the surface of Cu and hardly adheres to the surface of metals other than Cu. Thereby, the first adhesion layer 81 is formed on the entire surface of the mounting wiring layer 30 on which the semiconductor element 50 is mounted, and the second adhesion layer 82 is formed on the entire surface of the element wiring layer 54 and the element electrode 55 of the mounted semiconductor element 50.

[0114] As shown in FIG. 29, the method for manufacturing the semiconductor device 1B includes a step of forming a resin layer 960. In this step, the resin layer 960 is formed by, for example, compression molding, in the same manner as the step shown in FIG. 15 of the first embodiment. The resin layer 960 is filled between the resin layer 910 and the actual wiring layer 30 and the semiconductor element 50, and is formed so as to contact the surfaces of the first adhesion layer 81 and the second adhesion layer 82.

[0115] After this step, through the steps shown in FIGS. 16 to 20 of the first embodiment, the semiconductor device 1B is formed. (Operation) Next, the operation of the semiconductor device 1B of the present embodiment will be described.

[0116] The semiconductor device 1B of the present embodiment has a first adhesion layer 81. The first adhesion layer 81 covers the surface of the actual wiring layer 30. In other words, the semiconductor device 1B has a first adhesion layer 81 that contacts the surface of the actual wiring layer 30. The first adhesion layer 81 is an organic film. The first adhesion layer 81 contains an adhesion improver. With this first adhesion layer 81, the adhesion between the actual wiring layer 30 and the sealing resin 60 that contacts the actual wiring layer 30 can be further improved.

[0117] The semiconductor device 1B has a second adhesion layer 82. The element wiring layer 54 has an element wiring front surface 541, an element wiring back surface 542, and an element wiring side surface 543. The element wiring back surface 542 is in contact with the main surface 531 of the insulating film 53. The element wiring front surface 541 and the element wiring side surface 543 are rough surfaces with a larger surface roughness than the actual wiring back surface 302 of the actual wiring layer 30. The second adhesion layer 82 is in contact with the element wiring front surface 541 and the element wiring side surface 543 that are rough surfaces. The second adhesion layer 82 is an organic film. The second adhesion layer 82 contains an adhesion improver. With this second adhesion layer 82, the adhesion between the element wiring layer 54 and the sealing resin 60 that contacts the element wiring layer 54 can be further improved.

[0118] FIG. 30 shows the evaluation results of the presence or absence of peeling when the rough surface roughness and the coating film thickness are changed. In FIG. 30, peeling was not observed in the hatched area. In FIG. 30, the surface roughness is the arithmetic mean roughness Ra. The coating film thickness is the film thicknesses of the first adhesion layer 81 and the second adhesion layer 82.

[0119] When the coating film thicknesses of the first adhesion layer 81 and the second adhesion layer 82 are 40 nm or more and the surface roughness is 0.16 μm or more, no peeling was observed. Note that even when the coating film thickness is less than 40 nm, if the surface roughness is 0.30 μm or more, no peeling was observed. And in the state where the coating film thickness is 0 nm, that is, in the state where the first adhesion layer 81 and the second adhesion layer 82 are absent, that is, in the state of the semiconductor device 1A of the first embodiment, if the surface roughness is 0.30 μm or more, no peeling was observed.

[0120] That is, for the actual wiring layer 30 and the element wiring layer 54, by making the surface roughness a rough surface of 0.3 μm or more, the first adhesion layer 81 and the second adhesion layer 82 can be omitted. And by making the coating film thicknesses of the first adhesion layer 81 and the second adhesion layer 82 40 nm, peeling can be suppressed for the actual wiring layer 30 and the element wiring layer 54 having a rough surface with a surface roughness of 0.16 μm or more and less than 0.30 μm.

[0121] (Effect) As described above, according to the present embodiment, in addition to the effects of the first embodiment, the following effects are obtained.

[0122] (2-1) The semiconductor device 1B of the present embodiment has the first adhesion layer 81. The first adhesion layer 81 covers the surface of the actual wiring layer 30. In other words, the semiconductor device 1B has the first adhesion layer 81 in contact with the surface of the actual wiring layer 30. The first adhesion layer 81 is an organic film. The first adhesion layer 81 contains an adhesion improver. By this first adhesion layer 81, the adhesion between the actual wiring layer 30 and the sealing resin 60 in contact with the actual wiring layer 30 can be further improved.

[0123] (2-2) The semiconductor device 1B of this embodiment has a second adhesion layer 82. The element wiring layer 54 has an element wiring front surface 541, an element wiring back surface 542, and an element wiring side surface 543. The element wiring back surface 542 is in contact with the main surface 531 of the insulating film 53. The element wiring front surface 541 and the element wiring side surface 543 are rough surfaces with a larger surface roughness than the actual mounting wiring back surface 302 of the actual mounting wiring layer 30. The second adhesion layer 82 is in contact with the element wiring front surface 541 and the element wiring side surface 543 which are rough surfaces. The second adhesion layer 82 is an organic film. The second adhesion layer 82 contains an adhesion improver. With this second adhesion layer 82, the adhesion between the element wiring layer 54 and the sealing resin 60 in contact with the element wiring layer 54 can be further improved.

[0124] (Modification example) The above embodiment can be modified as follows, for example. The above embodiment and each of the following modification examples can be combined with each other as long as no technical contradiction occurs. In the following modification examples, parts common to the above embodiment are denoted by the same reference numerals as those in the above embodiment, and the description thereof is omitted.

[0125] · In the method of manufacturing a semiconductor device, it may also be configured to include a step of roughening the surface of the actual mounting wiring layer 30 and a step of roughening the surface of the element wiring layer 54. For example, a semiconductor element 50 with a rough surface of the element wiring layer 54 and the element electrode 55 may be mounted on the actual mounting wiring layer 30. The surface of the actual mounting wiring layer 30 may be configured to be rough before mounting the semiconductor element 50. Also, the surface of the actual mounting wiring layer 30 may be configured to be rough after mounting the semiconductor element 50.

[0126] · In the second embodiment, it may also be configured to include a step of forming the first adhesion layer 81 and a step of forming the second adhesion layer 82. For example, a semiconductor element 50 with a second adhesion layer 82 formed in contact with the element wiring layer 54 and the element electrode 55 may be mounted on the actual mounting wiring layer 30. The first adhesion layer 81 in contact with the actual mounting wiring layer 30 may be configured to be formed before mounting the semiconductor element 50. Also, the first adhesion layer 81 may be configured to be formed after mounting the semiconductor element 50.

[0127] ·The configuration may also be such that the external conductive film 70 is omitted. ·Regarding the external conductive film 70, the configuration may be such that either one of the first conductive film 71 and the second conductive film 72 is omitted.

[0128] ·In the step of making the surface of the terminal portion 20 rough, an acidic solution may be used as the roughening solution. ·The step of making the surface of the terminal portion 20 rough may be omitted.

[0129] (Supplementary Note) The technical idea that can be grasped from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than limitation, the components described in the supplementary note are assigned the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples for the purpose of assisting understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0130] (Supplementary Note 1) A resin layer (10) having a resin main surface (101), An actual mounting wiring layer (30) disposed on the resin main surface (101) and having an actual mounting wiring main surface (301) facing the same side as the resin main surface (101) and an actual mounting wiring back surface (302) facing the side of the resin main surface (101), A semiconductor element (50) mounted on the actual mounting wiring main surface (301) and having an element wiring main surface (541) facing the side of the resin layer (10) and connected to the actual mounting wiring layer (30), A sealing resin (60) for sealing the actual mounting wiring layer (30) and the semiconductor element (50), Comprising, The actual mounting wiring main surface (301) and the element wiring main surface (541) are rough surfaces having a larger surface roughness than the actual mounting wiring back surface (302), Semiconductor device.

[0131] (Supplementary Note 2) The actual mounting wiring layer (30) has an actual mounting wiring side surface (303) connected to the actual mounting wiring main surface (301) and the actual mounting wiring back surface (302), The front surface of the actual mounting line (303) is a rough surface with a larger surface roughness than the back surface of the actual mounting line (302). The semiconductor device according to Supplementary Note 1.

[0132] (Supplementary Note 3) It is provided on the main surface of the actual mounting line (301) and has a joint portion (40) to which the semiconductor element (50) is connected. The main surface of the actual mounting line (301) includes a flat first covered portion (3011) covered by the joint portion (40) and a first exposed portion (3012) that is exposed from the joint portion (40) and has a larger surface roughness than the back surface of the actual mounting line (302). The semiconductor device according to Supplementary Note 1 or Supplementary Note 2.

[0133] (Supplementary Note 4) The semiconductor element (50) has an element electrode (55) provided on the main surface of the element wiring (541). The main surface of the element wiring (541) includes a flat second covered portion (5411) covered by the element electrode (55) and a second exposed portion (5412) that is exposed from the element electrode (55) and has a larger surface roughness than the back surface of the actual mounting line (302). The semiconductor device according to any one of Supplementary Notes 1 to 3.

[0134] (Supplementary Note 5) The element electrode (55) includes a conductive layer (56) connected to the element wiring layer (54) and a barrier layer (57) connected to the conductive layer (56). The side surface (563) of the conductive layer (56) is a rough surface with a larger surface roughness than the back surface of the actual mounting line (302). The side surface (573) of the barrier layer (57) is a flat surface. The semiconductor device according to Supplementary Note 4.

[0135] (Supplementary Note 6) The surface roughness of the main surface of the actual mounting line (301) is 0.3 μm or more. The semiconductor device according to any one of Supplementary Notes 1 to 5.

[0136] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the surface roughness of the main surface (541) of the element wiring is 0.3 μm or more.

[0137] (Supplementary Note 8) A first adhesion layer (81) in contact with the main surface (301) of the actual mounting wiring, A second adhesion layer (82) in contact with the main surface (541) of the element wiring, The semiconductor device according to any one of Supplementary Notes 1 to 5, comprising:

[0138] (Supplementary Note 9) The semiconductor device according to Supplementary Note 8, wherein the first adhesion layer (81) and the second adhesion layer (82) are organic films.

[0139] (Supplementary Note 10) The semiconductor device according to Supplementary Note 8 or 9, wherein the film thickness of the first adhesion layer (81) is 40 nm or more, and the surface roughness of the main surface (301) of the actual mounting wiring is 0.16 μm or more.

[0140] (Supplementary Note 11) The semiconductor device according to any one of Supplementary Notes 8 to 10, wherein the film thickness of the second adhesion layer (82) is 40 nm or more, and the surface roughness of the main surface (541) of the element wiring is 0.16 μm or more.

[0141] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 8 to 11, wherein the film thickness of the first adhesion layer (81) is 120 nm or less.

[0142] (Supplementary Note 13) The semiconductor device according to any one of Supplementary Notes 8 to 12, wherein the film thickness of the second adhesion layer (82) is 120 nm or less.

[0143] (Supplementary Note 14) The resin layer (10) has a resin back surface (201) facing the side opposite to the resin main surface (101), and a through hole (11) penetrating the resin layer (10) from the resin main surface (101) to the resin back surface (102). The semiconductor device has a terminal portion (20) provided in the through hole (11) and connected to the mounting wiring layer (30). The semiconductor device according to any one of Appendices 1 to 13.

[0144] (Appendix 15) The terminal portion (20) has a back surface (202) exposed from the resin back surface (102). The semiconductor device has an external conductive film (70) in contact with the back surface (202) of the terminal portion (20). The semiconductor device according to Appendix 14.

[0145] (Appendix 16) The terminal portion (20) has a side surface (204) exposed from the resin side surface (104) of the resin layer (10). The external conductive film (70) has a first conductive film (71) in contact with the back surface (202) of the terminal portion (20) and a second conductive film (72) in contact with the side surface (204) of the terminal portion (20). The semiconductor device according to Appendix 15.

[0146] (Appendix 17) A step of forming a resin layer (10) having a resin main surface (101). A step of forming a mounting wiring layer (30) having a mounting wiring main surface (301) facing the same direction as the resin main surface (101) and a mounting wiring back surface (302) facing the side of the resin main surface (101) on the resin main surface (101). A step of mounting a semiconductor element (50) having an element wiring layer (54) with an element wiring main surface (541) facing the side of the resin main surface (101) on the mounting wiring layer (30). A step of making the mounting wiring main surface (301) a rough surface with a surface roughness larger than that of the mounting wiring back surface (302). A step of making the element wiring main surface (541) a rough surface with a surface roughness larger than that of the mounting wiring back surface (302). A step of forming a sealing resin (60) in contact with the resin main surface (101) to seal the mounting wiring layer (30) and the semiconductor element (50). A method for manufacturing a semiconductor device including

[0147] (Appendix 18) After mounting the semiconductor element (50) on the actual mounting wiring layer (30), roughening the actual mounting wiring main surface (301) and the element wiring main surface (541) simultaneously, the method for manufacturing a semiconductor device according to Appendix 17.

[0148] (Appendix 19) A step of forming a first adhesion layer (81) in contact with the roughened actual mounting wiring main surface (301); A step of forming a second adhesion layer (82) in contact with the roughened element wiring main surface (541); The method for manufacturing a semiconductor device according to Appendix 17 or Appendix 18, including

[0149] (Appendix 20) Simultaneously forming the first adhesion layer (81) and the second adhesion layer (82), the method for manufacturing a semiconductor device according to Appendix 19.

[0150] (Appendix 21) A step of forming a terminal portion (920) on the main surface (9001) of a support substrate (900); A step of roughening the surface of the terminal portion (920); A step of forming a first resin layer (910) in contact with the surface of the terminal portion (920); Grinding the first resin layer (910) to form the resin layer (910) having a resin main surface (9101) and exposing the main surface (9201) of the terminal portion (920); Including The actual mounting wiring layer (30) is disposed on the resin main surface (9101) and is in contact with the main surface (9201) of the terminal portion (920), The method for manufacturing a semiconductor device according to any one of Appendices 17 to 20.

[0151] (Appendix 22) A step of removing the support substrate (900) and exposing the back surface (202) of the terminal portion (20) from the resin layer (10) Forming a separation groove (904) in the resin layer (10) toward the encapsulating resin (60) to expose the side surface (204) of the terminal portion (20); Forming an external conductive film (70) in contact with the back surface (202) and the side surface (204) of the terminal portion (20); including A method for manufacturing a semiconductor device according to Supplementary Note 21.

[0152] The above description is merely illustrative. Those skilled in the art can recognize that there are many more possible combinations and substitutions other than the components and methods (manufacturing processes) listed for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to encompass all alternatives, modifications, and changes within the scope of the present disclosure, including the scope of the claims.

Explanation of Reference Numerals

[0153] 1A, 1B Semiconductor device 10 Resin layer 101 Resin main surface 102 Resin back surface 103 Resin side surface 11 Through hole 113 Inner wall surface 20 Terminal portion 201 Terminal main surface 202 Terminal back surface 203 Terminal side surface 204 Terminal side surface 30 Actual mounting wiring layer 301 Actual mounting wiring main surface 3011 Coated portion 3012 Exposed portion 302 Actual mounting wiring back surface 303 Actual mounting wiring side surface 304 Actual mounting wiring side surface 31 Metal layer 311 Main surface 312 Back surface 313 Side surface 32 Conductive layer 321 Main surface 322 Back surface 323 Side surface 40 Joint 41 Plating layer 42 Solder layer 50 Semiconductor element 51 Element substrate 511 Main surface of the substrate 512 Back surface of the substrate 513 Side surface of the substrate 52 Electrode pad 53 Insulating film 531 Main surface 532 Back surface 54 Element wiring layer 541 Main surface of the element wiring 5411 Coated portion 5412 Exposed portion 542 Back surface of the element wiring 543 Side surface of the element wiring 55 Element electrode 56 Conductive layer 561 Main surface 562 Back surface 563 Side surface 57 Barrier layer 571 Main surface 572 Back surface 573 Side surface 60 Encapsulating resin 601 Main surface of the resin 602 Back surface of the resin 603 Side surface of the resin 603a First side surface of the resin 603b Second side surface of the resin 60A First resin portion 60B Second resin portion 61 Step 70 External conductive film 71 First conductive film 72 Second conductive film 81 First adhesion layer 82 Second adhesion layer 821 Wiring coating portion 822 Electrode coating portion 900 Support substrate 9001 Main surface 9002 Back surface 901 Seed layer 902 Mask 9021 Opening 903 Mask 9031 Opening 904 Separation Groove 910 Resin Layer 9101 Main Resin Surface 9102 Back Resin Surface 920 Terminal Part 9201 Main Surface 9202 Back Surface 930 Actual Mounting Line Layer 931 Seed Layer 932 Plating Layer 960 Resin Layer 9601 Main Surface DL1~DL3 Dashed Lines Ra Arithmetic Mean Roughness

Claims

1. A resin layer having a resin main surface, An actual mounting wiring layer disposed on the resin main surface, having an actual mounting wiring main surface facing the same side as the resin main surface and an actual mounting wiring back surface facing the side of the resin main surface, A semiconductor element mounted on the actual mounting wiring main surface, having an element wiring main surface facing the side of the resin layer and connected to the actual mounting wiring layer, A sealing resin for sealing the actual mounting wiring layer and the semiconductor element, comprising The actual mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the actual mounting wiring back surface, A semiconductor device.

2. The actual mounting wiring layer has an actual mounting wiring side surface connected to the actual mounting wiring main surface and the actual mounting wiring back surface, The actual mounting wiring side surface is a rough surface having a larger surface roughness than the actual mounting wiring back surface, The semiconductor device according to claim 1.

3. Provided on the actual mounting wiring main surface and having a joint portion to which the semiconductor element is connected, The actual mounting wiring main surface includes a flat first covering portion covered by the joint portion and a first exposed portion exposed from the joint portion and having a larger surface roughness than the actual mounting wiring back surface, The semiconductor device according to claim 1 or claim 2.

4. The semiconductor element has an element electrode provided on the element wiring main surface, The element wiring main surface includes a flat second covering portion covered by the element electrode and a second exposed portion exposed from the element electrode and having a larger surface roughness than the actual mounting wiring back surface, The semiconductor device according to any one of claims 1 to 3.

5. The element electrode includes a conductive layer connected to the element wiring layer and a barrier layer connected to the conductive layer, The side surface of the conductive layer is a rough surface with a surface roughness greater than that of the back surface of the actual mounting line. The side surface of the barrier layer is a flat surface. The semiconductor device according to claim 4.

6. The semiconductor device according to any one of claims 1 to 5, wherein the surface roughness of the main surface of the actual mounting line is 0.3 μm or more.

7. The semiconductor device according to any one of claims 1 to 6, wherein the surface roughness of the main surface of the element wiring is 0.3 μm or more.

8. A first adhesion layer in contact with the main surface of the actual mounting line, A second adhesion layer in contact with the main surface of the element wiring, The semiconductor device according to any one of claims 1 to 5, comprising:

9. The semiconductor device according to claim 8, wherein the first adhesion layer and the second adhesion layer are organic films.

10. The semiconductor device according to claim 8 or 9, wherein the film thickness of the first adhesion layer is 40 nm or more, and the surface roughness of the main surface of the actual mounting line is 0.16 μm or more.

11. The semiconductor device according to any one of claims 8 to 10, wherein the film thickness of the second adhesion layer is 40 nm or more, and the surface roughness of the main surface of the element wiring is 0.16 μm or more.

12. The resin layer has a resin back surface facing the side opposite to the resin main surface, and a through hole penetrating the resin layer from the resin main surface to the resin back surface. The semiconductor device has a terminal portion provided in the through hole and connected to the actual mounting line layer. The semiconductor device according to any one of claims 1 to 11.

13. The terminal portion has a back surface exposed from the resin back surface. The semiconductor device has an external conductive film in contact with the back surface of the terminal portion. The semiconductor device according to claim 12.

14. A step of forming a resin layer having a resin main surface; A step of forming a mounting wiring layer having a mounting wiring main surface facing the same direction as the resin main surface and a mounting wiring back surface facing the side of the resin main surface on the resin main surface; A step of mounting a semiconductor element having an element wiring main surface facing the side of the resin main surface on the mounting wiring layer; A step of making the mounting wiring main surface a rough surface having a larger surface roughness than the mounting wiring back surface; A step of making the element wiring main surface a rough surface having a larger surface roughness than the mounting wiring back surface; A step of forming a sealing resin that contacts the resin main surface and seals the mounting wiring layer and the semiconductor element; A method for manufacturing a semiconductor device including the above.

15. After mounting the semiconductor element on the mounting wiring layer, making the mounting wiring main surface and the element wiring main surface rough surfaces at the same time, the method for manufacturing a semiconductor device according to claim 14.

16. A step of forming a first adhesion layer that contacts the rough mounting wiring main surface; A step of forming a second adhesion layer that contacts the rough element wiring main surface; A method for manufacturing a semiconductor device according to claim 14 or claim 15, including the above.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the first adhesion layer and the second adhesion layer are formed at the same time.

18. A step of forming a terminal portion on the main surface of a support substrate; A step of making the surface of the terminal portion a rough surface; A step of forming a first resin layer that contacts the surface of the terminal portion; A step of grinding the first resin layer to form the resin layer having the resin main surface and exposing the main surface of the terminal portion; Including, The actual mounting line layer is disposed on the resin main surface and contacts the main surface of the terminal portion. The method for manufacturing a semiconductor device according to any one of claims 14 to 17.

19. Removing the support substrate to expose the back surface of the terminal portion from the resin layer; Forming a separation groove in the resin layer toward the encapsulating resin to expose the side surface of the terminal portion; Forming an external conductive film in contact with the back surface and the side surface of the terminal portion; comprising The method for manufacturing a semiconductor device according to claim 18.

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