Voltage detection device

Abstract

To provide a voltage detection device enabling enlargement of a range in which input leak is canceled, without requiring increase of a circuit area.SOLUTION: The voltage detector comprises a leak cancellation circuit 5 that uses a differential voltage detection circuit 4 sampling the respective voltages of two input nodes and detecting a differential voltage, to thereby generate a compensation current flowing in a direction opposite a leak current leaking from the two input nodes to the differential voltage detection circuit 4 side. The leak cancellation circuit 5 comprises: a D / A converter 6 that generates a command voltage for generating the compensation current; and an amplifier 7 that uses a MOS transistor having threshold voltage lower than a prescribed voltage as an input transistor to which the voltage generated by the D / A converter 6 is input.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a voltage detection device.

Background Art

[0002] The technology related to the present application is disclosed in Patent Document 1. According to the technology described in Patent Document 1, a differential voltage detection circuit having a differential configuration is provided. The differential voltage detection circuit includes two detection capacitors paired in its differential configuration, a first detection switch that opens and closes between one of the two detection capacitors and one of the two input nodes, a second detection switch that opens and closes between the other of the two detection capacitors and the other of the two input nodes, and a third detection switch that opens and closes between the two detection capacitors. The first and second detection capacitors and the third detection switch are turned on and off complementarily. Further, the leak canceling circuit has a differential configuration, and includes two compensation capacitors paired in the differential configuration, a first compensation switch that opens and closes between one of the two compensation capacitors and one of the two input nodes, a second compensation switch that opens and closes between the other of the two compensation capacitors and the other of the two input nodes, and a third compensation switch that opens and closes between the two compensation capacitors. The first and second compensation capacitors and the third compensation switch are turned on and off complementarily.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The inventors have discovered that when an amplifier using a normal MOS transistor is configured as a voltage generation circuit in the technology described in Patent Document 1, the amplitude becomes large and the characteristics deteriorate. In order to maintain the characteristics, it is necessary to increase the leak cancellation capacitance, which is not preferable because it increases the circuit area.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a voltage detection device capable of canceling leakage while suppressing the circuit area as much as possible.

Means for Solving the Problems

[0006] The invention according to claim 1 is directed to a voltage detection device that detects a differential voltage between two input nodes. When the leak cancellation circuit uses a differential voltage detection circuit that samples the voltages of the two input nodes to detect the differential voltage, the leak cancellation circuit generates a compensation current that flows in a direction opposite to the leak current that leaks from the two input nodes to the differential voltage detection circuit side.

[0007] The leak cancellation circuit includes a voltage generation circuit and an amplifier. The voltage generation circuit generates a voltage that depends on the compensation current for generating the compensation current. The amplifier is configured using a MOS transistor having a threshold voltage lower than a predetermined value as an input transistor that inputs and amplifies the output voltage of the voltage generation circuit. It has been confirmed that by using a MOS transistor with a low threshold voltage as the input transistor, it is possible to suppress characteristic variations in amplitude at a wide input voltage. As a result, it is not necessary to increase the leak cancellation capacitance, and the range for canceling input leakage can be expanded without increasing the circuit area.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7A

Figure 7B

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Modes for Carrying Out the Invention

[0009] Hereinafter, several embodiments of the voltage detection device will be described with reference to the drawings. In each of the embodiments described below, components that perform the same or similar operations are denoted by the same or similar reference numerals, and the description thereof will be omitted as necessary.

[0010] (First Embodiment) The first embodiment will be described with reference to FIGS. 1 to 10. As shown in FIG. 1, the assembled battery is configured by connecting a plurality of battery cells Cea, Ceb... that are secondary batteries in series in multiple stages. In FIG. 1, only two stages of the battery cells Cea and Ceb are shown, and subscripts a and b are attached to the symbol "Ce" representing the battery cell Ce, respectively. Also, for the components provided corresponding to each stage of these battery cells Cea and Ceb, for example, resistors R1, capacitors C1, and resistors R2, subscripts a and b are attached to represent resistors R1a, R1b, capacitors C1a, C1b, and resistors R2a, R2b. Further, to the terminal Ts, together with these subscripts a and b, subscript 1 is attached to the upstream side and subscript 2 is attached to the downstream side to represent terminals Tsa1, Tsa2, Tsb1, and Tsb2. In the following description, since the same configuration is provided for each stage, the subscripts a, b, 1, and 2 attached to the battery cell Ce, resistors R1, R2, capacitor C1, and terminal Ts may be omitted as necessary for the description.

[0011] A common mode voltage is superimposed on each battery cell Ce. The common mode voltage becomes higher for the battery cell Ce (for example, Cea) connected to the upper stage side, that is, the high potential side of the assembled battery, and the common mode voltage superimposed on the battery cell Ce is, for example, about several hundred volts. The battery monitoring device 1 is a device that monitors the voltage of the assembled battery, and is configured to be divided into an internal circuit of the monitoring IC2 and an external circuit 3 provided outside the monitoring IC2.

[0012] The monitoring IC2 is an integrated circuit provided for monitoring the voltages of the respective battery cells Cea, Ceb... of the assembled battery. Outside the monitoring IC2, an RC filter composed of resistors R1 (=R1a, R1b) and R2 (=R2a, R2b) and capacitors C1 (=C1a, C1b) is configured as the external circuit 3, and EMC countermeasures are thereby implemented. And the voltages of the respective battery cells Ce (=Cea, Ceb...) are input through terminals Ts (=Tsa1, Tsa2) and (=Tsb1, Tsb2...), respectively.

[0013] Inside the monitoring IC2, a multiplexer MUX, a switch SW, a differential voltage detection circuit 4, and a leakage cancellation circuit 5 are configured. The multiplexer MUX inputs the inter-terminal voltages of each battery cell Ce to input nodes N1a, N1b, N2a, N2b... and selectively outputs them. The switch SW is a switch for inputting the voltages of the input nodes N1a, N1b, N2a, N2b... to the differential voltage detection circuit 4 through the multiplexer MUX. The switch SW is configured by combining switches S1 to S4 and is configured to be able to change the voltage input polarity to the operational amplifier 13.

[0014] The differential voltage detection circuit 4 samples the voltages of the input nodes N1 and N2 of the multiplexer MUX to detect the differential voltage. At this time, the leakage cancellation circuit 5 is configured to generate a compensation current that flows in the opposite direction to the leakage current leaking from the two input nodes N1a, N2a, N1b, N2b to the differential voltage detection circuit 4 side. While the leakage cancellation circuit 5 energizes the compensation current, the differential voltage detection circuit 4 detects the differential voltage between the input nodes N1 and N2, so that the differential voltage can be detected with high accuracy without being affected by the voltage drop due to the influence of the leakage current.

[0015] Figure 2 shows a specific example of the internal configuration of the monitoring IC2. The differential voltage detection circuit 4 samples the voltages Vip and Vim of the differential input nodes of the differential voltage detection circuit 4 to detect the differential voltage, and is a sample and hold circuit with a differential configuration. Note that the differential voltage detection circuit 4 is configured by combining the fully differential operational amplifier 12 with switches 12a to 12j and capacitors C2a, C2b, C3a, and C3b. The capacitors C2a and C2b are configured in pairs and are set to the same value as each other, and the capacitors C3a and C3b are also configured in pairs and are set to the same value as each other. The switches 12a to 12j are configured by, for example, MOS transistors and are on / off controlled from the control circuit 15.

[0016] The common voltage of the operational amplifier 13 is set equal to the reference voltage Vcm that serves as the reference for voltage detection. The reference voltage Vcm is the intermediate voltage (e.g., +2.5V) of the power supply voltage VDD (e.g., +5V) of each circuit included in the voltage detection device. The operational amplifier 13 outputs differential voltages from its non-inverting output terminal and inverting output terminal, respectively. This differential voltage is A / D converted by the A / D converter 14, and various processes are performed by inputting this A / D conversion data to the upper device.

[0017] The leak canceling circuit 5 includes a D / A converter 6 as a voltage generation circuit, an amplifier 7, and a switch capacitor block 8. The D / A converter 6 is configured to input a digital command value for creating a compensation current, perform analog conversion, output two command voltages, and input them to the amplifier 7. The D / A converter 6 is composed of a fully differential type DAC whose input / output characteristics are shown in FIG. 3 or a pseudo differential type DAC whose input / output characteristics are shown in FIG. 4. The fully differential type DAC shown in FIG. 3 outputs two command voltages, namely, a first voltage that is directly proportional to the digital command value with a positive gradient and a second voltage that is directly proportional to the digital command value with a negative gradient. The pseudo differential type DAC shown in FIG. 4 outputs two command voltages, namely, a constant first voltage regardless of the digital command value and a second voltage that is directly proportional to the digital command value.

[0018] The amplifier 7 shown in FIG. 2 is composed of a differential amplifier formed by configuring two operational amplifiers 7a and 7b as voltage followers respectively, inputs the outputs of the two command voltages by the D / A converter 6, performs impedance conversion by the voltage followers, and outputs voltages respectively.

[0019] FIG. 5 shows the equivalent circuit diagrams of the operational amplifiers 7a and 7b. Since the electrical configuration of the operational amplifier 7b is the same as that of the operational amplifier 7a, the configuration of the operational amplifier 7a will be described here and the description of the configuration of the operational amplifier 7b will be omitted.

[0020] The operational amplifier 7a has a configuration of a two-stage amplifier section including an input stage Aa and an output stage Ab. The input stage Aa includes a constant current source formed by an MOS transistor Mp and a differential input section formed by input MOS transistors M1p and M1m. Further, the input stage Aa includes a so-called folded cascode type amplifier circuit Mcn having a cascode connection section Ca1 in which N-channel MOS transistors M4p, M4m, M7p, M7m, M8p, and M8m are cascode-connected in the illustrated form.

[0021] The cascode connection section Ca1 connects the sources of the MOS transistors M7p and M7m to the ground VSS, commonly connects the drain of the MOS transistor M7p and the source of the MOS transistor M8p, and further commonly connects the drain of the MOS transistor M7m and the source of the MOS transistor M8m. Further, the cascode connection section Ca1 connects between the drain of the MOS transistor M8m and the common gate of the MOS transistors M7p and M7m. Note that the gates of the MOS transistors M7p and M7m are commonly connected and a bias voltage Vb7 is applied. Also, the gates of the MOS transistors M8p and M8m are commonly connected and a bias voltage Vb8 is applied.

[0022] Further, an N-channel MOS transistor M4p is further cascode-connected between the MOS transistors M7p and M8p, and an N-channel MOS transistor M4m is further cascode-connected between the MOS transistors M7m and M8m. The gates of the MOS transistors M4p and M4m are commonly connected to each other, and a bias voltage Vb4 is applied.

[0023] Further, the input stage Aa includes a constant current source formed by an MOS transistor Mn and a differential input section formed by input MOS transistors M2p and M2m. Further, the input stage Aa includes a so-called folded cascode type amplifier circuit Mcp having a cascode connection section Ca2 in which P-channel MOS transistors M3p, M3m, M5p, M5m, M6p, and M6m are cascode-connected in the illustrated form.

[0024] The cascode connection part Ca2 connects the sources of the MOS transistors M5p and M5m to the node of the power supply voltage VDD, commonly connects the drain of the MOS transistor M5p and the source of the MOS transistor M6p, and further commonly connects the drain of the MOS transistor M5m and the source of the MOS transistor M6m. The cascode connection part Ca2 is configured by connecting between the drain of the MOS transistor M6m and the common gate of the MOS transistors M5p and M5m. Note that the gates of the MOS transistors M5p and M5m are commonly connected and a bias voltage Vb5 is applied. Also, the gates of the MOS transistors M6p and M6m are commonly connected and a bias voltage Vb6 is applied.

[0025] Further, a P-channel MOS transistor M3p is cascode-connected to the MOS transistors M5p and M6p, and a P-channel MOS transistor M3m is cascode-connected to the MOS transistors M5m and M6m. The gates of the MOS transistors M3p and M3m are commonly connected to each other, and a bias voltage Vb3 is applied.

[0026] Also, the drain of the MOS transistor M4m and the source of the MOS transistor M3m are commonly connected, and the source of the MOS transistor M4m and the drain of the MOS transistor M3m are commonly connected. Also, the drain of the MOS transistor M4p and the source of the MOS transistor M3p are commonly connected at the node No1, and the source of the MOS transistor M4p and the drain of the MOS transistor M3p are commonly connected at the node No2.

[0027] The output stage Ab includes a P-channel output MOS transistor Mo1 and an N-channel output MOS transistor Mo2. The aforementioned node No1 is connected to the gate of the output MOS transistor Mo1 of the output stage Ab, and the node No2 is connected to the gate of the output MOS transistor Mo2 of the output stage Ab.

[0028] The sources / drains of the output MOS transistors Mo1 and Mo2 are connected in series between the nodes of the power supply voltage VDD and the ground VSS. Also, the drains of the output MOS transistors Mo1 and Mo2 are commonly connected at node No3, and the output voltage Vout is output from node No3. In this operational amplifier 7a, the output stage Ab is bias - set to operate in class AB.

[0029] <Regarding the input MOS transistors M1p, M1m, M2p, M2m> It is desirable that the operational amplifiers 7a and 7b be configured using input MOS transistors M1p, M1m, M2p, M2m with a threshold voltage Vt lower than a predetermined value. When the saturation voltages of the MOS transistors Mp and Mn constituting the current source of the input stage are Vdsat, the input voltage ranges Vmin and Vmax in which the two input MOS transistors M1p, M1m, M2p, M2m operate in the saturation state are Vmin > VSS + VT + Vdsat Vmax < VDD - VT - Vdsat can be expressed as.

[0030] In the case of a general enhancement - type MOS transistor with a high threshold voltage, the threshold voltage Vt ≒ 0.6V. On the other hand, it is desirable that the threshold voltage Vt of the input MOS transistors M1p, M1m, M2p, M2m of the operational amplifiers 7a and 7b of this embodiment be a voltage lower than a predetermined value of 0.4V or less, or 0.3V or less, and further 0.2V or less. Furthermore, it is desirable to use a depletion - type MOSFET to make it 0V or less. Then, it can operate with a large amplitude, and capacitors 10a and 10b for leak cancellation with small capacitance values can be used, and the circuit area can be configured to be as small as possible.

[0031] Also, it is desirable that the input MOS transistors M1p and M1m be fabricated with their mutual conductances gm matched, and it is desirable that the input MOS transistors M2p and M2m be fabricated with their mutual conductances gm matched. Then, the influence of so - called PVT variations such as process and temperature can be suppressed.

[0032] Also, when the output voltage Vout approaches 0V or near the power supply voltage VDD, the drain-source voltage VDS of the output MOS transistors Mo1 and Mo2 becomes less than the saturation voltage Vdsat and enters the triode region, so the mutual conductance gm decreases. To suppress the transient fluctuation characteristics, in this embodiment, phase compensation capacitors Cp1 and Cp2 are connected between the node No3 that outputs the output voltage Vout and the cascode connection parts Ca1 and Ca2. By connecting the phase compensation capacitors Cp1 and Cp2 to the cascode connection parts Ca1 and Ca2, the transient response characteristics can be improved.

[0033] Next, the leak canceling operation will be described. Even when the switch SW is in the off state, as shown in FIG. 6, leakage current is generated from the nodes N1 and N2 through the off-state resistances Ra and Rb of the multiplexer MUX and the switch SW. Therefore, the leak canceling circuit 5 cancels the influence of this leakage current.

[0034] The control circuit 15 switches the switches 9, 11a to 11d, and 12a to 12j on or off by applying on-off switching control signals to the switches 9, 11a to 11d, and 12a to 12j. As shown in FIGS. 7A and 7B, the control circuit 15 controls the switches S5, S8, S11a, S11b, S12a, S12b, S12e, and S12f to be on and controls the switches S6, S7, S11c, S11d, and S12c to be off during the sample period. The control circuit 15 controls the switches S5, S8, S11a, S11b, S12a, S12b, S12e, and S12f to be on and controls the switches S6, S7, S11c, S11d, and S12c to be off during the hold period. At this time, the control circuit 15 reduces the error at the time of on-off switching by using the on-off switching control signal as a non-overlap signal.

[0035] As shown in FIG. 7A, the on / off switching of switches S5, S8, S11a, S11b, S12a, S12b, S12e, and S12f may be performed simultaneously, and the on / off switching of switches S6, S7, S11c, S11d, and S12c may also be performed simultaneously. As shown in FIG. 7B, the on / off switching timings of switches S5, S8, S11a, and S11b and switches S12a, S12b, S12e, and S12f may be shifted, and the on / off switching timings of switches S6, S7 and switches S11c, S11d, and S12c may be shifted.

[0036] FIG. 8 shows the connection state of the switches during the hold period, and FIG. 9 shows the connection state of the switches during the sample period. Switch 9 is configured by combining switches S5 to S8 in the illustrated form, and the connection can be configured to be a straight connection or a cross connection. After these hold period and sample period, differential voltage detection circuit 4 performs A / D conversion on the sample voltage. During the hold period shown in FIG. 8, switches 11a, 11b, 12a, and 12b are turned off to cut off the connection of input voltages Vdp and Vdm to capacitors C2a and C2b, switch 12c is turned on, and switches 12e and 12f are turned off to switch the holding voltages of capacitors C2a and C2b to be input to the differential input terminals of operational amplifier 13. Note that the potential of the differential input terminals of operational amplifier 13 becomes a potential that is virtually shorted with a reference voltage Vcm that is a common mode voltage. Also, control circuit 15 switches the input polarities of input voltages Vdp and Vdm to capacitors 10a and 10b by cross-connecting switch 9.

[0037] Also, during the sample period shown in FIG. 9, the control circuit 15 switches the switch 9 to a straight connection to change the input polarities of the input voltages Vdp and Vdm to the capacitors 10a and 10b. The leak canceling circuit 5 is configured to cancel the leak current by flowing a compensation current. During this sample period, the leak current flowing into the operational amplifier 13 of the differential voltage detection circuit 4 is equal to the leak charge per unit time with the sampling operation period of the switch capacitor circuit by the capacitors C2a to C2j as the unit time. The charge Qsh flowing during sampling can be expressed as in equation (1). Let Csh be the sampling capacitance by the input capacitors C2a and C2b of the operational amplifier 13, then Qsh = Csh × [((Vip + Vim) / 2 - Vip) - (Vcm - Vcm)] …(1) On the other hand, the charge Qlc flowing due to the operation of the leak canceling circuit 5 can be expressed as in equation (2). Let Clc be the leak canceling capacitance by the capacitors 10a and 10b, then Qlc = Clc × ((Vdm - Vdp) - ((Vip + Vim) / 2 - Vip)) …(2)

[0038] Assuming the voltage ΔVi = Vip - Vim and the leak canceling voltage ΔVd = Vdp - Vdm, equations (3) and (4) hold. Qsh = Csh × (-ΔVi / 2) …(3) Qlc = Clc × (-ΔVd + ΔVi / 2) …(4)

[0039] By setting Qsh = Qlc in these equations (3) and (4), the leak canceling action by the leak canceling circuit 5 can be efficiently achieved. When the right side of the above equation (3) = the right side of equation (4), it can be expanded into an equation as in equation (5). Csh × (-ΔVi / 2) = Clc × (-ΔVd + ΔVi / 2) …(5) Also, it can be obtained as in the following equations (6) and (7). Csh / Clc × (-ΔVi / 2) = (-ΔVd + ΔVi / 2) …(6) ΔVd = ΔVi / 2 + Csh / Clc × (ΔVi / 2) ΔVd = (1 + Csh / Clc) × (ΔVi / 2) …(7) Therefore, it is advisable to set the leakage cancellation voltage ΔVd so that this equation (7) holds true.

[0040] When the sampling capacitance Csh is constant, by using a MOS transistor with a low threshold voltage Vt, the leakage cancellation voltage ΔVd with respect to the input voltage ΔVi can be increased, and a leakage cancellation capacitance Clc with a small capacitance value can be used. If the value of the leakage cancellation capacitance Clc can be reduced, the circuit area can be miniaturized.

[0041] The technical significance of this embodiment will be described with reference to FIG. 10. <Comparative Example> Consider the case where normal enhancement-type MOS transistors are used for the input MOS transistors M1p and M1m. When the input voltage approaches 0V or the power supply voltage VDD, the MOS transistors Mn or Mp that constitute the current source are turned off. As a result, the characteristics change compared to when the input voltage is near the center. In particular, when using an amplifier that utilizes a normal enhancement-type MOS transistor with a threshold voltage Vt of 0.6V or higher, the characteristics deteriorate when the input voltage is outside a predetermined range and has a large amplitude. At this time, the error voltage based on the offset voltage increases, and the EMC characteristics deteriorate.

[0042] <Technical Significance of this Embodiment> In contrast, according to this embodiment, when amplifying the command voltage output by the D / A converter 6 by inputting it, MOS transistors with a lower threshold voltage Vt than a predetermined value are used as the input MOS transistors M1p and M1m. Since MOS transistors with a low threshold voltage Vt are used as the input MOS transistors M1p and M1m, they are less likely to turn off even when the input voltage approaches the power supply voltage VDD or zero, and the variation in offset becomes stable.

[0043] At this time, it has been confirmed that the accuracy can be improved near the maximum and minimum values at both ends of the amplitude regardless of how the PVT variation fluctuates. By adopting the configuration of this characteristic, it becomes possible to reduce the capacitor capacitance while maintaining the overall accuracy, and thus the circuit area can be reduced.

[0044] In particular, by configuring the operational amplifiers 7a and 7b using depletion-type MOSFETs for the input MOS transistors M1p and M1m, the threshold voltage Vt can be made low as zero, and it can be configured more effectively.

[0045] Also, as shown in the comparative example of the leak cancellation circuit 103 in FIG. 10, when a single-ended configuration is adopted for reducing the consumption current, a problem occurs in that the EMC characteristics deteriorate. In the present embodiment, as the D / A converter 6, a DAC configuration having outputs of two command voltages is adopted, such as a fully differential type DAC shown in FIG. 3 or a pseudo-differential type DAC shown in FIG. 4.

[0046] By adopting the D / A converter 6 having two outputs as compared with a D / A converter having one output, the offset DC voltage can be made low. Also, by configuring the leak cancellation circuit 5 in a pseudo-differential configuration using two operational amplifiers 7a and 7b, the impedances can be made equal to each other at the frequency of the EMC noise input in the common mode, and the EMC tolerance can be improved.

[0047] (Second Embodiment) The second embodiment will be described with reference to FIGS. 11 to 14. In the present embodiment, a form of correlated double sampling will be described. The leak cancellation circuit 205 shown in FIG. 11 according to the present embodiment includes switch capacitor blocks 8a and 8b connected in parallel together with the D / A converter 6 and the amplifier 7. Also, since the other configurations are the same as those in the foregoing embodiment, the description thereof will be omitted.

[0048] As shown in the equivalent circuit in FIG. 12, the switch capacitor blocks 8a and 8b have the same configuration as each other and the same configuration as the switch capacitor block 8 described in the foregoing embodiment. Therefore, the same reference numerals as those in the foregoing embodiment are assigned to the respective components of the switch capacitor blocks 8a and 8b, and they are illustrated with subscripts a and b respectively. The switch capacitor block 8a includes a switch 9a having switches S5a to S8a, and capacitors 10aa, 10ba, switches 11aa, 11ba, 11ca, 11da. The switch capacitor block 8b includes a switch 9b having switches S5b to S8b, and capacitors 10ab, 10bb, switches 11ab, 11bb, 11cb, 11db. The description of the connection of these capacitors 10aa, 10ba, 10ab, 10bb, switches 9a, 9b, 11aa, 11ba, 11ca, 11da, 11ab, 11bb, 11cb, 11db is omitted.

[0049] Next, the leak canceling operation will be described. In the foregoing embodiment, a form of canceling the leak current only during the sample period is shown, but in this form, the leak current can be canceled both during the hold period and the sample period.

[0050] The control circuit 15 switches the switches 9a, 9b, 11aa to 11da, 11ab to 11db, 12a to 12j on or off to make the connection as shown in the hold period in FIG. 13 and the sample period in FIG. 14. After repeating these hold periods and sample periods, the differential voltage detection circuit 4 performs A / D conversion on the sample voltage. At this time, during correlated double sampling, two switch capacitor blocks 8a and 8b are prepared and operated alternately, and the leak current is canceled by passing a compensation current both during the hold period and the sample period.

[0051] In the steady state of the hold period shown in FIG. 13, the capacitors 10aa and 10ba of the switch capacitor block 8a hold charges based on the input voltages Vdp and Vdm of the switch capacitor block 8a and the intermediate potential (Vip + Vim) / 2 of the differential node of the differential voltage detection circuit 4 into which the leakage current flows.

[0052] At this time, the non-inverting input terminal and the inverting input terminal of the operational amplifier 13 are connected so as to be short-circuited by turning on the switches 12e and 12f, and the differential input terminals of the operational amplifier 13 are each held at the voltage of (Vip + Vim) / 2. In the hold period shown in FIG. 13, conversely, the switch capacitor block 8b passes a current based on the charge Qlc through the capacitors 10ab and 10bb of the switch capacitor block 8b to the input side of the operational amplifier 13. Thereby, the charge Qsh due to the leakage current flowing in the hold period is canceled.

[0053] Also, in the steady state of the sample period shown in FIG. 14, the capacitors 10ab and 10bb of the switch capacitor block 8b hold charges based on the input voltages Vdp and Vdm and the intermediate potential (Vip + Vim) / 2 of the differential node into which the leakage current flows. Also, the non-inverting input terminal and the inverting input terminal of the operational amplifier 13 are open and in an imaginary short state. Conversely, in the sample period shown in FIG. 14, in the switch capacitor block 8a, a current based on the charge Qlc is passed through the capacitors 10aa and 10ba to the input side of the operational amplifier 13 to cancel the charge Qsh due to the leakage current flowing in the sample period.

[0054] The leakage current flowing into the operational amplifier 13 is equal to the leakage charge per unit time with the sampling operation period of the switch capacitor blocks 8a and 8b by the capacitors C2a to C2j as the unit time. The charge Qsh flowing during sampling can be expressed as in equation (11). Qsh = Csh × ((Vim - Vip) - (Vcm - Vcm)) …(11) The charge Qsh flowing during the hold can also be expressed as in Equation (12). Qsh = Csh × ((Vim - Vip) - (Vcm - Vcm)) …(12) The charge Qlc flowing by operating one of the leak cancel circuits 5 can be expressed as in Equation (13). Qlc = Clc × ((Vdm - Vdp) - ((Vip + Vim) / 2 - Vip)) …(13)

[0055] Assuming the input voltage ΔVi (= Vip - Vim) and the leak cancel voltage ΔVd (= Vdp - Vdm), Qsh = Csh × (-ΔVi) …(14) Qlc = Clc × (-ΔVd + ΔVi / 2) …(15) Leak cancellation is achieved when Qsh = Qlc. At this time, it is preferable to set the leak cancel voltage ΔVd as in Equation (16). ΔVd = ((2Csh + Clc) / (2 × Clc)) × ΔVi …(16)

[0056] Similar to the first embodiment, when the sampling capacitance Csh is constant, by using an MOS transistor with a low threshold voltage Vt, the leak cancel voltage ΔVd with respect to the input voltage ΔVi can be increased, and a leak cancel capacitance Clc with a small capacitance value can be used. If the value of the leak cancel capacitance Clc can be made small, the circuit area can be reduced.

[0057] According to this embodiment, since the leak cancel circuit 5 performs correlated double sampling based on the command voltage from the D / A converter 6 to generate a compensation current, it has the same effects as the previous embodiments, and can cancel the leak current during the hold period and the sample period in the case of correlated double sampling.

[0058] (Third Embodiment) The third embodiment will be described with reference to FIG. 15. In this embodiment, a mode will be described in which the operational amplifier 7a for leak cancellation is used as an amplifier that buffers an external voltage by switching the switches SW, SW2, and SW3.

[0059] In the device shown in FIG. 15, switches SW2, SW3, and multiplexer MUX2 are provided outside the leak cancellation circuit 5. The switch SW2 is configured by connecting the switches S9 to S12 in the illustrated form, and is configured to be cross-connectable or straight-connectable based on the control of the control circuit 15. Further, the multiplexer MUX2 can switch and input the detection signals of the external temperature detection circuit 30 using a thermistor or the like and the BLK voltage detection circuit 31 via the external connection terminals T1 and T2. Also, a chip temperature detection circuit 32 that uses a current source and a diode to detect the heat generation temperature of the semiconductor chip is connected to the multiplexer MUX2.

[0060] The switch SW2 indicates a switch that selects whether to input the signal input from the multiplexer MUX2 to the operational amplifier 7a of the leak cancellation circuit 205. The switch SW3 indicates a switch that selects whether to input the output of the operational amplifier 7a to the input side of the switch SW.

[0061] When using the operational amplifier 7a for leak cancellation as an amplifier that buffers an external voltage, the control circuit 15 uses the switches SW, SW2, and SW3 in the on state and the switch 9 in the off state.

[0062] At this time, when the multiplexer MUX2 selects and switches the output signal of any one of the external temperature detection circuit 30, the BLK voltage detection circuit 31, and the chip temperature detection circuit 32 based on the control of the control circuit 15 and outputs it, as in the path Ka indicated by the thick line in FIG. 15, the detection signal selected and switched through the multiplexer MUX2 can be input to the operational amplifier 7a of the differential voltage detection circuit 4. At this time, by turning on the switch SW by the control circuit 15, the voltage after voltage buffering by the operational amplifier 7a can be input to the differential voltage detection circuit 4. As a result, the operational amplifier 7a having an input transistor with a low threshold voltage Vt can be used as a voltage buffer for processing an external signal.

[0063] (Other embodiments) The present invention is not limited to the above-described embodiments, and can be implemented in various modifications, and is applicable to various embodiments without departing from the gist thereof.

[0064] Regarding the external RC filter in which the resistors R1 and R2 and the capacitor C1 are connected outside the monitoring IC2, a form in which the resistors R1 and R2 and the capacitor C1 are configured in a π shape is shown, but the present invention is not limited thereto, and the resistors R1 and R2 and the capacitor C1 may be configured in an L shape. The monitoring IC2 equipped with the leak canceling circuit 5 may reduce the RC filter for EMC countermeasures externally attached to the monitoring IC2. Although the D / A converter 6 is configured as a "voltage generation circuit", any voltage generation circuit may be used as long as it is a voltage generation circuit that generates a command voltage for generating a compensation current.

[0065] The present invention has been described in accordance with the above-described embodiments, but it is understood that the present invention is not limited to the embodiments and structures. The present invention also includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, and further, other combinations and forms including one element, more, or less thereof, are within the scope and spirit of the present invention.

Explanation of reference numerals

[0066] In the drawing, 2 indicates a voltage detection circuit (integrated circuit), 4 indicates a differential voltage detection circuit, 5 indicates a leak canceling circuit, 6 indicates a D / A converter (voltage generation circuit), 7 indicates an amplifier, and 7a and 7b indicate operational amplifiers.

Claims

1. A voltage detection device for detecting a differential voltage between two input nodes, comprising a differential voltage detection circuit that samples the voltages of the two input nodes to detect the differential voltage, and a leakage canceling circuit (5) that generates a compensation current flowing in a direction opposite to the leakage current flowing from the two input nodes to the differential voltage detection circuit side; The leakage canceling circuit, comprises a voltage generation circuit (6) that generates a command voltage for generating the compensation current, and an amplifier (7) using a MOS transistor with a threshold voltage lower than a predetermined value as an input transistor that inputs the voltage generated by the voltage generation circuit, the voltage detection device.

2. The leakage canceling circuit performs correlated double sampling based on the command voltage from the voltage generation circuit to generate the compensation current, the voltage detection device according to claim 1.

3. The voltage generation circuit of the leakage canceling circuit outputs two command voltages, a first voltage that is directly proportional to the digital command value with a positive gradient and a second voltage that is directly proportional to the digital command value with a negative gradient, or is composed of a D / A converter that outputs two command voltages, a constant first voltage regardless of the digital command value and a second voltage that is directly proportional to the digital command value, The amplifier is composed of two operational amplifiers, and each of the outputs of the two command voltages from the D / A converter is connected to the inputs of the two operational amplifiers to perform voltage follower and output, the voltage detection device according to claim 1.

4. It is configured as an integrated circuit, and an RC filter configured by connecting a resistor and a capacitor is provided outside the integrated circuit, and the signal input through the RC filter is input through two input nodes, the voltage detection device according to claim 1.

5. The leak canceling circuit is configured with an amplification unit having two stages, an input stage and an output stage, and the output stage is configured to operate in class AB. The voltage detection device according to claim 1.

6. The input stage is constituted by a folded cascode type amplifier circuit including a differential input unit constituted by the input transistor and a cascode connection unit cascode-connected to the differential input unit. The amplifier is configured by connecting a capacitor for phase compensation between the cascode connection unit of the input stage and the output stage. The voltage detection device according to claim 5.

7. The voltage detection device according to claim 3, wherein the operational amplifier is selectively used as a voltage buffer for buffering an external voltage.

Images