TS synthesis device and broadcast system

Abstract

Provided are a TS synthesizing apparatus and a broadcast system that can synchronize internal SF phases between TS synthesizing apparatuses without relying on an SF synchronization signal generating apparatus. 【Solution means】The TS synthesizing apparatus is a redundantly configured TS (Transport Stream) synthesizing apparatus, and includes: a generating means that generates an internal phase using a clock signal within a receiving station; and a setting means that sets, as an internal phase to be used by its own apparatus, the internal phase generated by the generating means of a TS synthesizing apparatus that was started earlier among a plurality of redundantly configured TS synthesizing apparatuses.

Description

Technical Field

[0001] The present disclosure relates to a TS synthesizer that synthesizes TS signals and a broadcasting system.

Background Art

[0002] In satellite broadcasting, the ISDB (Integrated Services Digital Broadcasting)-S system is used. A transport stream (TS) signal having a structure for satellite broadcasting transmitted from a signal processing device (hereinafter referred to as a transmission-side signal processing device) of a broadcasting company (hereinafter referred to as a consigning station) is transmitted to an uplink station (hereinafter referred to as a receiving station). At the receiving station, a TS synthesizer synthesizes TS signals from a plurality of consigning stations. The synthesized TS signal is transmitted from the transmission facility to a broadcasting satellite. Hereinafter, the TS signal is expressed as TS.

[0003] The clock signal at the consigning station and the clock signal at the receiving station need to be frequency-synchronized. If the synchronization between the consigning station and the receiving station is lost, an overflow or an underflow occurs in the input buffer of the TS synthesizer. When an overflow or an underflow occurs, video freezes, audio muting, etc. occur. Hereinafter, video freezes and the like are referred to as video noise. Also, audio muting and the like are referred to as audio noise.

[0004] The transmission-side signal processing device generates a TS having a superframe (hereinafter referred to as SF) structure synchronized with the clock signal at the consigning station, and transmits the generated TS to the receiving station. When the pseudo-synchronization method is used at the receiving station, a TS pseudo-synchronization device is installed. The TS pseudo-synchronization device regenerates (reconstructs) the TS transmitted by the transmission-side signal processing device into a TS synchronized with the clock signal at the receiving station and outputs it to the TS synthesizer.

[0005] An SF phase is generated at the receiving station. The SF phase is a phase used for the signal output operation of the device. Hereinafter, the SF phase held by each device at the receiving station is referred to as an internal SF phase.

[0006] The receiving office has two systems, an active system (N system) and a standby system (E system), for stable operation. Therefore, the receiving office has an N-system TS synthesizer and an E-system TS synthesizer. For example, when a failure occurs in the N system, the N system and the E system are switched, and the E system becomes the active system. For example, Patent Document 1 describes an example of using two TS synthesizers in a redundant configuration.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] In a redundant configuration of a general TS synthesizer, a reference synchronization configuration is adopted to synchronize the internal SF phases of two TS synthesizers. In the reference synchronization configuration, the internal SF phases of two TS synthesizers are synchronized based on the SF phase generated by the SF synchronization signal generator.

[0009] However, the SF synchronization signal generator is not redundantly configured. Therefore, when the SF synchronization signal generator fails, a phase shift may occur in the internal SF phases between the N-system TS synthesizer and the E-system TS synthesizer, and synchronization may be lost. Strictly speaking, when either the N-system TS synthesizer or the E-system TS synthesizer is restarted after the SF synchronization signal generator fails, a phase shift may occur in the internal SF phases between the N-system TS synthesizer and the E-system TS synthesizer, and synchronization may be lost. Then, the continuity between the TS from the N-system TS synthesizer and the TS from the E-system TS synthesizer is impaired. As a result, packet duplication or loss of one SF occurs immediately after system switching. When packet duplication or loss occurs, video noise or audio noise may occur.

[0010] FIG. 12 is an explanatory diagram showing an example in which a phase shift occurs in the internal SF phase of two TS synthesizers. FIG. 12 shows the SF phase output from the SF synchronization signal generator, the internal SF phase of the first TS synthesizer, and the internal SF phase of the second TS synthesizer.

[0011] When the first TS synthesizer is started, it inputs the SF phase generated by the SF synchronization signal generator and synchronizes its internal SF phase with the input SF phase. Similarly to the first TS synthesizer, when the second TS synthesizer is started, it inputs the SF phase generated by the SF synchronization signal generator and synchronizes its internal SF phase with the input SF phase. As a result, the first TS synthesizer and the second TS synthesizer are in a state where their internal SF phases are synchronized.

[0012] Thereafter, for example, due to a failure, maintenance, etc., the SF synchronization signal generator restarts. The TS synthesizer holds the internal SF phase synchronized with the SF phase input at startup. Therefore, as long as there is no problem with the clock, the first TS synthesizer and the second TS synthesizer can maintain the state where their internal SF phases are synchronized. However, a phase shift occurs between the SF phase generated by the SF synchronization signal generator and the internal SF phases of the first TS synthesizer and the second TS synthesizer. Specifically, the SF synchronization signal generator outputs the SF phase generated internally without inputting the SF phase from the outside at startup (or restart). Therefore, the SF phase output by the SF synchronization signal generator after restart does not match the SF phase output before restart. Thus, a phase shift occurs between the SF phase output by the SF synchronization signal generator and the internal SF phase of the TS synthesizer.

[0013] When any of the TS synthesizers restarts after the SF synchronization signal generator restarts, a phase shift occurs in the internal SF phases of the two TS synthesizers. For example, after the SF synchronization signal generator restarts, only the first-system TS synthesizer restarts. Then, when the first-system TS synthesizer starts up, it synchronizes its internal SF phase with the SF phase generated by the SF synchronization signal generator after restart. On the other hand, the second-system TS synthesizer synchronizes its internal SF phase with the SF phase generated by the SF synchronization signal generator before restart. Therefore, a phase shift (phase difference) occurs between the internal SF phase of the first-system TS synthesizer and the internal SF phase of the second-system TS synthesizer.

[0014] An object of the present disclosure is to provide a TS synthesizer and a broadcast system that can synchronize the internal SF phases between TS synthesizers without relying on an SF synchronization signal generator.

Means for Solving the Problem

[0015] The TS synthesizer according to the present disclosure is a redundantly configured TS (Transport Stream) synthesizer, and includes a generation means for generating an internal phase using a clock signal in a receiving station, and a plurality of redundantly configured TS synthesizers In the case where the own device starts up later, the previous to the of other systems internal phase generated by the generation means of the started own TS synthesizer is set and when the own device starts up first, set the internal phase generated by the generation means of the own device as the internal phase used by the own device as the internal phase to be used in the device.

[0016] The broadcast system according to the present disclosure includes a clock signal generation unit that generates a clock signal, and a TS synthesizer that synthesizes a TS (Transport Stream). The TS synthesizer includes a generation means for generating an internal phase using the clock signal generated by the clock signal generation unit, and a plurality of redundantly configured TS synthesizers In the case where the own device starts up later, the previous to the of other systems internal phase generated by the generation means of the started own TS synthesizer is set and when the own device starts up first, set the internal phase generated by the generation means of the own device as the internal phase used by the own device as the internal phase to be used in the device.

Effect of the Invention

[0017] According to the present disclosure, internal SF phase synchronization can be achieved mutually between TS synthesizers.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0020] FIG. 1 is a system configuration diagram showing a system including a trustee station and a consignor station having a general redundant configuration TS synthesizer. In FIG. 1, a trustee station 100, consignor stations 200, 210, and a transmission facility 300 are shown. The transmission facility 300 transmits the TS received from the trustee station 100 to a broadcasting satellite.

[0021] The trustee station 100 is provided with an N-system TS pseudo-synchronization device 101, an E-system TS pseudo-synchronization device 102, a clock signal generation device 110, an SF synchronization signal generation device 120, an N-system TS synthesizer 130, and an E-system TS synthesizer 131.

[0022] The TS pseudo-synchronization devices 101, 102 reconstruct the TS transmitted by the consignor station 200 into a TS synchronized with the clock signal at the trustee station, and output the reconstructed TS to the TS synthesizers 130, 131.

[0023] The clock signal generation device 110 generates a clock signal and supplies the clock signal to the TS pseudo-synchronization devices 101, 102, the SF synchronization signal generation device 120, and the TS synthesizers 130, 131. The dotted lines in FIG. 1 indicate the supply of the clock signal.

[0024] The SF synchronization signal generation device 120 generates an SF phase signal based on the clock signal. The SF phase signal is supplied to the TS synthesizers 130, 131.

[0025] The TS synthesizers 130, 131 are redundantly configured. The redundant configuration means that a plurality of devices are provided so that the operation can be continued even if some of them fail. The TS synthesizers 130, 131 select either the TS output by the N-system TS pseudo-synchronization device 101 or the TS output by the E-system TS pseudo-synchronization device 101. Then, the TS synthesizers 130, 131 synthesize the input TS from a plurality of consignor stations. The TS synthesizers 130, 131 transmit the synthesized TS to the transmission facility 300.

[0026] The commissioning office 200 is provided with an N-system transmission-side signal processing device (not shown) and an E-system transmission-side signal processing device (not shown). The N-system transmission-side signal processing device and the E-system transmission-side signal processing device generate a TS synchronized with the clock signal supplied within the commissioning office 200 and transmit the TS to the receiving office 100.

[0027] The commissioning office 210 is configured in the same manner as the commissioning office 200. Although two commissioning offices 200 and 210 are shown in FIG. 1, there may be three or more commissioning offices. When there are two or more commissioning offices, the receiving office 100 has an N-system TS pseudo-synchronization device and an E-system TS pseudo-synchronization device corresponding to each commissioning office.

[0028] FIG. 2 is a block diagram showing a configuration example of the general TS synthesizing device 130 shown in FIG. 1. The TS synthesizing device 130 includes a TS multiplexing unit 1301 and an internal SF phase generating unit 1302. The TS synthesizing device 131 shown in FIG. 1 is also configured in the same manner as the TS synthesizing device 130. The arrows in FIG. 2 clearly indicate the direction of the signal (data) flow, but do not exclude bidirectionality. This also applies to other block diagrams.

[0029] The TS multiplexing unit 1301 multiplexes and outputs a plurality of input TSs using the internal SF phase generated by the internal SF phase generating unit 1302.

[0030] The internal SF phase generating unit 1302 inputs the SF phase signal generated by the SF synchronization signal generating device 120 of the receiving office 100. The internal SF phase generating unit 1302 inputs the clock signal generated by the clock signal generating device 110 of the receiving office 100. The internal SF phase generating unit 1302 generates an internal SF phase using the clock signal with the SF phase signal as a reference. That is, the internal SF phase generating unit 1302 synchronizes the internal SF phase with the SF phase generated by the SF synchronization signal generating device 120.

[0031] In the redundant configuration of the general TS synthesizer shown in FIGS. 1 and 2, a reference synchronization configuration is adopted to synchronize the internal SF phases of the two TS synthesizers 130 and 131. In the reference synchronization configuration, the internal SF phases of the two TS synthesizers 130 and 131 are synchronized based on the SF phase generated by the SF synchronization signal generator 120.

[0032] However, the SF synchronization signal generator 120 is not redundantly configured. Therefore, when the SF synchronization signal generator 120 fails, the internal SF phases of the TS synthesizers 130 and 131 may not be synchronized. As a result, depending on the system switching timing of the TS synthesizer, packet duplication or omission of 1 SF may occur, and video noise or audio noise may occur.

[0033] FIG. 3 is a system configuration diagram showing a system including a receiving station and a commissioning station having the redundant configuration TS synthesizer of the present embodiment.

[0034] In the configuration of the present embodiment shown in FIG. 3, unlike the configuration of the receiving station 100 shown in FIG. 1, the SF synchronization signal generator 120 is not provided in the receiving station 100A. Further, the receiving station 100A includes TS synthesizers 140 and 141 instead of the general TS synthesizers 130 and 131 illustrated in FIG. 1.

[0035] FIG. 4 is a block diagram showing a configuration example of the TS synthesizer 140 of the present embodiment. The TS synthesizer 140 includes a TS multiplexing unit 1401, an internal SF phase generation unit 1402, and an internal SF phase setting unit 1403. The TS synthesizer 141 shown in FIG. 3 is also configured in the same manner as the TS synthesizer 140.

[0036] The TS multiplexing unit 1401 multiplexes and outputs a plurality of input TSs using the internal SF phase set by the internal SF phase setting unit 1403.

[0037] The internal SF phase generation unit 1402 receives the clock signal generated by the clock signal generator 110 of the receiving office 100A. The internal SF phase generation unit 1402 generates an internal SF phase using the clock signal. As an example, the internal SF phase generation unit 1402 is implemented by a counter circuit.

[0038] FIG. 5 is an explanatory diagram showing a specific example of the SF phase. In the present embodiment, the SF phase is represented by incrementing the count value of the counter based on the clock signal output from the clock signal generator 110.

[0039] The internal SF phase generation unit 1402 sets the count value to 0 when the TS synthesizer 140 is started. The internal SF phase generation unit 1402 counts up the count value (i.e., adds 1) at a clock timing of, for example, 56.61 MHz. Then, when the count value reaches 626,687, the internal SF phase generation unit 1402 increments the SF number and resets the count value. Thereafter, the internal SF phase generation unit 1402 counts up again from the count value 0. The count value at this time corresponds to the SF phase.

[0040] The internal SF phase setting unit 1403 sets the internal SF phase used in the own device (i.e., the TS synthesizer 140). The internal SF phase setting unit 1403 sets, as the internal SF phase used in the own device, the internal SF phase generated by the TS synthesizer that started first among a plurality of redundant-configured TS synthesizers (e.g., TS synthesizers 140 and 141). The internal SF phase setting unit 1403 may be implemented by hardware (e.g., an electronic circuit, etc.) or a combination of hardware and software (e.g., a combination of an electronic circuit and a program for controlling it, etc.).

[0041] For example, the internal SF phase setting unit 1403 transmits and receives packets in which the count value of the own device is set to / from other TS synthesizers. Also, the internal SF phase setting unit 1403 determines the TS synthesizer that started first based on the count value extracted from the received packet.

[0042] For example, the internal SF phase setting unit 1403 determines that the own device (i.e., the TS synthesizer 140) has started up earlier than other TS synthesizers (i.e., the TS synthesizer 141). In this case, the internal SF phase setting unit 1403 sets the internal SF phase generated by the internal SF phase generation unit 1402 of the own device as the internal SF phase to be used by the own device.

[0043] For example, the internal SF phase setting unit 1403 determines that the own device (i.e., the TS synthesizer 140) has started up at the same time as other TS synthesizers (i.e., the TS synthesizer 141). In this case, the internal SF phase setting unit 1403 sets the internal SF phase generated by the internal SF phase generation unit 1402 of the own device as the internal SF phase to be used by the own device.

[0044] For example, the internal SF phase setting unit 1403 determines that other TS synthesizers (i.e., the TS synthesizer 141) have started up earlier than the own device (i.e., the TS synthesizer 140). In this case, the internal SF phase setting unit 1403 sets the internal SF phase generated by the internal SF phase generation unit 1402 of the other TS synthesizer as the internal SF phase to be used by the own device. That is, the internal SF phase setting unit 1403 synchronizes the internal SF phase of the own device with the internal SF phase generated and used in the other TS synthesizer.

[0045] In the present embodiment, when synchronizing the internal SF phase of the own device with the internal SF phase of the other TS synthesizer, the count value of the own device is synchronized with the count value of the other TS synthesizer. Hereinafter, such an operation is also expressed as pulling in the internal SF phase (or count value) of the other TS synthesizer.

[0046] Next, the operation of the TS synthesizer of this embodiment will be described. FIG. 6 is a flowchart showing an operation example of the TS synthesizer. The TS synthesizer A and the TS synthesizer B shown in FIG. 6 correspond to, for example, the TS synthesizer 140 and the TS synthesizer 141 shown in FIG. 3. This is the same in FIGS. 7 to 9. Although FIG. 6 shows an operation example of the TS synthesizer A (TS synthesizer 140), the TS synthesizer B (TS synthesizer 141) operates in the same manner.

[0047] At startup, the TS synthesizer A transmits a startup packet to the other system's synthesizer B (step S1).

[0048] If the internal SF phase setting unit 1403 of the TS synthesizer A does not receive a startup packet from the TS synthesizer B within a predetermined period (for example, 10 msec, 20 msec, etc.) after transmitting the startup packet (N in step S2), and does not receive a response packet either (N in step S3), the internal SF phase setting unit 1403 determines that the TS synthesizer B has not started up. That is, the internal SF phase setting unit 1403 determines that the TS synthesizer A has started up earlier than the TS synthesizer B. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A sets the internal SF phase generated by the internal SF phase generation unit 1402 of the TS synthesizer A as the internal SF phase to be used in the TS synthesizer A (step S4). After that, the TS synthesizer A operates with the set internal SF phase.

[0049] If the internal SF phase setting unit 1403 of the TS synthesizer A does not receive a startup packet from the TS synthesizer B within a predetermined period (for example, 10 msec, 20 msec, etc.) after transmitting the startup packet (N in step S2), and receives a response packet (Y in step S3), the internal SF phase setting unit 1403 determines that the TS synthesizer B has started up. That is, the internal SF phase setting unit 1403 determines that the TS synthesizer B has started up earlier than the TS synthesizer A. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A pulls in the internal SF phase generated and used by the internal SF phase generation unit 1402 of the TS synthesizer B, and sets it as the internal SF phase to be used in the TS synthesizer A (step S5). After that, the TS synthesizer A operates with the set internal SF phase.

[0050] When the internal SF phase setting unit 1403 of the TS synthesizer A receives a startup packet from the TS synthesizer B within a predetermined period (for example, 10 msec, 20 msec, etc.) from the transmission of the startup packet (Y in step S2), it determines that the TS synthesizer B has started up almost simultaneously with the TS synthesizer A. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A compares the count value of the TS synthesizer A with the count value of the TS synthesizer B (step S6).

[0051] Next, when the count value of the TS synthesizer A is greater than the count value of the TS synthesizer B (Y in step S6), the internal SF phase setting unit 1403 determines that the TS synthesizer A has started up earlier than the TS synthesizer B. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A sets the internal SF phase generated by the internal SF phase generation unit 1402 of the TS synthesizer A as the internal SF phase to be used in the TS synthesizer A (step S7). Thereafter, the TS synthesizer A operates with the set internal SF phase.

[0052] Also, when the count value of the TS synthesizer A is the same as the count value of the TS synthesizer B (Y in step S6), the internal SF phase setting unit 1403 determines that the TS synthesizer A and the TS synthesizer B have started up simultaneously. When the count value of the TS synthesizer A is the same as the count value of the TS synthesizer B, it means that the synchronization of the internal SF phase has already been achieved. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A sets the internal SF phase generated by the internal SF phase generation unit 1402 of the TS synthesizer A as the internal SF phase to be used in the TS synthesizer A (step S7). Thereafter, the TS synthesizer A operates with the set internal SF phase.

[0053] On the other hand, when the count value of the TS synthesizer A is smaller than the count value of the TS synthesizer B (N in step S6), the internal SF phase setting unit 1403 determines that the TS synthesizer B has been started earlier than the TS synthesizer A. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A pulls in the internal SF phase generated and used by the internal SF phase generation unit 1402 of the TS synthesizer B and sets it as the internal SF phase to be used in the TS synthesizer A (step S8). After that, the TS synthesizer A operates with the set internal SF phase.

[0054] FIG. 7 is a timing diagram showing an example of setting the internal SF phase of the TS synthesizer. FIG. 7 shows an example in which the TS synthesizer A is started earlier than the TS synthesizer B.

[0055] In the present embodiment, five types of packets, namely, a startup packet, a response packet, a synchronization packet, a response synchronization packet, and an SF phase packet, are transmitted and received between the TS synthesizers. The startup packet is a packet transmitted to another system's TS synthesizer at startup. The response packet is a packet transmitted as a response when the startup packet is received. The synchronization packet is a packet transmitted when synchronizing the internal SF phase with another system's TS synthesizer. The response synchronization packet is a packet transmitted as a response when the synchronization packet is received. The SF phase packet is a packet transmitted at regular intervals after the internal SF phase is set. All of these packets conform to the packet format of MPEG-2 TS (MPEG-2 Transport Stream) defined in ISO / IEC 13818-1.

[0056] When the TS synthesizer A starts up, it performs clock locking in synchronization with the clock signal supplied from the clock signal generator 110. The internal SF phase generation unit 1402 of the TS synthesizer A generates an internal SF phase when the clock locking is completed.

[0057] Next, the TS synthesizer A (e.g., the internal SF phase setting unit 1403) transmits a startup packet to the TS synthesizer B. At this time, the TS synthesizer B has not yet started up (or the clock lock after startup is not completed). Therefore, the TS synthesizer B cannot transmit a response packet in response to the startup packet.

[0058] Since the internal SF phase setting unit 1403 of the TS synthesizer A does not receive a response packet from the TS synthesizer B within a predetermined period from the transmission of the startup packet, it sets the internal SF phase to the internal SF phase that uses the internal SF phase generated at startup. After that, the TS synthesizer A starts operating using the set internal SF phase. Thereafter, the TS synthesizer A (e.g., the internal SF phase setting unit 1403) transmits an SF phase packet in which its own internal SF phase (count value) is set to the TS synthesizer B at regular intervals.

[0059] Next, the TS synthesizer B whose clock lock after startup is completed transmits a startup packet to the TS synthesizer A. When the TS synthesizer A (e.g., the internal SF phase setting unit 1403) receives the startup packet, it transmits a response packet to the TS synthesizer B. Also, the TS synthesizer A stops transmitting the SF phase packet and prepares to receive a synchronization packet from the TS synthesizer B.

[0060] The synchronization packet and the response synchronization packet transmitted and received between the TS synthesizers include an SF synchronization counter and an SF response synchronization counter. When the internal SF phase setting unit 1403 of the TS synthesizer B receives the response packet, it sets the count value of the TS synthesizer B to the SF synchronization counter of the synchronization packet. Then, the TS synthesizer B (e.g., the internal SF phase setting unit 1403) transmits the synchronization packet to the TS synthesizer A.

[0061] When the internal SF phase setting unit 1403 of the TS synthesizer A receives a synchronization packet, it sets the value of the SF synchronization counter of the synchronization packet to the SF synchronization counter of the response synchronization packet. Also, the internal SF phase setting unit 1403 of the TS synthesizer A sets the count value of the TS synthesizer A to the SF response synchronization counter of the response synchronization packet. Then, the TS synthesizer A transmits the response synchronization packet to the TS synthesizer B. Thereafter, the TS synthesizer A transmits an SF phase packet to the TS synthesizer B at regular intervals. The SF phase packet is used, for example, to determine whether there is a phase shift in the internal SF phase between the TS synthesizers.

[0062] When the internal SF phase setting unit 1403 of the TS synthesizer B receives a response synchronization packet, it sets the count value of the TS synthesizer B based on the value of the SF response synchronization counter included in the response synchronization packet. That is, the internal SF phase setting unit 1403 performs control to pull in the internal SF phase (count value) of the TS synthesizer A. After the TS synthesizer B has pulled in the internal SF phase of the TS synthesizer A, it counts the count value based on the clock signal until the pull-in control is performed again. Note that the pull-in control is executed again when the TS synthesizer is restarted or when the internal SF phase is shifted due to a deviation of the reference clock in both systems. Thereafter, the TS synthesizer B transmits an SF phase packet to the TS synthesizer A at regular intervals.

[0063] FIG. 8 is a timing diagram showing an example of setting the internal SF phase of the TS synthesizer. FIG. 8 shows an example in which the TS synthesizer A and the TS synthesizer B are started up almost simultaneously.

[0064] When the TS synthesizer A and the TS synthesizer B are started up almost simultaneously, they transmit startup packets to each other almost simultaneously. Then, the TS synthesizer A and the TS synthesizer B receive the startup packets within a predetermined period (for example, 10 msec, 20 msec, etc.) from the transmission of the startup packets. In this case, the TS synthesizer A and the TS synthesizer B determine that they have been started up almost simultaneously with the other TS synthesizer.

[0065] When the internal SF phase setting unit 1403 of the TS synthesizer A receives the startup packet within a predetermined period from the transmission of the startup packet, it sets the count value of the TS synthesizer A in the SF synchronization counter of the synchronization packet. Then, the TS synthesizer A transmits the synchronization packet to the TS synthesizer B.

[0066] Similar to the TS synthesizer A, when the internal SF phase setting unit 1403 of the TS synthesizer B receives the startup packet within a predetermined period from the transmission of the startup packet, it sets the count value of the TS synthesizer B in the SF synchronization counter of the synchronization packet. Then, the TS synthesizer B transmits the synchronization packet to the TS synthesizer A.

[0067] Next, when the internal SF phase setting unit 1403 of the TS synthesizer A receives the synchronization packet, it sets the value of the SF synchronization count of the synchronization packet in the SF synchronization counter of the response synchronization packet. Also, the internal SF phase setting unit 1403 of the TS synthesizer A sets the count value of the TS synthesizer A in the SF response synchronization counter of the response synchronization packet. Then, the TS synthesizer A transmits the response synchronization packet to the TS synthesizer B.

[0068] Similar to the TS synthesizer A, when the internal SF phase setting unit 1403 of the TS synthesizer B receives the synchronization packet, it sets the value of the SF synchronization count of the synchronization packet in the SF synchronization counter of the response synchronization packet. Also, the internal SF phase setting unit 1403 of the TS synthesizer B sets the count value of the TS synthesizer B in the SF response synchronization counter of the response synchronization packet. Then, the TS synthesizer B transmits the response synchronization packet to the TS synthesizer A.

[0069] Next, when the internal SF phase setting unit 1403 of the TS synthesizer A receives a response synchronization packet, it compares the count value of the TS synthesizer A with the count value of the TS synthesizer B based on the value of the SF response synchronization counter included in the response synchronization packet. When the count value of the TS synthesizer B is larger than the count value of the TS synthesizer A, the internal SF phase setting unit 1403 of the TS synthesizer A performs control to draw in the internal SF phase (count value) of the TS synthesizer B. On the other hand, when the count value of the TS synthesizer A is larger than the count value of the TS synthesizer B, or when they are equal, the TS synthesizer A uses the internal SF phase generated in the TS synthesizer A as it is.

[0070] Similar to the TS synthesizer A, when the internal SF phase setting unit 1403 of the TS synthesizer B receives a response synchronization packet, it compares the count value of the TS synthesizer B with the count value of the TS synthesizer A based on the value of the SF response synchronization counter included in the response synchronization packet. When the count value of the TS synthesizer A is larger than the count value of the TS synthesizer B, the internal SF phase setting unit 1403 of the TS synthesizer B performs control to draw in the internal SF phase (count value) of the TS synthesizer A. On the other hand, when the count value of the TS synthesizer B is larger than the count value of the TS synthesizer A, or when they are equal, the TS synthesizer B uses the internal SF phase generated in the TS synthesizer B as it is.

[0071] In this embodiment, the TS synthesizer is configured to compare the count value of its own device with the count value of a TS synthesizer of another system and synchronize with the one having the larger count value. However, the TS synthesizer may be configured to compare the count value of its own device with the count value of a TS synthesizer of another system and synchronize with the one having the smaller count value, for example.

[0072] Next, the control for drawing in the internal SF phase from a TS synthesizer of another system will be described. FIG. 9 is an explanatory diagram showing an example of the control for drawing in the internal SF phase from a TS synthesizer of another system. FIG. 9 shows the control in which the TS synthesizer B draws in the internal SF phase (count value) of the TS synthesizer A.

[0073] The TS synthesizer B sets the count value k of the TS synthesizer B in the SF synchronization counter of the synchronization packet. s Then, the TS synthesizer B transmits the synchronization packet to the TS synthesizer A.

[0074] The TS synthesizer A receives the synchronization packet transmitted by the TS synthesizer B. The period from the time when the TS synthesizer B generates the synchronization packet (i.e., the time of the count value k s ) to the time when the TS synthesizer A receives the synchronization packet is defined as the transmission delay t s .

[0075] Next, the TS synthesizer A sets the value of the SF synchronization counter of the synchronization packet (count value k s ) in the SF synchronization counter of the response synchronization packet. Also, the TS synthesizer A sets the count value k of the TS synthesizer A in the SF response synchronization counter of the response synchronization packet a . Then, the TS synthesizer A transmits the response synchronization packet to the TS synthesizer B. The period from the time when the TS synthesizer A receives the synchronization packet to the time when the TS synthesizer A generates the response synchronization packet (i.e., the time of the count value k a ) is defined as the processing delay α.

[0076] The TS synthesizer B receives the response synchronization packet transmitted by the TS synthesizer A. The period from the time when the TS synthesizer A generates the response synchronization packet (i.e., the time of the count value k a ) to the time when the TS synthesizer B receives the response synchronization packet is defined as the transmission delay t a .

[0077] The TS synthesizer B extracts the value of the SF response synchronization counter from the received response synchronization packet. Next, the TS synthesizer B performs control to pull in the internal SF phase of the TS synthesizer A. The period from the time when the TS synthesizer B receives the response synchronization packet to the time when the control to pull in the internal SF phase of the TS synthesizer A starts is defined as the processing delay β. The count value of the TS synthesizer B at the time when the control to pull in the internal SF phase of the TS synthesizer A starts is kb Let it be so.

[0078] The count value of the TS synthesizer A set in the SF response synchronization counter of the response synchronization packet is k s However, the control to pull in the internal SF phase (count value) of the TS synthesizer A in the TS synthesizer B starts after the count value k s is set in the TS synthesizer A, and after passing through the processing delay α, the transmission delay t a , and the processing delay β. Therefore, at the time when the control to pull in the internal SF phase of the TS synthesizer A starts, the count value of the TS synthesizer A is the value counted up from k s .

[0079] Therefore, the TS synthesizer B calculates the count value of the TS synthesizer A at the time when the control to pull in the internal SF phase of the TS synthesizer A starts (hereinafter referred to as the count value K). Then, the TS synthesizer B sets the calculated count value K as its own count value. The count value K is calculated, for example, as follows.

[0080] Assuming that the cable lengths between the TS synthesizers A and B are the same, the value of the transmission delay t s and the value of the transmission delay t a are considered to be the same. Therefore, t = t s = t a Let it be so.

[0081] Let the transmission and reception delay from the time when the startup packet is transmitted to the time when the pull-in control starts be t sa . Then, t sa = t s + α + t a + β = 2t + α + β. Then, t = (t sa - α - β) / 2 is considered.

[0082] Also, the transmission and reception delay t sa is the period from the time when the count value in the TS synthesizer B is k s to the time when it is k b . Therefore, t sa = kb -k s It becomes.

[0083] From the above, the count value K of the TS synthesizer A is calculated as follows. K=k a +t+β =k a +{(t sa -α-β) / 2}+β =k a +{(k b -k s ) / 2}-(α-β) / 2

[0084] Therefore, the count value K is k a ,k b ,k s , α, and β, where α and β are known design values.

[0085] The internal SF phase setting unit 1403 of the TS synthesizer B sets the count value k b and the count value k extracted from the response synchronization packet. s ,k a and the known values ​​of processing delays α and β, the count value K of TS synthesizer A is calculated. Then, the internal SF phase setting unit 1403 of TS synthesizer B sets the calculated count value K as the count value of TS synthesizer B. Through this operation, TS synthesizer B can pull in the internal SF phase of TS synthesizer A.

[0086] As described above, a typical redundant TS synthesizer employs a reference synchronization configuration that uses the SF synchronization signal generator 120. However, the SF synchronization signal generator 120 is not configured redundantly. Therefore, if the SF synchronization signal generator 120 fails, the internal SF phases of the TS synthesizers may not be synchronized.

[0087] In this embodiment, the TS synthesizer 140 and the TS synthesizer 141 are configured to synchronize their internal SF phases with each other. With such a configuration, the process of synchronizing the internal SF phases between the TS synthesizers can be completed. Also, the SF synchronization signal generator 120 that is not redundantly configured can be abolished. As a result, in the receiving station 100A, all devices can be redundantly configured.

[0088] FIG. 10 is a block diagram showing the main part of the TS synthesizer. The TS synthesizer 10 shown in FIG. 10 (which is realized by the TS synthesizers 140 and 141 in the embodiment) is a redundantly configured TS (Transport Stream) synthesizer, and includes generation means 11 (which is realized by the internal SF phase generation unit 1402 in the embodiment) for generating an internal phase (for example, corresponding to the internal SF phase in the embodiment) using a clock signal in the receiving station (corresponding to the receiving station 100A in the embodiment), and setting means 12 (which is realized by the internal SF phase setting unit 1403 in the embodiment) for setting, as the internal phase to be used by its own device, the internal phase generated by the generation means 11 of the TS synthesizer 10 that started up earlier among the plurality of redundantly configured TS synthesizers 10. With such a configuration, the internal SF phases can be synchronized with each other between the TS synthesizers without relying on the SF synchronization signal generator. Also, in the receiving station, all devices can be redundantly configured.

[0089] FIG. 11 is a block diagram showing the main part of a broadcast system. The broadcast system 20 (corresponding to the receiving station 100A) shown in FIG. 11 includes a clock signal generation unit 23 (which is realized by the clock signal generation device 110 in the embodiment) that generates a clock signal, and TS synthesizers 21 and 22 (which are realized by the TS synthesizers 140 and 141 in the embodiment) that perform the synthesis of a TS (Transport Stream). The TS synthesizers 21 and 22 include a generation means 11 (which is realized by the internal SF phase generation unit 1402 in the embodiment) that generates an internal phase (for example, corresponding to the internal SF phase in the embodiment) using the clock signal generated by the clock signal generation unit 23, and a setting means 12 (which is realized by the internal SF phase setting unit 1403 in the embodiment) that sets the internal phase generated by the generation means 11 of the TS synthesizer that started first among the plurality of redundantly configured TS synthesizers 21 and 22 as the internal phase to be used by its own device. With such a configuration, it is possible to synchronize the internal SF phases with each other between the TS synthesizers without relying on the SF synchronization signal generation device. Also, within the receiving station, all devices can be redundantly configured.

[0090] As described above, the present disclosure has been described with reference to the embodiments, but the present disclosure is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. And each embodiment can be combined with other embodiments as appropriate.

[0091] The drawings are merely examples for explaining one or more embodiments. Each drawing may be associated with not only one specific embodiment but also one or more other embodiments. As can be understood by those skilled in the art, various features or steps described with reference to any one drawing can be combined with the features or steps shown in one or more other drawings, for example, to create embodiments that are not explicitly illustrated or described. Not all of the features or steps shown in any one drawing for explaining exemplary embodiments are necessarily essential, and some features or steps may be omitted. The order of the steps described in any drawing may be changed as appropriate.

Explanation of Reference Numerals

[0092] 10, 21, 22, 130, 131, 140, 141 TS synthesizer 11 Generation means 12 Setting means 20 Broadcasting system 23 Clock signal generation unit 100, 100A Trustee station 101, 102 TS pseudo-synchronization device 110 Clock signal generation device 120 SF synchronization signal generation device 200, 210 Consigning station 300 Transmission equipment 1301, 1401 TS multiplexer 1302, 1402 Internal SF phase generation unit 1403 Internal SF setting unit

Claims

1. A redundantly configured TS (Transport Stream) synthesizing device, A generating means for generating an internal phase using a clock signal in a trustee station; In a plurality of TS synthesizers having a redundant configuration, when the own device is started later, the internal phase generated by the generating means of the TS synthesizer of the other system that was started earlier is set as the internal phase to be used in the own device, and when the own device is started earlier, the internal phase generated by the generating means of the own device is set as the internal phase to be used in the own device. A TS synthesis device comprising:

2. When a response is received within a predetermined period of time after a startup packet is transmitted to the TS synthesizer of the other system at startup, the setting means sets the internal phase generated by the generating means of the TS synthesizer of the other system as the internal phase to be used in the own system.

2. The TS synthesis device according to claim 1.

3. The setting means sets the internal phase generated by the generating means of the own device as the internal phase to be used in the own device when a response is not received within a predetermined period of time after a startup packet is transmitted to the TS synthesizer of the other system at startup.

3. The TS synthesizer according to claim 1.

4. The setting means is When the startup packet is received from the TS synthesizer of the other system, a response synchronization packet is transmitted including a count value indicating an internal phase used by the own device; When the response synchronization packet is received, the internal phase used by the device itself is set based on the count value.

3. The TS synthesis device according to claim 2.

5. The setting means, when receiving the startup packet from the TS synthesizer of the other system within a predetermined period after transmitting the startup packet to the TS synthesizer of the other system at startup and then receiving the response synchronization packet, sets an internal phase to be used in the own device based on the larger of the count value of the TS synthesizer of the other system and the count value of the own device.

5. The TS synthesizer according to claim 4.

6. a clock signal generating unit that generates a clock signal; A TS synthesizing device for synthesizing a TS (Transport Stream), The TS synthesis device includes: a generating means for generating an internal phase using the clock signal generated by the clock signal generating unit; In the plurality of TS synthesizers having a redundant configuration, when the own device is started later, the internal phase generated by the generating means of the TS synthesizer of the other system that was started earlier is set as the internal phase to be used in the own device, and when the own device is started earlier, the internal phase generated by the generating means of the own device is set as the internal phase to be used in the own device. A broadcasting system comprising:

7. When a response is received within a predetermined period of time after a startup packet is transmitted to the TS synthesizer of the other system at startup, the setting means sets the internal phase generated by the generating means of the TS synthesizer of the other system as the internal phase to be used in the own system. The broadcasting system according to claim 6.

8. The setting means sets the internal phase generated by the generating means of the own device as the internal phase to be used in the own device when a response is not received within a predetermined period of time after a startup packet is transmitted to the TS synthesizer of the other system at startup.

8. The broadcasting system according to claim 6 or 7.

9. The setting means is When the startup packet is received from the TS synthesizer of the other system, a response synchronization packet is transmitted including a count value indicating an internal phase used by the own device; When the response synchronization packet is received, the internal phase used by the device itself is set based on the count value. The broadcasting system according to claim 7.

10. The setting means, when receiving the startup packet from the TS synthesizer of the other system within a predetermined period after transmitting the startup packet to the TS synthesizer of the other system at startup and then receiving the response synchronization packet, sets an internal phase to be used in the own device based on the larger of the count value of the TS synthesizer of the other system and the count value of the own device. The broadcasting system according to claim 9.

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