Thermal Conductive Slug / Active Die for Improving Cooling of Stacked Bottom Die

Abstract

An embodiment includes a semiconductor package. The semiconductor package includes first and second bottom dies on a package substrate, a plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die. The semiconductor package includes a plurality of thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs comprise a high thermal conductivity material. The plurality of thermally conductive slugs are disposed on outer edges of the top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and / or directly on the top surface of the package substrate. The high thermal conductivity material of the thermally conductive slugs comprises copper, silver, boron nitride, or graphene. The plurality of thermally conductive slugs may have two different thicknesses. The semiconductor package may also include an active die and / or an integrated heat spreader having a pedestal.

Description

Technical Field

[0001] Embodiments relate to packaging semiconductor devices. More specifically, embodiments relate to semiconductor devices having stacked dies, thermal conduction slugs, and / or active dies for improving the cooling of stacked bottom dies.

Background Art

[0002] Over the past few decades, feature scaling in integrated circuits (ICs) has been the driving force behind the ever-growing semiconductor industry. Scaling to ever-smaller features enables increasing the density of functional units on the limited real estate of semiconductor devices. However, the movement to shrink features within an IC, such as a microelectronics package, while optimizing the performance of each device, is not without problems.

[0003] One major problem relates to the thermal management of such packages. For example, the thermal management of microelectronics packages has become extremely important as the power requirements and the number of dies in microelectronics packages steadily increase. These microelectronics packages typically include multiple stacked dies including high-power and high-density bottom dies. Typically, the performance of these microelectronics packages is limited by hot spots at the edges of the bottom dies. This leads to other problems when the high-power density bottom die edges are covered with low-thermal conductivity mold materials.

[0004] Accordingly, existing packaging solutions may attempt to improve the performance of the system cooling solution by covering the bottom die edge with a high thermal conductivity mold material or reducing the thickness of the top die and / or mold layer. However, such existing packaging solutions can substantially increase packaging costs, time, and uncertainties such as leading to other unexpected problems. Also, reducing the top die thickness can slightly lower the hot spot temperature, but reducing the top die thickness does not remove (or mitigate) the actual hot spot generated by the edge of the bottom die.

Brief Description of the Drawings

[0005] The embodiments described herein are shown by way of example and not limitation in the figures of the accompanying drawings. In the drawings, like reference numerals refer to like elements. Also, some conventional details are omitted so as not to obscure the inventive concepts described herein.

Figure 1A

Figure 1B

Figure 1C

Figure 2A

Figure 2B

Figure 2C

Figure 3

[0006] Semiconductor packages having thermal conduction slugs and / or active silicon dies, and methods of forming such semiconductor packages are described herein. The semiconductor packages and methods of forming such semiconductor packages described below may include an integrated heat spreader (IHS), a thermal interface material (TIM), a plurality of top dies, a plurality of bottom dies, a plurality of thermal conduction slugs, and a package substrate. Further, in these embodiments, the semiconductor packages described herein may include an IHS having a plurality of pedestals and / or active dies (e.g., bridge dies, active silicon dies, etc.).

[0007] In these embodiments, the semiconductor package may have a plurality of trenches drilled / laser machined in an encapsulation layer that surrounds (or embeds) the bottom die. Those trenches may be positioned (or placed) over the edge of the bottom die. Thus, in some embodiments, the trenches can expose the top surface of the upper end of the bottom die, and subsequently, a thermal conduction slug can be placed directly over the exposed top surface of the bottom die within the drilled trenches, whereby the thermal conduction slug can be positioned directly over the upper end of the bottom die and on the top surface of the package substrate. Further, in these embodiments, an active die may be placed in one of the trenches together with the thermal conduction slug, and the active die can be positioned directly over the exposed top surfaces of both bottom dies. The active die can be a bridge (or bridge die) that can communicatively couple the stacks of the bottom die and the top die to each other. In some alternative embodiments, the pedestal of the IHS may be placed directly over the exposed top surface of the bottom die within the drilled trenches, whereby the pedestal of the IHS can be positioned directly over the top surface of the upper end of the bottom die.

[0008] The embodiments described herein provide improvements over existing packaging solutions by substantially increasing the thermal design power (TDP) capabilities of the semiconductor packages described herein. Further, these embodiments also enable removal of hot spots generated by high-power and high-density bottom dies, thereby enabling a significant reduction in the overall temperature of the semiconductor package without the need to reduce the thickness (or z-height) of the top die. The embodiments described herein also improve the packaging solution by implementing trenches in a single via process (or the like) without additional cost, where the trenches can be disposed (or filled therewith) with a thermal conduction slug (or the like). Thus, in these embodiments, the thermal resistance from the upper end of the bottom die to the IHS is significantly reduced by the thermal conduction slug, the active die, and / or the high thermal conductivity material of the pedestal of the IHS (e.g., copper, silicon, and the like).

[0009] The technology described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technology described herein include, for example, microelectromechanical systems (MEMS)-based electromechanical systems, gyroscopes, advanced driver assistance systems (ADAS), 5G communication systems, cameras, mobile phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosk terminals, netbook computers, notebook computers, Internet devices, payment terminals, personal digital assistants, media players and / or recorders, servers (e.g., blade servers, rack-mounted servers, combinations thereof, etc.), set-top boxes, smartphones, tablet personal computers, ultra-mobile personal computers, landline telephones, combinations thereof, and the like, including any type of mobile device and / or stationary device. Such devices may be portable or stationary. In some embodiments, the technology described herein may be used in desktop computers, laptop computers, smartphones, tablet computers, netbook computers, notebook computers, personal digital assistants, servers, combinations thereof, and the like. More generally, the technology described herein may be used in any of a variety of electronic devices, including semiconductor packages having an IHS, an IHS with a pedestal, a top die, a bottom die, a thermal conduction slug, an active die (or bridge die), and a package substrate with an embedded bridge die.

[0010] In the following description, various aspects of the exemplary implementation are described using terms commonly used by those skilled in the art to convey the content of their work to other skilled artisans. However, it will be apparent to those skilled in the art that the present embodiment may be implemented using only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are described to provide a complete understanding of the exemplary implementation. However, it will be apparent to those skilled in the art that the present embodiment may be implemented without such specific details. Also, well-known mechanisms are omitted or simplified so as not to obscure the exemplary implementation.

[0011] Various processes will be described in turn as a plurality of individual processes in the most useful way for understanding the present embodiment, but the order of description should not be construed as meaning that those processes are necessarily order-dependent. In particular, those processes do not need to be performed in the presented order.

[0012] As used herein, when the terms "top", "bottom", "upper", "lower", "lowest", and "uppermost" are used in relation to one or more elements, they are intended to convey a relative physical configuration rather than an absolute physical configuration. Thus, an element described as the "uppermost element" or "top element" within a device may, when the device is turned over, instead form the "lowest element" or "bottom element" within the device. Similarly, an element described as the "lowest element" or "bottom element" within a device may, when the device is turned over, instead form the "uppermost element" or "top element" within the device.

[0013] Next, referring to FIG. 1A, a cross-sectional view of a semiconductor package 100 according to one embodiment is shown. In some embodiments, the semiconductor package 100 may include, according to one embodiment, an IHS 120, a plurality of top dies 110a - 110b, a plurality of bottom dies 121a - 121b, a TIM 140, a plurality of thermal conduction slugs 141a - 141b, an encapsulation layer 180, and a package substrate 103. In one embodiment, the bottom dies 121a - 121b (or the first dies) may be disposed and bonded to the top surface of the package substrate 103 using an adhesive layer 123 (or the like). In one embodiment, the top dies 110a - 110b (or the second dies) may be respectively disposed and bonded on the bottom dies 121a - 121b.

[0014] In some embodiments, the bottom dies 121a - 121b may include a plurality of interconnects 131 that couple the package substrate 103 to the respective top dies 110a - 110b. In these embodiments, the interconnects 131 may be through - silicon vias (TSVs), through - glass vias (TGVs), and / or the like. In some embodiments, as described above, the semiconductor package 100 may include a plurality of trenches 138 (or cavities) disposed within the encapsulation layer 180 surrounding the thermal conduction slugs 141a - 141b. In one embodiment, the thermal conduction slugs 141a - 141b may be positioned directly on the top surfaces of the bottom dies 121a - 121b. Similarly, in these embodiments, the thermal conduction slugs 141a - 141b may be positioned adjacent to the top dies 110a - 110b and separated from each other by the encapsulation layer 180.

[0015] In particular, as shown in FIG. 1A, the thermal conduction slugs 141a-b are positioned directly on the top surfaces of the outer upper ends of the bottom dies 121a-b to remove the formation of hot spots on these outer upper ends of the bottom dies 121a-b. In some embodiments, the thermal conduction slugs 141a-141b can be directly and thermally coupled to the outer upper ends of the bottom dies 121a-121b, the TIM 140, and the IHS 120. In one embodiment, the IHS 120 can be disposed on top of the top dies 110a-110b, and the IHS 120 can be coupled to the top dies 110a-110b using the TIM 140. In one embodiment, the IHS 120 can be a heat sink or the like, and the heat sink can be a single shared heat sink or two separate heat sinks.

[0016] In one embodiment, a bridge 150 may be disposed within the package substrate 103, and the bridge 150 can communicatively couple the bottom die 121a to the bottom die 121b. In one embodiment, the bridge 150 can have an electrical routing (or interconnect structure) that can communicatively couple the bottom die 121a to the bottom die 121b. In one embodiment, the bridge 150 can be a silicon bridge, a glass bridge, or a bridge made of another substrate material suitable for bridge formation. In some embodiments, the bridge 150 can be referred to as an embedded multi-die interconnect bridge (EMIB). In a further embodiment, the bridge 150 can include a plurality of TSVs that can be used to communicatively couple the bottom dies 121a-121b to each other.

[0017] In one embodiment, the encapsulation layer 180 can be disposed to cover the bottom dies 121a - 121b, and the encapsulation layer 180 also surrounds the top dies 110a - 110b and the thermal conduction slugs 141a - 141b. Further, as shown in FIG. 1A, the encapsulation layer 180 can be disposed between the top dies 110a - 110b, and the encapsulation layer 180 can be disposed between the top surface of the bottom dies 121a - 121b and the bottom surface of the TIM 140. In one embodiment, the encapsulation layer 180 can be planarized such that the top surface of the encapsulation layer 180 can be substantially coplanar with the top surfaces of the top dies 110a - 110b.

[0018] Note that according to some embodiments, the semiconductor package 100 is merely an example of one embodiment of a semiconductor package system. That is, the semiconductor package 100 is not limited to the illustrated semiconductor package system, and thus can be designed / formed using fewer, alternative, or additional packaging components, and / or different interconnect structures. For example, although one package substrate 103 is illustrated with one IHS 120, one TIM 140, two thermal conduction slugs 141a, one thermal conduction slug 141b, two bottom dies 121a - 121b, two sets of top dies 110a - 110b, and one bridge 150, it should be understood that the semiconductor package 100 can include any number of package substrates 103 with sets of IHS 120, TIM 140, thermal conduction slugs 141a - 141b, bottom dies 121a - 121b, top dies 110a - 110b, and bridges 150.

[0019] In one embodiment, semiconductor package 100 may include a ball grid array (BGA) package, a land grid array (LGA) package, and / or a pin grid array (PGA) package. In other embodiments, one or more of bottom dies 121a - 121b, top dies 110a - 110b, and / or package substrate 103 may be coupled via solder balls (or the like) that can be implemented as solder bumps / joints formed from respective micro - bumps. The solder balls (or joints) formed by soldering of micro - bumps according to one embodiment may themselves be referred to as “bumps” and / or “micro - bumps”. Further, in other embodiments, one or more of top dies 110a - 110b, bottom dies 121a - 121b, and package substrate 103 may be coupled using an anisotropic conductive film (ACF) or the like.

[0020] Package substrate 103 may include various electronics structures formed thereon or therein. In certain embodiments, package substrate 103 may be an organic substrate composed of one or more layers of a polymer - based material or a ceramic - based material with conductive regions for transmitting signals. In some embodiments, package substrate 103 may include, but is not limited to, a package, a substrate, a printed circuit board (PCB), and a motherboard. In one embodiment, package substrate 103 is a PCB. In one embodiment, the PCB is made of an FR - 4 glass epoxy substrate with thin copper foils laminated on both sides. In certain embodiments, a multilayer PCB made by fabricating additional layers using prepreg and copper foil can be used. For example, the multilayer PCB can include one or more dielectric layers, which can be photosensitive dielectric layers. In one embodiment, the PCB can also include one or more conductive layers, which can further include copper (or metal) traces, lines, pads, vias, holes, and / or planes.

[0021] In one embodiment, the bottom dies 121a-b and the top dies 110a-b can have, but are not limited to, semiconductor dies, electronic devices (e.g., wireless devices), integrated circuits (ICs), central processing units (CPUs), graphics processing units (GPUs), microprocessors, platform controller hubs (PCHs), memories (e.g., high bandwidth memories (HBM)), and / or field programmable gate arrays (FPGAs). Further, in other embodiments, the bottom dies 121a-121b can be composed of one or more materials including glass, crystal, diamond, low thermal conductivity materials, high thermal conductivity materials (e.g., gallium nitride (GaN), etc.), silicon, glass-based materials, and / or silicon-based materials (e.g., silicon carbide (SiC), etc.). As described above, in some embodiments, the top dies 110a-110b can be a plurality of chiplet dies. On the other hand, in another embodiment, the top die 110a and / or the top die 110b can be a single monolithic die instead of a plurality of chiplet dies. The bottom dies 121a-121b and the top dies 110a-110b can be formed from a material such as silicon, for example, and can have circuits that will be coupled to the package substrate 103 and / or to each other. In this regard, some embodiments, but not limited to, the package substrate 103 can then be coupled to another mechanism, such as, for example, a computer motherboard (or the like).

[0022] In one embodiment, bottom die 121a may have a thickness substantially equal to that of bottom die 121b. In one embodiment, bottom dies 121a - 121b may have a thickness of about 100 μm or less. In some embodiments, top die 110a may have a thickness substantially equal to that of top die 110b. In one embodiment, top dies 110a - 110b may have a thickness of about 200 μm - 600 μm. In some embodiments, top dies 110a - 110b may have a thickness substantially equal to that of bottom dies 121a - 121b, or may have a different thickness. In one embodiment, top dies 110a - 110b may have a top surface substantially coplanar with the top surface of encapsulation layer 180. Note that in some embodiments, the thickness of TIM 140 disposed to cover top die 110a may be substantially equal to or different from the thickness of TIM 140 disposed to cover top die 110b. In one embodiment, TIM 140 may have a thickness of about 25 μm - 400 μm.

[0023] One or more connections between package substrate 103, top dies 110a - 110b, and bottom dies 121a - 121b may include one or more interconnect structures and, if desired, an underfill layer. In some embodiments, these interconnect structures (or connections) may variously have alloys of nickel, palladium, and tin (and, in some embodiments, copper). In one embodiment, the underfill layer may be one or more polymeric materials injected between the respective components. Alternatively, the underfill layer may be a molded underfill (MUF) or the like.

[0024] In one embodiment, the encapsulation layer 180 may completely and / or partially surround the outer walls of the top dies 110a - 110b and / or the thermal conduction slugs 141a - 141b. For example, in one embodiment, the encapsulation layer 180 may completely surround the thermal conduction slug 141b, but the encapsulation layer 180 may also be disposed between the outer wall of the top die 110 and the thermal conduction slug 141a. Note that in an alternative embodiment, the encapsulation layer 180 may be implemented to partially or completely surround the bottom dies 121a - 121b. In some embodiments, the encapsulation layer 180 may include one or more encapsulation materials such as, for example, molding materials, underfill materials, filling materials, any similar materials, and / or any combination thereof.

[0025] Furthermore, as described above, the thermal conduction slugs 141a - 141b may be directly disposed on the outer upper ends of the bottom dies 121a - 121b. Also, in these embodiments, one of the thermal conduction slugs 141a can be disposed on one of the bottom dies 121a - 121b and the package substrate 103 (e.g., as shown by the two left - right thermal conduction slugs 141a), and the thermal conduction slug 141b can be directly positioned on both of the bottom dies 121a - 121b (e.g., as shown by the central thermal conduction slug 141b). Thus, in these embodiments, as shown in FIG. 1A, the thermal conduction slugs 141a - 141b can have the same width or different widths based on the desired packaging design.

[0026] According to some embodiments, the thermal conduction slugs 141a - 141b may have copper or the like. Similarly, in some embodiments, the thermal conduction slugs 141a - 141b may have one or more high - thermal - conductivity materials including, but not limited to, for example, copper, silver, boron nitride, graphene, and / or the like. For example, in these embodiments, the thermal conduction slugs 141a - 141b may have a high thermal conductivity of about 400 W / mK or more.

[0027] In some embodiments, the thermal conduction slugs 141a-141b can have one or more thicknesses, and the thermal conduction slug 141a can have a first thickness while the thermal conduction slug 141b can have a second thickness. For example, the first thickness of the thermal conduction slug 141a can be greater than the second thickness of the thermal conduction slug 141b, where the first thickness of the thermal conduction slug 141a can be defined from the top surface of the package substrate 103 to the bottom surface of the TIM 140, and the second thickness of the thermal conduction slug 141b can be defined from the top surface of the bottom die 121a-b to the bottom surface of the TIM 140.

[0028] In these embodiments, the first thickness of the thermal conduction slug 141a can be about 400 μm - 1000 μm. In another embodiment, the first thickness of the thermal conduction slug 141a can be about 1000 μm or less. In some embodiments, the second thickness of the thermal conduction slug 141b can be about 200 μm - 600 μm. In another embodiment, the second thickness of the thermal conduction slug 141b can be about 600 μm or less.

[0029] Also, as shown in FIG. 1A, the thermal conduction slug 141a can be shaped as a thermal conduction block region with pedestals (or legs). In these embodiments, the thermal conduction slug 141a can have two different thicknesses, and the thermal conduction block region of the thermal conduction slug 141a can be directly disposed and bonded on the outer upper end of the bottom dies 121a - 121b, and the pedestals of the thermal conduction slug 141a can be directly disposed and bonded on the top surface of the package substrate 103. That is, in these embodiments, the thermal conduction block region of the thermal conduction slug 141a can have a thickness substantially equal to the second thickness of the thermal conduction slug 141b (e.g., a thickness of about 200 μm - 600 μm), and the thermal conduction pedestals of the thermal conduction slug 141a can have a thickness substantially equal to the first thickness of the thermal conduction slug 141a (e.g., a thickness of about 400 μm - 1000 μm). Note that, as shown in FIG. 1A, a slight gap may be provided between the pedestals of the thermal conduction slug 141a and the outer walls of the bottom dies 121a - 121b. Further, in some embodiments, the thermal conduction block region of the thermal conduction slug 141a, the thermal conduction slug 141b, and / or the trench 138 can have one or more side walls shaped as tapered side walls and / or substantially vertical side walls.

[0030] Furthermore, the TIM 140 can be directly disposed and bonded on the top surfaces of the top dies 110a - 110b, the encapsulation layer 180, and / or the thermal conduction slugs 141a - 141b, and the TIM 140 can be positioned between the top surface of the top dies 110a - 110b and the bottom surface of the IHS 120. In one embodiment, the TIM 140 can be a solder TIM (STIM), such as indium STIM or the like. In other embodiments, the TIM 140 can include one or more highly thermally conductive materials, such as, for example, a metal TIM, STIM, polymer TIM (PTIM), and / or similar highly thermally conductive (one or more) materials. The TIM 140 can be a two - split / separated TIM or a single / shared TIM based on the desired packaging design.

[0031] In one embodiment, the IHS 120 may be arranged with the TIM 140, the top dies 110a - 110b, the bottom dies 121a - 121b, and the package substrate 103. The IHS 120 can be manufactured (or shaped) to include a lid and / or a plurality of legs (or pedestals), the lid of the IHS 120 can be placed directly on the top surface of the TIM 140, and the legs of the IHS 120 can be placed directly on the top surface of the package substrate 103. In some embodiments, the IHS 120 can be a heat sink, a heat spreader, a heat exchanger, a manifold, a cold plate, and / or any similar heat solution (or device) that can be used to help transfer heat from the electrical components of the semiconductor package 100 to the ambient environment (or a further heat spreader). In some embodiments, the IHS 120 can be a shared heat sink placed on both of the top dies 110a - 110b, or alternatively, the IHS 120 can be a split heat sink separated into two separate heat sinks placed individually on only the top die 110a and only the top die 110b.

[0032] Note that the semiconductor package 100 of FIG. 1A may include fewer or additional packaging components based on the desired packaging design.

[0033] Next, referring to FIG. 1B, a cross-sectional view of a semiconductor package 101 according to one embodiment is shown. In some embodiments, the semiconductor package 101 can be substantially the same as the semiconductor package 100 described above in FIG. 1A, except that: an active die 151 can be disposed on the upper ends inside both of the bottom dies 121a - 121b, and thus the active die 151 can replace the thermal conduction slug 141b and the bridge 150 in FIG. 1A. That is, while the bridge 150 is embedded in the package substrate 103 of FIG. 1A, the active die 151 can be disposed and bonded on the upper ends inside both of the bottom dies 121a - 121b. According to some embodiments, the active die 151 can be implemented to communicatively couple the stack of the top die 110a and the bottom die 121a to the stack of the top die 110b and the bottom die 121b without the need for an embedded bridge in the package substrate 103.

[0034] In these embodiments, the active die 151 can be an active silicon die or the like. As shown in FIG. 1B, the active die 151 can be surrounded (or embedded) by the encapsulation layer 180, the TIM 140, and the bottom dies 121a - 121b, and the active die 151 can be positioned directly between the top die 110a and the top die 110b. In one embodiment, the active die 151 can have a top surface that is substantially in the same plane as the top surfaces of the top dies 110a - 110b, and the active die 151 can have a thickness that is substantially equal to the thickness of the top dies 110a - 110b (for example, the thickness can be about 200μm - 600μm). Also, in some embodiments, the active die 151 can have a width of about 1 mm to 4 mm. In another embodiment, the active die 151 can have a width of about 4 mm or less.

[0035] In particular, in these embodiments, the active die 151 can be a bridge (or bridge die). In one embodiment, the active die 151 can have an electrical routing (or interconnect structure) that communicatively couples the bottom die 121a to the bottom die 121b. In one embodiment, the active die 151 can be a bridge made of silicon bridge, glass bridge, or other substrate material suitable for bridge formation. In some embodiments, the active die 151 can be referred to as EMIB. In a further embodiment, the active die 151 can include a plurality of TSVs that can be used to communicatively couple the bottom dies 121a - 121b and / or the top dies 110a - 110b.

[0036] Note that the semiconductor package 101 of FIG. 1B can include fewer or additional packaging components based on the desired packaging design.

[0037] Next, referring to FIG. 1C, a cross-sectional view of a semiconductor package 102 according to one embodiment is shown. In some embodiments, the semiconductor package 102 can be substantially the same as the semiconductor package 100 described above with respect to FIG. 1A, except that the IHS 120 can include a plurality of pedestals 120a - 120b, and the pedestals 120a - 120b of the IHS 120 can replace the thermal conduction slugs 140a - 140b of FIG. 1A. That is, in FIG. 1A, the thermal conduction slugs 141a - 141b are disposed and coupled on the top surfaces of the bottom dies 121a - 121b, but according to some embodiments, the pedestals 120a - 120b of the IHS 120 can be disposed on the top surfaces of the bottom dies 121a - 121b and directly coupled, and the pedestals 120a - 120b can be part of the IHS 120 and / or directly coupled to the bottom surface of the IHS 120.

[0038] In these embodiments, the pedestals 120a-120b can be implemented as a plurality of legs on the IHS 120, and the pedestals 120a-120b can have the same thermal conductive material as the IHS 120. As shown in FIG. 1C, the pedestals 120a-120b can be surrounded (or embedded) by the encapsulation layer 180, the TIM 140, and the bottom dies 121a-121b, and the pedestals 120a-120b can be positioned directly between the top surfaces of the bottom dies 121a-121b and the bottom surface of the IHS 120. In one embodiment, the pedestals 120a-b of the IHS 120 can have a thickness of about 300 μm - 900 μm. In another embodiment, the pedestals 120a-b of the IHS 120 can have a thickness of about 900 μm or less. In these embodiments, the pedestals 120a-120b of the IHS 120 can have a thickness greater than (or equal to) the thickness of the top dies 110a-110b.

[0039] Also, in some embodiments, the pedestal 120b (or the second pedestal) can have a width of about 1 mm to 4 mm. In another embodiment, the pedestal 120b can have a width of about 4 mm or less. In these embodiments, the pedestal 120b can have a width greater than the width of the pedestal 120a (or the plurality of first pedestals). In some embodiments, the pedestals 120a-120b can have one or more sidewalls shaped as tapered sidewalls and / or substantially vertical sidewalls. In an alternative embodiment, the pedestal 120b can be replaced with an active die similar to the active die 151 described above in FIG. 1B.

[0040] Note that the semiconductor package 102 of FIG. 1C can include fewer or additional packaging components based on the desired packaging design.

[0041] Figures 2A-2C are cross-sectional views of a semiconductor package 200 according to some embodiments. In some embodiments, as shown in FIGS. 2A-2C, the semiconductor package 200 may include an IHS 220, a TIM 240, a encapsulation layer 280, a plurality of trenches 238, a plurality of thermal conduction slugs 241a-241b, a plurality of top dies 210a-210b, a plurality of bottom dies 221a-221b, a plurality of interconnects 231, an adhesive layer 223, a bridge 250, and a package substrate 203. In these embodiments, the semiconductor package 200 of FIGS. 2A-2C having the thermal conduction slugs 241a-b may be substantially similar to the semiconductor package 100 having the thermal conduction slugs 141a-141b described above in FIG. 1A.

[0042] Similarly, the components of the semiconductor package 200 may be substantially similar to the components of the semiconductor package 100 described above in FIG. 1A. Accordingly, the IHS 220, the TIM 240, the encapsulation layer 280, the trenches 238, the top dies 210a-210b, the bottom dies 221a-221b, the interconnects 231, the adhesive layer 223, the bridge 250, and the package substrate 203 may be substantially similar to the IHS 120, the TIM 140, the encapsulation layer 180, the trenches 138, the top dies 110a-110b, the bottom dies 121a-121b, the interconnects 131, the adhesive layer 123, the bridge 150, and the package substrate 103 described above in FIG. 1A.

[0043] Next, referring to FIG. 2A, a cross-sectional view of a semiconductor package 200 according to one embodiment is shown. In some embodiments, the semiconductor package 200 can include top dies 210a-210b and bottom dies 221a-221b stacked on a package substrate 203 respectively, and the bottom dies 221a-221b can be coupled to the package substrate 203 with an adhesive layer 223. An encapsulation layer 280 can be disposed over the top surfaces of the bottom dies 221a-221b and can surround the top dies 210a-210b, and in particular, the encapsulation layer 280 can be disposed over the outer upper ends of the bottom dies 221a-221b. In some embodiments, the top surface of the encapsulation layer 280 can be planarized by a polishing / grinding process (or the like), and thus can be substantially coplanar with the top surfaces of the top dies 210a-210b.

[0044] Next, referring to FIG. 2B, a cross-sectional view of a semiconductor package 200 according to one embodiment is shown. In some embodiments, the semiconductor package 200 can implement a trench 238 in the encapsulation layer 280, and the trench 238 can expose the top surfaces of the bottom dies 221a-221b. In one embodiment, the trench 238 can be implemented by a drilling process, a laser process, or the like, and the drilled / laser processed trench can have tapered sidewalls or substantially vertical sidewalls. As described above, the trench 238 can provide an opening over the upper ends of the bottom dies 221a-221b.

[0045] Next, referring to FIG. 2C, a cross-sectional view of a semiconductor package 200 according to one embodiment is shown. In some embodiments, a plating process (or the like) can be used to dispose (or deposit / plate) thermal conduction slugs 241a-241b in trenches 238 such that the thermal conduction slugs 241a-241b are mounted directly on the upper ends of respective bottom dies 221a-221b. In these embodiments, a TIM 240 can then be disposed covering the thermal conduction slugs 241a-241b, the encapsulation layer 280, and the top dies 210a-210b. Finally, as shown in FIG. 2C, an IHS 220 can be disposed on the TIM 240 and the package substrate 203, such that the thermal conduction slugs 241a-241b create a low thermal resistance path from the upper ends of the bottom dies 221a-221b to the TIM 240 and the IHS 220, and thus can substantially improve the TDP of the semiconductor package 200. Also, in alternative embodiments, the semiconductor package 200 may be implemented with one or more pedestals (e.g., pedestals 120a-120b of FIG. 1C) of an active die (e.g., active die 151 of FIG. 1B) and / or the IHS 220.

[0046] Note that the semiconductor package 200 of FIGS. 2A-2C can include fewer or additional packaging components based on a desired packaging design.

[0047] FIG. 3 shows a schematic block diagram of a computer system 300 that utilizes a device package 310 (or semiconductor package) having an IHS, TIM, a plurality of top dies, a plurality of bottom dies, a plurality of thermal conduction slugs, a plurality of pedestals of the IHS, an active die, and / or a package substrate according to one embodiment. FIG. 3 shows an example of a computing device 300. The computing device 300 houses a motherboard 302. The motherboard 302 can include a number of components including, but not limited to, a processor 304, a device package 310 (or semiconductor package), and at least one communication chip 306. The processor 304 is physically and electrically coupled to the motherboard 302. In some embodiments, at least one communication chip 306 is also physically and electrically coupled to the motherboard 302. In other embodiments, at least one communication chip 306 is part of the processor 304.

[0048] Depending on its use, the computing device 300 can include other components, which may or may not be physically and electrically coupled to the motherboard 302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive), a compact disc (CD), a digital versatile disc (DVD), and the like.

[0049] At least one communication chip 306 may enable wireless communication for the transmission of data to and from the computing device 300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data via a non-solid medium using modulated electromagnetic radiation. This term does not mean that the associated device does not include any wires (in some embodiments, it may not include any wires). At least one communication chip 306 may implement any of a number of wireless standards or protocols. Those standards or protocols include, but are not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth®, derivatives thereof, and other wireless protocols designated as 3G, 4G, 5G, and beyond. The computing device 300 may include multiple communication chips 306. For example, a first communication chip 306 may be used for shorter-range wireless communication, such as Wi-Fi and / or Bluetooth®, and a second communication chip 306 may be used for longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and / or others.

[0050] The processor 304 of the computing device 300 includes an integrated circuit die packaged within the processor 304. The device package 310 can be a semiconductor package that can include, but is not limited to, a substrate, a package substrate, and / or a PCB. In one embodiment, the device package 310 can be substantially similar to the semiconductor packages 100 - 102 and 200 of FIGS. 1A - 1C and 2A - 2C described herein. The device package 310 can include a thermal conduction slug (and / or an active die, an IHS pedestal, etc.) directly disposed and bonded on the top surface of the bottom die and / or the package substrate, as described herein (e.g., as illustrated and described with respect to the thermal conduction slug, active die, and / or IHS pedestal of FIGS. 1A - 1C and 2A - 2C), or any other component from the figures described herein.

[0051] Note that when materials, mechanisms, and components can be limited to the device package 310 and / or any other component of the computing device 300 that may require the thermal conduction slug (and / or an active die, an IHS pedestal, etc.) described herein (e.g., the motherboard 302, the processor 304, and / or any other component of the computing device 300 that may require the embodiments of the semiconductor packages described herein), the device package 310 can be a single component / device, a subset of multiple components, and / or the entire system.

[0052] In certain embodiments, the integrated circuit die can be packaged with one or more devices on a package substrate that includes a thermally stable RFIC and antenna and a device package for use with wireless communication, as described herein, to reduce the z - height of the computing device. The term "processor" can mean any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0053] At least one communication chip 306 also includes an integrated circuit die packaged within the communication chip 306. In some embodiments, the integrated circuit die of the communication chip 306 can be packaged together with one or more devices on a package substrate that includes one or more device packages as described herein.

[0054] In the foregoing specification, embodiments have been described with reference to their specific exemplary embodiments. However, it should be noted that all of these and similar terms are associated with appropriate physical quantities and are merely convenient labels attached to those quantities. It will become apparent that various changes can be made to them without departing from the broader spirit and scope. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a limiting sense.

[0055] The following examples relate to further embodiments. The various mechanisms of the different embodiments can be variously combined by including some mechanisms and excluding other parts so as to be suitable for various different applications.

[0056] The following examples relate to further embodiments.

[0057] Example 1 is a semiconductor package, and the semiconductor package includes a first bottom die and a second bottom die on a package substrate, with the first bottom die adjacent to the second bottom die, the first bottom die and the second bottom die, a plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die, and a plurality of heat conduction slugs on the first bottom die and the second bottom die, the plurality of heat conduction slugs having a high heat conduction material, the plurality of heat conduction slugs including a plurality of first heat conduction slugs and a second heat conduction slug, and an encapsulation layer on the first and second bottom dies, an encapsulation layer surrounding the plurality of first top dies, the plurality of second top dies, and the second heat conduction slug, and a TIM covering the plurality of first top dies, the plurality of second top dies, the plurality of heat conduction slugs, and the encapsulation layer.

[0058] In Example 2, the matters according to Example 1 may optionally include that the plurality of first heat conduction slugs are directly disposed on the top surface of the package substrate, the plurality of first heat conduction slugs are also directly disposed on the outer ends of the top surface of the first bottom die and the outer ends of the top surface of the second bottom die, and the second heat conduction slug is directly disposed on the inner ends of the top surface of the first bottom die and the inner ends of the top surface of the second bottom die. The semiconductor package according to Example 1.

[0059] In Example 3, the matters according to Examples 1 - 2 may optionally include that the plurality of heat conduction slugs have a top surface substantially in the same plane as the top surface of the encapsulation layer and the top surfaces of the plurality of first and second top dies.

[0060] In Example 4, the matters according to Examples 1 - 3 may optionally include that the high heat conduction material of the plurality of heat conduction slugs includes copper, silver, boron nitride, or graphene.

[0061] In Example 5, the matters according to Examples 1-4 can optionally include that the plurality of first heat conduction slugs have a first thickness greater than the second thickness of the second heat conduction slug.

[0062] In Example 6, the matters according to Examples 1-5 can optionally include that the second thickness of the second heat conduction slug is substantially equal to the thicknesses of the plurality of first and second top dies.

[0063] In Example 7, the matters according to Examples 1-6 can optionally include that the top surface of the first bottom die is substantially coplanar with the top surface of the second bottom die, the plurality of first heat conduction slugs are shaped as a plurality of heat conduction block regions with a plurality of pedestals, the plurality of heat conduction block regions of the plurality of first heat conduction slugs have a third thickness substantially equal to the second thickness of the second heat conduction slug, the first thickness of the plurality of first heat conduction slugs is greater than the third thickness of the plurality of first heat conduction slugs, the plurality of heat conduction block regions of the plurality of first heat conduction slugs are directly coupled on the outer ends of the top surfaces of the first and second bottom dies, the plurality of pedestals of the plurality of first heat conduction slugs are directly coupled on the top surface of the package substrate, the encapsulation layer is directly on the top surfaces of the first and second bottom dies, and the plurality of first heat conduction slugs are separated from the plurality of first and second top dies by the encapsulation layer.

[0064] In Example 8, the matters according to Examples 1-7 are, optionally, bridges within the package substrate, the bridges communicatively coupling the first bottom die to the second bottom die, the first and second bottom dies including a plurality of interconnects, the plurality of interconnects of the first and second bottom dies communicatively coupling the package substrate to the plurality of first and second top dies, a bonding layer bonding the package substrate to the first and second bottom dies, an IHS on the TIM, the plurality of thermal conduction slugs, and the package substrate, the plurality of thermal conduction slugs thermally coupling the top surfaces of the first and second bottom dies to the IHS, and the TIM being located between the bottom surface of the IHS and the top surfaces of the first and second top dies, the plurality of thermal conduction slugs, and the encapsulation layer.

[0065] In Example 9, the matters according to Examples 1-8 are, optionally, the plurality of pedestals of the plurality of first thermal conduction slugs being spaced from the first and second bottom dies by a slight gap, and the plurality of thermal conduction slugs having tapered sidewalls or substantially vertical sidewalls. It can be. The semiconductor package according to Example 8.

[0066] Example 10 is a semiconductor package, and the semiconductor package includes a first bottom die and a second bottom die on a package substrate, with the first bottom die adjacent to the second bottom die, the first bottom die and the second bottom die, a plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die, a plurality of heat conduction slugs on the first bottom die and the second bottom die, the plurality of heat conduction slugs having a high thermal conductivity material, active dies on the first bottom die and the second bottom die, an active die communicatively coupling the first bottom die to the second bottom die, an encapsulation layer on the first and second bottom dies, the encapsulation layer surrounding the plurality of first top dies, the plurality of second top dies, and the active die, and a TIM covering the plurality of first top dies, the plurality of second top dies, the plurality of heat conduction slugs, the active die, and the encapsulation layer.

[0067] In Example 11, the matters according to Example 10 can optionally include that the plurality of heat conduction slugs are directly disposed on the top surface of the package substrate, the plurality of heat conduction slugs are also directly disposed on the outer ends of the top surface of the first bottom die and the outer ends of the top surface of the second bottom die, and the active die is directly disposed on the inner ends of the top surface of the first bottom die and the inner ends of the top surface of the second bottom die.

[0068] In Example 12, the matters according to Examples 10 - 11 can optionally include that the plurality of heat conduction slugs have a top surface substantially in the same plane as the top surface of the encapsulation layer and the top surfaces of the plurality of first and second top dies, and the active die has a top surface substantially in the same plane as the top surface of the plurality of heat conduction slugs, the plurality of first and second top dies, and the encapsulation layer.

[0069] In Example 13, the matters related to Examples 10-12 can optionally include that the high thermal conductivity material of the plurality of thermal conduction slugs has copper, silver, boron nitride, or graphene, and the active die is an active silicon die or an EMIB die.

[0070] In Example 14, the matters related to Examples 10-13 can optionally include that the plurality of thermal conduction slugs have a first thickness that is greater than the second thickness of the active die.

[0071] In Example 15, the matters related to Examples 10-14 can optionally include that the second thickness of the active die is substantially equal to the thicknesses of the plurality of first and second top dies.

[0072] In Example 16, the matters related to Examples 10-15 can optionally include that the top surface of the first bottom die is substantially in the same plane as the top surface of the second bottom die, the plurality of thermal conduction slugs are shaped as a plurality of thermal conduction block regions with a plurality of pedestals, the plurality of thermal conduction block regions of the plurality of thermal conduction slugs have a third thickness that is substantially equal to the second thickness of the active die, the first thickness of the plurality of thermal conduction slugs is greater than the third thickness of the plurality of thermal conduction slugs, the plurality of thermal conduction block regions of the plurality of thermal conduction slugs are directly coupled on the outer ends of the top surfaces of the first and second bottom dies, the plurality of pedestals of the plurality of thermal conduction slugs are directly coupled on the top surface of the package substrate, the encapsulation layer is directly on the top surfaces of the first and second bottom dies, and the plurality of thermal conduction slugs are separated from the plurality of first and second top dies by the encapsulation layer.

[0073] In Example 17, the matters related to Examples 10 - 16 are, optionally, a plurality of interconnects within the first and second bottom dies, and the plurality of interconnects of the first and second bottom dies are a plurality of interconnects that communicably couple the package substrate to the plurality of first and second top dies, an adhesive layer that couples the package substrate to the first and second bottom dies, the TIM, the plurality of thermal conduction slugs, the active die, and an integrated heat spreader (IHS) on the package substrate, wherein the plurality of thermal conduction slugs thermally couple the top surfaces of the first and second bottom dies to the IHS, and the TIM is an IHS that is positioned between the bottom surface of the IHS and the top surfaces of the first and second top dies, the plurality of thermal conduction slugs, the active die, and the encapsulation layer, and can include the same.

[0074] In Example 18, the matters related to Examples 10 - 17 are, optionally, the plurality of pedestals of the plurality of thermal conduction slugs are spaced from the first and second bottom dies by a slight gap, and the plurality of thermal conduction slugs can include having tapered sidewalls or substantially vertical sidewalls. The semiconductor package according to Example 17.

[0075] Example 19 is a semiconductor package, the semiconductor package including a first bottom die and a second bottom die on a package substrate, the first bottom die adjacent to the second bottom die, the package substrate including a bridge that communicably couples the first bottom die to the second bottom die, the first bottom die and the second bottom die, a plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die, an encapsulation layer on the first and second bottom dies, a TIM that covers the plurality of first top dies, the plurality of second top dies, and the encapsulation layer. An IHS having a plurality of pedestals on the TIM, the first and second bottom dies, and the package substrate, wherein the plurality of pedestals of the IHS are on the first bottom die and the second bottom die, the plurality of pedestals of the IHS have a high thermal conductivity material, the pedestals of the IHS include a plurality of first pedestals and the second pedestal, and the encapsulation layer surrounds the plurality of first top dies, the plurality of second top dies, and the pedestals of the IHS.

[0076] In Example 20, the matters according to Example 19 can optionally include that the plurality of first pedestals are directly disposed on the outer ends of the top surface of the first bottom die and the outer ends of the top surface of the second bottom die, and the second pedestal is directly disposed on the inner ends of the top surface of the first bottom die and the inner ends of the top surface of the second bottom die.

[0077] In Example 21, the matters according to Examples 19 - 20 can optionally include that the encapsulation layer has a top surface substantially coplanar with the top surfaces of the plurality of first and second top dies, the pedestals of the IHS have a thickness greater than the thickness of the plurality of first and second top dies, and the plurality of first pedestals have a first width greater than a second width of the second pedestal.

[0078] In Example 22, optionally, for the matters related to Examples 19-21, the high thermal conductivity material of the pedestal of the IHS has copper, silver, boron nitride, or graphene, the first and second bottom dies include a plurality of interconnects, the plurality of interconnects of the first and second bottom dies communicatively couple the package substrate to the plurality of first and second top dies, the package substrate is bonded to the first and second bottom dies with an adhesive layer, the plurality of pedestals of the IHS are thermally bonded to the top surfaces of the first and second bottom dies, and the TIM can be located between the bottom surface of the IHS, the first and second top dies, and the top surface of the encapsulation layer.

[0079] In Example 23, optionally, for the matters related to Examples 19-22, the second pedestal of the IHS can be surrounded by the encapsulation layer and the TIM.

[0080] In Example 24, optionally, for the matters related to Examples 19-23, the top surface of the first bottom die is substantially in the same plane as the top surface of the second bottom die, the encapsulation layer is directly on the top surfaces of the first and second bottom dies, and the plurality of first pedestals of the IHS are separated from the plurality of first and second top dies by the encapsulation layer.

[0081] In Example 25, optionally, for the matters related to Examples 19-24, the pedestals of the IHS can have tapered sidewalls or substantially vertical sidewalls.

[0082] In the foregoing specification, methods and apparatuses have been described with reference to specific exemplary embodiments thereof. Obviously, various changes can be made to them without departing from their broader spirit and scope. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a limiting sense.

Claims

1. A first bottom die and a second bottom die on a package substrate, wherein the first bottom die is adjacent to the second bottom die, the first bottom die and the second bottom die, and A plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die, and A plurality of heat conduction slugs on the first bottom die and the second bottom die, the plurality of heat conduction slugs having a high heat conduction material, the plurality of heat conduction slugs including a plurality of first heat conduction slugs and a second heat conduction slug, a plurality of heat conduction slugs, and An encapsulation layer on the first and second bottom dies, an encapsulation layer surrounding the plurality of first top dies, the plurality of second top dies, and the second heat conduction slug, and A thermal interface material (TIM) covering the plurality of first top dies, the plurality of second top dies, the plurality of heat conduction slugs, and the encapsulation layer, and having, Each of the plurality of first heat conduction slugs is directly disposed on the top surface of the package substrate and directly disposed on an outer end of the top surface of the first bottom die or an outer end of the top surface of the second bottom die. The second heat conduction slug is not disposed on the top surface of the package substrate and is directly disposed on an inner end of the top surface of the first bottom die and an inner end of the top surface of the second bottom die. A semiconductor package.

2. The semiconductor package according to claim 1, wherein the plurality of heat conduction slugs have a top surface substantially coplanar with the top surface of the encapsulation layer and the top surfaces of the plurality of first and second top dies.

3. The semiconductor package according to claim 1 or 2, wherein the plurality of first heat conduction slugs have a first thickness greater than a second thickness of the second heat conduction slug.

4. The semiconductor package according to claim 3, wherein the second thickness of the second heat conduction slug is substantially equal to the thicknesses of the plurality of first and second top dies.

5. The top surface of the first bottom die is substantially in the same plane as the top surface of the second bottom die, the plurality of first heat conduction slugs are shaped as a plurality of heat conduction block regions having a plurality of pedestals, the plurality of heat conduction block regions of the plurality of first heat conduction slugs have a third thickness substantially equal to the second thickness of the second heat conduction slug, the first thickness of the plurality of first heat conduction slugs is greater than the third thickness of the plurality of first heat conduction slugs, the plurality of heat conduction block regions of the plurality of first heat conduction slugs are directly coupled on the outer ends of the top surfaces of the first and second bottom dies, the plurality of pedestals of the plurality of first heat conduction slugs are directly coupled on the top surface of the package substrate, the encapsulation layer is directly on the top surfaces of the first and second bottom dies, and the plurality of first heat conduction slugs are separated from the plurality of first and second top dies by the encapsulation layer. The semiconductor package according to claim 3 or 4.

6. The semiconductor package according to claim 5, wherein the plurality of pedestals of the plurality of first heat conduction slugs are separated from the first and second bottom dies by only a slight gap, and the plurality of heat conduction slugs have tapered side walls or substantially vertical side walls.

7. A bridge within the package substrate, the bridge communicatively coupling the first bottom die to the second bottom die, the first and second bottom dies including a plurality of interconnects, and the plurality of interconnects of the first and second bottom dies communicatively coupling the package substrate to the plurality of first and second top dies. A bridge, An adhesive layer that couples the package substrate to the first and second bottom dies, The TIM, the plurality of thermal conduction slugs, and an integrated heat spreader (IHS) on the package substrate, wherein the plurality of thermal conduction slugs thermally couple the top surfaces of the first and second bottom dies to the IHS, and the TIM is located between the bottom surface of the IHS and the top surfaces of the first and second top dies, the plurality of thermal conduction slugs, and the encapsulation layer, an IHS The semiconductor package according to any one of claims 1 to 6, further comprising

8. The semiconductor package according to any one of claims 1 to 7, wherein the high thermal conductivity material of the plurality of thermal conduction slugs comprises copper, silver, boron nitride, or graphene.

9. Each of the plurality of thermal conduction slugs is a plating layer. The semiconductor package according to any one of claims 1 to 7.

10. A first bottom die and a second bottom die on a package substrate, wherein the first bottom die is adjacent to the second bottom die, the first bottom die and the second bottom die A plurality of first top dies on the first bottom die and a plurality of second top dies on the second bottom die A plurality of thermal conduction slugs on the first bottom die and the second bottom die, the plurality of thermal conduction slugs having a high thermal conductivity material Active dies on the first bottom die and the second bottom die, the active dies communicatively coupling the first bottom die to the second bottom die An encapsulation layer on the first and second bottom dies, the encapsulation layer surrounding the plurality of first top dies, the plurality of second top dies, and the active dies A thermal interface material (TIM) covering the plurality of first top dies, the plurality of second top dies, the plurality of thermal conduction slugs, the active dies, and the encapsulation layer A semiconductor package having

11. The plurality of thermal conduction slugs are directly disposed on the top surface of the package substrate, and the plurality of thermal conduction slugs are also directly disposed on the outer ends of the top surface of the first bottom die and the outer ends of the top surface of the second bottom die. The active die is directly disposed on the inner ends of the top surface of the first bottom die and the inner ends of the top surface of the second bottom die. The semiconductor package according to claim 10.

12. The plurality of thermal conduction slugs have a top surface that is substantially coplanar with the top surface of the encapsulation layer and the top surfaces of the plurality of first and second top dies. The active die has a top surface that is substantially coplanar with the top surfaces of the plurality of thermal conduction slugs, the plurality of first and second top dies, and the encapsulation layer. The semiconductor package according to claim 11.

13. The plurality of thermal conduction slugs have a first thickness that is greater than a second thickness of the active die. The semiconductor package according to claim 12.

14. The second thickness of the active die is substantially equal to the thicknesses of the plurality of first and second top dies. The semiconductor package according to claim 13.

15. The top surface of the first bottom die is substantially coplanar with the top surface of the second bottom die. The plurality of heat conduction slugs are shaped as a plurality of heat conduction block regions each having a plurality of pedestals. The plurality of heat conduction block regions of the plurality of heat conduction slugs have a third thickness substantially equal to the second thickness of the active die. The first thickness of the plurality of heat conduction slugs is greater than the third thickness of the plurality of heat conduction slugs. The plurality of heat conduction block regions of the plurality of heat conduction slugs are directly bonded onto the outer ends of the top surfaces of the first and second bottom dies. The plurality of pedestals of the plurality of heat conduction slugs are directly bonded onto the top surface of the package substrate. The encapsulation layer is directly on the top surfaces of the first and second bottom dies. The plurality of heat conduction slugs are separated from the plurality of first and second top dies by the encapsulation layer. The semiconductor package according to claim 13 or 14.

16. The plurality of pedestals of the plurality of heat conduction slugs are separated from the first and second bottom dies by only a slight gap. The plurality of heat conduction slugs have tapered side walls or substantially vertical side walls. The semiconductor package according to claim 15.

17. A plurality of interconnects within the first and second bottom dies, the plurality of interconnects of the first and second bottom dies communicatively coupling the package substrate to the plurality of first and second top dies, and An adhesive layer bonding the package substrate to the first and second bottom dies, and An integrated heat spreader (IHS) on the TIM, the plurality of heat conduction slugs, the active die, and the package substrate, the plurality of heat conduction slugs thermally bonding the top surfaces of the first and second bottom dies to the IHS, the TIM being located between the bottom surface of the IHS and the top surfaces of the first and second top dies, the plurality of heat conduction slugs, the active die, and the encapsulation layer. The semiconductor package according to any one of claims 11 to 16, further having . **Claim 18** The high thermal conductivity material of the plurality of thermal conduction slugs has copper, silver, boron nitride, or graphene, and the active die is an active silicon die or an embedded multi-die interconnect bridge (EMIB) die. The semiconductor package according to any one of claims 10 to 17. **Claim 19** A first bottom die and a second bottom die on a package substrate, the first bottom die adjacent to the second bottom die, the package substrate including a bridge communicatively coupling the first bottom die to the second bottom die, the first bottom die and the second bottom die, and A plurality of first top dies on the first bottom die and a plurality of second top dies on the second bottom die, and An encapsulation layer on the first and second bottom dies, and A thermal interface material (TIM) covering the plurality of first top dies, the plurality of second top dies, and the encapsulation layer, and An integrated heat spreader (IHS) integrally formed on the TIM, the first and second bottom dies, and the package substrate, the IHS having a plurality of pedestals disposed on the first bottom die and the second bottom die, the IHS having a high thermal conductivity material, the pedestals of the IHS including a plurality of first pedestals and a second pedestal, the plurality of first pedestals being disposed directly on outer ends of a top surface of the first bottom die and outer ends of a top surface of the second bottom die, the second pedestal being disposed directly on inner ends of the top surface of the first bottom die and inner ends of the top surface of the second bottom die, and the encapsulation layer surrounding the plurality of first top dies, the plurality of second top dies, and the second pedestal of the IHS. The IHS and A semiconductor package having . **Claim 20** The encapsulation layer has a top surface that is substantially coplanar with the top surfaces of the plurality of first and second top dies, the pedestal of the IHS has a thickness greater than the thicknesses of the plurality of first and second top dies, and the plurality of first pedestals have a first width greater than a second width of the second pedestal. The semiconductor package according to claim 19.

21. The high thermal conductivity material of the IHS includes copper, silver, boron nitride, or graphene. The first and second bottom dies include a plurality of interconnects. The plurality of interconnects of the first and second bottom dies communicatively couple the package substrate to the plurality of first and second top dies. The package substrate is bonded to the first and second bottom dies by an adhesive layer. The plurality of pedestals of the IHS are thermally bonded to the top surfaces of the first and second bottom dies. The TIM is located between the bottom surface of the IHS, the first and second top dies, and the top surface of the encapsulation layer. The semiconductor package according to claim 19 or 20.

22. The second pedestal of the IHS is surrounded by the encapsulation layer and the TIM. The semiconductor package according to any one of claims 19 to 21.

23. The top surface of the first bottom die is substantially coplanar with the top surface of the second bottom die. The encapsulation layer is directly on the top surfaces of the first and second bottom dies. The plurality of first pedestals of the IHS are separated from the plurality of first and second top dies by the encapsulation layer. The semiconductor package according to any one of claims 19 to 22.

24. The pedestals of the IHS have tapered sidewalls or substantially vertical sidewalls. The semiconductor package according to any one of claims 19 to 23.

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