Indicating device

Abstract

To provide a display device that has improved transmittance in an area in which a camera or sensor is disposed.SOLUTION: A display device 100 comprises: a substrate including a non-display area NDA and a display area DA which includes an optical area DA1 containing a light-emitting area and a transmissive area, and a general area NA surrounding the optical area; a planarization layer disposed on the substrate in the display area; a plurality of light-emitting elements disposed on the planarization layer and including an anode, a light-emitting layer, and a cathode; a bank disposed on the planarization layer to cover an end of the anode; and a deposition-suppressing layer disposed on the light-emitting layer in the transmissive area among the light-emitting area and the transmissive area of the optical area. The bank is disposed in the light-emitting area among the light-emitting area and the transmissive area of the optical area.SELECTED DRAWING: Figure 1a

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, to a display device capable of preventing the lifting of a film laminated in an area where a camera or a sensor is disposed.

Background Art

[0002] With the advent of the information age, the field of display devices that visually display electrical information signals has been rapidly developing, and research has continued to develop performance such as thinning, weight reduction, and low power consumption for various display devices.

[0003] Typical display devices include a liquid crystal display (LCD), a field emission display (FED), an electro-wetting display (EWD), and an organic light emitting display (OLED).

[0004] The field emission display typified by the organic light emitting display is a self-luminous display device, and unlike the liquid crystal display, it does not require a separate light source and can be manufactured in a lightweight and thin form. In addition, the field emission display is not only advantageous in terms of power consumption by low voltage driving, but also excellent in hue reproduction, response speed, viewing angle, and contrast ratio (CR), and is expected to be utilized in various fields.

[0005] In recent years, the multimedia functions of mobile terminals have been improving. For example, a camera or a sensor is basically built into the front of the display device. However, the camera or sensor arranged on the front of the display device limits the screen design and makes the screen design difficult. In order to reduce the space occupied by the camera or sensor on the front of the display device, a design including a notch or a punch hole has been adopted for the display device, but the size of the screen is still limited by the camera or sensor, and it is difficult to implement a full-screen display.

[0006] In order to implement a full-screen display, a scheme has been proposed in which an area where low-resolution pixels are arranged is provided within the screen of the display device, and a camera and / or various sensors are arranged in the area where the low-resolution pixels are arranged.

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] The problem to be solved in one embodiment of this specification is to provide a display device with improved transmittance in the area where a camera or a sensor is arranged.

[0008] The problem to be solved in another embodiment of this specification is to provide a display device that can prevent the lifting of the laminated film in the area where a camera or a sensor is arranged.

[0009] The problem to be solved in still another embodiment of this specification is to provide a display device that can prevent the pixel shrinkage phenomenon of the light-emitting part due to the outgassing of organic substances caused by the transmission of UV light during the evaluation of UV reliability in the area where a camera or a sensor is arranged.

[0010] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problem

[0011] The display device according to an embodiment of the present specification includes a substrate including a display area and a non-display area including an optical area including a light-emitting area and a transmissive area and a general area surrounding the optical area, a planarization layer disposed on the substrate in the display area, a plurality of light-emitting elements disposed on the planarization layer and including an anode, a light-emitting layer, and a cathode, a bank disposed on the planarization layer so as to cover the end of the anode, and an antireflection layer disposed on the light-emitting layer in the transmissive area of the light-emitting area and the transmissive area in the optical area, and the bank is disposed in the light-emitting area of the light-emitting area and the transmissive area in the optical area.

[0012] Specific matters of other embodiments are included in the detailed description and the drawings.

[0013] In the display device according to an embodiment of the present specification, a camera or a sensor is disposed at the lower end of a light-emitting element or a touch electrode in the display area, so that the display or touch above it does not need to be interrupted.

[0014] In the display device according to an embodiment of the present specification, an antireflection layer is disposed in an area overlapping with the area where the camera or the sensor is disposed, and then a metal electrode is vapor-deposited, so that a transmissive area where an opaque component such as a metal electrode is not disposed can be positioned on the antireflection layer. Thereby, the light transmittance in the area where the camera or the sensor is disposed can be improved, and the visual sensitivity of the display device can be improved.

[0015] The effects according to the present specification are not limited to the contents exemplified above, and more various effects are included in the present specification.

Brief Description of the Drawings

[0016]

Figure 1a

Figure 1b

Figure 1c

Figure 1d

Figure 2

Figure 3

Figure 4

Figure 5a

Figure 5b

Figure 6

Figure 7

Figure 8a

Figure 8b

Figure 9

Figure 10a

Figure 10b

Figure 11

Figure 12

Best Mode for Carrying Out the Invention

[0017] The advantages and features of this specification, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, and can be embodied in various different forms. Merely, these embodiments are provided so that the disclosure of this specification becomes complete, and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of one embodiment of this specification.

[0018] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so the embodiments of this specification are not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining one embodiment of this specification, if it is determined that a detailed description of related known technologies may muddy the gist of one embodiment of this specification, that detailed description will be omitted. When terms such as "including", "having", "being made" are used in this specification, as long as "only" is not used, other parts can be added. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0019] When interpreting components, even without separate explicit description, they are interpreted as including an error range.

[0020] When it is an explanation of the positional relationship, for example, when the positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., as long as "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0021] An element or layer being referred to as "on" another element or layer includes both the case where there is another layer or another element immediately above the other element or intervening therebetween.

[0022] Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0023] Throughout the specification, the same reference numerals refer to the same components.

[0024] The area and thickness of each configuration shown in the drawings are shown for convenience of explanation, and one embodiment of this specification is not necessarily limited to the area and thickness of the shown configuration.

[0025] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various technical linkages and drives, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0026] Hereinafter, with reference to the drawings, one embodiment of this specification will be described.

[0027] FIGS. 1a to 1d are schematic plan views of a display device according to one embodiment of this specification.

[0028] Referring to FIGS. 1a to 1d, a display device 100 according to one embodiment of this specification can include a display panel DP for displaying an image and one or more optoelectronic devices 170, 170a, 170b. The optoelectronic devices 170, 170a, 170b can include light-receiving devices that receive light, such as cameras or sensors.

[0029] The display panel DP is a panel for displaying an image to the user.

[0030] The display panel DP can include a display element for displaying an image, a driving element for driving the display element, and wirings for transmitting various signals to the display element and the driving element. The display element can be differently defined depending on the type of the display panel DP. For example, when the display panel DP is an organic light-emitting display panel, the display element may be an organic light-emitting element including an anode, a light-emitting layer, and a cathode. For example, when the display panel DP is a liquid crystal display panel, the display element may be a liquid crystal display element.

[0031] In the following, it is assumed that the display panel DP is an organic light-emitting display panel, but the display panel DP is not limited to an organic light-emitting display panel.

[0032] On the other hand, the display panel DP can be configured to include a substrate, and a number of insulating films, a transistor layer, a light-emitting element layer, etc. on the substrate. The display panel DP can include a number of sub-pixels and various signal lines for driving the number of sub-pixels for image display. The signal lines can include a number of data lines, a number of gate lines, a number of power supply lines, etc. At this time, each of the number of sub-pixels can include a transistor located in the transistor layer and a light-emitting element located in the light-emitting element layer.

[0033] The display panel DP can include a display area DA and a non-display area NDA.

[0034] The display area DA is an area where an image is displayed on the display panel DP.

[0035] In the display area DA, a number of sub-pixels that make up a number of pixels and a circuit for driving the number of sub-pixels can be arranged. The number of sub-pixels is the minimum unit that constitutes the display area DA. A display element can be arranged for each of the number of sub-pixels, and the number of sub-pixels can constitute a pixel. For example, an organic light-emitting element including an anode, a light-emitting layer, and a cathode can be arranged for each of the number of sub-pixels, but it is not limited thereto. In addition, the circuit for driving the number of sub-pixels may include driving elements, wirings, and the like. For example, the circuit may be composed of a thin-film transistor, a storage capacitor, a gate line, a data line, etc., but it is not limited thereto.

[0036] The non-display area NDA is an area where an image is not displayed.

[0037] The non-display area NDA can be bent so as not to be visible from the front or hidden by a case (not shown), and is also referred to as a bezel area.

[0038] In FIGS. 1a to 1d, the non-display area NDA is shown as surrounding the rectangular display area DA, but the form and arrangement of the display area DA and the non-display area NDA are not limited to the examples shown in FIGS. 1a to 1d. That is, the display area DA and the non-display area NDA may be in a form suitable for the design of an electronic device equipped with the flexible display device 100. For example, exemplary forms of the display area DA may be pentagonal, hexagonal, circular, elliptical, etc.

[0039] In the non-display area NDA, various wirings and circuits for driving the organic light-emitting elements of the display area DA can be arranged. For example, in the non-display area NDA, link wirings for transmitting signals to a number of sub-pixels and circuits in the display area DA, GIP (Gate-In-Panel) wirings, or driving ICs such as a gate driver IC and a data driver IC can be arranged, but it is not limited thereto.

[0040] The display device 100 may further include various additional elements for generating various signals or driving the pixels in the display area DA. The additional elements for driving the pixels may include an inverter circuit, a multiplexer, an Electro Static Discharge (ESD) circuit, etc. The display device 100 may also include additional elements related to functions other than driving the pixels. For example, the display device 100 may further include additional elements for providing a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, a tactile feedback function, etc. The aforementioned additional elements may be located in the non-display area NDA and / or an external circuit connected to the connection interface.

[0041] Referring to FIGS. 1a to 1d, the display area DA may include, but is not limited to, a first optical area DA1 and a second optical area DA2.

[0042] In FIGS. 1a to 1d, one or more optoelectronic devices 170, 170a, 170b are electronic components located under the display panel DP (opposite the viewing surface).

[0043] Light may be incident on the front surface (viewing surface) of the display panel DP, pass through the display panel DP, and be transmitted to one or more optoelectronic devices 170, 170a, 170b located under the display panel DP (opposite the viewing surface).

[0044] One or more optoelectronic devices 170, 170a, 170b may be devices that receive the light transmitted through the display panel DP and perform functions determined by the received light.

[0045] For example, the optoelectronic devices 170, 170a, 170b may include one or more of a camera or a proximity sensor.

[0046] As described above, the optoelectronic devices 170, 170a, 170b are devices that require light reception and can be located below the display panel DP. That is, the optoelectronic devices 170, 170a, 170b can be located on the opposite side of the viewing surface of the display panel DP. The optoelectronic devices 170, 170a, 170b are not exposed on the front surface of the flexible display device 100. Therefore, when the user views the front surface of the flexible display device 100, the optoelectronic devices 170, 170a, 170b cannot be seen.

[0047] As an example, the camera located below the display panel DP is a front camera that captures the front surface and can also be seen through the camera lens.

[0048] The optoelectronic devices 170, 170a, 170b can be arranged to overlap with the display area DA of the display panel DP. That is, the optoelectronic devices 170, 170a, 170b can be located within the display area DA.

[0049] Referring to FIGS. 1a to 1d, the display area DA can include a general area NA and one or more optical areas DA1, DA2.

[0050] One or more optical areas DA1, DA2 may be areas that overlap with one or more optoelectronic devices 170, 170a, 170b.

[0051] According to the example of FIG. 1a, the display area DA can include a general area NA and a first optical area DA1. Here, at least a part of the first optical area DA1 can overlap with the first optoelectronic device 170.

[0052] Although FIG. 1a shows a structure in which the first optical area DA1 is circular, the shape of the first optical area DA1 according to the embodiments of this specification is not limited thereto.

[0053] For example, as shown in FIG. 1b, the shape of the first optical area DA1 can be octagonal, and in addition, it can be made into various polygonal shapes.

[0054] According to the illustration of FIG. 1c, the display area DA can include a general area NA, a first optical area DA1, and a second optical area DA2. In the illustration of FIG. 1c, a general area NA may exist between the first optical area DA1 and the second optical area DA2. Here, at least a part of the first optical area DA1 can be superimposed on the first optoelectronic device 170a, and at least a part of the second optical area DA2 can be superimposed on the second optoelectronic device 170b.

[0055] According to the illustration of FIG. 1d, the display area DA can include a general area NA, a first optical area DA1, and a second optical area DA2. In the illustration of FIG. 1d, there is no general area NA between the first optical area DA1 and the second optical area DA2. That is, the first optical area DA1 and the second optical area DA2 can be in contact with each other. Here, at least a part of the first optical area DA1 can be superimposed on the first optoelectronic device 170a, and at least a part of the second optical area DA2 can be superimposed on the second optoelectronic device 170b.

[0056] One or more of the optical areas DA1, DA2 must have both an image display structure and a light transmission structure formed. That is, since one or more of the optical areas DA1, DA2 are part of the display area DA, sub-pixels for image display must be arranged in one or more of the optical areas DA1, DA2. A light transmission structure for transmitting light to one or more of the optoelectronic devices 170, 170a, 170b must be formed in one or more of the optical areas DA1, DA2.

[0057] One or more of the optoelectronic devices 170, 170a, 170b are devices that require light reception, but are located on the back (below, opposite the viewing surface) of the display panel DP to receive light transmitted through the display panel DP.

[0058] One or more of the optoelectronic devices 170, 170a, 170b are not exposed on the front (viewing surface) of the display panel DP. Therefore, when the user looks at the front of the flexible display device 100, the optoelectronic devices 170, 170a, 170b are not visible to the user.

[0059] For example, the first optoelectronic devices 170, 170a may be cameras, and the second optoelectronic device 170b may be a sensing sensor such as a proximity sensor or an illuminance sensor. For example, the sensing sensor may be an infrared sensor that senses infrared rays.

[0060] Conversely, the first optoelectronic devices 170, 170a may be sensing sensors, and the second optoelectronic device 170b may be a camera.

[0061] In the following, for the sake of convenience of explanation, an example will be given in which the first optoelectronic devices 170, 170a are cameras and the second optoelectronic device 170b is a sensing sensor. Here, the camera may be a camera lens or an image sensor.

[0062] When the first optoelectronic devices 170, 170a are cameras, this camera is located behind (below) the display panel DP, but may be a front camera that shoots in the front direction of the display panel DP. Therefore, the user can take a picture through a camera that is not visible on the viewing surface while looking at the viewing surface of the display panel DP.

[0063] The general area NA and the one or more optical areas DA1, DA2 included in the display area DA are areas where video display is possible. However, the general area NA is an area where a light transmission structure does not need to be formed, and the one or more optical areas DA1, DA2 are areas where a light transmission structure must be formed.

[0064] Therefore, the one or more optical areas DA1, DA2 must have a transmittance of a certain level or higher, and the general area NA may not have light transmissivity or may have a low transmittance below a certain level.

[0065] For example, the one or more optical areas DA1, DA2 and the general area NA may differ from each other in terms of resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure.

[0066] For example, the number of sub-pixels per unit area in one or more optical regions DA1, DA2 may be smaller than the number of sub-pixels per unit area in the general region NA. That is, the resolution of one or more optical regions DA1, DA2 may be lower than the resolution of the general region NA. At this time, the number of sub-pixels per unit area is a unit for measuring resolution, and can also be said to be PPI (Pixels Per Inch), which means the number of pixels within 1 inch.

[0067] For example, the number of sub-pixels per unit area in the first optical region DA1 may be smaller than the number of sub-pixels per unit area in the general region NA. The number of sub-pixels per unit area in the second optical region DA2 may be equal to or greater than the number of sub-pixels per unit area in the first optical region DA1.

[0068] The first optical region DA1 may have various patterns such as circular, elliptical, square, hexagonal, or octagonal. The second optical region DA2 may have various patterns such as circular, elliptical, square, hexagonal, or octagonal. The first optical region DA1 and the second optical region DA2 may have the same pattern or different patterns.

[0069] Referring to FIG. 1c, when the first optical region DA1 and the second optical region DA2 are in contact, the overall optical region including the first optical region DA1 and the second optical region DA2 may also have various patterns such as circular, elliptical, square, hexagonal, or octagonal.

[0070] In the following, for the sake of convenience of explanation, it is assumed that each of the first optical region DA1 and the second optical region DA2 is circular.

[0071] In the flexible display device 100 according to an embodiment of the present specification, when the first optoelectronic devices 170, 170a hidden under the display panel DP without being exposed to the outside are cameras, the flexible display device 100 according to the embodiment of the present specification can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0072] According to this, in the case of the flexible display device 100 according to the embodiment of the present specification, since a notch or a camera hole for camera exposure is not formed in the display panel DP, a reduction in the area of the display area DA does not occur.

[0073] As a result, a notch or a camera hole for camera exposure may not be formed in the display panel DP, so that the size of the bezel area can be reduced, there are no design constraints, and the degree of freedom in design can be increased.

[0074] In the flexible display device 100 according to an embodiment of the present specification, although one or more optoelectronic devices 170, 170a, 170b are hidden and located behind the display panel DP, the one or more optoelectronic devices 170, 170a, 170b must be able to receive light normally and perform the defined functions normally.

[0075] Also, in the flexible display device 100 according to an embodiment of the present specification, although one or more optoelectronic devices 170, 170a, 170b are hidden and located behind the display panel DP and are located so as to overlap the display area DA, normal video display must be possible in one or more optical areas DA1, DA2 that overlap the one or more optoelectronic devices 170, 170a, 170b in the display area DA.

[0076] Therefore, the flexible display device 100 according to an embodiment of the present specification may have a structure capable of improving the transmittance of the first optical area DA1 and the second optical area DA2 that overlap the optoelectronic devices 170, 170a, 170b.

[0077] FIG. 2 is a system configuration diagram of a display device according to an embodiment of the present specification.

[0078] Referring to FIG. 2, the display device 100 may include a display panel DP and a display driving circuit as components for video display.

[0079] The display driving circuit is a circuit for driving the display panel DP, and may include a data driving circuit DDC, a gate driving circuit GDC, a display controller DCTR, and the like.

[0080] The display panel DP can include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The non-display area NDA may be an outer area of the display area DA, and can also be referred to as a bezel area. All or part of the non-display area NDA may be an area visible on the front surface of the display device 100, or may be an area that is bent and not visible on the front surface of the display device 100.

[0081] The display panel DP can include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. Further, the display panel DP can further include various types of signal lines in order to drive the plurality of sub-pixels SP.

[0082] The display device 100 according to an embodiment of the present specification may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel DP emits light by itself. When the display device 100 according to the embodiment of the present specification is a self-emitting display device, each of the plurality of sub-pixels SP can include a light-emitting element.

[0083] For example, the display device 100 according to the embodiment of the present specification may be an organic light-emitting display device in which the light-emitting element is embodied as an organic light-emitting diode (OLED). As another example, the display device 100 according to the embodiment of the present specification may be an inorganic light-emitting display device in which the light-emitting element is embodied as a light-emitting diode on an inorganic substrate. As still another example, the display device 100 according to the embodiment of the present specification may be a quantum dot display device in which the light-emitting element is embodied as a quantum dot that emits light by itself, which is a semiconductor crystal.

[0084] The structure of each of the plurality of sub-pixels SP may vary depending on the type of the display device 100. For example, when the display device 100 is a self-emitting display device in which the sub-pixel SP emits light by itself, each sub-pixel SP may include a light-emitting element that emits light by itself, one or more transistors, and one or more capacitors.

[0085] For example, various types of signal lines may include a plurality of data lines DL that transmit data signals (also referred to as data voltages or video signals) and a plurality of gate lines GL that transmit gate signals (also referred to as scan signals).

[0086] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction.

[0087] Here, the first direction may be the column direction, and the second direction may be the row direction. Or, the first direction may be the row direction, and the second direction may be the column direction.

[0088] The data driving circuit DDC is a circuit for driving the plurality of data lines DL and can output a data signal to the plurality of data lines DL. The gate driving circuit GDC is a circuit for driving the plurality of gate lines GL and can output a gate signal to the plurality of gate lines GL.

[0089] The display controller DCTR is a device for controlling the data driving circuit DDC and the gate driving circuit GDC, and can control the driving timing for the plurality of data lines DL and the driving timing for the plurality of gate lines GL.

[0090] The display controller DCTR can supply a data driving control signal DCS to the data driving circuit DDC to control the data driving circuit DDC, and supply a gate driving control signal GCS to the gate driving circuit GDC to control the gate driving circuit GDC.

[0091] The display controller DCTR can receive input video data from the host system HSYS and supply video data Data to the data driving circuit DDC based on the input video data.

[0092] The data driving circuit DDC can supply data signals to a plurality of data lines DL under the driving timing control of the display controller DCTR.

[0093] The data driving circuit DDC can receive video data Data in digital form from the display controller DCTR, convert the received video data Data into analog-form data signals, and output them to a plurality of data lines DL.

[0094] The gate driving circuit GDC can supply gate signals to a plurality of gate lines GL under the timing control of the display controller DCTR. The gate driving circuit GDC can receive the supply of a first gate voltage corresponding to the turn-on level voltage and a second gate voltage corresponding to the turn-off level voltage together with various gate driving control signals GCS, generate a gate signal, and supply the generated gate signal to a plurality of gate lines GL.

[0095] The gate driving circuit GDC supplies a gate signal to the gate line GL according to the gate driving control signal GCS supplied from the display controller DCTR. The gate driving circuit GDC may be arranged on one side or both sides of the display panel 100 in the GIP (Gate In Panel) method.

[0096] The gate driving circuit GDC sequentially outputs a gate signal to a plurality of gate lines GL under the control of the display controller DCTR. The gate driving circuit GDC can sequentially supply the signal to the gate line GL by shifting the gate signal using a shift register.

[0097] The gate signal can include a scan signal SC and a light emission control signal EM in an organic light emitting display device. The scan signal SC includes a scan signal pulse that swings between a first gate voltage and a second gate voltage. The light emission control signal EM can include a light emission control signal pulse that swings between a third gate voltage and a fourth gate voltage.

[0098] The scan pulse selects the sub-pixel SP of the line where data is written in synchronization with the data voltage Vdata. The light emission control signal EM defines the light emission time of each sub-pixel SP.

[0099] The gate driving circuit GDC can include a light emission control signal driving unit EDC that outputs the light emission control signal EM and at least one or more scan driving units SDC that output the scan signal SC.

[0100] The light emission control signal driving unit EDC outputs the light emission control signal EM in response to a start pulse and a shift clock from the display controller DCTR, and sequentially shifts the light emission control signal pulses by the shift clock.

[0101] At least one or more scan driving units SDC output the scan signal SC in response to a start pulse and a shift clock from the display controller DCTR, and shift the scan signal pulses according to the shift clock timing.

[0102] The gate driving circuit GDC arranged in the GIP method can have shift registers symmetrically configured on both sides of the display area DA. Also, the gate driving circuit GDC can be configured such that the shift register on one side of the display area DA includes at least one scan driving unit SDC and a light emission control signal driving unit 310, and the shift register on the other side of the display area DA includes at least one scan driving unit SDC respectively. However, it is not limited thereto, and the light emission control signal driving unit EDC and at least one scan driving unit SDC can be arranged differently according to the embodiment.

[0103] The data driving circuit DDC may be connected to the display panel DP in a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel DP in a chip on glass (COG) or chip on panel (COP) method, or may be implemented in a chip on film (COF) method and connected to the display panel DP.

[0104] The gate driving circuit GDC may be connected to the display panel DP in a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel DP in a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel DP by a chip on film (COF) method. Alternatively, the gate driving circuit GDC may be formed in the non-display area NDA of the display panel DP in a gate in panel (GIP) type. The gate driving circuit GDC may be disposed on or connected to the substrate. That is, when the gate driving circuit GDC is of the GIP type, it may be disposed in the non-display area NDA of the substrate. When the gate driving circuit GDC is of the chip on glass (COG) type, chip on film (COF) type, etc., it may be connected to the substrate.

[0105] On the other hand, at least one of the data driving circuit DDC and the gate driving circuit GDC may be disposed in the display area DA of the display panel DP. For example, at least one of the data driving circuit DDC and the gate driving circuit GDC may be disposed so as not to overlap with the sub-pixel SP, or may be disposed so as to partially or entirely overlap with the sub-pixel SP.

[0106] The data driving circuit DDC may be connected to one side (e.g., the upper side or the lower side) of the display panel DP. Depending on the driving method, panel design method, etc., the data driving circuit DDC may be connected to both sides (e.g., the upper side and the lower side) of the display panel DP, or may be connected to two or more sides out of the four sides of the display panel DP.

[0107] The gate driving circuit GDC may be connected to one side (e.g., the left side or the right side) of the display panel DP. Depending on the driving method, panel design method, etc., the gate driving circuit GDC may be connected to both sides (e.g., the left side and the right side) of the display panel DP, or may be connected to two or more sides out of the four sides of the display panel DP.

[0108] The display controller DCTR may be embodied as a separate component from the data driving circuit DDC, or may be integrated with the data driving circuit DDC and embodied in an integrated circuit.

[0109] The display controller DCTR may be a timing controller used in ordinary display technology, or a control device that includes a timing controller and can further perform other control functions, or a control device different from the timing controller, or a circuit within the control device. The display controller DCTR may be embodied in various circuits and electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable GATE Array), ASIC (Application Specific Integrated Circuit), or a processor.

[0110] The display controller DCTR may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit DDC and the gate driving circuit GDC through the printed circuit board, the flexible printed circuit, etc.

[0111] The display controller DCTR can transmit and receive signals with the data driving circuit DDC through one or more predetermined interfaces. Here, for example, the interfaces can include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Clock Point-to-Point Interface), an SPI (Serial Peripheral Interface), and the like.

[0112] In order to further provide a touch sensing function in addition to the video display function, the display device 100 according to the embodiment of the present specification can include a touch sensor and a touch sensing circuit that senses the touch sensor and detects whether a touch has occurred or detects a touch position by a touch object such as a finger or a pen.

[0113] The touch sensing circuit can further include a touch driving circuit that drives and senses the touch sensor to generate and output touch sensing data, and a touch controller or the like that can sense touch occurrence or detect a touch position using the touch sensing data.

[0114] The touch sensor can include a plurality of touch electrodes. The touch sensor can further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit.

[0115] The touch sensor may exist in the form of a touch panel outside the display panel DP or inside the display panel DP. When the touch sensor exists outside the display panel DP in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is of the external type, the touch panel and the display panel DP can be separately manufactured and combined in the assembly process. The external type touch panel can include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate and the like.

[0116] When the touch sensor exists inside the display panel DP, the touch sensor can be formed on the substrate SUB together with signal lines, electrodes, etc. related to display driving during the manufacturing process of the display panel DP.

[0117] The touch drive circuit TDC can supply a touch drive signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0118] The touch sensing circuit can perform touch sensing in a self - capacitance sensing method or a mutual - capacitance sensing method.

[0119] When the touch sensing circuit performs touch sensing in the self - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., finger, pen, etc.).

[0120] According to the self - capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch drive circuit TDC can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0121] When the touch sensing circuit performs touch sensing in the mutual - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0122] According to the mutual - capacitance sensing method, the plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch drive circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0123] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented in separate devices or in one device. Also, the touch driving circuit and the data driving circuit DDC may be implemented in separate devices or in one device.

[0124] The display device 100 may further include a power supply circuit or the like that supplies various power supplies to the display driving circuit and / or the touch sensing circuit.

[0125] The display device 100 according to the embodiments of this specification may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or a television (TV) of various sizes, and is not limited thereto, and may be a display of various types and sizes that can display information and images.

[0126] As described above, in the display panel DP, the display area DA may include a general area NA and one or more optical areas DA1, DA2.

[0127] The general area NA and one or more optical areas DA1, DA2 are areas where video display is possible. However, the general area NA is an area where a light transmission structure does not need to be formed, and one or more optical areas DA1, DA2 are areas where a light transmission structure must be formed.

[0128] As described above, in the display panel DP, the display area DA may include one or more optical areas DA1, DA2 together with the general area NA. For the sake of convenience of explanation, assume that the display area DA includes all of the first optical area DA1 and the second optical area DA2 (FIGS. 1c and 1d).

[0129] FIG. 3 is an equivalent circuit diagram of sub-pixels in a display panel according to an embodiment of this specification.

[0130] FIG. 3 merely exemplarily shows a pixel circuit for explanation purposes, and is not limited as long as it has a structure capable of controlling the emission of the light-emitting elements ED and 120 by applying the emission signal EM(n). For example, the pixel circuit can include additional scan signals and switching thin-film transistors connected thereto, and switching thin-film transistors to which additional initialization voltages are applied, and the connection relationships of the switching elements and the connection positions of the capacitors can also be arranged in various ways. In the following, for the sake of convenience of explanation, a display device having the pixel circuit structure of FIG. 3 will be described.

[0131] Referring to FIG. 3, each of the plurality of sub-pixels SP can include a pixel circuit having a driving transistor Td, and light-emitting elements ED and 120 connected to the pixel circuit.

[0132] Each of the sub-pixels SP arranged in the general region NA, the first optical region DA1, and the second optical region DA2 included in the display region DA of the display panel DP can include the light-emitting elements ED and 120, a driving transistor Td for driving the light-emitting elements ED and 120, a plurality of scan transistors T1 to T7 for operating the driving transistor Td, a capacitor Cst for maintaining a constant voltage during one frame, and the like.

[0133] The pixel circuit can control the driving current flowing through the light-emitting elements ED and 120 to drive the light-emitting elements ED and 120. The pixel circuit can include the driving transistor Td, the first to seventh transistors T1 to T7, and the capacitor Cst. Each of the transistors DT, T1 to T7 can include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode can be a source electrode, and the other of the first electrode and the second electrode can be a drain electrode.

[0134] Each of the transistors DT, T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. In the embodiment of FIG. 3, the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the other remaining transistors DT, T2 to T6 are configured as P-type thin film transistors. However, the present invention is not limited thereto, and all or part of the transistors DT, T1 to T7 may be P-type thin film transistors or N-type thin film transistors depending on the embodiment. Further, the N-type thin film transistor may be an oxide thin film transistor, and the P-type thin film transistor may be a polycrystalline silicon thin film transistor.

[0135] In the following, the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the other remaining transistors DT, T2 to T6 are P-type thin film transistors as an example for explanation. Therefore, a high voltage is applied to the first transistor T1 and the seventh transistor T7 to turn them on, and a low voltage is applied to the other remaining transistors DT, T2 to T6 to turn them on.

[0136] According to an example, the first transistor T1 constituting the pixel circuit can function as a compensation transistor, the second transistor T2 can function as a data supply transistor, the third and fourth transistors T3 and T4 can function as light emission control transistors, the fifth transistor T5 can function as a bias transistor, and the sixth and seventh transistors T6 and T7 can function as initialization transistors.

[0137] The light emitting element ED, 120 may include an anode electrode (or an anode electrode) and a cathode electrode. The anode electrode of the light emitting element ED, 120 may be connected to the fifth node N5, and the cathode electrode may be connected to the low potential driving voltage EVSS.

[0138] The drive transistor Td can include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The drive transistor Td can provide a drive current Id to the light-emitting element ED, 120 based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst described later).

[0139] The first transistor T1 can include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode that receives the first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1(n), and the data voltage Vdata can sample the threshold voltage Vth of the drive transistor Td by being diode-connected between the first node N1 and the third node N3. Such a first transistor T1 can be a compensation transistor.

[0140] The capacitor Cst can be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst can store or maintain the provided high-potential drive voltage EVDD. Also, in some cases, the capacitor Cst may further include one or more capacitors.

[0141] The second transistor T2 can include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode that receives the second scan signal SC2(n). The second transistor T2 is turned on in response to the second scan signal SC2(n) and can transmit the data voltage Vdata to the second node N2. Such a second transistor T2 can be a data supply transistor.

[0142] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) are connected between the high-potential drive voltage EVDD and the light-emitting element ED, 120 and can form a current path through which the drive current Id generated by the drive transistor Td moves.

[0143] The third transistor T3 can include a first electrode connected to the fourth node N4 to receive a high potential drive voltage EVDD, a second electrode connected to the second node N2, and a gate electrode to receive a light emission control signal EM(n).

[0144] The fourth transistor T4 can include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode electrode of the light emitting element ED, 120), and a gate electrode to receive a light emission control signal EM(n).

[0145] The third and fourth transistors T3, T4 are turned on in response to the light emission control signal EM(n). In this case, a drive current Id is provided to the light emitting element ED, 120, and the light emitting element ED, 120 can emit light with a luminance corresponding to the drive current Id.

[0146] The fifth transistor T5 can include a first electrode to receive a bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode to receive a third scan signal SC3(n). Such a fifth transistor T5 can be a bias transistor.

[0147] The sixth transistor T6 can include a first electrode to receive a first initialization voltage Var, a second electrode connected to the fifth node N5, and a gate electrode to receive a third scan signal SC3(n).

[0148] The sixth transistor T6 is turned on in response to the third scan signal SC3(n) before the light-emitting elements ED, 120 emit light (or after the light-emitting elements ED, 120 have emitted light), and can initialize the anode electrode (or pixel electrode) of the light-emitting elements ED, 120 using the first initialization voltage Var. The light-emitting elements ED, 120 can have a parasitic capacitor formed between the anode electrode and the cathode electrode. And while the light-emitting elements ED, 120 emit light, the parasitic capacitor is charged and the anode electrode of the light-emitting elements ED, 120 can have a specific voltage. Therefore, the amount of charge accumulated in the light-emitting elements ED, 120 can be initialized by applying the first initialization voltage Var to the anode electrode of the light-emitting elements ED, 120 through the sixth transistor T6.

[0149] In this specification, the gate electrodes of the fifth and sixth transistors T5, T6 are configured to commonly receive the third scan signal SC3(n). However, it is not necessarily limited thereto, and the gate electrodes of the fifth and sixth transistors T5, T6 can be configured to receive separate scan signals and be independently controlled.

[0150] The seventh transistor T7 can include a first electrode that receives the second initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode that receives the fourth scan signal SC4(n).

[0151] The seventh transistor T7 is turned on in response to the fourth scan signal SC4(n), and can initialize the gate electrode of the driving transistor Td using the second initialization voltage Vini. Unnecessary charges can remain in the gate electrode of the driving transistor Td due to the high-potential driving voltage EVDD stored in the capacitor Cst. Therefore, the amount of remaining charge can be initialized by applying the second initialization voltage Vini to the gate electrode of the driving transistor Td through the seventh transistor T7.

[0152] On the one hand, as one method for increasing the transmittance of at least one of the first optical region DA1 and the second optical region DA2, a design method such as a pixel density difference can be applied as described above. According to the design method such as a pixel density difference, the display panel DP can be designed such that the number of sub-pixels per unit area of at least one of the first optical region DA1 and the second optical region DA2 is less than the number of sub-pixels per unit area of the general region NA.

[0153] However, in some cases, differently, as another method for increasing the transmittance of at least one of the first optical region DA1 and the second optical region DA2, a design method such as a pixel size difference can be applied. According to the design method such as a pixel size difference, the number of sub-pixels per unit area of at least one of the first optical region DA1 and the second optical region DA2 is the same as or similar to the number of sub-pixels per unit area of the general region NA, and the size of each sub-pixel SP (i.e., the size of the light-emitting region) arranged in at least one of the first optical region DA1 and the second optical region DA2 is smaller than the size of each sub-pixel SP (i.e., the size of the light-emitting region) arranged in the general region NA, so that the display panel DP can be designed.

[0154] In the following, for the convenience of explanation, it is assumed that the design method of pixel density difference and other methods (design methods such as pixel density difference and pixel size difference) for increasing the transmittance of at least one of the first optical region DA1 and the second optical region DA2 is applied for explanation.

[0155] FIG. 4 is a diagram showing the arrangement of sub-pixels in the display area of a display panel according to an embodiment of the present specification.

[0156] That is, FIG. 4 shows the arrangement of sub-pixels SP in three regions NA, DA1, and DA2 included in the display area of the display panel according to the embodiment of the present specification.

[0157] Referring to FIG. 4, a plurality of sub-pixels SP can be arranged in each of the general region NA, the first optical region DA1, and the second optical region DA2 included in the display area.

[0158] As an example, the plurality of sub-pixels SP can include a red sub-pixel Red SP that emits red light, a green sub-pixel Green SP that emits green light, and a blue sub-pixel Blue SP that emits blue light.

[0159] Accordingly, each of the general region NA, the first optical region DA1, and the second optical region DA2 can include the light-emitting region EA of the red sub-pixel Red SP, the light-emitting region EA of the green sub-pixel Green SP, and the light-emitting region EA of the blue sub-pixel Blue SP.

[0160] Referring to FIG. 4, the general region NA does not include a light-transmitting structure and can include the light-emitting region EA.

[0161] However, the first optical region DA1 and the second optical region DA2 must not only include the light-emitting region EA but also include a light-transmitting structure.

[0162] Therefore, the first optical region DA1 can include the light-emitting region EA and the first transmission region TA1, and the second optical region DA2 can include the light-emitting region EA and the second transmission region TA2.

[0163] The light-emitting region EA and the transmission regions TA1, TA2 can be distinguished by whether light transmission is possible. That is, the light-emitting region EA can be a region where light transmission is impossible, and the transmission regions TA1, TA2 can be regions where light transmission is possible.

[0164] Also, the light-emitting region EA and the transmission regions TA1, TA2 can be distinguished by the presence or absence of the formation of a specific metal layer. For example, a cathode electrode may be formed in the light-emitting region EA, and a cathode electrode may not be formed in the transmission regions TA1, TA2. Also, a light-shielding layer may be formed in the light-emitting region EA, and a light-shielding layer may not be formed in the transmission regions TA1, TA2.

[0165] At this time, since the first optical region DA1 includes the first transmission region TA1 and the second optical region DA2 includes the second transmission region TA2, both the first optical region DA1 and the second optical region DA2 are regions through which light can pass.

[0166] At this time, the transmittance (degree of transmission) of the first optical region DA1 and the transmittance (degree of transmission) of the second optical region DA2 may be the same.

[0167] In this case, the first transmission region TA1 of the first optical region DA1 and the second transmission region TA2 of the second optical region DA2 may have the same pattern or size. Or, even if the pattern and size of the first transmission region TA1 of the first optical region DA1 and the second transmission region TA2 of the second optical region DA2 are different, the ratio of the first transmission region TA1 in the first optical region DA1 and the ratio of the second transmission region TA2 in the second optical region DA2 may be the same.

[0168] In contrast, the transmittance (degree of transmission) of the first optical region DA1 and the transmittance (degree of transmission) of the second optical region DA2 may be different from each other.

[0169] In this case, the first transmission region TA1 of the first optical region DA1 and the second transmission region TA2 of the second optical region DA2 may have different patterns or sizes. Or, even if the pattern and size of the first transmission region TA1 of the first optical region DA1 and the second transmission region TA2 of the second optical region DA2 are the same, the ratio of the first transmission region TA1 in the first optical region DA1 and the ratio of the second transmission region TA2 in the second optical region DA2 may be different from each other.

[0170] For example, when the first optoelectronic device over which the first optical region DA1 is superimposed is a camera and the second optoelectronic device over which the second optical region DA2 is superimposed is a sensing sensor, the camera may require a larger amount of light than the sensing sensor.

[0171] Therefore, the transmittance (degree of transmission) of the first optical region DA1 may be higher than the transmittance (degree of transmission) of the second optical region DA2.

[0172] In this case, the first transmission region TA1 of the first optical region DA1 may have a size that is even larger than the second transmission region TA2 of the second optical region DA2. Alternatively, even if the first transmission region TA1 of the first optical region DA1 and the second transmission region TA2 of the second optical region DA2 have the same size, the ratio of the first transmission region TA1 within the first optical region DA1 may be larger than the ratio of the second transmission region TA2 within the second optical region DA2.

[0173] In the following, for the sake of convenience of explanation, the case where the transmittance (degree of transmission) of the first optical region DA1 is larger than the transmittance (degree of transmission) of the second optical region DA2 will be taken as an example for explanation.

[0174] Also, as shown in FIG. 4, in one embodiment of this specification, the transmission regions TA1 and TA2 can also be said to be transparent regions, and the transmittance can also be said to be the transparency.

[0175] Also, as shown in FIG. 4, in one embodiment of this specification, assume the case where the first optical region DA1 and the second optical region DA2 are located at the upper end of the display region of the display panel and are arranged side by side.

[0176] Referring to FIG. 4, the horizontal display region where the first optical region DA1 and the second optical region DA2 are arranged is referred to as the first horizontal display region HA1, and the horizontal display region where the first optical region DA1 and the second optical region DA2 are not arranged is referred to as the second horizontal display region HA2.

[0177] Referring to FIG. 4, the first horizontal display region HA1 can include the general region NA, the first optical region DA1, and the second optical region DA2. In contrast, the second horizontal display region HA2 can include only the general region NA.

[0178] FIG. 5a is a diagram showing, by way of example, the arrangement of signal lines in the first optical region and the general region in a display panel according to an embodiment of this specification.

[0179] FIG. 5b is a diagram showing, by way of example, the arrangement of signal lines in the second optical region and the general region, respectively, in a display panel according to an embodiment of the present specification.

[0180] That is, FIG. 5a shows the arrangement of signal lines in the first optical region DA1 and the general region NA, respectively, in a display panel according to an embodiment of the present specification, and FIG. 5b shows the arrangement of signal lines in the second optical region DA2 and the general region NA, respectively, in a display panel according to an embodiment of the present specification.

[0181] The first horizontal display region HA1 shown in FIGS. 5a and 5b is a part of the first horizontal display region HA1 in the display panel DP, and the second horizontal display region HA2 is a part of the second horizontal display region HA2 in the display panel.

[0182] The first optical region DA1 shown in FIG. 5a is a part of the first optical region DA1 in the display panel, and the second optical region DA2 shown in FIG. 5b is a part of the second optical region DA2 in the display panel.

[0183] Referring to FIGS. 5a and 5b, the first horizontal display region HA1 can include the general region, the first optical region DA1, and the second optical region DA2. The second horizontal display region HA2 can include the general region.

[0184] Various types of horizontal lines HL1, HL2 can be arranged on the display panel, and various types of vertical lines VLn, VL1, VL2 can be arranged.

[0185] In an embodiment of the present specification, the horizontal direction and the vertical direction mean two intersecting directions, and the horizontal direction and the vertical direction may differ depending on the viewing direction. As an example, in an embodiment of the present specification, the horizontal direction may mean the direction in which one gate line extends and is arranged, and the vertical direction may mean the direction in which one data line extends and is arranged. In this way, the horizontal and vertical directions are taken as examples.

[0186] Referring to FIGS. 5a and 5b, the horizontal lines disposed on the display panel can include a first horizontal line HL1 disposed in the first horizontal display area HA1 and a second horizontal line HL2 disposed in the second horizontal display area HA2.

[0187] The horizontal lines disposed on the display panel may be gate lines. That is, the first horizontal line HL1 and the second horizontal line HL2 may be gate lines. The gate lines can include various types of gate lines depending on the structure of the sub-pixels.

[0188] Referring to FIGS. 5a and 5b, the vertical lines disposed on the display panel can include general vertical lines VLn disposed only in the general area, a first vertical line VL1 passing through the first optical area DA1 and the general area, and a second vertical line VL2 passing through the second optical area DA2 and the general area.

[0189] The vertical lines disposed on the display panel can include data lines, driving voltage lines, etc., and moreover, can further include reference voltage lines, initialization voltage lines, etc. That is, the general vertical lines VLn, the first vertical line VL1, and the second vertical line VL2 can include data lines, driving voltage lines, etc., and moreover, can further include reference voltage lines, initialization voltage lines, etc.

[0190] In one embodiment of the present specification, the term "horizontal" for the second horizontal line HL2 only means that the signal is transmitted from the left side (or right side) to the right side (or left side), and does not necessarily mean that the second horizontal line HL2 extends in a straight line form only in the exact horizontal direction. That is, in FIGS. 5a and 5b, although the second horizontal line HL2 is shown in a straight line form, on the contrary, the second horizontal line HL2 can include bent or curved portions. Similarly, the first horizontal line HL1 can also include bent or curved portions.

[0191] In one embodiment of the present specification, in the general vertical line Vln, the term "vertical" only means that the signal is transmitted from the upper side (or lower side) to the lower side (or upper side), and does not mean that the general vertical line Vln extends in a straight line form only in the exact vertical direction. That is, in FIGS. 5a and 5b, although the general vertical line Vln is shown in a straight line form, on the contrary, the general vertical line Vln can include bent or curved portions. Similarly, the first vertical line VL1 and the second vertical line VL2 can also include bent or curved portions.

[0192] Referring to FIG. 5a, the first optical region DA1 included in the first horizontal region HA1 can include a light emitting region and a first transmission region. Within the first optical region DA1, the outer region of the first transmission region can include a light emitting region.

[0193] Referring to FIG. 5a, in order to improve the transmittance of the first optical region DA1, the first horizontal line HL1 passing through the first optical region DA1 can pass by avoiding the first transmission region within the first optical region DA1.

[0194] Therefore, each of the first horizontal lines HL1 passing through the first optical region DA1 can include a curved section or a bending section that bypasses outside the frame of the outline of each first transmission region.

[0195] As a result, the first horizontal line HL1 arranged in the first horizontal region HA1 and the second horizontal line HL2 arranged in the second horizontal region HA2 can have different patterns or lengths from each other. That is, the first horizontal line HL1 passing through the first optical region DA1 and the second horizontal line HL2 not passing through the first optical region DA1 can have different patterns or lengths from each other.

[0196] Also, in order to improve the transmittance of the first optical region DA1, the first vertical line VL1 passing through the first optical region DA1 can pass by avoiding the first transmission region within the first optical region DA1.

[0197] Therefore, each of the first vertical lines VL1 passing through the first optical region DA1 can include a curved section or a bending section that bypasses outside the frame of the outline of each first transmission region.

[0198] As a result, the first vertical line VL1 passing through the first optical region DA1 and the general vertical line VLn arranged in the general region without passing through the first optical region DA1 can have different patterns, lengths, etc. from each other.

[0199] Referring to FIG. 5a, the first transmission regions included in the first optical region DA1 within the first horizontal region HA1 can be arranged in a slanted direction.

[0200] Referring to FIG. 5a, in the first optical region DA1 within the first horizontal region HA1, a light-emitting region can be arranged between two adjacent first transmission regions on the left and right. In the first optical region DA1 within the first horizontal region HA1, a light-emitting region can be arranged between two adjacent first transmission regions above and below.

[0201] Referring to FIG. 5a, the first horizontal line HL1 arranged in the first horizontal region HA1, that is, the first horizontal line HL1 passing through the first optical region DA1, can all include at least one curved section or a bending section that bypasses outside the frame of the outline of the first transmission region.

[0202] Referring to FIG. 5b, the second optical region DA2 included in the first horizontal region HA1 can include a light-emitting region and a second transmission region TA2. Within the second optical region DA2, the outer region of the second transmission region TA2 can include a light-emitting region.

[0203] The positions and arrangement states of the light-emitting region and the second transmission region TA2 within the second optical region DA2 may be the same as the positions and arrangement states of the light-emitting region and the second transmission region within the first optical region DA1 in FIG. 5a.

[0204] In contrast, as shown in FIG. 5b, the positions and arrangement states of the light-emitting region and the second transmission region TA2 within the second optical region DA2 can be different from the positions and arrangement states of the light-emitting region and the second transmission region within the first optical region DA1 in FIG. 5a.

[0205] For example, referring to FIG. 5b, within the second optical region DA2, the second transmission region TA2 can be arranged in the horizontal direction (left - right direction). A light - emitting region does not have to be arranged between two adjacent second transmission regions TA2 in the horizontal direction (left - right direction). Also, the light - emitting region within the second optical region DA2 can be arranged between second transmission regions TA2 adjacent in the vertical direction (up - down direction). That is, a light - emitting region can be arranged between rows of two second transmission regions TA2.

[0206] When the first horizontal line HL1 passes through the second optical region DA2 and the general region around it within the first horizontal region HA1, it can pass in the same form as in FIG. 5a.

[0207] In contrast, as shown in FIG. 5b, when the first horizontal line HL1 passes through the second optical region DA2 and the general region around it within the first horizontal region HA1, it can pass in a form different from that in FIG. 5a.

[0208] That is, because the positions and arrangement states of the light - emitting region and the second transmission region TA2 within the second optical region DA2 in FIG. 5b are different from the positions and arrangement states of the light - emitting region and the second transmission region within the first optical region DA1 in FIG. 5a.

[0209] Referring to FIG. 5b, when the first horizontal line HL1 passes through the second optical region DA2 and the general region around it within the first horizontal region HA1, it can pass in a straight - line form between vertically adjacent second transmission regions TA2 without a curved section or a bending section.

[0210] In other words, one first horizontal line HL1 has a curved section or a bending section within the first optical region DA1, but does not have to have a curved section or a bending section within the second optical region DA2.

[0211] For the improvement of the transmittance of the second optical region DA2, the second vertical line VL2 passing through the second optical region DA2 can avoid passing through the second transmission region TA2 within the second optical region DA2.

[0212] Therefore, each of the second vertical lines VL2 passing through the second optical region DA2 can include a curved section or a bending section that bypasses outside the frame of the outline of each second transmission region TA2.

[0213] As a result, the second vertical lines VL2 passing through the second optical region DA2 and the general vertical lines VLn arranged in the general region without passing through the second optical region DA2 can have different patterns or lengths, etc. from each other.

[0214] As shown in FIG. 5a, the first horizontal line HL1 passing through the first optical region DA1 can have a curved section or a bending section that bypasses outside the frame of the outline of the first transmission region.

[0215] Therefore, the length of the first horizontal line HL1 passing through the first optical region DA1 and the second optical region DA2 can be slightly longer than the length of the second horizontal line HL2 arranged only in the general region without passing through the first optical region DA1 and the second optical region DA2.

[0216] As a result, the resistance of the first horizontal line HL1 passing through the first optical region DA1 and the second optical region DA2 (hereinafter also referred to as the first resistance) can be slightly larger than the resistance of the second horizontal line HL2 arranged only in the general region without passing through the first optical region DA1 and the second optical region DA2 (hereinafter also referred to as the second resistance).

[0217] Referring to FIGS. 5a and 5b, due to the light transmission structure, the first optical region DA1 that at least partially overlaps with the first optoelectronic device 170a includes a plurality of first transmission regions TA1, and the second optical region DA2 that at least partially overlaps with the second optoelectronic device 170b includes a plurality of second transmission regions TA2. Therefore, the first optical region DA1 and the second optical region DA2 can have fewer sub-pixels per unit area than the general region NA.

[0218] The number of sub-pixels to which a first horizontal line HL1 passing through a first optical region DA1 and a second optical region DA2 is connected, and the number of sub-pixels to which a second horizontal line HL2 disposed only in a general region without passing through the first optical region DA1 and the second optical region DA2 is connected can be different from each other.

[0219] The number of sub-pixels (first number) to which a first horizontal line HL1 passing through a first optical region DA1 and a second optical region DA2 is connected can be less than the number of sub-pixels (second number) to which a second horizontal line HL2 disposed only in a general region without passing through the first optical region DA1 and the second optical region DA2 is connected.

[0220] The difference between the first number and the second number can vary depending on the difference in resolution between each of the first optical region DA1 and the second optical region DA2 and the resolution of the general region. For example, as the difference in resolution between each of the first optical region DA1 and the second optical region DA2 and the resolution of the general region increases, the difference between the first number and the second number can increase.

[0221] As described above, since the number of sub-pixels (first number) to which a first horizontal line HL1 passing through a first optical region DA1 and a second optical region DA2 is connected is less than the number of sub-pixels (second number) to which a second horizontal line HL2 disposed only in a general region without passing through the first optical region DA1 and the second optical region DA2 is connected, the area where the first horizontal line HL1 overlaps with other peripheral electrodes and lines can be smaller than the area where the second horizontal line HL2 overlaps with other peripheral electrodes and lines.

[0222] Therefore, the parasitic capacitance (hereinafter referred to as the first capacitance) formed by the first horizontal line HL1 and other peripheral electrodes and lines can be larger or smaller than the parasitic capacitance (hereinafter referred to as the second capacitance) formed by the second horizontal line HL2 and other peripheral electrodes and lines.

[0223] When considering the magnitude relationship between the first resistance and the second resistance (first resistance ≥ second resistance) and the magnitude relationship between the first capacitance and the second capacitance (first capacitance ≪ second capacitance), the RC (Resistance-Capacitance) value of the first horizontal line HL1 passing through the first optical region DA1 and the second optical region DA2 (hereinafter also referred to as the first RC value) can be much smaller than the RC value of the second horizontal line HL2 disposed only in the general region without passing through the first optical region DA1 and the second optical region DA2 (hereinafter also referred to as the second RC value) (first RC value ≪ second RC value).

[0224] Due to the difference between the first RC value of the first horizontal line HL1 and the second RC value of the second horizontal line HL2 (hereinafter referred to as the RC Load deviation), the signal transmission characteristics through the first horizontal line HL1 and the signal transmission characteristics through the second horizontal line HL2 can change.

[0225] Hereinafter, for a more detailed description of the cross-sectional structure of the general region NA of the display device 100, reference is made to FIG. 6 together.

[0226] FIG. 6 is a cross-sectional view showing the cross-sectional structure of one pixel region disposed in the general region according to an embodiment of the present specification.

[0227] In the general region NA, a transistor layer TRL may be disposed on the upper part of the substrate SUB, and a planarization layer PLN may be disposed on the upper part of the transistor layer TRL. Further, a light-emitting element layer EDL may be disposed on the upper part of the planarization layer PLN, a sealing layer ENCAP may be disposed on the upper part of the light-emitting element layer EDL, a touch sensing layer TSL may be disposed on the upper part of the sealing layer ENCAP, and a protection layer PAC may be disposed on the upper part of the touch sensing layer TSL. Further, an organic layer PCL may be disposed on the upper part of the protection layer PAC, and a polarizing layer POL may be disposed on the upper part of the organic layer PCL.

[0228] The substrate SUB is configured to support various components included in the display device 100 and can be made of an insulating material. The substrate SUB can include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c can be disposed between the first substrate 110a and the second substrate 110b. By configuring the substrate SUB with the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c in this way, moisture penetration can be prevented. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates.

[0229] In the general region NA, in the transistor layer TRL, various patterns 131, 132, 133, 134, 231, 232, 233, 234 for forming transistors such as a driving transistor Td and at least one switching transistor Ts, and transistors such as at least one capacitor, various insulating films 111a, 111b, 112, 113a, 113b, 114, and various metal patterns TM, GM, 135 can be disposed.

[0230] Hereinafter, the laminated structure of the transistor layer TRL will be described in more detail.

[0231] A multi-buffer layer 111a is disposed on the second substrate 110b, and an active buffer layer 111b can be disposed on the multi-buffer layer 111a.

[0232] A metal layer 135 can be disposed on the multi-buffer layer 111a.

[0233] Here, the metal layer 135 can serve as a light shield and can also be referred to as a light-shielding layer.

[0234] An active buffer layer 111b can be disposed on the metal layer 135.

[0235] The first active layer 134 of the driving transistor Td can be disposed on the active buffer layer 111b. For example, the first active layer 134 can be formed of polycrystalline silicon (p-Si), amorphous silicon (a-Si), or an oxide semiconductor, but is not limited thereto. On the other hand, the driving transistor Td is formed on the active buffer layer 111b and includes a first active layer 134, a first gate insulating film 112 covering the first active layer 134, a first gate electrode 131 disposed on the first gate insulating film 112, a first interlayer insulating film 113a covering the first gate electrode 131, a second gate insulating film 113b disposed on the first interlayer insulating film 113a, a third interlayer insulating film 113c disposed on the second gate insulating film 113b, a first source electrode 132 and a first drain electrode 133 disposed on the third interlayer insulating film 113c.

[0236] The first gate insulating film 112 can be disposed on the first active layer 134. The first gate insulating film 112 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer thereof.

[0237] Also, the first gate electrode 131 of the driving transistor Td can be disposed on the first gate insulating film 112. The first gate electrode 131 is disposed so as to overlap the first active layer 134 on the first gate insulating layer 112. The first gate electrode 131 can be formed of various conductive materials, for example, magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or an alloy thereof, etc., but is not limited thereto.

[0238] The gate material layer GM can be disposed on the first gate insulating film 112 at a position different from the formation position of the driving transistor Td.

[0239] The first interlayer insulating film 113a can be disposed on the first gate electrode 131 and the gate material layer GM. The metal pattern TM can be disposed on the first interlayer insulating film 113a. The second interlayer insulating film 113b can be disposed while covering the metal pattern TM disposed on the first interlayer insulating film 113a.

[0240] The second interlayer insulating film 113b separates the first active layer 134 from the second active layer 234 and provides a substrate on which the second active layer 234 can be formed.

[0241] On the second interlayer insulating film 113b, the second active layer 234 of the switching transistor Ts can be disposed. For example, the second active layer 234 can be formed of polycrystalline silicon, amorphous silicon, or an oxide semiconductor, but is not limited thereto.

[0242] The second gate insulating film 113c can be disposed on the second active layer 234. Also, the second gate electrode 231 of the switching transistor Ts can be disposed on the second gate insulating film 113c. The second gate electrode 231 is disposed so as to overlap the second active layer 234 on the second gate film 113c.

[0243] The second gate insulating film 113c covers the second active layer 234 of the switching transistor Ts. Since the second gate insulating film 113c is formed on the second active layer 234, it is embodied as an inorganic film. For example, the second gate insulating film 113c may be silicon oxide (SiO2), silicon nitride (SiNx), or a multilayer thereof.

[0244] The second gate electrode 231 is composed of a metallic substance. For example, the second gate electrode 231 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0245] On one hand, the switching transistor Ts is formed on the second interlayer insulating film 113b and includes a second active layer 234, a second gate insulating film 113c covering the second active layer 234, a second gate electrode 231 disposed on the second gate insulating film 113c, a third interlayer insulating film 113c covering the second gate electrode 231, a second source electrode 232 and a second drain electrode 233 disposed on the third interlayer insulating film 113c.

[0246] The switching transistor Ts is located below the first interlayer insulating film 113a and further includes a gate material layer GM that overlaps with the second active layer 234. The gate material layer GM can block the light incident on the second active layer 234 to ensure the reliability of the switching transistor Ts. The gate material layer GM is formed of the same material as the first gate electrode 131 and can be formed on the upper surface of the first gate insulating film 112. The gate material layer GM can also be electrically connected to the second gate electrode 234 to form a dual gate. On the third interlayer insulating film 113d, the first source electrode 132 and the first drain electrode 133 of the driving transistor Td and the second source electrode 232 and the second drain electrode 233 of the switching transistor Ts can be disposed.

[0247] The second source electrode 232 and the second drain electrode 233 can be formed of the same material simultaneously on the third interlayer insulating film 113d together with the first source electrode 132 and the first drain electrode 133, thereby reducing the number of mask processes.

[0248] The first source electrode 132 and the first drain electrode 133 can be respectively connected to one side and the other side of the first active layer 134 through the contact holes provided in the third interlayer insulating film 113d, the second gate insulating film 113c, the second interlayer insulating film 113b, the first interlayer insulating film 113a and the first gate insulating film 112.

[0249] The second source electrode 232 and the second drain electrode 233 can be respectively connected to one side and the other side of the second active layer 234 through the contact holes provided in the third interlayer insulating film 113d and the second gate insulating film 113c.

[0250] The first source electrode 132, the first drain electrode 133, the second source electrode 232, and the second drain electrode 233 may be a single layer or a multilayer made of various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, but are not limited thereto.

[0251] The portion of the first active layer 134 that overlaps with the first gate electrode 131 is the channel region. One of the first source electrode 132 and the first drain electrode 133 is connected to one side of the channel region in the first active layer 134, and the other one is connected to the other side of the channel region in the first active layer 134. The second active layer 234 may be configured in the same form as the first active layer 134. When the second active layer 234 is implemented with an oxide semiconductor material, it includes an intrinsic second channel region not doped with impurities and a second source region and a second drain region doped with impurities and made conductive.

[0252] A passivation layer 114 may be disposed on the first source electrode 132, the first drain electrode 133, the second source electrode 232, and the second drain electrode 233. The passivation layer 114 is for protecting the driving transistor Td and may be made of an inorganic film, such as silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0253] On the other hand, a capacitor Cst can be implemented by disposing a gate material layer GM and a metal pattern TM to overlap on the first gate insulating film 112. The metal pattern TM may be a single layer or a multilayer made of any one of, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0254] The capacitor Cst stores the data voltage applied through the data line DL for a certain period and then provides it to the light-emitting element ED, 120. The capacitor Cst includes two electrodes corresponding to each other and a dielectric disposed therebetween. A first interlayer insulating film 113a is located between the gate material layer GM and the metal pattern TM.

[0255] In the capacitor Cst, the gate material layer GM or the metal pattern TM can be electrically connected to the switching transistor Ts, the second source electrode 232, or the second drain electrode 233. However, it is not limited thereto, and the connection relationship of the capacitor Cst can be changed by the pixel driving circuit.

[0256] Also, a metal layer 135 can be disposed on the multi-buffer layer 111a so as to further overlap the gate material layer GM and the metal pattern TM to form a double capacitor Cst.

[0257] In the embodiments of this specification, at least one switching transistor Ts uses an oxide semiconductor as an active layer. A transistor using an oxide semiconductor as an active layer has an excellent leakage current blocking effect and is relatively inexpensive in manufacturing cost compared to a transistor using polycrystalline silicon as an active layer. Therefore, in order to reduce power consumption and lower the manufacturing cost, the pixel circuit according to the embodiments of this specification includes a driving transistor or at least one switching transistor using an oxide semiconductor material.

[0258] Any of the transistors constituting the pixel circuit including the driving transistor can embody the active layer using an oxide semiconductor, or only some of the transistors can be embodied using an oxide semiconductor.

[0259] However, it is difficult to ensure the reliability of transistors using oxide semiconductors, and transistors using polycrystalline silicon have a high operating speed and excellent reliability. Therefore, the embodiments of this specification include both transistors using oxide semiconductors and transistors using polycrystalline silicon. However, the present invention is not limited thereto, and depending on the design, it is also possible to configure a pixel circuit by applying only transistors using oxide semiconductors or only transistors using polycrystalline silicon.

[0260] A planarization layer PLN may be located on top of the transistor layer TRL.

[0261] The planarization layer PLN can include a first planarization layer 115a and a second planarization layer 115b. The planarization layer PLN protects the driving transistor Td and planarizes its upper part.

[0262] The first planarization layer 115a can be disposed on the passivation layer 114.

[0263] A connection electrode 125 can be disposed on the first planarization layer 115a.

[0264] The connection electrode 125 can be connected to one of the first source electrode 132 and the first drain electrode 133 through a contact hole provided in the first planarization layer 115a.

[0265] A second planarization layer 115b can be disposed on the connection electrode 125.

[0266] An emission element layer EDL may be located on top of the second planarization layer 115b.

[0267] Hereinafter, the stacked structure of the emission element layer EDL will be examined in detail.

[0268] An anode 121 can be disposed on the second planarization layer 115b. At this time, the anode 121 can be electrically connected to the connection electrode 125 through a contact hole provided in the second planarization layer 115b. The anode 121 can be formed of a metallic material.

[0269] When the display device 100 is of the top emission type in which the light emitted by the light emitting elements ED, 120 is emitted above the substrate SUB on which the light emitting elements ED, 120 are arranged, the anode 121 can further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer can be made of a transparent conductive oxide such as, for example, ITO, IZO, etc., and the reflective layer can be made of, for example, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof, etc.

[0270] The bank 116 can be arranged while covering the anode 121. A portion of the bank 116 corresponding to the light emitting region of the sub-pixel can be open. A part of the anode 121 can be exposed in the open portion of the bank 116 (hereinafter referred to as the open region). At this time, the bank 116 can be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or an organic insulating material such as a benzocyclobutene-based resin, an acrylic-based resin, or an imide-based resin, but is not limited thereto.

[0271] Although not shown in the figure, spacers can be further located on the bank 116. The spacers can be made of the same material as the bank 116.

[0272] The light emitting layer 122 can be arranged in the open region of the bank 116 and its periphery. Thereby, the light emitting layer 122 can be arranged on the anode 121 exposed through the open region of the bank 116.

[0273] The cathode 123 can be arranged on the light emitting layer 122.

[0274] The light emitting elements ED, 120 can be formed by the anode 121, the light emitting layer 122, and the cathode 123. The light emitting layer 122 can include a number of organic films.

[0275] An encapsulation layer ENCAP may be located on top of the light emitting element layer EDL.

[0276] The encapsulation layer ENCAP may have a single-layer structure or a multi-layer structure. For example, the encapsulation layer ENCAP may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0277] In this case, the first and third sealing layers 117a and 117c may be made of an inorganic film, and the second sealing layer 117b may be made of an organic film. Among the first, second and third sealing layers 117a, 117b and 117c, the second sealing layer 117b is the thickest and may serve as a planarization layer.

[0278] The first encapsulation layer 117a may be disposed on the cathode 123 and may be disposed closest to the light emitting element ED, 120. The first encapsulation layer 117a may be formed of an inorganic insulating material that can be deposited at low temperatures. For example, the first encapsulation layer 117a may be composed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Since the first encapsulation layer 117a is deposited in a low temperature atmosphere, it is possible to prevent the light emitting layer 122, which includes organic matter that is vulnerable to high temperature atmospheres, from being damaged during the deposition process.

[0279] The second encapsulation layer 117b may be formed to have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b may play a role of buffering to relieve stress between layers due to warping of the flexible display device and to enhance planarization performance.

[0280] For example, the second sealing layer 117b may be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbon (SiOC), etc. For example, the second sealing layer 117b may be formed through an inkjet method, but is not limited thereto.

[0281] The third encapsulation layer 117c can be formed to cover the upper surfaces and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a on the upper part of the substrate SUB on which the second encapsulation layer 117b is formed. At this time, the third encapsulation layer 117c can minimize or block the penetration of external moisture and oxygen into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c can be composed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0282] Although not shown in the drawings, a color filter can be disposed on the encapsulation layer ENCAP, but is not limited thereto.

[0283] The touch sensing layer TSL can be disposed on the upper part of the above-described encapsulation layer ENCAP.

[0284] A touch buffer film 118a is disposed on the upper part of the encapsulation layer ENCAP, and a touch line 140 can be disposed on the touch buffer film 118a.

[0285] The touch line 140 can include a touch sensor metal 141 and a bridge metal 142 located in different layers. A touch interlayer insulating film 118b can be disposed between the touch sensor metal 141 and the bridge metal 142.

[0286] For example, the touch sensor metal 141 can include a first touch sensor metal, a second touch sensor metal, and a third touch sensor metal disposed adjacent to each other. The first touch sensor metal and the second touch sensor metal are electrically connected to each other. However, if there is a third touch sensor metal between the first touch sensor metal and the second touch sensor metal, the first touch sensor metal and the second touch sensor metal can be electrically connected through the bridge metal 142 in another layer. The bridge metal 142 can be insulated from the third touch sensor metal by the touch interlayer insulating film 118b.

[0287] When forming the touch sensing layer TSL, chemical solutions (such as developer or etchant) or external moisture used in the process may be generated. By disposing the touch buffer film 118a and arranging the touch sensing layer TSL thereon, it is possible to prevent chemical solutions, moisture, etc. during the manufacture of the touch sensing layer TSL from penetrating into the light emitting layer 122 containing organic substances. Accordingly, the touch buffer film 118a can prevent damage to the light emitting layer 122 that is vulnerable to chemical solutions or moisture.

[0288] The touch buffer film 118a can be formed of an organic insulating material that can be formed at a certain temperature (e.g., a low temperature of 100 °C or less) and has a low dielectric constant of 1 to 3 in order to prevent damage to the light emitting layer 122 containing organic substances that is vulnerable to high temperatures. For example, the touch buffer film 118a can be formed of a material of an acrylic series, an epoxy series, or a siloxane series. Due to the warping of the flexible display device, the encapsulation layer ENCAP may be damaged, and the touch sensor metal 141 located above the touch buffer film 118a may be cracked. Even if the flexible display device is warped, the touch buffer film 118a made of an organic insulating material and having a planarization performance can prevent damage to the encapsulation layer ENCAP and cracking of the metals 141 and 142 constituting the touch line 140.

[0289] The protective layer PAC, 119 can be disposed so as to cover the touch line 140. The protective layer 119 can be composed of an organic insulating film.

[0290] The organic layer PCL, 150 is disposed so as to cover the protective layer 119.

[0291] When only the protective layer 119 made of an organic insulating film is disposed on the uppermost layer of the display device 100, the protective layer 119 alone cannot perfectly complement the step caused by the touch sensing layer TSL disposed below the protective layer 119, and there may occur a problem that spots caused by the touch line 140 are visually recognized by the user.

[0292] By adding the organic layer 150 made of an organic insulating film on the upper part of the protective layer 119, it is possible to prevent a step on the uppermost layer of the display device 100 and improve the visibility of the display device 100.

[0293] The organic layer 150 can be formed of the same material as the second encapsulation layer 117b of the encapsulation layer ENCAP, and can be composed of an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or a silicon oxycarbide (SiOC), for example. The organic layer 150 may be formed through an inkjet method, but is not limited thereto.

[0294] A polarizing layer POL, 160 is disposed on the organic layer 150.

[0295] The polarizing layer 160 suppresses reflection of external light on the display area DA of the substrate SUB. When the display device 100 is used externally, external natural light may flow in and be reflected by the reflective layer included in the anode 121 of the light-emitting element, or may be reflected by the electrode made of metal disposed below the light-emitting element 120. The image of the display device 100 may not be visible due to the light reflected in this way. The polarizing layer 160 polarizes the light flowing in from the outside in a specific direction, and prevents the reflected light from being emitted outside the display device 100.

[0296] Although not shown, a cover glass may be adhered to the polarizing layer 160 by an adhesive layer. The adhesive layer can serve to adhere the components of the display device 100 to each other, and can be formed using an optically transparent display adhesive such as a pressure-sensitive adhesive, an optical clear adhesive (OCR), an optical clear resin (OCR), etc., but is not limited thereto.

[0297] The cover glass can protect the components of the display device 100 from external impacts and prevent damage such as scratches from occurring.

[0298] In the following, FIGS. 7 and 8 are both referred to for a more detailed description of the first optical region DA1 of the display device 100.

[0299] FIG. 7 is a cross-sectional view showing a cross-sectional structure of a light-emitting region and a transmissive region in an optical region according to an embodiment of the present specification. FIG. 8a is a diagram showing a positional relationship between a transmissive region and an anti-vapor deposition layer according to an embodiment of the present specification. FIG. 8b is an enlarged view showing an enlarged transmissive region according to an embodiment of the present specification.

[0300] In the following, for the sake of convenience of explanation, a case where the display region DA includes the general region NA and the first optical region DA1 in the display panel DP (FIGS. 1a and 1b) will be taken as an example for explanation. However, the explanation of the first optical region DA1 can be equally applied to the second optical region DA2.

[0301] Referring to FIG. 7, the first optical region DA1 includes a light-emitting region EA and a transmissive region TA.

[0302] Both the light-emitting region EA and the transmissive region TA of the first optical region DA1 can basically include a substrate SUB, a transistor layer TRL, a planarization layer PLN, a light-emitting element layer EDL, a sealing layer ENCAP, a touch sensor layer TSL, a protective layer PAC, an organic layer PCL, and a polarizing layer POL.

[0303] Since the substrate SUB, the transistor layer TRL, the planarization layer PLN, the light-emitting element layer EDL, the sealing layer ENCAP, the touch sensor layer TSL, the protective layer PAC, the organic layer PCL, and the polarizing layer POL included in the first optical region DA1 are substantially the same as the components having the same reference numerals arranged in the general region NA of the display panel DP, duplicate explanations will be omitted.

[0304] Since the light-emitting region EA in the first optical region DA1 is substantially the same as the structure of the general region NA of the display panel DP, duplicate explanations will be omitted.

[0305] In the following, the transmissive region TA arranged in the first optical region DA1 will be described.

[0306] The substrate SUB and various insulating films 111a, 111b, 112, 113a, 113b, 114, 115a, 115b, 117a, 117b, 117c, PAC disposed in the light-emitting region EA of the first optical region DA1 can also be identically disposed in the transmission region TA of the first optical region DA1.

[0307] However, except for the insulating substances disposed in the light-emitting region EA of the first optical region DA1, substance layers having electrical characteristics or opaque characteristics do not have to be disposed in the transmission region TA of the first optical region DA1.

[0308] According to one embodiment of the present specification, in order to ensure the transmittance of the transmission region TA, the cathode 123 is not disposed in the transmission region TA.

[0309] To embody this, an evaporation prevention layer 150 is disposed on the light-emitting layer 122 of the transmission region TA.

[0310] For example, the evaporation prevention layer 150 can be deposited using a mask (fine metal mask, FMM) so as to correspond to the transmission region TA. Specifically, after positioning the FMM so as to expose the transmission region TA, the evaporation prevention layer 150 can be formed.

[0311] When the cathode 123 is deposited after the evaporation prevention layer 150 is disposed on the light-emitting layer 122 of the transmission region TA, since the adhesion of the evaporation prevention layer 150 to the layer disposed on its upper part is low, the cathode 123 may not be deposited in the region where the evaporation prevention layer 150 is disposed.

[0312] Therefore, the cathode 123 does not have to be disposed in the transmission region TA according to one embodiment of the present specification.

[0313] Also, in the transmission region TA, the metal substance layers 135, 131, GM, TM, 132, 133, 125 related to the transistor and the semiconductor layer 134 are not disposed. Also, the anode 121 included in the light-emitting element 120 does not have to be disposed in the transmission region TA. Also, the touch line does not have to be disposed in the transmission region TA.

[0314] That is, since the transmission region TA of the first optical region overlaps with the optoelectronic device 170, in order for the optoelectronic device 170 to operate normally, the transmittance of the transmission region TA can be increased by not arranging opaque components such as metal electrodes in the transmission region TA.

[0315] Also, since no components such as metal electrodes are arranged in the transmission region TA of the first optical region DA1, the transmission region TA of the first optical region DA1 can be composed of only a flat layer.

[0316] On the other hand, if the cathode is removed to ensure the transmittance of the transmission region TA in the UDC model or the UDIR model, the UV reliability may become vulnerable. That is, pixel shrinkage defects in the light-emitting part may occur due to the generation of outgassing of organic substances caused by the transmission of UV light.

[0317] Therefore, according to an embodiment of the present specification, by removing a part of the organic substances in the transmission region TA to reduce the volume of the organic substances, the generation of outgassing of the organic substances due to the transmission of UV light can be suppressed.

[0318] According to an embodiment of the present specification, in the transmission region TA of the first optical region DA1, the lower surface of the light-emitting layer 122 may be in contact with the planarization layer PLN. That is, the bank 116 may not be arranged in the transmission region TA. Thereby, the volume of the organic substances arranged in the transmission region TA can be reduced.

[0319] For example, when reducing the volume of organic substances such as a bank in the transmission region, hereafter, the evaporation-preventing layer arranged in the transmission region can be arranged not only on the upper part of the light-emitting layer but also on the side surface of the bank. Since the adhesion force between the evaporation-preventing layer and the layer arranged above or below the evaporation-preventing layer is low, if there is a step at the lower part of the evaporation-preventing layer, the film may float due to the step.

[0320] Therefore, according to an embodiment of the present specification, in the optical region DA1, the anti-reflection layer 150 can be disposed on a flat surface. That is, according to an embodiment of the present specification, in the optical region DA1, the lower portion of the anti-reflection layer 150 can be flat, and the anti-reflection layer 150 may not overlap with the bank 116.

[0321] According to an embodiment of the present specification, since there is no step in the lower portion of the anti-reflection layer 150, it is possible to prevent the film from lifting due to the arrangement of the anti-reflection layer 150.

[0322] On the other hand, by disposing the anti-reflection layer 150, hereinafter, when the cathode 123 is deposited, the cathode 123 will not be disposed on the upper portion of the anti-reflection layer 150. That is, the cathode 123 can be disposed only in the light-emitting region EA of the optical region DA1. The side surface of the cathode 123 disposed in the light-emitting region EA and the side surface of the anti-reflection layer 150 disposed in the transmission region TA of the optical region DA1 may be in contact with each other, but are not limited thereto.

[0323] On the other hand, referring to both FIGS. 8A and 8B, the area of the transmission region TA and the area of the anti-reflection layer 150 may be the same. At this time, the thickness of the anti-reflection layer 150 may be constant.

[0324] That is, by disposing the anti-reflection layer 150 throughout the transmission region TA, an opaque electrode such as the cathode 123 is not disposed in the transmission region TA, and the transmittance can be improved.

[0325] Although FIG. 8A shows a structure in which the transmission region TA is triangular, the shape of the transmission region TA according to an embodiment of the present specification is not limited thereto. For example, the transmission region TA may have various patterns such as a circle, an ellipse, a rectangle, a hexagon, or an octagon.

[0326] Hereinafter, a display device according to another embodiment of the present specification will be described with reference to FIGS. 9 and 10.

[0327] FIG. 9 is a cross-sectional view showing a cross-sectional structure of a light-emitting region EA and a transmissive region TA in an optical region DA1 of a display device 200 according to another embodiment of the present specification. FIG. 10a is a diagram showing a positional relationship between the transmissive region TA and the anti-deposition layer 250 according to another embodiment of the present specification. FIG. 10b is an enlarged view showing an enlarged view of the transmissive region TA according to another embodiment of the present specification.

[0328] The display device of FIG. 9 has substantially the same configuration as the display devices of FIGS. 1 to 8 except for the anti-deposition layer 250. Therefore, for convenience of explanation, duplicate explanations are omitted.

[0329] Referring to FIGS. 9 and 10, the anti-deposition layer 250 according to an embodiment of the present specification may include a first portion 253 having a constant thickness and a second portion 255 disposed so as to surround the first portion and having a thickness thinner than that of the first portion.

[0330] At this time, the first portion 253 and the second portion 255 may be integrally formed and made of the same material.

[0331] For example, the thickness of the second portion 255 may decrease as it is farther from the first portion 253.

[0332] Specifically, according to another embodiment of the present specification, when forming the anti-deposition layer 250, the anti-deposition layer 250 is deposited using an FMM. At this time, considering the process margin, when the FMM is disposed so as to overlap a part of the flat surface of the transmissive region TA to form the anti-deposition layer 250, the region exposed by the FMM is formed in the first portion 253 having a constant thickness, and the region overlapping the FMM is formed in the second portion 255 whose thickness decreases as it is farther from the first portion 253 due to the process margin.

[0333] Referring to both FIGS. 10a and 10b, the area of the transmissive region TA may be the same as the area of the anti-deposition layer 250 composed of the first portion 253 and the second portion 255. At this time, the width w in FIG. 10a corresponds to the width w of the second portion 255 whose thickness decreases as it is farther from the first portion 253 in FIG. 10b.

[0334] Therefore, since the thickness of the second portion 255 decreases as it approaches the light-emitting region EA, the vapor deposition prevention layer 250 composed of the first portion 253 and the second portion 255 according to other embodiments of the present specification is not disposed at portions where steps are formed, such as the bank 116 disposed in the light-emitting region EA, and can be more easily disposed only on the flat surface of the optical region DA1.

[0335] According to other embodiments of the present specification, the effect of preventing the film from lifting due to the arrangement of the vapor deposition prevention layer 250 can be further improved.

[0336] FIG. 11 is a plan view showing a first optical region of a flexible display device according to another embodiment of the present specification. FIG. 12 is an enlarged view showing the X region of FIG. 11.

[0337] First, referring to FIG. 11, the first optical region DA1 may include a central region 310 and a bezel region 320 located on the outer periphery of the central region 310.

[0338] The first optical region DA1 may include a plurality of horizontal lines HL. Transistors located in the bezel region 320 and light-emitting elements located in the central region 310 may be connected by the plurality of horizontal lines HL.

[0339] The flexible display device 300 according to the embodiment may include a routing structure 340. By including the routing structure 340, the central region 310 can be expanded by a predetermined region a. This is because pixels located in the predetermined region a can be connected to transistors located in the bezel region 320 by the routing structure 340.

[0340] Specifically examining the structure of the first optical region DA1 including the routing structure 340, it is as follows.

[0341] Referring to FIG. 12, the first optical region may include a central region 310 and a plurality of light-emitting elements ED located in the bezel region 320. By including the plurality of light-emitting elements ED in the first optical region, the first optical region can display an image.

[0342] The first optical region can include a plurality of transistors 350 located in the bezel region 320. The central region 310 may not have transistors 350 located therein. By not having transistors located in the central region 310, the central region 310 can have a higher transmittance.

[0343] The first optical region includes a plurality of rows, and can include a first row R1 and a second row R2. The plurality of rows included in the first optical region can be any region that horizontally crosses the first optical region and can be defined by the pattern of the transistors 350.

[0344] The flexible display device can include a light-emitting element ED located in the central region 310 and at the first row R1, and a transistor 350 located in the bezel region 320 and at the second row R2.

[0345] The flexible display device can include a routing structure 340 that electrically connects the light-emitting element ED located at the first row R1 and the transistor 350 located at the second row R2.

[0346] Due to the routing structure 340, the transistors 350 and the light-emitting elements ED located in different rows can be connected to each other. Thus, the transistors 350 located in the row where a larger number of transistors 350 are arranged than the light-emitting element ED, and the light-emitting elements ED located in the row where a larger number of light-emitting elements ED are arranged than that can be connected to each other.

[0347] The number of light-emitting elements ED included in the central region 310 in the first row R1 can be even larger than the number of light-emitting elements ED included in the central region 310 in the second row R2. Therefore, a larger number of transistors 350 are required to drive the light-emitting elements ED included in the first row R1, and a smaller number of transistors 350 are required to drive the light-emitting elements ED included in the second row R2. Accordingly, surplus transistors 350 that are not electrically connected to the light-emitting elements ED located in the second row R2 among the transistors 350 located in the second row R2 of the bezel region 320 can be electrically connected to the light-emitting elements ED located in the first row R1 by the routing structure 340.

[0348] The central region 310 may have substantially the same number of pixels per unit area throughout the central region 310. Having substantially the same number of pixels per unit area may mean, for example, that one pixel pattern is substantially uniform throughout the central region 310. Therefore, more light-emitting elements ED can be located in the first row R1, whose area overlapping with the central region 310 is larger than that of the second row R2.

[0349] For example, the number of transistors 350 included in the bezel region 320 in the first row R1 can be substantially the same as the number of transistors 350 included in the bezel region 320 in the second row R2. In the above example, if the number of light-emitting elements ED included in the central region 310 in the first row R1 is even larger and the number of light-emitting elements ED included in the central region 310 in the second row R2 is even smaller, some of the transistors 350 included in the second row R2 may not be electrically connected to the light-emitting elements ED located in the second row R2 and can be electrically connected to the light-emitting elements ED located in the first row R1.

[0350] And the bezel region 320 may have substantially the same number of transistors 350 per unit area throughout the bezel region 320. Having substantially the same transistor pattern per unit area may mean that one transistor pattern is substantially uniform throughout the bezel region 320.

[0351] The area of the region where the bezel region 320 overlaps with the first row R1 may be substantially the same as the area of the region where the bezel region 320 overlaps with the second row R2. In such an example, the number of transistors 350 located in the first row R1 of the bezel region 320 may be substantially the same as the number of transistors 350 located in the second row R2 of the bezel region.

[0352] In such a case of the bezel region 320, the number of transistors 350 located in the rows of the bezel region 320 may be kept constant, and the excess transistors in a specific row may be electrically connected to the excess light-emitting elements in other rows by the routing structure 340. Thus, the flexible display device according to the embodiment can have a wider central region 310 than the flexible display device of the comparative example.

[0353] The display devices according to various embodiments of the present specification may be described as follows.

[0354] A display device according to an embodiment of the present specification includes a substrate including a display region including an optical region including a light-emitting region and a transmissive region and a general region surrounding the optical region and a non-display region, a planarization layer disposed on the substrate in the display region, a plurality of light-emitting elements disposed on the planarization layer and including an anode, a light-emitting layer, and a cathode, a bank disposed on the planarization layer so as to cover an end of the anode, and an anti-reflection layer disposed on the light-emitting layer in the transmissive region of the light-emitting region and the transmissive region in the optical region, and the bank is disposed in the light-emitting region of the light-emitting region and the transmissive region in the optical region.

[0355] According to another feature of the present specification, it may further include an optoelectronic device disposed below the substrate in the optical region.

[0356] According to another feature of the present specification, in the transmissive region of the optical region, the anti-reflection layer may be disposed on a flat surface.

[0357] According to another feature of the present specification, in the transmissive region of the optical region, the lower surface of the light-emitting layer may be in contact with the planarization layer.

[0358] According to other features of this specification, in the optical region, the anti-deposition layer and the bank may not overlap with each other.

[0359] According to other features of this specification, the side surface of the cathode disposed in the light-emitting region of the optical region and the side surface of the anti-deposition layer disposed in the transmissive region of the optical region may be in contact with each other.

[0360] According to other features of this specification, the anti-deposition layer may have a constant thickness.

[0361] According to other features of this specification, the anti-deposition layer may include a first portion having a constant thickness and a second portion disposed so as to surround the first portion and having a thickness thinner than that of the first portion.

[0362] According to other features of this specification, the thickness of the second portion may decrease as it is farther from the first portion.

[0363] According to other features of this specification, the first portion and the second portion may be integrally formed and made of the same material.

[0364] As described above, with reference to the accompanying drawings, the embodiments of this specification have been described in more detail. However, this specification is not necessarily limited to such embodiments, and various modifications can be made within the scope not departing from the technical idea of this specification. Therefore, the embodiments disclosed in this specification are not for limiting the technical idea of this specification, but for explaining it, and the scope of the technical idea of this specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. The protection scope of this specification should be interpreted according to the following claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of this specification.

Claims

1. A substrate including a display area including an optical area including a light-emitting area and a transmissive area and a general area surrounding the optical area, and a non-display area; A planarization layer disposed on the substrate in the display area; A plurality of light-emitting elements disposed on the planarization layer and including an anode, a light-emitting layer, and a cathode; A bank disposed on the planarization layer so as to cover an end of the anode; and Including an anti-deposition layer disposed on the light-emitting layer in the transmissive area of the light-emitting area and the transmissive area of the optical area, The bank is disposed in the light-emitting area of the optical area among the light-emitting area and the transmissive area of the optical area, The cathode is not disposed in the transmissive area, a display device.

2. The display device according to claim 1, further including an optoelectronic device disposed below the substrate in the optical area.

3. In the transmissive area of the optical area, the anti-deposition layer is disposed on a flat surface, the display device according to claim 1.

4. In the transmissive area of the optical area, a lower surface of the light-emitting layer is in contact with the planarization layer, the display device according to claim 1.

5. In the optical area, the anti-deposition layer and the bank do not overlap each other, the display device according to claim 1.

6. A side surface of the cathode disposed in the light-emitting area of the optical area and a side surface of the anti-deposition layer disposed in the transmissive area of the optical area are in contact with each other, the display device according to claim 1.

7. The anti-deposition layer has a constant thickness, the display device according to claim 1.

8. The anti-deposition layer is A first portion having a constant thickness; and The display device according to claim 7, comprising a second portion disposed so as to surround the first portion and having a thickness thinner than that of the first portion.

9. The display device according to claim 8, wherein the thickness of the second portion decreases as the distance from the first portion increases.

10. The display device according to claim 8, wherein the first portion and the second portion are integral and made of the same material.

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