Semiconductor device and electronic equipment

Abstract

Provided is a semiconductor device capable of improving the capacitance density of a capacitive element without lowering an operating voltage. The semiconductor device comprises: a first semiconductor substrate that has a first capacitive element part including at least one capacitive element; a second semiconductor substrate that is laminated on the first semiconductor substrate; and a second capacitive element part that is formed by a metal joint part provided on a joint surface between the first semiconductor substrate and the second semiconductor substrate. The first and second capacitive element parts are connected in parallel with each other.

Description

Technical Field

[0001] The technology related to the present disclosure (this technology) relates to a semiconductor device and an electronic device including the semiconductor device.

Background Art

[0002] As solid-state imaging devices for imaging an image, for example, there are a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor. However, a CMOS image sensor that can be manufactured by an existing CMOS process without requiring special capital investment has attracted attention, and its adoption in a camera system built in a mobile phone or a monitoring system has been rapidly progressing.

[0003] As the application of CMOS image sensors to various fields has advanced, miniaturization and high performance have been required. Therefore, in order to achieve such requirements, a stacked CMOS image sensor has been proposed in which a sensor part and a peripheral circuit part are formed on different wafers, and these wafers are bonded together using the WoW technology to provide a function as an image sensor (Patent Document 1).

[0004] In the above-described stacked CMOS image sensor, incident light is received by the sensor part, and photoelectric conversion is performed by a photodiode in the sensor part. The charge generated by the photodiode is subjected to analog / digital conversion into a pixel signal by the peripheral circuit part. Here, in the peripheral circuit part, a coupling capacitor for blocking the DC component of the input signal is used.

[0005] The coupling capacitor can be miniaturized as the capacitance density (capacitance value per unit area) of the capacitive element used is larger, but it is required that the bias dependence of the capacitance value is small. This is because if the bias dependence of the capacitance value is large, for example, the pixel signal and the reference signal transmitted to the gate electrode of the differential input transistor of the comparator are distorted, and the accuracy of analog-to-digital conversion is significantly deteriorated.

[0006] Also, the transition to finer CMOS processes for manufacturing peripheral circuit parts has been progressing. However, even when transitioning to finer processes, logic circuits that process digital signals composed of MOSFETs such as SRAM and logic circuits can be miniaturized, but miniaturization of analog circuits that process analog signals output from the sensor unit is not easy. The reason is that the performance of an image sensor is better as the maximum charge amount that can be read out by the sensor unit is larger. However, since the detected charge amount is converted into voltage and propagated through the circuit, as long as the performance of the maximum charge amount is maintained even as the generation of the manufacturing process is miniaturized, the operating voltage of the devices that make up the analog circuit that receives the signal from the sensor unit does not decrease, and the devices themselves cannot be miniaturized according to the scaling law.

[0007] As for the capacitor elements formed on the semiconductor substrate, the use of MOS-type capacitor elements shown in Patent Document 2, comb-shaped wiring capacitor elements shown in Patent Document 3, and MIM (Metal Insulator Metal) capacitor elements shown in Patent Document 4 has been proposed. The capacitance density of MOS-type capacitor elements and MIM capacitor elements is almost determined by the film thickness (d) and the dielectric constant (ε) of the gate insulating film (ε / d). As a method for increasing the capacitance density, increasing the dielectric constant increases the manufacturing cost. Generally, a method of reducing the film thickness is used. However, if the film thickness of the insulating film is reduced without lowering the operating voltage of the capacitor element, TDDB (Time Dependent Dielectric Breakdown), which is the lifetime of the insulating film, deteriorates, and the product lifetime becomes short.

[0008] In addition, the comb-shaped wiring capacitive element is an element that utilizes the parasitic capacitance formed by opposing wirings as a capacitive element. However, in order to increase the capacitance density, it is necessary to narrow the space between the wirings. However, if the wiring space is narrowed without lowering the operating voltage of the capacitive element, the TDDB of the insulating film between the wiring spaces deteriorates and the product life becomes short. In addition, as the process miniaturization progresses, a Low-K film with a lower dielectric constant is used for the insulating film covering the wiring layer, which is also a cause for the capacitance value of the comb-shaped wiring capacitive element not increasing. In addition, regarding the MIM capacitive element as disclosed in Patent Document 4, the reliability of the insulating film becomes an issue as in the case of the MOS-type capacitive element described above, and the capacitance density cannot be improved.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0010] As described above, there is a strong demand for a technology that can dramatically increase the capacitance density of a capacitive element without lowering its operating voltage.

[0011] The present disclosure has been made in view of such circumstances, and an object thereof is to provide a semiconductor device and an electronic device capable of improving the capacitance density of a capacitive element without lowering the operating voltage.

Means for Solving the Problems

[0012] One aspect of the present disclosure is a semiconductor device including a first semiconductor substrate having a first capacitor element portion including at least one capacitor element, a second semiconductor substrate laminated on the first semiconductor substrate, and a second capacitor element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, wherein the first and second capacitor element portions are connected in parallel to each other.

[0013] Another aspect of the present disclosure is an electronic device including a semiconductor device including a first semiconductor substrate having a first capacitor element portion including at least one capacitor element, a second semiconductor substrate laminated on the first semiconductor substrate, and a second capacitor element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, wherein the first and second capacitor element portions are connected in parallel to each other.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to below, the same or similar parts are denoted by the same or similar reference numerals, and duplicate descriptions are omitted. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0016] In this specification, "the first conductivity type" is one of p-type or n-type, and "the second conductivity type" means one different from "the first conductivity type" among p-type or n-type. Also, the "+" and "-" attached to "n" and "p" respectively mean semiconductor regions with relatively high or low impurity densities compared to the semiconductor regions without the attached "+" and "-". However, even for semiconductor regions with the same "n" and "n" attached, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same.

[0017] Also, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated by 90° and observed, up and down are read as left and right, and if it is rotated by 180° and observed, up and down are read in reverse, which goes without saying. Note that the effects described in this specification are merely illustrative and not limiting, and there may be other effects.

[0018] <First Embodiment> <Overall Configuration of Solid-State Imaging Device> As a first embodiment, the case where the semiconductor device according to the present technology is applied to a solid-state imaging device (CMOS image sensor) is exemplified. As shown in FIG. 1, the solid-state imaging device 100 according to the first embodiment includes a pixel array unit 110 and a peripheral circuit that reads an electrical signal from the pixel array unit 110 and performs predetermined signal processing.

[0019] The solid-state imaging device 100 according to the first embodiment includes, as a peripheral circuit, a row selection circuit 120 that controls a row address and row scanning, a horizontal transfer scanning circuit 130 that controls a column address and column scanning, and a timing control circuit 140 that generates an internal clock as a control circuit. Further, the solid-state imaging device 100 according to the first embodiment includes, as a peripheral circuit, an ADC group 150, a digital-to-analog conversion device (DAC) 160 as a ramp signal generator, an amplifier circuit 170, a signal processing circuit 180, and a horizontal transfer line 190. Further, the solid-state imaging device 100 according to the first embodiment includes, as a peripheral circuit, a DC power supply circuit (not shown).

[0020] As shown in FIG. 2, the pixel array unit 110 is configured by arranging a large number of pixels 30 in an array (matrix) form. As shown in FIG. 3, for example, the pixel 30 has a photoelectric conversion element D1 composed of, for example, a photodiode (PD). The pixel 30 has four transistors, namely, a transfer transistor T1, a reset transistor T2, an amplification transistor T3, and a selection transistor T4, as active elements with respect to the photoelectric conversion element D1. Further, in order to extract the signal from the pixel 30 as a voltage fluctuation, a constant current source load Z1 is connected to a vertical signal line (LSGN) shared by the pixels 30 in the column direction.

[0021] The photoelectric conversion element D1 photoelectrically converts incident light into an amount of electric charge (here, electrons) corresponding to the amount of the light. The transfer transistor T1 as a transfer element is connected between the photoelectric conversion element D1 and a floating diffusion FD as an input node, and a transfer signal TRG, which is a control signal, is applied to its gate (transfer gate) through a transfer control line LTRG. Thereby, the transfer transistor T1 transfers the electrons photoelectrically converted by the photoelectric conversion element D1 to the floating diffusion FD.

[0022] The reset transistor T2 is connected between a power supply line LVDD to which a power supply voltage VDD is supplied and the floating diffusion FD, and a reset signal RST, which is a control signal, is applied to its gate through a reset control line LRST. Thereby, the reset transistor T2 as a reset element resets the potential of the floating diffusion FD to the potential of the power supply line LVDD.

[0023] The gate of the amplification transistor T3 as the amplification element is connected to the floating diffusion FD. That is, the floating diffusion FD functions as the input node of the amplification transistor T3 as the amplification element. The amplification transistor T3 and the selection transistor T4 are connected in series between the power supply line LVDD to which the power supply voltage VDD is supplied and the signal line LSGN. In this way, the amplification transistor T3 is connected to the signal line LSGN via the selection transistor T4, and constitutes a constant current source IS outside the pixel portion and a source follower. Then, a selection signal SEL, which is a control signal corresponding to the address signal, is applied to the gate of the selection transistor T4 through the selection control line LSEL, and the selection transistor T4 is turned on. When the selection transistor T4 is turned on, the amplification transistor T3 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line LSGN. Through the signal line LSGN, the voltages output from the respective pixels are output to the ADC group 150. These operations are performed simultaneously for each pixel in one row because, for example, the gates of the transfer transistor T1, the reset transistor T2, and the selection transistor T4 are connected in row units.

[0024] The reset control line LRST, the transfer control line LTRG, and the selection control line LSEL wired in the pixel array unit 110 are wired in units of each row of the pixel array as a set. M reset control lines LRST, M transfer control lines LTRG, and M selection control lines LSEL are provided respectively. These reset control line LRST, transfer control line LTRG, and selection control line LSEL are driven by the row selection circuit 120.

[0025] By the way, a decoupling capacitor CV1 is connected between the power supply line LVDD and the ground (GND). The decoupling capacitor CV1 removes the noise components mixed in the DC power supply voltage supplied to drive the circuit. The total area of this decoupling capacitor CV1 may exceed 10 mm 2 and the ratio it occupies in the chip area of the stacked CMOS image sensor is large.

[0026] The ADC group 150 shown in FIG. 1 is an array of multiple columns of single-slope ADCs each having a comparator 151, a counter 152, and a latch 153. The comparator 151 has a differential amplifier circuit including differential input transistors T21 and T22 forming a differential pair and active load transistors T11 and T12 composed of a current mirror circuit, as shown in FIG. 4, for example. The differential input transistors T21 and T22 are composed of n-type MOSFETs (hereinafter also referred to as "nMOS"), and the active load transistors T11 and T12 are composed of p-type MOSFETs (hereinafter also referred to as "pMOS"). In the peripheral circuit of the solid-state imaging device according to the first embodiment, the active load transistors T11 and T12 and the differential input transistors T21 and T22 serve as noise sources.

[0027] Sampling capacitors C1 and C2 are connected in series to the two differential input terminals of the comparator 151, respectively. The comparator 151 compares a reference voltage (DAC-side input) Vslop, which is a ramp waveform with the reference voltage generated by the DAC 160 changed stepwise, with an analog signal (VSL (Vertical Signal Line)-side input) obtained from the pixel via the vertical signal line LSGN for each row line.

[0028] The counter 152 shown in FIG. 1 counts the comparison time of the comparator 151. The ADC group 150 has an n-bit digital signal conversion function, is arranged for each vertical signal line (column line), and forms a column-parallel ADC block. The output of each latch 153 is connected to, for example, a horizontal transfer line 190 with a 2n-bit width. Then, 2n amplifier circuits 170 corresponding to the horizontal transfer line 190 and a signal processing circuit 180 are arranged.

[0029] The sampling capacitances C1 and C2 shown in FIG. 4 can be miniaturized as the capacitance density (capacitance value per unit area) of the capacitance elements to be used increases, but it is required that the bias dependence of the capacitance value be small. If the bias dependence of the capacitance value is large, for example, the pixel signals and reference signals transmitted to the gate electrodes of the differential input transistors of the comparator will be distorted, and the accuracy of analog-to-digital conversion will deteriorate significantly. Also, a decoupling capacitor CV2 is connected between the power supply line Vdd and the ground (GND) of the comparator 151.

[0030] Therefore, in the first embodiment of the present disclosure, even when the solid-state imaging device 100 is miniaturized, a capacitance element with a small bias dependence of the capacitance value and a large capacitance density is realized without reducing the operating voltage. FIG. 5 shows an arrangement diagram on the semiconductor chip of each circuit constituting the solid-state imaging device 100 according to the first embodiment. The solid-state imaging device 100 according to the first embodiment is a stacked-type image sensor in which two semiconductor chips, an upper semiconductor substrate 210 and a lower semiconductor substrate 220, are stacked, and a part of the wirings of the upper and lower chips are electrically connected by a metal bonding portion MC1 such as a through-silicon via (TSV). In this case, a pixel array portion 110 in which pixels 30 are arranged in a matrix is mounted on the upper semiconductor substrate 210, and peripheral circuits such as an ADC group 150 and a signal processing circuit 180 other than the pixel array portion 110 are mounted on the lower semiconductor substrate 220.

[0031] FIG. 6 is a cross-sectional view of the solid-state imaging device 100 according to the first embodiment. FIG. 6(a) shows the outside of the pixel, and FIG. 6(b) shows the inside of the pixel. In FIG. 6, the upper semiconductor substrate 210 is composed of a photoelectric conversion layer 211, an inter-brow insulating film 213, and a wiring layer 214 from top to bottom. The photoelectric conversion layer 211 is a layer in which a photodiode (PD) 31 is formed, and generates charges corresponding to the amount of incident light through photoelectric conversion. The PD 31 is electrically separated by element isolation parts 33a and 33b formed in the photoelectric conversion layer 211 for each pixel 30. Also, a p-type well 32 is formed in a region where the PD 31 is not formed in the photoelectric conversion layer 211. An FD 34 and an n-type diffusion layer 35 are formed in the p-type well 32. Note that outside the pixel 30, as shown in FIG. 6(a), only the p-type well 32 remains.

[0032] The charges generated in the PD 31 are transferred to the FD 34 through a transfer transistor T1 provided in the inter-brow insulating film 213. Near the n-type diffusion layer 35, an amplification transistor T3 provided in the inter-brow insulating film 213 is located. Element isolation parts 33b and 33c are formed at both ends of the n-type diffusion layer 35. Thereby, the FD 34 and the pixel transistor T3 are electrically separated by the n-type diffusion layer 35 and the element isolation parts 33b and 33c.

[0033] The wiring layer 214 is configured to include wirings (M1 to M4) 215 laminated in a plurality of layers. Through the plurality of layers of wirings (M1 to M4) 215 formed in the wiring layer 214, the transfer transistor T1, the reset transistor T2, the amplification transistor T3, and the selection transistor T4 constituting each pixel 30 are driven. Also, a metal bonding part 231 made of copper (Cu) is provided in the wiring layer 214 for bonding with the lower semiconductor substrate 220.

[0034] On the other hand, the lower semiconductor substrate 220 is composed of an inter-brow insulating film 221 and a wiring layer 222 from top to bottom. The wiring layer 222 is configured to include all wirings 223 and wirings (M1 to M6) 224 laminated in a plurality of layers. Also, a metal bonding part 232 made of copper (Cu) for bonding with the metal bonding part 231 of the upper semiconductor substrate 210 is provided in the inter-brow insulating film 221.

[0035] In the solid-state imaging device 100 having the above configuration, when the light incident on the upper semiconductor substrate 210 is photoelectrically converted by the PD 31, charges are generated. Then, the generated charges are output as pixel signals to the ADC group 150 formed on the lower semiconductor substrate 220 through the signal line LSGN shown in FIG. 1 formed by the wirings (M1 to M4) 215 and the wirings (M1 to M6) 224 of the lower semiconductor substrate 220 via the amplification transistor T3.

[0036] As shown in FIG. 6(a), an N+ accumulation type MOS capacitor element 310 is arranged on the lower semiconductor substrate 220. As shown in FIG. 7, in this MOS capacitor element 310, if the electrode closer to the mounted lower semiconductor substrate 220 side is the lower electrode 312, for example, the lower electrode 312 mounted on the element isolation portion 311 is an n-type diffusion layer formed in the p-type well 228, and there is a gate insulating film 316 made of silicon oxide (SiO2) on the lower electrode 312, and an upper electrode 313 made of n-type polycrystalline silicon is formed on the gate insulating film 316. Since electrons are accumulated on the surface of the lower electrode 312 during operation, this MOS capacitor element 310 is called an N+ accumulation type MOS capacitor.

[0037] In the region where the wirings (M1 to M6) 224, which are the upper layer in the same region where the MOS capacitor element 310 is arranged, are formed, a MIM (Metal Insulator Metal) capacitor element 320 formed by laminating a lower electrode 322 located closer to the lower semiconductor substrate 220 side, an insulating film (including a High-K material), and an upper electrode 321 is mounted. This insulating film is a single-layer film or a plurality of laminated films of any one of Ta2O2, Nb2O3, ZrO2, HfO2, La2O3, Pr2O3, AL2O3, SiO2, and SiN. As shown in FIG. 9, the lower electrode 322 and the upper electrode 321 are a single-layer film or a plurality of laminated films of any one of Cu, Al, Ti, TiN, Ta, and TaN.

[0038] The wiring (M5) 224 is provided with a negative (Minus) terminal 225 and a positive (Plus) terminal 226. Also, on the lower semiconductor substrate 220, using wirings (M1 to M4) 224, the MOM capacitor element 330 shown in FIG. 8 is formed. These N+ accumulation type MOS capacitor elements 310, MIM capacitor elements 320, and MOM capacitor elements 330 are connected in parallel. In this case, the upper electrode 331 of the MOM capacitor element 330 is connected to the lower electrode 312 of the MOS capacitor element 310, the lower electrode 322 of the MIM capacitor element 320, via vias 315 and wiring (M6) 224. Also, the lower electrode 332 of the MOM capacitor element 330 is connected to the upper electrode 313 of the MOS capacitor element 310, the upper electrode 321 of the MIM capacitor element 320, via vias 314 and wiring (M6) 224. By adopting such a structure, it becomes possible to further increase the capacitance density.

[0039] The upper semiconductor substrate 210 is composed of a p-type well 32, an interlayer insulating film 213, and a wiring layer 214 from above. Below the upper semiconductor substrate 210, an N+ accumulation type MOS capacitor element 410 is arranged. In this MOS capacitor element 410, the lower electrode 412 is an n-type diffusion layer formed in the p-type well 32. On the lower electrode 412, there is a gate insulating film 416 made of silicon oxide (SiO2). On the gate insulating film 416, an upper electrode 413 made of n-type polycrystalline silicon is formed.

[0040] In the same region where the MOS capacitor element 410 is arranged, in the region where the wirings (M1 to M4) 215 are formed, a MOM capacitor element 420 serving as a comb-shaped wiring capacitor is formed using the wirings (M1 to M4) 215. In this case, the upper electrode of the MOM capacitor element 420 is connected to the upper electrode 413 of the MOS capacitor element 410 via a via 414. Also, the lower electrode of the MOM capacitor element 420 is connected to the lower electrode 412 of the MOS capacitor element 410 via a via 415.

[0041] Furthermore, the upper electrodes of the MOS capacitor element 410 and the MOM capacitor element 420 are connected to the upper electrode 313 of the MOS capacitor element 310 on the lower semiconductor substrate 220 side, the upper electrode 321 of the MIM capacitor element 320, and the upper electrode of the MOM capacitor element 330 via the metal joints 231 and 232 made of copper (Cu). Also, the lower electrodes of the MOS capacitor element 410 and the MOM capacitor element 420 are connected to the lower electrode 312 of the MOS capacitor element 310 on the lower semiconductor substrate 220 side, the lower electrode 322 of the MIM capacitor element 320, and the lower electrode of the MOM capacitor element 330 via the metal joints 231 and 232 made of copper (Cu).

[0042] In FIG. 6, the solid-state imaging device 100 forms a capacitor element by joining the metal joint 231 on the upper semiconductor substrate 210 side and the metal joint 232 on the lower semiconductor substrate 220 side disposed on the bonding surface, and further increases the capacitance density by connecting it in parallel with other capacitor elements. This capacitor element is called the joint capacitor element 230.

[0043] The upper electrode 234 of the joint capacitor element 230 is connected to the upper electrode 413 of the MOS capacitor element 410, the upper electrode of the MOM capacitor element 420, and via the via 414. Also, the lower electrode 235 of the joint capacitor element 230 is connected to the lower electrode 412 of the MOS capacitor element 410, the lower electrode of the MOM capacitor element 420, and via the via 415.

[0044] Furthermore, the upper electrode 234 of the joint capacitor element 230 is connected to the upper electrode 313 of the MOS capacitor element 310 on the lower semiconductor substrate 220 side, the upper electrode 321 of the MIM capacitor element 320, and the upper electrode of the MOM capacitor element 330. Also, the lower electrode 235 of the joint capacitor element 230 is connected to the lower electrode 312 of the MOS capacitor element 310 on the lower semiconductor substrate 220 side, the lower electrode 322 of the MIM capacitor element 320, and the lower electrode of the MOM capacitor element 330.

[0045] <Operational Effects of the First Embodiment> According to the first embodiment as described above, the junction capacitance element 230 is formed by the metal bonding portions 231 and 232 between the upper semiconductor substrate 210 and the lower semiconductor substrate 220, and this junction capacitance element 230 is provided in the upper semiconductor substrate 210 with the MOS capacitance element 410 and the MOM capacitance element 420, and the MOS capacitance element 310, the MIM capacitance element 320, and the MOM capacitance element 330 provided in the lower semiconductor substrate 220 are connected in parallel, so that the capacitance value of the entire capacitance element can be increased. Therefore, it is possible to improve the capacitance density of the capacitance element without reducing the operating voltage.

[0046] <Modification Example of the First Embodiment> FIG. 10 is a cross-sectional view of the solid-state imaging device 100 according to a modification example of the first embodiment. In FIG. 10, the same parts as those in FIG. 6(a) are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0047] In FIG. 10, the solid-state imaging device 100 is an example using a PIP (Poly Insulator Poly) capacitance element 340. As shown in FIG. 11, the PIP capacitance element 340 is a capacitance element using polycrystalline silicon as an electrode. For example, it is a capacitance element formed by sequentially laminating N-type polycrystalline Si serving as a lower electrode 342, SiO2 serving as an insulating film, and N-type polycrystalline Si serving as an upper electrode. As a feature, the bias dependence of the capacitance value is small.

[0048] The upper electrode 343 of the PIP capacitance element 340 is connected to the upper electrode 321 of the MIM capacitance element 320 via the via 314 and the wiring (M6) 224. Also, the lower electrode 342 of the PIP capacitance element 340 is connected to the lower electrode 322 of the MIM capacitance element 320 via the via 315 and the wiring (M6) 224. Therefore, even in the modification example of the first embodiment, the same operational effects as those of the first embodiment can be obtained.

[0049] <Second Embodiment> FIG. 12 is a cross-sectional view of the solid-state imaging device 100 according to the second embodiment. In FIG. 12, the same parts as those in FIG. 6(a) are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0050] In FIG. 12, the solid-state imaging device 100 forms a junction capacitance element 510 by joining a metal bonding portion 511 on the upper semiconductor substrate 210 side and a metal bonding portion 512 on the lower semiconductor substrate 220 side disposed on the bonding surface. In the second embodiment, the capacitance value of the capacitance element of the solid-state imaging device 100 can be further increased by bringing the upper electrode 514 and the lower electrode 515 of the junction capacitance element 510 closer to each other to a distance allowable by the processing accuracy of the process, thereby increasing the lateral capacitance component.

[0051] <Operational Effects of the Second Embodiment> As described above, according to the second embodiment, in the junction capacitance element 510, by utilizing the capacitance component in the direction (Y direction in FIG. 12) orthogonal to the stacking direction (Z direction in FIG. 12) of the upper semiconductor substrate 210 and the lower semiconductor substrate 220, that is, the lateral direction, the capacitance value can be further increased.

[0052] <First Modification of the Second Embodiment> FIG. 13 is a plan view showing an arrangement example of the junction capacitance element 510 as a first modification of the second embodiment of the present technology. As shown in FIG. 13, by stretching and opposing vias 516 connected to the metal bonding portion, the capacitance value can be further increased by utilizing the lateral capacitance component of the vias 516. Note that even in the arrangement examples of the junction capacitance element 510 shown in FIGS. 14 and 15, the capacitance value can be further increased.

[0053] <Second Modification of the Second Embodiment> FIG. 16 is a cross-sectional view of the solid-state imaging device 100 according to a second modification of the second embodiment of the present technology. In FIG. 16, the same parts as those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0054] In FIG. 16, the solid-state imaging device 100 forms a junction capacitance element 520 by joining the first metal films 521 and 523 on the upper semiconductor substrate 210 side and the second metal films 522 and 524 on the lower semiconductor substrate 220 side, which are arranged on the bonding surface. The problem with the junction capacitance element 520 is that if the misalignment is large when the upper semiconductor substrate 210 (sensor section) and the lower semiconductor substrate 220 (peripheral circuit section) are joined, the variation in capacitance values will become large. However, by adopting the layout shown in FIG. 17, the variation in capacitance values with respect to the joining misalignment can be reduced. The specific layout has a ring-shaped first electrode 525 and a second electrode 526 located at the center thereof. The inner diameter of the first metal film 521 constituting the first electrode 525 is larger than the inner diameter of the second metal film 522 constituting the first electrode 525. Also, the outer diameter of the first metal film 523 constituting the second electrode 526 is larger than the outer diameter of the second metal film 524 constituting the second electrode 526. Although FIG. 17 shows a square layout for the first electrode 525 and the second electrode 526 of the junction capacitance element 520, it may be circular.

[0055] By adopting such a layout, as shown in FIG. 18, for example, when the upper semiconductor substrate 210 (sensor section) is displaced to the left with respect to the lower semiconductor substrate 220 (peripheral circuit section), the capacitance value of the left side surface of the junction capacitance element 520 increases, but the capacitance value of the right side surface decreases. Therefore, the variation in the capacitance value of the entire junction portion can be made small.

[0056] Also, when the upper semiconductor substrate 210 (sensor section) is displaced to the right with respect to the lower semiconductor substrate 220 (peripheral circuit section), the above-described reverse increase and decrease in capacitance value occur. Also in this case, the variation in the capacitance value of the entire junction portion is small. As a result, even if the misalignment of the junction portion is large, it is an element structure in which the variation in the junction capacitance value does not become large.

[0057] Also, even in the layout shown in FIG. 19, variations in capacitance values with respect to bonding misalignment can be reduced. In this case, the inner diameter of the first metal film 521 constituting the first electrode 525 is smaller than the inner diameter of the second metal film 522 constituting the first electrode 525. And, the outer diameter of the first metal film 523 constituting the second electrode 526 is made smaller than the outer diameter of the second metal film 524 constituting the second electrode 526.

[0058] Examples of the types of capacitive elements arranged on each chip and the magnification of the capacitance value when they are connected in parallel are shown in FIG. 20. Based on the capacitance value when the MOM capacitive element 330 alone arranged on the lower semiconductor substrate 220 (peripheral circuit portion) is used as a reference, when all the described capacitive elements are connected in parallel, the capacitance value increases by a factor of 10. Note that when the storage-type MOS capacitive element 310 and the MIM capacitive element 320 arranged on the lower semiconductor substrate 220 (peripheral circuit portion) are connected in parallel, the capacitance value increases by a factor of 5.1. Also, when the storage-type MOS capacitive element 310, the MIM capacitive element 320, and the MOM capacitive element 330 arranged on the lower semiconductor substrate 220 (peripheral circuit portion) are connected in parallel, the capacitance value increases by a factor of 6.1.

[0059] <Operational effects according to the second modification of the second embodiment> According to the second modification of the second embodiment, even if the misalignment of the bonding portion is large due to the upper semiconductor substrate 210 being displaced to the left or right with respect to the lower semiconductor substrate 220, variations in the capacitance value of the bonding portion capacitive element 520 do not increase.

[0060] <The third modification of the second embodiment> FIG. 21 is a cross-sectional view of the solid-state imaging device 100 according to the third modification of the second embodiment of the present technology. In FIG. 21, the same parts as those in FIG. 12 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0061] In the example of FIG. 21, a charge storage type MOS capacitor element 310 and a MIM capacitor element 320 are arranged on the same area of the lower semiconductor substrate 220 (peripheral circuit section), a junction capacitor element 510 is arranged at the junction, and a charge storage type MOS capacitor element 410 is arranged on the upper semiconductor substrate 210 (sensor section). This is an example of a capacitor element in which these charge storage type MOS capacitor elements 310, MIM capacitor elements 320, junction capacitor elements 510, and charge storage type MOS capacitor elements 410 are all connected in parallel. Even in such a third modification, the same operational effects as those of the second embodiment can be obtained.

[0062] <Fourth Modification of the Second Embodiment> FIG. 22 is a cross-sectional view of a solid-state imaging device 100 according to a fourth modification of the second embodiment of the present technology. In FIG. 22, the same parts as those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0063] In the example of FIG. 22, a charge storage type MOS capacitor element 310 and a MOM capacitor element 330 are arranged on the same area of the lower semiconductor substrate 220 (peripheral circuit section), a junction capacitor element 510 is arranged at the junction, and a charge storage type MOS capacitor element 410 and a MOM capacitor element 420 are arranged on the upper semiconductor substrate 210 (sensor section). This is an example of a capacitor element in which these charge storage type MOS capacitor elements 310, MOM capacitor elements 330, junction capacitor elements 510, charge storage type MOS capacitor elements 410, and MOM capacitor elements 420 are all connected in parallel. Even in such a fourth modification, the same operational effects as those of the second embodiment can be obtained.

[0064] <Fifth Modification of the Second Embodiment> FIG. 23 is a cross-sectional view of a solid-state imaging device 100 according to a fifth modification of the second embodiment of the present technology. In FIG. 23, the same parts as those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0065] In the example of FIG. 23, a charge storage type MOS capacitor element 310 and a MOM capacitor element 330 are arranged on the same area of the lower semiconductor substrate 220 (peripheral circuit section), a junction capacitor element 510 is arranged at the junction, and no capacitor element is arranged on the upper semiconductor substrate 210 (sensor section). This is an example of a capacitor element in which these charge storage type MOS capacitor elements 310, MOM capacitor elements 330, and junction capacitor elements 510 are connected in parallel. Even in such a fifth modification, the same operational effects as those of the second embodiment can be obtained.

[0066] <Another modification of the second embodiment> The second embodiment is not limited to this. For example, when the upper semiconductor substrate 210 (sensor section) and the lower semiconductor substrate 220 (peripheral circuit section) are manufactured by a general CMOS process, there are a plurality of capacitor elements that can be mounted on each. It is easily imaginable to those skilled in the art that there are many combinations of capacitor elements that can be connected in parallel when the junction capacitor element 510 shown in FIG. 12 is added. The designer may select the capacitor elements to be connected in parallel so as to be optimal according to the layout of the entire circuit and the required capacitance value.

[0067] <Third embodiment> FIG. 24 is a cross-sectional view of a solid-state imaging device 100A according to the third embodiment. In FIG. 24, the same parts as those in FIG. 6(b) are denoted by the same reference numerals, and detailed description thereof is omitted.

[0068] In FIG. 24, the solid-state imaging device 100A forms a junction capacitor element 530 by joining a first metal film 531, 533 on the upper semiconductor substrate 210 side and a second metal film 532, 534 on the lower semiconductor substrate 220 side arranged on the bonding surface. The junction capacitance element 530 has a ring-shaped first electrode 535 and a second electrode 536 located at its center. The inner diameter of the first metal film 531 that constitutes the first electrode 535 is smaller than the inner diameter of the second metal film 532 that constitutes the first electrode 535. Also, the outer diameter of the first metal film 533 that constitutes the second electrode 536 is made smaller than the outer diameter of the second metal film 534 that constitutes the second electrode 536. FIG. 24 shows that the first electrode 535 and the second electrode 536 of the junction capacitance element 530 have a square layout, but this may also be circular.

[0069] The solid-state imaging device 100A expands the dynamic range of the imaging element by providing a capacitance element in the pixel that accumulates the charge overflowing from the photodiode 31. In such a stacked image sensor having a pixel internal capacitance element, the present invention is preferably applied. The junction capacitance element 530 is formed by joining two first metal films 531, 533 and two second metal films 532, 534 arranged for each pixel. Even if misalignment occurs at the joining surface of this junction capacitance element 530, the variation in capacitance value between the electrodes becomes small, and the variation in the dynamic range of the pixel can be reduced. In addition, in the prior art, a manufacturing process was required to form the pixel internal capacitance in the sensor section, but in the third embodiment, the first metal films 531, 533 and the second metal films 532, 534 that connect the upper semiconductor substrate 210 (sensor section) and the lower semiconductor substrate 220 (peripheral circuit section) are used to form the pixel internal capacitance. Therefore, the manufacturing process is not increased, and the dynamic range can be expanded at low cost.

[0070] <Fourth Embodiment> The fourth embodiment of the present disclosure will describe a solid-state imaging device in which a photoelectric conversion element and an amplification transistor that amplifies a signal from the photoelectric conversion element are arranged on different substrates, and three substrates including a sensor section where the photoelectric conversion element and a transfer gate (TRG) are arranged, a pixel transistor section where pixel transistors such as the amplification transistor are arranged, and a peripheral circuit section where a signal processing circuit that processes a signal from the amplification transistor are stacked by the WoW technology.

[0071] FIG. 25 is a cross-sectional view of the solid-state imaging device 100B according to the fourth embodiment. FIG. 25(a) shows the outside of the pixel, and FIG. 25(b) shows the inside of the pixel. In FIG. 25, the same parts as those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted. The solid-state imaging device 100B is composed of a sensor unit 610, a pixel transistor unit 620, and a peripheral circuit unit 630 from above. As shown in FIG. 26, the solid-state imaging device 100B is a stacked-type image sensor in which three semiconductor chips of a sensor unit 610, a pixel transistor unit 620, and a peripheral circuit unit 630 are stacked, and a part of the wiring is electrically connected by a metal bonding part 640. In the sensor unit 610, as shown in FIG. 27, a transfer transistor T1, a photodiode 31, and a floating diffusion FD34 are arranged. In the pixel transistor unit 620, a reset transistor T2, an amplification transistor T3, and a selection transistor T4 are arranged.

[0072] Returning to FIG. 25, the sensor unit 610 is composed of a photoelectric conversion layer 611 and an interlayer insulating film 612 from above. The photoelectric conversion layer 211 is a layer in which a photodiode (PD) 31 is formed, and generates charges corresponding to the amount of incident light by photoelectric conversion. The PD31 is electrically separated by element isolation parts 33a and 33b formed in the photoelectric conversion layer 611 for each pixel 30. Further, in the photoelectric conversion layer 611, the FD34 and the gate electrode 36 of the transfer transistor T1 are formed. Note that outside the pixel 30, as shown in FIG. 25(a), only the p-type well 32 remains. The transfer transistor T1 is formed in the interlayer insulating film 612.

[0073] The pixel transistor section 620 is composed of a p-type well 621 and a wiring layer 622 from top to bottom. An n-type diffusion layer is formed in the p-type well 621. The wiring layer 622 is configured to include wirings (M1 to M4) 623 laminated in multiple layers. Through the multiple layers of wirings (M1 to M4) 623 formed in the wiring layer 622, the transfer transistor T1, the reset transistor T2, the amplification transistor T3, and the selection transistor T4 that constitute each pixel 30 are driven. Also, a metal bonding portion 641 made of copper (Cu) is provided in the wiring layer 622 for bonding with the peripheral circuit section 630.

[0074] On the other hand, the peripheral circuit section 630 is composed of an interlayer insulating film and a wiring layer from top to bottom. The wiring layer is configured to include all wirings 631 and wirings (M1 to M6) 632 laminated in multiple layers. Also, a metal bonding portion 642 made of copper (Cu) for bonding with the metal bonding portion 641 of the pixel transistor section 620 is provided in the interlayer insulating film.

[0075] In the solid-state imaging device 100B having the above configuration, when the light incident on the sensor section 610 is photoelectrically converted by the PD 31, charges are generated. Then, the generated charges are output as pixel signals to the ADC group 150 formed in the peripheral circuit section 630 through the wirings (M1 to M4) 623 and the signal line LSGN shown in FIG. 1 formed by the wirings (M1 to M6) 632 of the peripheral circuit section 630 via the amplification transistor T3.

[0076] As shown in FIG. 25(a), an N+-accumulation type MOS capacitor element 310 is arranged on the peripheral circuit section 630. An MOM capacitor element 330 and an MIM capacitor element 320 are arranged on the upper layer of the MOS capacitor element 310. Below the pixel transistor section 620, an N+ accumulation type MOS capacitor element 410 is arranged. In the region for forming the wiring (M1 to M4) 623, which is the layer on the side opposite to the pixel transistor section 620 side within the same region where the MOS capacitor element 410 is arranged, a MOM capacitor element 420 is formed using the wiring (M1 to M4) 623. In this case, as shown in FIG. 26, the upper electrode 421 of the MOM capacitor element 420 is connected to the upper electrode 413 of the MOS capacitor element 410 via a via 414. Also, the lower electrode 422 of the MOM capacitor element 420 is connected to the lower electrode 412 of the MOS capacitor element 410 via a via 415.

[0077] Furthermore, the upper electrode 413 of the MOS capacitor element 410 and the upper electrode 421 of the MOM capacitor element 420 are connected to the upper electrode 313 of the MOS capacitor element 310 on the side of the peripheral circuit section 630, the lower electrode 322 of the MIM capacitor element 320, and the upper electrode 331 of the MOM capacitor element 330 via copper (Cu) metal bonding parts 641, 642. Also, the lower electrode 412 of the MOS capacitor element 410 and the lower electrode 422 of the MOM capacitor element 420 are connected to the lower electrode 312 of the MOS capacitor element 310 on the side of the peripheral circuit section 630, the upper electrode 321 of the MIM capacitor element 320, and the lower electrode 332 of the MOM capacitor element 330 via copper (Cu) metal bonding parts 641, 642.

[0078] <Operation and Effect according to the Fourth Embodiment> As described above, according to the fourth embodiment, the same operation and effect as those of the first embodiment can be obtained.

[0079] <Fifth Embodiment> The fifth embodiment of the present disclosure will describe a solid-state imaging device applied to an optical detection device using a SPAD (Single Photon Avalanche Diode).

[0080] Fig. 28 shows an arrangement diagram on a semiconductor chip of each circuit constituting the solid-state imaging device 100C according to the fifth embodiment. The solid-state imaging device 100C according to the fourth embodiment is a stacked-type image sensor in which two semiconductor chips, an upper semiconductor substrate 710 and a lower semiconductor substrate 720, are stacked, and a part of the wirings of the upper and lower chips are electrically connected by a metal bonding part MC2 such as a TSV (Through-silicon via). In this case, SPAD photodiodes 41 are arranged in a matrix on the upper semiconductor substrate 710, and peripheral circuits 51 such as an ADC group 150 and a signal processing circuit 180 other than the SPAD photodiodes 41 are mounted on the lower semiconductor substrate 720.

[0081] Fig. 29 is a cross-sectional view of the solid-state imaging device 100C according to the fifth embodiment. In Fig. 29, the upper semiconductor substrate 710 is composed of a photoelectric conversion layer 711, an interlayer insulating film 713, and a wiring layer 714 from above. The photoelectric conversion layer 711 is a layer in which the SPAD photodiodes 41 are formed, detects incident light (photons), and converts the carriers generated thereby into electrical signal pulses using avalanche multiplication. The SPAD photodiodes 41 are electrically separated by a p-type diffusion layer 42a and an n-type diffusion layer 42b formed in the photoelectric conversion layer 711 for each pixel 30.

[0082] The electrical signal pulses generated from the SPAD photodiodes 41 are output to wirings (M1 to M4) 715 formed in the wiring layer 714 through vias 716 formed in the interlayer insulating film 713. A copper (Cu) metal bonding part 731 is provided in the wiring layer 714 for bonding with the lower semiconductor substrate 720.

[0083] On the other hand, the lower semiconductor substrate 720 is composed of an interlayer insulating film 721 and a wiring layer 722 from above. The wiring layer 722 includes all wirings 723 and wirings (M1 to M6) 724 stacked in a plurality of layers. Further, a copper (Cu) metal bonding part 732 for bonding with the metal bonding part 731 of the upper semiconductor substrate 710 is provided in the interlayer insulating film 721.

[0084] In the solid-state imaging device 100C having the above configuration, when the light detected by the upper semiconductor substrate 210 is photoelectrically converted by the SPAD photodiode 41, an electrical signal pulse is generated. Then, the electrical signal pulse is output to the peripheral circuit 51 via the signal line LSGN shown in FIG. 1 formed by the wirings (M1 to M4) 715 and the wirings (M1 to M6) 724 of the lower semiconductor substrate 720.

[0085] <Operation and Effect according to the Fifth Embodiment> As described above, according to the fifth embodiment, the same operation and effect as those of the first embodiment can be obtained. By configuring the junction capacitance element 730, the junction capacitance element 730 can function as a memory element that temporarily stores an electrical signal from the upper semiconductor substrate 710 (sensor unit), and the performance of the SPAD can be improved.

[0086] <Sixth Embodiment> In the first to fifth embodiments, the case where the semiconductor device according to the present technology is applied to a solid-state imaging device which is an example of an electronic device is illustrated. In the sixth embodiment, the case where the semiconductor device according to the present technology is applied to other electronic devices is illustrated.

[0087] For example, the semiconductor device according to the present technology can be applied to a capacitor constituting a general filter circuit. As shown in FIG. 30, a general filter circuit includes a resistor R11 and a capacitor C11, and the semiconductor device according to the present technology can be applied as the configuration of the capacitor C11. By applying the semiconductor device according to the present technology to the capacitor C11 constituting the filter circuit, a large capacitance can be realized and the passband can be further widened.

[0088] In addition, the semiconductor device according to the present technology is applicable to capacitors constituting a general smoothing circuit. As shown in FIG. 31, a general filter circuit includes a diode D21 and a capacitor C21, and the semiconductor device according to the present technology can be applied to the configuration of the capacitor C21. By applying the semiconductor device according to the present technology to the capacitor C21 constituting the filter circuit, a large capacity can be realized, and alternating current can be accurately converted to direct current.

[0089] In addition, the semiconductor device according to the present technology is applicable to capacitors constituting a general integration circuit. As shown in FIG. 32, a general integration circuit includes a resistor R32, a capacitor C31, and an operational amplifier 800, and the semiconductor device according to the present technology can be applied to the configuration of the capacitor C31.

[0090] Furthermore, the semiconductor device according to the present technology is applicable to the capacitive DAC shown in FIG. 33. The capacitive DAC includes a plurality of stages of capacitors, and the semiconductor device according to the present technology can be applied to the configuration of the plurality of stages of capacitors.

[0091] <Other Embodiments> As described above, the present technology has been described by way of the first to sixth embodiments and the modified examples of the first and second embodiments. However, the discussions and drawings forming a part of this disclosure should not be understood as limiting the present technology. It will be apparent to those skilled in the art that various alternative embodiments, examples, and operation techniques can be included in the present technology if they understand the gist of the technical content disclosed in the above-described first to sixth embodiments. In addition, the configurations disclosed in the first to sixth embodiments and the modified examples of the first and second embodiments can be appropriately combined within a range where no contradiction occurs. For example, the configurations disclosed in a plurality of different embodiments may be combined, or the configurations disclosed in a plurality of different modified examples of the same embodiment may be combined.

[0092] <Application Examples to Electronic Devices> Next, an electronic device according to a seventh embodiment of the present disclosure will be described. FIG. 34 is a schematic configuration diagram of an electronic device 1000 according to the seventh embodiment of the present disclosure.

[0093] The electronic device 1000 according to the seventh embodiment includes a solid-state imaging device 1010, an optical lens 1020, a shutter device 1030, a drive circuit 1040, and a signal processing circuit 1050. The electronic device 1000 of the sixth embodiment shows an embodiment in which the solid-state imaging device 100 according to the first embodiment of the present disclosure is used in an electronic device (for example, a camera).

[0094] The optical lens 1020 forms an image of subject image light (incident light 1060) on the imaging surface of the solid-state imaging device 1010. As a result, signal charges are accumulated in the solid-state imaging device 1010 over a certain period. The shutter device 1030 controls the light irradiation period and the light shielding period to the solid-state imaging device 1010. The drive circuit 1040 supplies drive signals for controlling the transfer operation of the solid-state imaging device 1010 and the shutter operation of the shutter device 1030. Signal transfer of the solid-state imaging device 1010 is performed by the drive signals (timing signals) supplied from the drive circuit 1040. The signal processing circuit 1050 performs various signal processes on the signals (pixel signals) output from the solid-state imaging device 1010. The video signal on which the signal processing has been performed is stored in a storage medium such as a memory or output to a monitor.

[0095] With such a configuration, in the electronic device 1000 of the seventh embodiment, suppression of optical color mixing is achieved in the solid-state imaging device 1010, so that the image quality of the video signal can be improved. Note that the electronic device 1000 to which the solid-state imaging devices 100, 100A, and 100B can be applied is not limited to a camera, and can also be applied to other electronic devices. For example, it may be applied to an imaging device such as a camera module for mobile devices such as mobile phones.

[0096] Also, in the seventh embodiment, the solid-state imaging device 1010 is configured to use the solid-state imaging devices 100, 100A, 100B, and 100C according to the first to fifth embodiments in an electronic device, but other configurations may also be used.

[0097] <Usage example of solid-state imaging device> The above-described solid-state imaging device can be used, for example, in various cases where light such as visible light, infrared light, ultraviolet light, X-rays, etc. is sensed, as follows. · Devices for taking pictures of images for appreciation, such as digital cameras and mobile devices with camera functions · In-vehicle sensors for taking pictures of the front, rear, surroundings, inside the vehicle, etc. of a vehicle for safe driving such as automatic stop and recognition of the driver's state, surveillance cameras for monitoring moving vehicles and roads, ranging sensors for ranging between vehicles, etc., devices for traffic · Devices for home appliances such as TVs, refrigerators, air conditioners, etc. for taking pictures of the user's gestures and performing device operations according to the gestures · Devices for medical and healthcare use, such as endoscopes and devices for blood vessel imaging by receiving infrared light · Devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication · Devices for beauty use, such as skin measuring devices for taking pictures of the skin and microscopes for taking pictures of the scalp · Devices for sports use, such as action cameras and wearable cameras for sports applications · Devices for agricultural use, such as cameras for monitoring the state of fields and crops Note that the effects described in this specification are merely examples and are not limited, and there may be other effects.

[0098] Note that the present disclosure can also adopt the following configurations. (1) A first semiconductor substrate having a first capacitor element portion including at least one capacitor element, A second semiconductor substrate laminated on the first semiconductor substrate, A second capacitor element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate And comprising The first and second capacitor element portions are semiconductor devices connected in parallel to each other. (2) The semiconductor device according to (1) above, wherein the second semiconductor substrate has a third capacitor element portion including at least one capacitor element. (3) The first and third capacitor element portions each connect a plurality of capacitor elements in parallel. The plurality of capacitor elements are composed of two or more of a MOS type capacitor element, a comb-shaped wiring capacitor element, a MIM (Metal Insulator Metal) type capacitor element, and a PIP (Poly Insulator Poly) type capacitor element. The semiconductor device according to (2) above. (4) The semiconductor device according to any one of (1) to (3) above, wherein the second capacitor element portion includes a first metal bonding portion and a second metal bonding portion formed to face each other in a direction orthogonal to the stacking direction of the first semiconductor substrate and the second semiconductor substrate. (5) The first metal bonding portion is ring-shaped, and the second metal bonding portion is formed at the center of the ring shape. The semiconductor device according to (4) above. (6) The first metal bonding portion and the second metal bonding portion are constituted by a first metal film provided on the bonding surface of the first semiconductor substrate and a second metal film provided on the bonding surface of the second semiconductor substrate. For the first metal bonding portion, the inner diameter of the first metal film is smaller than the inner diameter of the second metal film. For the second metal bonding portion, the diameter of the first metal film is smaller than the diameter of the second metal film. The semiconductor device according to (5) above. (7) The first metal bonding portion and the second metal bonding portion include a structure that is square. The semiconductor device according to any one of (4) to (6) above. (8) The first semiconductor substrate has at least one of a pixel and a peripheral circuit that processes a signal from a pixel transistor that amplifies a signal from the pixel. The second semiconductor substrate has the other of the pixel and the peripheral circuit. The semiconductor device according to any one of (1) to (7) above. (9) The pixel is composed of a photodiode. Furthermore, a third semiconductor substrate having the pixel transistor is laminated on at least one of the first semiconductor substrate, the second semiconductor substrate, and between the first semiconductor substrate and the second semiconductor substrate. The semiconductor device according to (8) above. (10) The first semiconductor substrate has at least one of a sensor unit having a SPAD (Single Photon Avalanche Diode) photodiode and a peripheral circuit that processes signals from the sensor unit. The second semiconductor substrate has the other of the sensor unit and the peripheral circuit. The semiconductor device according to any one of (1) to (7) above. (11) The third capacitor element portion includes a pixel internal capacitance. The semiconductor device according to any one of (1) to (10) above. (12) A first semiconductor substrate having a first capacitor element portion including at least one capacitor element, A second semiconductor substrate laminated on the first semiconductor substrate, And a second capacitor element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate. Comprising: The first and second capacitor element portions are provided in a semiconductor device connected in parallel to each other. An electronic device.

Description of Reference Numerals

[0099] 30…Pixel, 31…Photodiode, 32,228,621…p-type well, 33a,33b,33c,311…Element isolation part, 35,42b…n-type diffusion layer, 36…Gate electrode, 41…SPAD photodiode, 42a…p-type diffusion layer, 51…Peripheral circuit, 100,110A,100B,100C…Solid-state imaging device, 110…Pixel array part, 120…Row selection circuit, 130…Horizontal transfer and scanning circuit, 140…Timing control circuit, 150…ADC group, 151…Comparator, 152…Counter, 153…Latch, 170…Amplifier circuit, 180…Signal processing circuit, 190…Horizontal transfer line, 210,710…Upper semiconductor substrate, 211,711…Photoelectric conversion layer, 213,221,713,721…Interlayer insulating film, 214,222,622,714,722…Wiring layer, 215,223,623,631,632,715,723,724…Wiring, 220,720…Lower semiconductor substrate, 225, 226…Terminal, 230,510,520,530,730…Junction capacitance element, 231,232,511,512,640,641,642,731,732…Metal bonding part, 234,313,321,331,343,413,421,514…Upper electrode, 235,312,322,332,342,412,422,515…Lower electrode, 310,410…Accumulation-type MOS capacitance element, 314,315,414,415…Via, 316,416…Gate insulating film, 320…MIM capacitance element, 330…MOM capacitance element, 340…PIP capacitance element, 420…MOM capacitance element, 521,523,531,533…First metal film, 522,524,532,534…Second metal film, 525,535…First electrode, 526,536…Second electrode, 610…Sensor part, 611…Photoelectric conversion layer, 612…Interlayer insulating film, 620…Pixel transistor part, 630…Peripheral circuit part, 800…Operational amplifier, 1000…Electronic device, 1010…Solid-state imaging device, 1020…Optical lens, 1030…Shutter device, 1040…Drive circuit, 1050…Signal processing circuit, 1060…Incident light

Claims

1. A first semiconductor substrate having a first capacitor element portion including at least one capacitor element, A second semiconductor substrate laminated on the first semiconductor substrate, And a second capacitor element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, comprising: The first and second capacitor element portions are connected in parallel to each other, The second capacitor element portion includes a first metal bonding portion and a second metal bonding portion formed to face each other in a direction orthogonal to a stacking direction of the first semiconductor substrate and the second semiconductor substrate, The first metal bonding portion is ring-shaped, and the second metal bonding portion is formed at a central portion of the ring shape, A semiconductor device.

2. The semiconductor device according to claim 1, wherein the second semiconductor substrate has a third capacitor element portion including at least one capacitor element.

3. The first and third capacitor element portions each connect a plurality of capacitor elements in parallel, The plurality of capacitor elements are composed of two or more of a MOS type capacitor element, a comb-shaped wiring capacitor element, a MIM (Metal Insulator Metal) type capacitor element, and a PIP (Poly Insulator Poly) type capacitor element. The semiconductor device according to claim 2.

4. The first metal bonding portion and the second metal bonding portion are constituted by a first metal film provided on a bonding surface of the first semiconductor substrate and a second metal film provided on a bonding surface of the second semiconductor substrate, For the first metal bonding portion, an inner diameter of the first metal film is smaller than an inner diameter of the second metal film, For the second metal bonding portion, a diameter of the first metal film is smaller than a diameter of the second metal film. The semiconductor device according to claim 1.

5. The first metal bonding portion and the second metal bonding portion include a square structure. The semiconductor device according to any one of claims 1 to 4.

6. The first semiconductor substrate has at least one of a pixel and a peripheral circuit that processes signals from the pixel transistor that amplifies signals from the pixel. The second semiconductor substrate has the other of the pixel and the peripheral circuit. The semiconductor device according to any one of claims 1 to 5.

7. The pixel consists of a photodiode. The semiconductor device according to claim 6.

8. The first semiconductor substrate has at least one of a sensor portion having a SPAD (Single Photon Avalanche Diode) photodiode and a peripheral circuit that processes signals from the sensor portion. The second semiconductor substrate has the other of the sensor portion and the peripheral circuit. The semiconductor device according to any one of claims 1 to 5.

9. The second capacitor element portion includes a pixel internal capacitance. The semiconductor device according to any one of claims 1 to 8.

10. A first semiconductor substrate having a first capacitor element portion including at least one capacitor element, A second semiconductor substrate laminated on the first semiconductor substrate, And a second capacitor element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate. Comprising, The first and second capacitor element portions are connected in parallel to each other. The second capacitor element portion includes a first metal bonding portion and a second metal bonding portion formed to face each other in a direction orthogonal to the stacking direction of the first semiconductor substrate and the second semiconductor substrate. The first metal bonding part is ring-shaped, and the second metal bonding part includes a semiconductor device formed at the center of the ring-shaped part, electronic device.

Images