Device including an integrated segment and method for manufacturing the same

Abstract

Disclosed herein are semiconductor devices, and associated systems and methods, that include one or more interface segments patterned within an outer protective layer. The one or more interface segments may provide an attachment interface / surface for a connection pad. One or more interface segments, or portions thereof, may be left uncovered or exposed and may provide for warpage control of the corresponding semiconductor device.

Description

Technical Field

[0001] This technology is directed to devices such as semiconductor devices including memories and processors, and some embodiments are directed to semiconductor devices including connection pads.

Background Art

[0002] Current trends in semiconductor manufacturing are to produce smaller, faster devices with higher density components for computers, mobile phones, pagers, personal digital assistants, and many other products. However, reducing the circuit size can lead to changes in the integrity or vulnerability of the structure. For example, the structure of a fabricated semiconductor device can peel and / or crack due to stress, temperature variations, and / or mismatches in the coefficient of thermal expansion (CTE) of the corresponding materials of the device's structure.

Brief Description of the Drawings

[0003]

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Embodiments for Carrying Out the Invention

[0004] In the following description, numerous specific details are discussed in order to provide a complete and executable description of embodiments of the present technology. However, those skilled in the art will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown or described in detail in order to avoid obscuring other aspects of the technology. In general, it should be understood that, in addition to the specific embodiments disclosed herein, various other devices, systems, and methods may be within the scope of the present technology.

[0005] Some embodiments of semiconductor devices, packages, and / or assemblies according to the present technology may include one or more interface segments located under one or more pads (e.g., underbump metallization (UBM) such as electrically activated pads, electrically insulating pads, and / or thermal pads). The interface segment (e.g., a section of silicon nitride (SiN)) may correspond to a patterned layer and may be embedded within an outer layer (e.g., a tetraethyl orthosilicate (TEOS) layer). In some embodiments, the interface segment may be directly bonded or connected to the corresponding pad and may have a width greater than the width of the corresponding pad. Thus, the peripheral portion of the interface segment may extend laterally beyond one or more or all of the perimeters of the corresponding pad. The interface segment may further surround a through-silicon via (TSV) located under the corresponding pad. Thus, the connection pad may contact the interface segment without contacting the outer layer.

[0006] The interface segment strengthens the bond between the corresponding pad and the body of the entire device. Further, the interface segment may include a material (e.g., SiN) that is more robust than the outer layer (e.g., TEOS) and is resistant to structural damage (e.g., cracks). Thus, the interface segment may reduce structural defects that may be caused by direct adhesion between the pad (e.g., UBM) and the outer layer.

[0007] FIG. 1A is a bottom view of a device 100 (e.g., a semiconductor device such as a chip, package, and / or assembly, etc.), and FIG. 1B is a schematic cross-sectional view of the device 100 taken along line 1B-1B of FIG. 1A according to an embodiment of the technology. Referring to FIGS. 1A and 1B together, the device 100 may include a surface 102 (e.g., the bottom surface, an inert surface, and / or the back surface of a semiconductor device) having a set of connection pads (e.g., UBM). As an example to illustrate, the device 100 may have a thermal pad 104 and / or an electrical pad 106 exposed / mounted on the surface 102. One or more of the pads such as the thermal pad 104 may have a pad width 108. The electrical pad 106 may be configured to provide an interface between the electrical circuit of the device 100 and an external circuit / device. The thermal pad 104 may be configured to provide an interface for removing thermal energy from the device 100. The thermal pad 104 may be electrically insulated from the electrical circuit within the device 100 and / or an external circuit.

[0008] The device 100 may have a substrate 112 (e.g., a wafer-level substrate such as a silicon substrate). The device 100 may have a passivation layer 116 (e.g., a TEOS layer). The passivation layer 116 may generally overlap the substrate 112 along the side surface or may cover the substrate 112. The passivation layer 116 may function as an electrical barrier and / or a physical barrier (e.g., against moisture or debris, etc.). In some embodiments, the passivation layer 116 may function as a solder resist.

[0009] Device 100 may include one or more interface segments 122 under and / or adjacent to the connection pads and / or adjacent to the passivation layer 116. For example, the interface segment 122 may be located within a recess / vacancy of the passivation layer 116. The passivation layer 116 and the interface segment 122 may have the same plane that together defines the surface 102. The thermal pad 104 and / or the electrical pad 106 may be directly attached to the corresponding interface segment 122 and / or on the corresponding interface segment 122. In some embodiments, the interface segment 122 may include a dielectric material such as SiN. The interface segment 122 may have a peripheral portion that extends laterally beyond / across one or all of the side edges of the corresponding pad. Thus, the interface segment 122 may have an interface width 124 (e.g., the distance measured between opposing outer edges) that is greater than the pad width 108. In some embodiments, the interface segment 122 may have a thickness that matches the thickness of the passivation layer 116.

[0010] Device 100 may include one or more TSVs 132 coupled to the electrical pads 106. The TSVs 132 may include conductive structures (e.g., copper pegs, nails, or spikes, etc.) that extend vertically and at least partially into the substrate 112 of the device 100. The TSVs 132 may electrically couple the corresponding electrical pads 106 to an electrical circuit within the device 100. The TSVs 132 may be surrounded by a via barrier 134 (e.g., a dielectric mask). For example, the via barrier 134 may be used to contain and / or shape the material forming the TSVs 132.

[0011] TSV 132 can overlap with the corresponding electrical pad 106 and can be electrically coupled to the corresponding electrical pad 106. In some embodiments, TSV 132 can extend through the openings of the passivation layer 116 and / or the interface segment 122. For example, the peripheral surface of TSV 132 and / or the peripheral surface of the via barrier 134 can be in direct contact with the interface segment 122 occupying the opening of the passivation layer 116. In some embodiments, the opening can have a width or dimension greater than the pad width 108.

[0012] Figures 2-7 illustrate exemplary stages of a manufacturing process according to embodiments of the technology. The exemplary stages can correspond to the manufacture of the apparatus 100 of FIG. 1A. FIG. 2 illustrates an intermediate structure 200 having a wafer-level substrate 202 (e.g., substrate 112) and a TSV structure 204 (e.g., corresponding to TSV 132 of FIG. 1B and / or the via barrier 134 of FIG. 1B). The wafer-level substrate 202 can correspond to the substrate 112 of FIG. 1B.

[0013] The wafer-level substrate 202 can have an uncovered surface 212. The TSV structure 204 can extend under the uncovered surface 212 and partially into the wafer-level substrate 202. The intermediate structure 200 can correspond to a post-processing stage of the wafer-level substrate 202. For example, the intermediate structure 200 can correspond to circuit formation (e.g., doping) on the wafer-level substrate 202, grinding / thinning of the silicon substrate, formation of one or more patterning structures (e.g., via barrier 134), creation of voids in the patterning structure and / or the device wafer, filling of the voids with a metallic material (e.g., via metal deposition / plating), and / or etching removal of a protective layer or patterning layer.

[0014] FIG. 3 illustrates an intermediate structure 300 having the structure 200 of FIG. 2 covered with an interface layer 302. The interface layer 302 can correspond to the interface segment 122 of FIG. 1A. For example, the interface layer 302 can include a dielectric layer such as a SiN layer.

[0015] In some embodiments, the manufacturing process may include depositing an interface layer 302 on the structure 200 (e.g., directly on the exposed surface 212 of FIG. 2). For example, the interface layer 302 may be deposited using corresponding chemical deposition and / or lamination processes. The interface layer 302 may have a thickness greater than the protrusion height of the TSV structure 204. The interface layer 302 may surround the TSV structure 204 protruding above the wafer-level substrate 202 and / or may conform to the TSV structure 204. The interface layer 302 may be applied with a thickness that covers the upper portion of the TSV structure 204. The interface layer 302 may be planarized.

[0016] FIG. 4 illustrates an intermediate structure 400 having the structure 300 of FIG. 3 with one or more segment structures (e.g., segment structures 402a and 402b) on the exposed surface 212. The structure 400 may be formed by etching away a portion of the interface layer 302 excluding the segment structures. The segment structures may correspond to the interface segments 122 of FIG. 1A.

[0017] In some embodiments, one or more of the structures (e.g., segment structure 402a) may be a solid / continuous block of an interface material (e.g., SiN). Also, one or more of the structures (e.g., segment structure 402b) may surround or encapsulate the TSV structure 204 protruding above the wafer-level substrate 202. For example, the interface material may directly contact the upper surface and / or the surrounding surface of the TSV structure 204 (e.g., via barrier 134 of FIG. 1B).

[0018] FIG. 5 illustrates an intermediate structure 500 having the structure 400 of FIG. 4 covered with a passivation structure 502 (e.g., a TEOS layer). For example, TEOS can be deposited over the uncovered surface 212 of FIG. 4 and / or over the segment structures of FIG. 4 (e.g., segment structures 402a and 402b). The deposited passivation structure 502 can have a thickness greater than that of the segment structures. Thus, the passivation structure 502 can cover the top of the segment structures and / or can surround and be in direct contact with the segment structures.

[0019] In some embodiments, the TSV structure 204 of FIG. 2 can remain exposed in the structure 400 (e.g., not covered by the segment structures). Thus, the passivation structure 502 can be in direct contact with and can encapsulate the TSV structure 204. The peripheral portion of the electrical pad 106 of FIG. 1A that is subsequently attached can be in direct contact with the passivation layer 116 of FIG. 1B instead of the interface segment 122 of FIG. 1A.

[0020] FIG. 6 can illustrate an intermediate structure 600 corresponding to the structure 500 of FIG. 5 with its top removed. For example, the manufacturing process can include chemical and / or mechanical removal processes (e.g., cutting, grinding, chemical mechanical polishing (CMP), etc.) to remove a portion of the passivation structure 502, a portion of each segment structure, a portion of the TSV structure 204 of FIG. 2, or a combination thereof. The remaining portion of the passivation structure 502 can correspond to the passivation layer 116 of FIG. 1B, the remaining portion of the segment structures can correspond to the interface segment 122 of FIG. 1A, and / or the remaining portion of the TSV structure 204 can correspond to the TSV 132 of FIG. 1B and / or the via barrier 134 of FIG. 1B. Further, the remaining portions can be in the same plane. In other words, the removal process can form or expose one or more segment structure surfaces (e.g., surfaces 614a and 614b) and / or one or more TSV surfaces 632 that are in the same plane as the top surface of the passivation structure 502.

[0021] FIG. 7 may illustrate an intermediate structure 600 on which a set of pads (UBM) is mounted / attached. The set of pads (e.g., thermal pad 104 and / or electrical pad 106) may be mounted above the segment structure surface (e.g., surfaces 614a and / or 614b) of FIG. 6 and / or the TSV surface 632 of FIG. 6. The pads may be mounted based on coupling and / or attaching the set of pads to the corresponding segment structure surface and / or the TSV surface 632 (e.g., via an adhesive). The structure of FIG. 1A may be formed based on attaching a set of pads to the intermediate structure 600.

[0022] In some embodiments, the segment structure surface may be exposed without any connection pads attached thereto. The corresponding interface segment 122 may be used to address warping and / or to adjust the capacitance between structures within the device 100.

[0023] FIG. 8 is a flow diagram illustrating an exemplary method 800 of manufacturing a device (e.g., device 100 of FIG. 1A) according to an embodiment of the present technology. Method 800 may include forming the interface segment 122 of FIG. 1A.

[0024] In block 802, method 800 may include providing a semiconductor substrate (e.g., substrate 112 of FIG. 1B such as the wafer-level substrate 202 of FIG. 2). The substrate 112 may correspond to the process associated with FIG. 2 and the structure 200 of FIG. 2. The provided substrate may include the TSV structure 204 of FIG. 2 as described above. In some embodiments, providing the substrate 112 may include manufacturing the wafer-level substrate 202 as described in block 804, such as through a semiconductor manufacturing process (e.g., doping or thinning).

[0025] In block 806, method 800 may include forming an interface layer. For example, forming the interface layer may include depositing and / or laminating a dielectric material or a barrier material such as SiN above the substrate 112 of FIG. 1B (e.g., the wafer-level substrate 202 of FIG. 2 and / or the uncovered surface 212 of FIG. 2). The interface layer may be formed in direct contact with the TSV structure 204 of FIG. 2 and / or surrounding or encapsulating the TSV structure 204. Forming the protective layer may correspond to the process associated with FIG. 3 and the structure 300 of FIG. 3.

[0026] In block 808, method 800 may include patterning the interface layer to form an interface pocket. Patterning the interface layer may include removing a portion of the interface layer by a cutting process, a grinding process, an etching process, or a CMP process, etc. Patterning the interface layer may correspond to the process associated with FIG. 4 and the structure 400 of FIG. 4. For example, removing a portion of the interface layer may correspond to forming an interface pocket (e.g., the segment structures 402a and 402b of FIG. 4). In some embodiments, one or more of the interface pockets may have the TSV structure 204 of FIG. 2 encapsulated therein.

[0027] In block 810, method 800 may include forming a passivation layer. Forming the passivation layer may include depositing and / or laminating an outer protective layer (e.g., a TEOS layer). The passivation layer may be formed around the wafer-level substrate 202 and / or the interface pocket, and / or in direct contact with the wafer-level substrate 202 and / or the interface pocket. For example, the passivation layer may be formed adjacent to, above, and / or in direct contact with an outer portion of a segment structure (e.g., segment structures 402a and 402b). The passivation layer may also be formed above and / or in direct contact with an uncovered surface 212 of the wafer-level substrate 202 after patterning of the segment structure. Forming the passivation layer may correspond to the process associated with FIG. 5 and the structure 500 of FIG. 5.

[0028] In block 812, method 800 may include removing a covered portion (e.g., an upper portion) of the passivation layer and / or the interface pocket. Removing the covered portion may include exposing a TSV structure (e.g., a vertically extending metal / conductive material). A portion of the passivation layer, the interface pocket, and / or the TSV structure may be removed based on etching, grinding, CMP, etc. The removal process may further correspond to a planarization process that forms a coplanar surface of the TSV structure, the interface pocket, and / or the passivation layer. Removing the covered portion may correspond to the process associated with FIG. 6 and the structure 600 of FIG. 6.

[0029] In block 814, method 800 may include attaching connection pads (e.g., UBMs) such as the electrical pad 106 of FIG. 1A and / or the thermal pad 104 of FIG. 1A. The connection pads may be attached to / on the planarized surface (e.g., surface 102 of FIG. 1A) resulting from removing the covered portion. The thermal pad 104 may be attached to the remaining interface pocket (e.g., interface segment 122). The electrical pad 106 may be coupled (e.g., electrically coupled) to the TSV structure 204 (e.g., TSV 132) and / or the corresponding interface segment 122, or may be directly attached.

[0030] The interface segment 122 may provide a reduction in the warpage of device 100. Considering the material differences, the interface segment 122 may be formed between portions of the passivation layer 116 to result in different temperature-related changes (e.g., expansion) than the passivation layer 116. Thus, the warpage of device 100 during other temperature-changing manufacturing processes (e.g., reflow) may be controlled or reduced. Further, the interface segment 122 may provide an improvement in the structural integrity of or under the connection pads. For example, the interface segment 122 may include a material (e.g., SiN) having greater rigidity and / or greater flexibility than the passivation layer 116 under various conditions. Thus, physically coupling the connection pads to the interface segment 122 instead of the passivation layer 116 may reduce structural damage (such as cracks) formed under the connection pads. Further, the interface segment 122 may be formed by leveraging existing processes (e.g., without increasing the complexity of manufacturing) without adversely affecting the solder joint interconnects.

[0031] FIG. 9 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. Any one of the semiconductor devices described with reference to FIGS. 1A-8 can be incorporated into any of countless larger and / or more complex systems, a representative example of which is system 990 schematically shown in FIG. 9. System 990 can include a semiconductor device 900 (“device 900”) (e.g., a semiconductor device, package, and / or assembly), a power supply 992, a driver 994, a processor 996, and / or other subsystems 998. Device 900 can include mechanisms substantially similar to the devices described above. The resulting system 990 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 990 can include, but are not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and household appliances. The components of system 990 may be housed in a single unit or distributed among multiple interconnected units (e.g., via a communication network). The components of system 990 can include a remote device and any of a variety of computer-readable media.

[0032] The present disclosure is not intended to be exhaustive or to limit the technology to the precise forms disclosed herein. Specific embodiments are disclosed herein for illustrative purposes, but as will be understood by those skilled in the art, various equivalent modifications are possible without departing from the technology. In some cases, well-known structures and functions are not shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the technology. Here, the steps of the method are presented in a particular order, but in alternative embodiments, the steps may be performed in a different order. Similarly, specific aspects of the technology disclosed in connection with a particular embodiment may be combined or deleted in other embodiments. Further, the advantages associated with particular embodiments of the technology may be disclosed in the context of those embodiments, but other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein in order to fall within the scope of the technology. Accordingly, the disclosure and related technology may include other embodiments not explicitly shown or described herein, and the invention is not limited except as by the appended claims.

[0033] Throughout this disclosure, the singular terms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Similarly, the word "or" as used in a list of two or more items is not explicitly limited to mean only a single item excluded from the other items in the list, and the use of "or" in such a list should be interpreted to include (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Also, the terms "comprising," "including," and "having" are used throughout to mean including at least the recited mechanism without excluding any greater number of the same mechanism and / or additional types of other mechanisms. References in this specification to "one embodiment," "an embodiment," "some embodiments," or similar expressions mean that a particular mechanism, structure, operation, or feature described in connection with the embodiment can be included in at least one embodiment of the technology. Thus, the appearance of such phrases or expressions in this specification does not necessarily all refer to the same embodiment. Further, the various particular mechanisms, structures, operations, or features can be combined in any suitable manner in one or more embodiments.

Claims

1. A semiconductor substrate, A passivation layer above the surface of the semiconductor substrate, An interface segment patterned within the passivation layer, The interface segment includes an electrically insulating material, The bottom surface of the interface segment is located on the semiconductor substrate, The interface segment and the passivation layer include different materials, The interface segment and the passivation layer are on the same plane as each other, An interface segment and A device comprising.

2. The passivation layer includes a tetraethyl orthosilicate (TEOS) layer, The interface segment includes silicon nitride (SiN), The device according to claim 1.

3. A connection pad directly coupled to the interface segment and configured to interface with a structure external to the device The device according to claim 1, further comprising.

4. The connection pad has a pad width measured along a lateral direction, The interface segment has an interface width along the lateral direction, and the interface width is greater than the pad width, The device according to claim 3.

5. One or more peripheral portions of the interface segment extend laterally beyond one or more corresponding side edges of the connection pad, the device according to claim 4.

6. The interface segment is surrounded by the passivation layer, and a peripheral portion of the interface segment is in direct contact with the passivation layer. The connection pad is surrounded by the peripheral portion of the interface segment without overlapping the passivation layer. The device according to claim 5.

7. The device according to claim 3, wherein the connection pad is a thermal pad configured to be electrically insulated from an active circuit on the device and to remove thermal energy from the device.

8. The device according to claim 7, wherein the thermal pad includes a bottom surface that extends between peripheries and is directly attached to the interface segment without overlapping the passivation layer.

9. The device according to claim 3, wherein the connection pad is an electrical pad electrically connected to one or more circuits on the device.

10. A silicon through-via (TSV) that at least partially extends along a vertical direction through a portion of the semiconductor substrate, the TSV being configured to electrically connect the electrical pad to the one or more circuits on the semiconductor substrate. The device according to claim 9, further comprising the TSV.

11. The device according to claim 10, wherein a portion of the TSV between the electrical pad and the semiconductor substrate is surrounded by the interface segment.

12. The device according to claim 11, wherein the interface segment and the passivation layer have a matching thickness.

13. The device according to claim 1, wherein the interface segment has an exposed surface that extends between peripheries of the interface segment.

14. A wafer-level substrate, The active circuit formed on the wafer-level substrate, The passivation layer above the surface of the wafer-level substrate, The interface segment embedded in the passivation layer, The interface segment includes an electrically insulating material, The bottom surface of the interface segment is located on the wafer-level substrate, The interface segment and the passivation layer include different materials, The interface segment and the passivation layer are in the same plane with each other, Interface segment, An electrical pad physically coupled to the wafer-level substrate and electrically coupled to the active circuit, the electrical pad configured to provide an external electrical interface to the active circuit within the semiconductor device, A thermal pad physically coupled to the interface segment and electrically insulated from the active circuit, the thermal pad configured to provide an external thermal interface for removing thermal energy from the semiconductor device A semiconductor device including.

15. The semiconductor device according to claim 14, wherein the thermal pad is directly attached to the interface segment without contacting the passivation layer.

16. The passivation layer includes a tetraethyl orthosilicate (TEOS) layer, The interface segment includes silicon nitride (SiN), The semiconductor device according to claim 15.

17. The semiconductor device according to claim 16, wherein a peripheral portion of the interface segment extends laterally beyond a periphery of the thermal pad.

18. The interface segment is a first SiN segment, a silicon through-via (TSV) electrically coupled to the electric pad and / or the active circuit, the TSV having a TSV length longer than the length of the electrically insulated extension, a second SiN segment embedded in the passivation layer and surrounding a peripheral portion of the TSV, the electric pad being directly attached to the second SiN segment, and a second SiN segment The semiconductor device according to claim 16, further comprising.

19. providing a semiconductor substrate having an active circuit thereon; forming an interface structure above the semiconductor substrate; forming one or more interface segments based on removing a portion of the interface structure; forming a passivation layer surrounding the one or more interface segments above the semiconductor substrate; planarizing the passivation layer and the interface segment, the planarized passivation layer and the interface segment having outer surfaces on the same plane, and planarizing including, the interface segment includes an electrically insulating material, a bottom surface of the interface segment is located on the semiconductor substrate, the interface segment and the passivation layer include different materials, A method of manufacturing a semiconductor device.

20. attaching a set of under bump metallization (UBM), the set of UBM including electric pads and / or thermal pads each directly attached to a corresponding interface structure without contacting the passivation layer, and attaching further comprising, Forming the interface structure includes depositing silicon nitride (SiN), The provided semiconductor substrate includes silicon through vias (TSVs) at least partially embedded therein, Forming the interface structure includes depositing silicon nitride (SiN) and encapsulating a portion of the TSVs extending above the semiconductor substrate, One of the one or more interface segments encapsulates the TSV, Forming the passivation layer includes depositing tetraethyl orthosilicate (TEOS) covering the upper portions of the one or more interface segments encapsulating the TSV, Planarizing the passivation layer and the interface segments includes removing the upper portions of the deposited TEOS and the deposited SiN, and removing includes exposing the TSV, The method according to claim 19.

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