Multilayer capacitor

Abstract

To provide a lamination capacitor capable of suppressing a short circuit.SOLUTION: A feedthrough capacitor 1 (lamination capacitor) comprises: an element assembly 2 having a pair of end faces 2a, a pair of side faces 2b, and a pair of main faces 2c; a pair of first external electrodes 3 disposed on the pair of end faces 2a; second electrodes 5 disposed on the pair of side faces 2b; a plurality of first internal electrodes 7; and a plurality of second internal electrodes 9. A relational expression Lg>b-(2×b×Tg1 / T) is satisfied, where b is a wraparound size of a wraparound part 31c, wrapped from one end face 2a to one main face 2c, of a first sintered electrode layer 31, Lg is a distance between the one end face 2a and ends 9d of the plurality of second internal electrodes 9 on the one end face 2a side, T is a distance between the pair of main faces 2c, 2c in a lamination direction D1, and Tg1 is a distance between the one main face 2c and a second internal electrode 9 nearest to the one main face 2c.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a multilayer capacitor.

Background Art

[0002] Conventionally, as a multilayer capacitor, a multilayer ceramic capacitor described in Patent Document 1 is known. This multilayer ceramic capacitor includes a laminate having a plurality of stacked dielectric layers and a plurality of internal electrodes, a first end face external electrode disposed on a first side face of the laminate, and a second end face external electrode disposed on a second side face of the laminate. That is, this multilayer ceramic capacitor is a so-called three-terminal type multilayer ceramic capacitor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the above three-terminal type multilayer ceramic capacitor is mounted on an electronic device, for example, the first end face external electrode and the second end face external electrode are soldered to the electronic device. As a result, due to thermal expansion or the like, the peripheral structure of each external electrode bends, and cracks may occur in the element body constituting the laminate. Such cracks may cause the internal electrodes to short-circuit.

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide a multilayer capacitor capable of suppressing short circuits.

Means for Solving the Problems

[0006] The multilayer capacitor according to the present invention includes a body having a pair of end faces facing each other, a pair of side faces and a pair of main faces located between the pair of end faces and extending in the facing direction of the pair of end faces, a pair of first external electrodes disposed on the pair of end faces, a second external electrode spaced apart from the pair of first external electrodes and disposed on at least one of the pair of side faces, a plurality of first internal electrodes disposed in the body and exposed from at least one end face, and a plurality of second internal electrodes disposed in the body and spaced apart from one end face. The pair of first external electrodes includes a sintered electrode layer that covers the pair of end faces and is connected to the plurality of first internal electrodes. Each of the plurality of first internal electrodes and the plurality of second internal electrodes is laminated with each other with the direction in which the pair of main faces face each other as the lamination direction. Among the sintered electrode layers covering one end face, the intrusion dimension in the facing direction of the intrusion portion that has intruded from one end face into one main face is defined as dimension b, the distance in the facing direction between one end face and the ends of the plurality of second internal electrodes on the one end face side is defined as dimension Lg, the distance between the pair of main faces in the lamination direction is defined as dimension T, and the distance between one main face and the second internal electrode closest to the one main face is defined as dimension Tg1. In this case, the relational expression Lg > b - (2 × b × Tg1 / T) is satisfied.

[0007] The multilayer capacitor according to the present invention has a first external electrode disposed on a pair of end faces facing each other, and a second external electrode disposed on at least one of a pair of side faces extending in the facing direction of the pair of end faces. This multilayer capacitor can be mounted on an electronic device by joining each external electrode to the electronic device. Therefore, this multilayer capacitor is mounted on an electronic device with any one of the main faces as the mounting face. Here, as a result of intensive research, the inventors have found that there is a high correlation between the position of cracks generated in the element due to thermal expansion or the like and the dimensions of each component of the multilayer capacitor. More specifically, when viewed from the direction in which the pair of side faces face each other, a virtual line segment connecting the end in the facing direction of the recessed portion that has recessed from one end face to one main face and the midpoint of one end face in the stacking direction is set in the sintered electrode layer covering one end face. The inventors have found that cracks are likely to occur in the region (referred to as the crack generation region) between the virtual line segment and the corner of the sintered electrode layer. On the other hand, the multilayer capacitor according to the present invention satisfies the relational expression of Lg>b-(2×b×Tg1 / T). In this case, on one end face side, even if the end of the second internal electrode having a different polarity from the first external electrode is the closest to the mounting face, it is located outside the crack generation region. Therefore, it is possible to suppress cracks from reaching any of the second internal electrodes having a different polarity from the first external electrode. Thereby, even when a crack occurs in the element, it is possible to suppress the occurrence of cracks in the region where the plurality of first internal electrodes and the plurality of second internal electrodes are stacked. From the above, short circuits can be suppressed.

[0008] When the distance between one main face and the first internal electrode closest to the one main face is defined as dimension Tg2, the relational expressions of Tg1>Tg2 and Lg>b-(2×b×Tg2 / T) may be satisfied. In this case, from one main face, the first internal electrode is closer than the second internal electrode. At this time, in the plurality of first internal electrodes, the portions corresponding to the ends of the plurality of second internal electrodes on one end face side are located outside the crack generation region. Thereby, even when a crack occurs in the element, it is possible to more reliably suppress the occurrence of cracks in the region where the plurality of first internal electrodes and the plurality of second internal electrodes are stacked. From the above, short circuits can be suppressed.

[0009] The dimension Lg may be smaller than the dimension b. In this case, the area of the region where the plurality of first internal electrodes and the plurality of second internal electrodes are stacked can be secured. Therefore, the capacitance can be secured.

[0010] When the length of the element body in the facing direction is defined as the dimension L, the relational expression Lg < 0.14 × L may be satisfied. In this case, the area of the region where the plurality of first internal electrodes and the plurality of second internal electrodes are stacked can be secured. Therefore, the capacitance can be secured.

[0011] The dimension Tg1 may be 90 μm to 150 μm. In this case, the stacking height of the plurality of first internal electrodes and the plurality of second internal electrodes can be secured. Therefore, the capacitance can be secured.

[0012] The dimension b may be 180 μm to 240 μm. In this case, the region where cracks occur in the element body can be kept small. Therefore, short - circuit can be suppressed.

[0013] The length in the longitudinal direction may be 1.6 mm or more, and the length in the short - hand direction may be 0.8 mm or more. In this case, the size of the multilayer capacitor in the longitudinal direction and the short - hand direction can be secured. Therefore, the capacitance can be secured. Also, in such a large - sized chip - type multilayer capacitor, the effect of suppressing short - circuit can be obtained more remarkably.

Advantages of the Invention

[0014] According to the present invention, a multilayer capacitor capable of suppressing short - circuit can be provided.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Mode for Carrying Out the Invention

[0016] Hereinafter, with reference to the drawings, a preferred embodiment of a multilayer capacitor according to one aspect of the present disclosure will be described in detail.

[0017] With reference to FIG. 1, a multilayer capacitor according to the present disclosure will be described. FIG. 1 is a schematic perspective view showing a through capacitor 1 according to an embodiment of the present invention. In the present embodiment, the through capacitor 1 is exemplified and described as a multilayer capacitor.

[0018] The through-hole capacitor 1 is a so-called three-terminal multilayer capacitor. The through-hole capacitor 1 can be mounted on an electronic device such as a circuit board as an example. In the present embodiment, the through-hole capacitor 1 is, for example, of the 1608 size (1.6 mm × 0.8 mm × 0.8 mm). The chip size of the through-hole capacitor 1 is not particularly limited, but it may be 1608 size or more, that is, the length in the longitudinal direction is 1.6 mm or more, the length in the short direction is 0.8 mm or more, and the thickness is 0.8 mm or more. As shown in FIG. 1, the through-hole capacitor 1 includes a body 2, a pair of first external electrodes 3, 3, and a pair of second external electrodes 5.

[0019] The body 2 is formed by laminating dielectric layers in the height direction of the through-hole capacitor 1. Each dielectric layer is composed of, for example, a sintered body of a ceramic green sheet containing a dielectric material (dielectric ceramic such as BaTiO3-based, Ba(Ti,Zr)O3-based, or (Ba,Ca)TiO3-based). In the actual body 2, each dielectric layer is integrated to such an extent that the boundary between the dielectric layers cannot be visually recognized. As shown in FIG. 1, the shape of the body 2 is substantially rectangular parallelepiped. The rectangular parallelepiped shape includes the shape of a rectangular parallelepiped with chamfered corners and ridge lines. The rectangular parallelepiped shape also includes the shape of a rectangular parallelepiped with rounded corners and ridge lines.

[0020] The base body 2 has a pair of end faces 2a, 2a facing each other. Hereinafter, the direction in which the pair of end faces 2a, 2a face each other is referred to as the facing direction D2. The base body 2 is located between the pair of end faces 2a, 2a and has a pair of side faces 2b, 2b and a pair of main faces 2c, 2c extending in the facing direction D2 of the pair of end faces 2a, 2a. Hereinafter, the direction in which the pair of main faces 2c, 2c face each other is referred to as the stacking direction D1, and the direction in which the pair of side faces 2b, 2b face each other is referred to as the width direction D3. In the present embodiment, the stacking direction D1 coincides with the height direction of the multilayer capacitor 1. The lengths of the facing direction D2 and the width direction D3 in the base body 2 are larger than the length of the stacking direction D1. Also, the length of the facing direction D2 in the base body 2 is larger than the length of the width direction D3. The length of the facing direction D2 of the base body 2 may be 900 μm to 3400 μm. The length of the width direction D3 of the base body 2 may be 460 μm to 1860 μm. The length of the stacking direction D1 (dimension T described later) of the base body 2 may be 280 μm to 1250 μm, preferably 550 μm to 900 μm.

[0021] Each of the pair of first external electrodes 3, 3 is disposed on the pair of end faces 2a. The pair of first external electrodes 3, 3 are spaced apart from each other and face each other in the facing direction D2. The first external electrode 3 has a main body portion 3a disposed on the end face 2a, a pair of wrapping portions 3b disposed on the side face 2b, and a pair of wrapping portions 3c disposed on the main face 2c. The wrapping portion 3b extends from both ends in the width direction D3 of the main body portion 3a in the facing direction D2. The wrapping portion 3c extends from both ends in the stacking direction D1 of the main body portion 3a in the facing direction D2. The main body portion 3a, the wrapping portions 3b, 3c are connected to each other.

[0022] The main body portion 3a of the first external electrode 3 covers the entire corresponding end face 2a. In the present embodiment, the wrapping portions 3b, 3c cover a portion having a length of 0.19 mm in the facing direction D2 from each end face 2a.

[0023] Each of the pair of second external electrodes 5, 5 is spaced apart from the pair of first external electrodes 3, 3 and is disposed on the pair of side surfaces 2b. In the present embodiment, the second external electrode 5 is disposed at the central portion of the element body 2 in the facing direction D2. The pair of second external electrodes 5 are spaced apart from each other and face each other in the width direction D3. The second external electrode 5 has a main body portion 5b disposed on the side surface 2b and a pair of wrapping portions 5c disposed on the main surface 2c. The wrapping portions 5c extend from both end portions of the main body portion 5b in the stacking direction D1 to the width direction D3. The main body portion 5b and the wrapping portions 5c are connected to each other.

[0024] The main body portion 5b of the second external electrode 5 has a width of a predetermined length in the facing direction D2 at the central portion of the side surface 2b in the facing direction D2. Further, the main body portion 5b covers the entire stacking direction D1 of the side surface 2b. The surface area of the main body portion 5b of the second external electrode 5 is smaller than the surface area of the main body portion 3a of the first external electrode 3. In the present embodiment, the length of the main body portion 5b in the facing direction D2 is 0.48 mm. Further, the length of the wrapping portion 5c in the width direction D3 is 0.25 mm.

[0025] Subsequently, with reference to FIGS. 2 to 5, the configuration inside the element body 2 in the through capacitor 1 will be described.

[0026] FIGS. 2 to 5 are schematic cross-sectional views showing the through capacitor 1 according to the embodiment of the present invention. FIG. 2 shows a cross-section of the through capacitor 1 in a plane parallel to the pair of side surfaces 2b, 2b. FIG. 3 shows a cross-section of the through capacitor 1 in a plane parallel to the pair of end surfaces 2a, 2a.

[0027] As shown in FIGS. 2 and 3, a plurality of first internal electrodes 7 and a plurality of second internal electrodes 9 are arranged in the base body 2. The first internal electrodes 7 and the second internal electrodes 9 are made of a conductive material (such as Ni or Cu) commonly used as internal electrodes of a multilayer electrical element. The first internal electrodes 7 and the second internal electrodes 9 are configured as sintered bodies of a conductive paste containing the above conductive material. Each of the plurality of first internal electrodes 7 and the plurality of second internal electrodes 9 is spaced apart from each other in the stacking direction D1 and is alternately stacked via the dielectric layer of the base body 2.

[0028] FIG. 4 shows a cross section of the through-capacitor 1 in a plane parallel to the pair of main surfaces 2c, 2c. FIG. 4 shows a cross-sectional view in which one of the plurality of first internal electrodes 7 is exposed. The first internal electrode 7 has a main electrode portion 7a having a substantially rectangular shape and a connection portion 7b. The main electrode portion 7a has a long side along the facing direction D2 and a short side along the width direction D3. As an example, the length of the long side of the main electrode portion 7a is 1.29 mm, and the length of the short side is 0.7 mm. Further, the connection portion 7b extends from the short side of the main electrode portion 7a toward the facing direction D2. The main electrode portion 7a and the connection portion 7b are integrally formed. The length of the connection portion 7b in the width direction D3 is smaller than the length of the main electrode portion 7a in the width direction D3. In the present embodiment, the length of the connection portion 7b in the width direction D3 is 0.35 mm.

[0029] Each of the first internal electrodes 7 is exposed from the pair of end faces 2a, 2a and is not exposed from the pair of side faces 2b, 2b and the pair of main faces 2c, 2c (see FIG. 2). Each of the first internal electrodes 7 is connected to the first external electrode 3 at the end face 2a. More specifically, the connection portion 7b formed on the short side of the main electrode portion 7a is exposed from the pair of end faces 2a, 2a. Further, the end portion 7d constituting the long side of the main electrode portion 7a is spaced apart from the second external electrode 5.

[0030] FIG. 5 shows a cross-section of the through-capacitor 1 in a plane parallel to the pair of main surfaces 2c, 2c. FIG. 5 shows a cross-sectional view in which one of the plurality of second internal electrodes 9 is exposed. The second internal electrode 9 has a main electrode portion 9a having a substantially rectangular shape and a connection portion 9b. The main electrode portion 9a has a long side along the opposing direction D2 and a short side along the width direction D3. As an example, the length of the long side of the main electrode portion 9a is 1.29 mm, and the length of the short side is 0.7 mm. Further, the connection portion 9b extends from the long side of the main electrode portion 9a toward the width direction D3. The main electrode portion 9a and the connection portion 9b are integrally formed. The length of the connection portion 9b in the opposing direction D2 is smaller than the length of the main electrode portion 9a in the opposing direction D2. In the present embodiment, the length of the connection portion 9b in the opposing direction D2 is 0.08 mm.

[0031] Each of the second internal electrodes 9 is exposed from the pair of side surfaces 2b, 2b and is not exposed from the pair of end surfaces 2a, 2a and the pair of main surfaces 2c, 2c (see FIG. 3). Each of the second internal electrodes 9 is connected to the second external electrode 5 on the side surface 2b. More specifically, the connection portion 9b formed on the long side of the main electrode portion 9a is exposed from the pair of side surfaces 2b, 2b. Further, the end portion 9d constituting the short side of the main electrode portion 9a is separated from the first external electrode 3.

[0032] Subsequently, the configuration of the first external electrode 3 will be described with reference to FIG. 6.

[0033] FIG. 6 is an enlarged cross-sectional view of a main part showing a configuration example of the first external electrode 3. As shown in FIG. 6, the first external electrode 3 is composed of a first sintered electrode layer 31, a second sintered electrode layer 32, a first plating layer 33, and a second plating layer 34.

[0034] The first sintered electrode layer 31 covers the end face 2a and is connected to a plurality of first internal electrodes 7. The first sintered electrode layer 31 has a main body portion 31a disposed on the end face 2a and a pair of wrapping portions 31c, 31c disposed on a pair of main faces 2c, 2c. In the present embodiment, the main body portion 31a covers the entire end face 2a and is connected to a connection portion 7b (see FIG. 4) exposed from the end face 2a. The wrapping portion 31c extends from both end portions of the main body portion 31a in the stacking direction D1 toward the opposing direction D2. Thereby, a corner portion 31r is formed by the main body portion 31a and the wrapping portion 31c. In the present embodiment, at the end portion 31d of the wrapping portion 31c in the opposing direction D2, the ridge line portion is rounded. The second sintered electrode layer 32 is disposed on the first sintered electrode layer 31 and covers the entire end face 2a via the first sintered electrode layer 31. That is, the second sintered electrode layer 32 covers the main body portion 31a of the first sintered electrode layer 31.

[0035] The first plating layer 33 is formed on the first sintered electrode layer 31 and the second sintered electrode layer 32 (hereinafter sometimes simply referred to as the "sintered electrode layer") by plating treatment. That is, the entire outer surface of the sintered electrode layer is covered by the first plating layer 33. Here, as an example, electroplating treatment may be used for the plating treatment. The second plating layer 34 is formed on the first plating layer 33 by plating treatment. That is, the entire outer surface of the first plating layer 33 is covered by the second plating layer 34. The main body portion 3a includes the sintered electrode layer, the first plating layer 33, and the second plating layer 34. The wrapping portion 3c includes the first sintered electrode layer 31, the first plating layer 33, and the second plating layer 34. Although not shown in FIG. 6, the configuration of the wrapping portion 3b is the same as that of the wrapping portion 3c.

[0036] The sintered electrode layer is formed by baking a conductive paste in a state where it is applied to the surface of the base body 2. The sintered electrode layer is formed by sintering the metal components (metal powders) contained in the conductive paste. In the present embodiment, the sintered electrode layer is a sintered metal layer made of Cu. Also, the sintered electrode layer may be a sintered metal layer made of Ni. As the conductive paste, a mixture of a powder made of a metal (for example, Cu or Ni), a glass component, an organic binder, and an organic solvent is used.

[0037] In the present embodiment, the first plating layer 33 is a Ni plating layer formed by Ni plating. Also, the first plating layer 33 may be a Sn plating layer, a Cu plating layer, or an Au plating layer. In the present embodiment, the second plating layer 34 is a Sn plating layer formed by Sn plating. Also, the second plating layer 34 may be a Cu plating layer or an Au plating layer.

[0038] Subsequently, with reference to FIG. 7, the mounting state of the through-capacitor 1 will be described.

[0039] As described above, the through-capacitor 1 is mounted on an electronic device as an example. The electronic device is, for example, a circuit board or other electronic component. FIG. 7 is a schematic cross-sectional view showing the mounting state of the through-capacitor. As shown in FIG. 7, the through-capacitor 1 is mounted on the electronic device 20 with one of the pair of main surfaces 2c, 2c as the mounting surface 21. More specifically, the through-capacitor 1 is mounted on the electronic device 20 such that one of the pair of main surfaces 2c, 2c faces the electronic device 20. In the present embodiment, one of the main surfaces 2c serves as the mounting surface 21 for the electronic device 20.

[0040] The pair of first external electrodes 3, 3 are soldered to pad electrodes (not shown) of the electronic device 20 as an example. That is, solder fillets 22 are formed between the first external electrode 3 and the pad electrode, and between the second external electrode 5 and the pad electrode. In the present embodiment, the solder fillet 22 is formed between one of the pair of recessed portions 3c, 3c that is in contact with the mounting surface 21 and the electronic device 20. The solder fillet 22 is also in contact with the main body portion 3a. The solder fillet 22 is formed between one of the pair of recessed portions 5c, 5c that is in contact with the mounting surface 21 and the electronic device 20.

[0041] Subsequently, with reference to FIG. 8, the dimensional relationships of the respective members in the through capacitor 1 described above will be described.

[0042] FIG. 8 is a schematic cross-sectional view showing the dimensional relationships of the respective members in the through capacitor 1. In FIG. 8, only the first sintered electrode layer 31 is shown in the configuration of the first external electrode 3, and other configurations are omitted. As shown in FIG. 8, it is defined as follows.

[0043] The dimension b is the intrusion dimension in the facing direction D2 of the intrusion portion 31c that extends from one end face 2a into the mounting surface 21 (one main surface 2c) in the first sintered electrode layer 31 covering one end face 2a. The dimension Lg is the distance in the facing direction D2 between one end face 2a and the end portions 9d of the plurality of second internal electrodes 9 on the one end face 2a side. During energization, the first internal electrode 7 becomes an internal electrode of the same polarity as the first external electrode 3, and the second internal electrode 9 becomes an internal conductor of the opposite polarity to the first external electrode 3. Therefore, the dimension Lg is the separation distance in the facing direction D2 of the internal electrodes of the opposite polarity with respect to the first external electrode 3. The dimension T is the distance between a pair of main surfaces 2c, 2c in the stacking direction D1. The dimension Tg1 is the distance between the mounting surface 21 and the second internal electrode 9 closest to the mounting surface 21. That is, the dimension Tg1 is the distance between the mounting surface 21 and the outermost internal electrode of the opposite polarity with respect to the first external electrode 3. The dimension Tg2 is the distance between the mounting surface 21 and the first internal electrode 7 closest to the mounting surface 21. That is, the dimension Tg2 is the distance between the mounting surface 21 and the outermost internal electrode of the same polarity with respect to the first external electrode 3. The dimension L is the length of the element body 2 in the facing direction D2 (see FIG. 2).

[0044] The virtual line segment C is a line segment connecting the end portion 31d in the facing direction D2 of the intrusion portion 31c of the first sintered electrode layer 31 and the midpoint Tc in the stacking direction D1 of one end face 2a. The intersection point P1 is the intersection of the virtual straight line extending the second internal electrode 9 closest to the mounting surface 21 in the facing direction D2 and the virtual line segment C. The intersection point L1 is the intersection of the virtual perpendicular line extending from the intersection point P1 toward the mounting surface 21 and the mounting surface 21. The length of the perpendicular line extending from the intersection point P1 to the intersection point L1 is equal to the dimension Tg1. The intersection point P2 is the intersection of the virtual straight line extending the first internal electrode 7 closest to the mounting surface 21 in the facing direction D2 and the virtual line segment C. The intersection point L2 is the intersection of the virtual perpendicular line extending from the intersection point P2 toward the mounting surface 21 and the mounting surface 21. The length of the perpendicular line extending from the intersection point P2 to the intersection point L2 is equal to the dimension Tg2.

[0045] In this embodiment, the dimension Lg is smaller than the dimension b. That is, the end portion 9d of the second internal electrode 9 is located outside in the facing direction D2 than the end portion 31d of the wrapping portion 31c. Further, the dimension Lg satisfies the relational expression of Lg < 0.14×L. The dimension Lg may be 90 μm to 440 μm, preferably 90 μm to 250 μm, and more preferably 90 μm to 190 μm. The dimension Tg1 may be 60 μm to 160 μm, preferably 90 μm to 150 μm. The dimension b may be 160 μm to 320 μm, preferably 180 μm to 240 μm.

[0046] As shown in FIG. 8, the triangle having the end portion 31d, the midpoint Tc, and the corner portion 31r as vertices is similar to the triangle having the end portion 31d, the intersection point P1, and the intersection point L1 as vertices. Therefore, assuming that the distance between one end face 2a and the intersection point P1 is X, from the ratio of the side lengths, the following relational expression of formula (1) is satisfied. Thereby, the relational expression of formula (2) is satisfied. In the through capacitor 1 according to the present invention, the dimension Lg is larger than X. That is, the relational expression of formula (3) is satisfied. T / 2:Tg1=b:(b-X) …(1) X=b-(2×b×Tg1 / T) …(2) Lg>b-(2×b×Tg1 / T) …(3)

[0047] In the example shown in FIG. 8, the first internal electrode 7 closest to the mounting surface 21 is closer to the mounting surface 21 than the second internal electrode 9 closest to the mounting surface 21. In such a state, the following relational expression of formula (4) is satisfied. The triangle having the end portion 31d, the midpoint Tc, and the corner portion 31r as vertices is similar to the triangle having the end portion 31d, the intersection point P2, and the intersection point L2 as vertices. Therefore, assuming that the distance between one end face 2a and the intersection point P2 is Y, from the ratio of the side lengths, the relational expression of formula (5) is satisfied. Thereby, the relational expression of formula (6) is satisfied. In the through capacitor 1 according to the present invention, the dimension Lg is larger than Y. That is, the relational expression of formula (7) is satisfied. Tg1>Tg2 …(4) T / 2:Tg2=b:(b - Y) …(5) Y = b-(2×b×Tg2 / T) …(6) Lg>b-(2×b×Tg2 / T) …(7)

[0048] In the example of FIG. 8, the aspect in which one main surface 2c is the mounting surface 21 has been described. Also, in the example of FIG. 8, the dimensional relationship on one end face 2a side and one main surface 2c side has been described. In the present embodiment, the relational expressions described above are also satisfied for the other end face 2a side facing one end face 2a and one main surface 2c side. Further, when the other main surface 2c facing one main surface 2c is the mounting surface 21, the through capacitor 1 also satisfies the relational expression of formula (3) for one end face 2a side and the other main surface 2c side. Also, the through capacitor 1 satisfies the relational expression of formula (3) for the other end face 2a side and the other main surface 2c side. Also, on the other main surface 2c side, Tg1 <Tg2, but in this case, if the relational expression of formula (3) holds, the relational expression of formula (7) naturally holds.

[0049] When the three-terminal type through capacitor 1 as described above is mounted on the electronic device 20, for example, the first external electrode 3 and the second external electrode 5 are soldered to the electronic device 20. At this time, in a conventional through capacitor, due to thermal expansion or the like, the peripheral structure of each external electrode bends, and cracks may occur in the element body. There has been a problem that such cracks may cause the internal electrodes to short-circuit.

[0050] Here, as a result of intensive research, the present inventors have found that there is a high correlation between the position of cracks generated in the base body 2 due to thermal expansion or the like and the dimensions of each component of the through capacitor 1. More specifically, when viewed from the direction (width direction D3) in which a pair of side surfaces 2b, 2b face each other, among the first sintered electrode layers 31 covering one end surface 2a, an end portion 31d in the facing direction D2 of the recessed portion 31c that has recessed from one end surface 2a to one main surface 2c and the midpoint Tc of one end surface 2a in the stacking direction D1 are connected to set a virtual line segment C. The present inventors have found that cracks are likely to occur in the region (referred to as the crack generation region CR) between the virtual line segment C and the corner portion 31r of the first sintered electrode layer 31.

[0051] On the other hand, the through capacitor 1 according to the present invention satisfies the relational expression of formula (3). In this case, on the side of one end surface 2a, even if the end portion 9d of the second internal electrode 9 having a different polarity from the first external electrode 3 is the closest to the mounting surface 21, it is located outside the crack generation region CR. Therefore, it is possible to suppress cracks from reaching any of the second internal electrodes 9 having a different polarity from the first external electrode 3. Thereby, even when a crack occurs in the base body 2, it is possible to suppress the occurrence of a crack in the region where the plurality of first internal electrodes 7 and the plurality of second internal electrodes 9 are stacked. From the above, short circuits can be suppressed.

[0052] Also, in the present embodiment, on the side of one main surface 2c (mounting surface 21), the relational expression of formula (4) is satisfied. At this time, even when the relational expression of formula (3) is satisfied, the portion (capacitance portion) of the first internal electrode 7 corresponding to the second internal electrode 9 may enter inside the crack generation region CR. Each of the first internal electrodes 7 has the same polarity as each other. However, even for internal electrodes of the same polarity, a problem may occur in the through capacitor 1 due to the occurrence of a crack in the capacitance portion. Therefore, when the relational expression of formula (4) is satisfied on the mounting surface 21 side, it is preferable that the relational expression of formula (7) is satisfied.

[0053] When the distance between one main surface 2c and the first internal electrode 7 closest to the one main surface 2c is defined as dimension Tg2, the relational expressions of Formula (4) and Formula (7) are satisfied. In this case, from the one main surface 2c, the first internal electrode 7 is closer than the second internal electrode 9. At this time, in the plurality of first internal electrodes 7, the portions corresponding to the ends 9d of the plurality of second internal electrodes 9 on the one end face 2a side are located outside the crack generation region CR. Thereby, even when a crack occurs in the element body 2, it is possible to more reliably suppress the occurrence of a crack in the region where the plurality of first internal electrodes 7 and the plurality of second internal electrodes 9 are laminated. From the above, short circuit can be suppressed.

[0054] Dimension Lg is smaller than dimension b. Also, when the length of the element body 2 in the facing direction D2 is defined as dimension L, the relational expression Lg < 0.14×L is satisfied. In this case, the area of the region where the plurality of first internal electrodes 7 and the plurality of second internal electrodes 9 are laminated can be secured. Therefore, the capacitance can be secured.

[0055] Dimension Tg1 may be 90 μm to 150 μm. Also, the length of the through capacitor 1 in the longitudinal direction (facing direction D2) is 1.6 mm or more, and the length in the short side direction (width direction D3) may be 0.8 mm or more. In this case, the lamination height of the plurality of first internal electrodes 7 and the plurality of second internal electrodes 9 can be secured. Also, the size of the through capacitor 1 in the longitudinal direction and the short side direction can be secured. Therefore, the capacitance can be secured. Also, in such a large chip size through capacitor 1, the effect of suppressing short circuit can be obtained more remarkably.

[0056] Dimension b may be 180 μm to 240 μm. In this case, the region where a crack occurs in the element body 2 can be kept small. Therefore, short circuit can be suppressed.

[0057] Subsequently, with reference to FIGS. 9 and 10, the evaluation test results of the above-described through capacitor will be described.

[0058] Figures 9 and 10 are diagrams showing the evaluation test results of the through-capacitor. In the evaluation test shown in Figure 9, a plurality of through-capacitors with different chip sizes, dimensions T [μm], dimensions b [μm], dimensions Tg1 [μm], and dimensions Lg [μm] were prepared. Also, in this evaluation test, each through-capacitor was mounted on an electronic device, and it was confirmed whether or not a short circuit occurred between the internal electrodes due to cracks generated in the element body caused by thermal expansion or the like. In Figure 9, the chip size is described in JIS notation.

[0059] As shown in Figure 9, in the through-capacitor that does not satisfy the relational expression of Equation (3), a short circuit occurred between the internal electrodes due to the cracks generated in the element body (see the upper diagram in Figure 9). On the other hand, in the through-capacitor that satisfies the relational expression of Equation (3), a short circuit did not occur between the internal electrodes due to the cracks generated in the element body (see the lower diagram in Figure 9). Therefore, it was confirmed that by configuring the through-capacitor so as to satisfy the relational expression of Equation (3), a short circuit between the internal electrodes can be suppressed.

[0060] Also, as shown in Figure 9, according to the through-capacitor in which the dimension Lg is smaller than the dimension b, the through-capacitor in which the dimension Tg1 is 90 μm to 150 μm, the through-capacitor in which the dimension b is 180 μm to 240 μm, and the through-capacitor in which the length in the longitudinal direction is 1.6 mm or more and the length in the short direction is 0.8 mm or more (that is, the chip size is C1608), a short circuit did not occur between the internal electrodes due to the cracks generated in the element body. From the results of this evaluation test, it was confirmed that the through-capacitor that satisfies these relational expressions can more preferably suppress a short circuit between the internal electrodes.

[0061] In the evaluation test shown in FIG. 10, a plurality of through capacitors with different dimensions L [μm] and dimension Lg [μm] were prepared. Also, in this evaluation test, each through capacitor was mounted on an electronic device, and the capacitance of the through capacitor was measured. In the left table in FIG. 10, each numerical value regarding the through capacitor (the through capacitor shown in the lower figure of FIG. 9) in which no short circuit occurred in FIG. 9 is described. That is, in the left table in FIG. 10, the dimension L, dimension Lg, and the ratio of the capacitance of each through capacitor are described. The ratio of the capacitance of each through capacitor was set to 100. Also, in the right table in FIG. 10, each numerical value regarding the through capacitor configured such that the dimension Lg of the through capacitor shown in the left table becomes 0.14×L [μm] is described. That is, in the right table in FIG. 10, the dimension Lg and the ratio of the capacitance of each through capacitor are described. The ratio of the capacitance of each through capacitor indicates the ratio of the capacitance when the capacitance of the through capacitor shown in the left table is set to 100.

[0062] As described above, the dimension Lg is the distance in the facing direction D2 between one end face 2a and the ends 9d of the plurality of second internal electrodes 9 on the one end face 2a side. The larger the dimension Lg, the farther the ends 9d of the second internal electrodes 9 are from the crack generation region CR, so the occurrence of a short circuit becomes less likely. On the other hand, the larger the dimension Lg, the smaller the area of the region where the plurality of first internal electrodes 7 and the plurality of second internal electrodes 9 are laminated on each other. Therefore, although a short circuit can be more reliably suppressed as the dimension Lg increases, the capacitance of the through capacitor 1 becomes smaller.

[0063] Here, the dimension Lg of the through-capacitor shown in the left table of FIG. 10 is set as a suitable dimension that can appropriately obtain the short-circuit suppression effect and also sufficiently obtain the capacitance at each chip size. When the dimension Lg is made larger than this dimension, the ratio of the capacitance decreases below 100%, but if it can be suppressed to 80% or more, it can be said that the capacitance can be sufficiently ensured. As shown in FIG. 10, even when the dimension Lg is 0.14×L [μm], for any chip size, the capacitance of the through-capacitor is 81% or more with respect to the capacitance of the through-capacitor in the left table. Therefore, it was confirmed that a sufficient capacitance can be ensured in a through-capacitor that satisfies the relational expression of Lg < 0.14×L.

[0064] The present invention is not limited to the above-described embodiments.

[0065] In the above-described embodiment, the through-capacitor 1 in which one main surface 2c is the mounting surface 21 is illustrated, but the other main surface 2c may be the mounting surface 21.

[0066] In the above-described embodiment, the relational expression of Equation (3) is satisfied on both sides of the pair of end faces 2a, 2a on one main surface 2c side. Also, regarding both sides of the pair of end faces 2a, 2a on the other main surface 2c side, the relational expression of Equation (3) is satisfied. However, the relational expression of Equation (3) may be satisfied only on either one of the end face 2a sides on the main surface 2c side that is the mounting surface 21 among the pair of main surfaces 2c, 2c.

[0067] Also, the relationship of each dimension is not limited to the above-described ones. Each dimension (dimension b, dimension Lg, dimension L, dimension T, dimension Tg1, and dimension Tg2) can be appropriately changed as long as the effects of the present invention are achieved.

[0068] Also, the connection mode of the first internal electrode 7 and the second internal electrode 9 is not limited to the above-described one. The first internal electrode 7 is exposed at at least one end face 2a, and the second internal electrode 9 may be separated from at least one end face 2a.

[0069] Also, the configuration of the first external electrode 3 is not limited to that described above. For example, the first external electrode 3 may not have the second sintered electrode layer 32.

Explanation of Reference Numerals

[0070] 1... Through-capacitor (multilayer capacitor), 2... Element body, 2a... End face, 2b... Side face, 2c... Main face, 3... First external electrode, 5... Second external electrode, 7... First internal electrode, 9... Second internal electrode, 9d... End portion, 31... First sintered electrode layer (sintered electrode layer), 31c... Wrapping portion, b, L, Lg, T, Tg1, Tg2... Dimensions, D1... Laminating direction, D2... Opposing direction (longitudinal direction), D3... Width direction (lateral direction).

Claims

【Claim 1】 A body having a pair of end faces facing each other, a pair of side faces and a pair of main faces that are located between the pair of end faces and extend in the facing direction of the pair of end faces; A pair of first external electrodes disposed on the pair of end faces; A second external electrode that is spaced apart from the pair of first external electrodes and disposed on at least one of the pair of side faces; A plurality of first internal electrodes disposed in the body and exposed from at least one of the end faces; A plurality of second internal electrodes disposed in the body and spaced apart from the one end face, comprising: The pair of first external electrodes includes a sintered electrode layer that covers the pair of end faces and is connected to the plurality of first internal electrodes; Each of the plurality of first internal electrodes and the plurality of second internal electrodes is laminated with each other with the direction in which the pair of main faces face each other as the lamination direction; Among the sintered electrode layers covering the one end face, the intrusion dimension in the facing direction of the intrusion portion that intrudes from the one end face to the one main face is defined as dimension b; The distance in the facing direction between the one end face and the end portions of the plurality of second internal electrodes on the one end face side is defined as dimension Lg; The distance between the pair of main faces in the lamination direction is defined as dimension T; When the distance between the one main face and the second internal electrode closest to the one main face is defined as dimension Tg1, The relational expression Lg > b - (2 × b × Tg1 / T) is satisfied; When the length of the body in the facing direction is defined as dimension L, The relational expression Lg < 0.14 × L is satisfied; The dimension Tg1 is 90 μm to 150 μm; The dimension b is 180 μm to 240 μm; Lg is 90 μm to 190 μm; The plurality of first internal electrodes and the plurality of second internal electrodes include a first adjacent internal electrode adjacent to one of the pair of main surfaces and a second adjacent internal electrode adjacent to the other of the pair of main surfaces. The plurality of first internal electrodes and the plurality of second internal electrodes are alternately arranged from the first adjacent internal electrode to the second adjacent internal electrode, and each of the first internal electrodes is adjacent to the corresponding second internal electrode, and each of the second internal electrodes is adjacent to the corresponding first internal electrode. A multilayer capacitor having a chip size of 1608. Claim 2 When the distance between the one main surface and the first internal electrode closest to the one main surface is defined as dimension Tg2, The multilayer capacitor according to claim 1, satisfying the relational expressions of Tg1 > Tg2 and Lg > b - (2 × b × Tg2 / T). Claim 3 The multilayer capacitor according to claim 1 or 2, wherein the dimension Lg is smaller than the dimension b.

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