Driver circuit, transmitter, and communication system

Abstract

A first driver (12) receives a first power supply (VDE) and operates, and outputs signals EXP, EXN in response to input signals ALP, ALN. A regulator (30) receives a second power supply (VDN) that has a lower voltage than the first power supply (VDE), and supplies a third power supply (VREG) that has a lower voltage than the second power supply (VDN). The second driver (11) receives the third power supply (VREG) and operates, and outputs signals EXP, EXN in response to input signals INP, INN. The outputs of the first driver (12) and the outputs of the second driver (11) are commonly connected to output terminals (21, 22).

Description

Technical Field

[0001] The present disclosure relates to a driver circuit used in a communication system.

Background Art

[0002] In a communication system, communication may be performed by connecting devices that transmit and receive signals conforming to a predetermined standard. As one of the communication standards, there is the MIPI D-PHY standard. This standard includes a low-speed low-power signal transmission mode (LPTX mode) and a high-speed small-amplitude signal transmission mode (HSTX mode). In the MIPI D-PHY standard, a high-speed low-power interface is realized by combining the LPTX mode and the HSTX mode at a certain ratio. However, when the operation rate of the HSTX mode is high with respect to the LPTX mode, the power consumption increases, and further power reduction is required.

[0003] Patent Document 1 discloses a configuration for switching the operation of a driver circuit according to the range of the power supply voltage so that wired communication can be appropriately performed in a communication system.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When the configuration of Patent Document 1 is applied to MIPI D-PHY where the LPTX mode is essential, the regulator that supplies power to the driver circuit needs to provide a power supply voltage equal to or higher than the signal amplitude (e.g., 1.2V) in the LPTX mode. On the other hand, in the HSTX mode, in order to pass a certain DC current through the output to obtain the desired output amplitude, power corresponding to the product of this DC current and the power supply voltage given to the regulator is consumed. For this reason, there is a problem that the power consumption in the HSTX mode becomes large.

[0006] Also, in the configuration of Patent Document 1, the driver circuit needs to use transistors with high breakdown voltage in order to support the LPTX mode. For this reason, it is more difficult to reduce power consumption.

[0007] An object of the present disclosure is to achieve power reduction for a driver circuit having two signal transmission modes with different amplitudes such as the LPTX mode and the HSTX mode.

Means for Solving the Problems

[0008] In a first aspect of the present disclosure, the driver circuit includes a first driver provided between a first power supply of a first voltage and a ground power supply, receiving a first input signal, and outputting a signal corresponding to the first input signal; a regulator connected to a second power supply of a second voltage lower than the first voltage and supplying a third power supply of a third voltage lower than the second voltage; a second driver provided between the third power supply and the ground power supply, receiving a second input signal, and outputting a signal corresponding to the second input signal; and an output terminal to which the output of the first driver and the output of the second driver are commonly connected.

[0009] According to this aspect, the first driver operates by receiving a first power supply and outputs a signal corresponding to the first input signal. The regulator receives a second power supply having a voltage lower than the first power supply supplied to the first driver, and supplies a third power supply having a voltage lower than the second power supply. The second driver operates by receiving the third power supply and outputs a signal corresponding to the second input signal. The outputs of the first driver and the second driver are commonly connected to the output terminal. That is, the first driver and the second driver are provided in parallel, and the power supply voltage of the regulator that supplies power to the second driver is lower than the power supply voltage of the first driver. Thereby, in the mode in which the second driver operates, the power consumption in the current path from the power supply of the regulator via the driver circuit is small, so that power reduction of the driver circuit can be realized.

[0010] In the second aspect of the present disclosure, the driver circuit includes a first driver provided between a first power supply of a first voltage and a ground power supply, receiving a first input signal, and outputting a signal corresponding to the first input signal; a regulator connected to a second power supply of a second voltage lower than the first voltage and supplying a third power supply of a third voltage lower than the second voltage; a second driver provided between the third power supply and the ground power supply, receiving a second input signal, and outputting a signal corresponding to the second input signal; an output terminal to which the output of the first driver and the output of the second driver are commonly connected; and an ESD (Electro Static Discharge) protection circuit provided between the second power supply and the output terminal and including one or two or more diodes connected in series.

[0011] According to this aspect, the same operational effects as those of the first aspect described above can be obtained. In addition, an ESD protection circuit including one or two or more diodes connected in series is provided between the second power supply and the output terminal. Thereby, the driver circuit can be protected from ESD.

[0012] In a third aspect of the present disclosure, the driver circuit includes a first driver provided between a first power supply of a first voltage and a ground power supply, receiving a first input signal, and outputting a signal corresponding to the first input signal; a regulator connected to a second power supply of a second voltage lower than the first voltage and supplying a third power supply of a third voltage lower than the second voltage; a second driver provided between the third power supply and the ground power supply, receiving a second input signal, and outputting a signal corresponding to the second input signal; an output terminal to which the output of the first driver and the output of the second driver are commonly connected; and a load fluctuation countermeasure circuit that suppresses fluctuations in the third voltage of the third power supply when transitioning from a first mode in which the first driver operates to a second mode in which the second driver operates. The load fluctuation countermeasure circuit is provided between the third power supply and the ground power supply and includes a current path whose conduction state and non-conduction state are switched according to a given signal. When transitioning from the first mode to the second mode, the current path is configured to be set to a conductive state during the first mode and to be set to a cut-off state when transitioning to the second mode by applying a signal to the current path.

[0013] According to this aspect, the same operational effects as those of the first aspect described above can be obtained. In addition, the load fluctuation countermeasure circuit can suppress voltage fluctuations in the third power supply when transitioning from the first mode in which the first driver operates to the second mode in which the second driver operates.

Advantages of the Invention

[0014] According to the present disclosure, it is possible to achieve power reduction for a driver circuit having two signal transmission modes with different amplitudes.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Embodiments for Carrying Out the Invention

[0016] Hereinafter, embodiments will be described with reference to the drawings. In the circuit configuration diagrams shown below, the illustration is simplified centering on the components related to the present disclosure. For this reason, for example, components shown as being directly connected may have other components arranged therebetween in the actual circuit configuration and may be indirectly connected

[0017] In the following description, "high", "low", "1", and "0" of a signal mean the logical levels on the high potential side and the low potential side of the signal. Also, "on" and "off" of a transistor mean whether the transistor is in a conductive state or a non-conductive state. Also, symbols such as "VDE", "VDN", "VREG", and "VSS" are used to represent both the power source itself and the power source potential. Symbols such as "R1" are used to represent both the resistor element itself and the resistance value of the resistor element

[0018] FIG. 1 is a schematic diagram of a configuration example of a communication system. The communication system 1 shown in FIG. 1 includes a transmitter 2, a receiver 3, and a transmission line 4. The transmitter 2 includes a transmission circuit 10 and a control circuit 5 that controls the transmission circuit 10. The receiver 3 includes a reception circuit 6 having a termination resistor Rt. The termination resistor Rt is, for example, 100Ω. The transmission line 4 is configured to be able to transmit differential signals and has a P-side transmission line 41 and an N-side transmission line 42. The output terminals 21 and 22 of the transmission circuit 10 are respectively connected to the P-side transmission line 41 and the N-side transmission line 42 of the transmission line 4. Here, it is assumed that the communication system 1 conforms to the MIPI D-PHY standard. As described above, in the MIPI D-PHY standard, a high-speed and low-power interface is realized by combining the LPTX mode and the HSTX mode

[0019] The transmission circuit 10 includes a high-speed driver (HSTX) 11, a low-speed driver (LPTX) 12, and a regulator 30. The output of the high-speed driver 11 and the output of the low-speed driver 12 are commonly connected to the output terminals 21 and 22 of the transmission circuit 10. The regulator 30 receives a control signal CTRL from the control circuit 5, generates a power supply voltage VREG, and supplies it to the high-speed driver 11. The high-speed driver 11 receives differential signals INP and INN from the control circuit 5 and generates signals EXP and EXN to be output to the transmission line 4. The low-speed driver 12 receives single-ended signals ALP and ALN from the control circuit 5 and generates signals EXP and EXN to be output to the transmission line 4. The transmission circuit 10 is an example of a driver circuit according to the present disclosure. The high-speed driver 11 corresponds to the second driver, and the low-speed driver 12 corresponds to the first driver.

[0020] The signals HS_EN and HS_ENB are switching signals between the HSTX mode and the LPTX mode and are complementary signals. When the signal HS_EN is high and the signal HS_ENB is low, the transmission circuit 10 operates in the HSTX mode. In the HSTX mode, the high-speed driver 11 operates. When the signal HS_EN is low and the signal HS_ENB is high, the transmission circuit 10 operates in the LPTX mode. In the LPTX mode, the low-speed driver 12 operates. Also, the signal SUSP is a signal used for controlling a load fluctuation countermeasure circuit 40 described later.

[0021] FIG. 2 is a diagram showing a circuit configuration example of the transmission circuit 10. The transmission circuit 10 in FIG. 2 includes a power supply VDE and a power supply VDN as power supplies. The power supply voltage VDN is lower than the power supply voltage VDE (VDN < VDE). For example, VDE is 1.2V and VDN is 0.75V. For example, the power supply VDN is a core power supply and the power supply VDE is an IO power supply. For ESD (Electro Static Discharge) protection, a core power supply clamp circuit 23 is provided between the power supply VDN and the ground power supply VSS, and an IO power supply clamp circuit 24 is provided between the power supply VDE and the ground power supply VSS.

[0022] Regulator 30 generates the power supply VREG for the operation of the high-speed driver 11 from the power supply VDN. The regulator 30 includes a resistor ladder 31, an operational amplifier 32, a P-type transistor MP1, an N-type transistor MN1, and a resistor element R1. The resistor ladder 31 generates a reference voltage VREF by resistively dividing the power supply voltage VDE. The resistor ladder 31 has a function of adjusting the reference voltage VREF around, for example, 0.4 V or 0.2 V according to the control signal CTRL. Between the power supply VDN and the power supply VSS, the P-type transistor MP1, the N-type transistor MN1, and the resistor element R1 are connected in series. The power supply voltage VREG is output from the connection node between the N-type transistor MN1 and the resistor element R1. The operational amplifier 32 has the reference voltage VREF as one input, and the power supply voltage VREG is fed back as the other input, and the output is connected to the gate of the N-type transistor MN1. Thereby, the power supply voltage VREG is set to, for example, 0.4 V or 0.2 V according to the reference voltage VREF. Note that the P-type transistor MP1 is provided for circuit protection, and its gate is fixed at low (0 V).

[0023] The high-speed driver 11 includes N-type transistors MN2, MN3, MN4, MN5, and resistor elements R2, R3, R4. One end of the resistor element R2 is connected to the power supply VREG. Between the other end of the resistor element R2 and the ground power supply VSS, the N-type transistor MN2, the resistor element R3, and the N-type transistor MN4 are connected in series, and in parallel with these, the N-type transistor MN3, the resistor element R4, and the N-type transistor MN5 are connected in series. The signal INP is input to the gates of the N-type transistors MN2, MN5, and the signal INN is input to the gates of the N-type transistors MN3, MN4. The node between the N-type transistor MN2 and the resistor element R3 is connected to the output terminal 21, and the signal EXP is output from the node. The node between the N-type transistor MN3 and the resistor element R4 is connected to the output terminal 22, and the signal EXN is output from the node.

[0024] The low-speed driver 12 includes P-type transistors MP2, MP3, MP4, MP5, N-type transistors MN6, MN7, MN8, MN9, and resistor elements R5, R6, R7, R8. Between the power supply VDE and the ground power supply VSS, the P-type transistors MP2, MP3, the resistor elements R5, R6, and the N-type transistors MN6, MN7 are connected in series. Also, between the power supply VDE and the ground power supply VSS, the P-type transistors MP4, MP5, the resistor elements R7, R8, and the N-type transistors MN8, MN9 are connected in series. The signal ALP is input to the gates of the P-type transistor MP3 and the N-type transistor MN6, and the signal ALN is input to the gates of the P-type transistor MP5 and the N-type transistor MN8. Also, the signal HS_EN is input to the gates of the P-type transistors MP2, MP4, and the signal HS_ENB is input to the gates of the P-type transistors MN7, MN9. The node between the resistor elements R5, R6 is connected to the output terminal 21, and the signal EXP is output from the node. The node between the resistor elements R7, R8 is connected to the output terminal 22, and the signal EXN is output from the node.

[0025] <Operation in HSTX Mode> When the signal HS_EN is high and the signal HS_ENB is low, the transmission circuit 10 enters the HSTX mode and the high-speed driver 11 operates. The low-speed driver 12 does not operate because the P-type transistors MP2, MP4 and the N-type transistors MN7, MN9 are turned off.

[0026] In the HSTX mode, when the signal INP is high and the signal INN is low, the N-type transistors MN2 and MN5 are turned on, and the N-type transistors MN3 and MN4 are turned off. At this time, the current flows from the power supply VREG, through the resistor element R2 → N-type transistor MN2 → output terminal 21 → P-side transmission line 41 → termination resistor Rx of the receiving circuit 6 → N-side transmission line 42 → output terminal 22 → resistor element R4 → N-type transistor MN5 → ground power supply VSS. On the other hand, when the signal INP is low and the signal INN is high, the N-type transistors MN3 and MN4 are turned on, and the N-type transistors MN2 and MN5 are turned off. At this time, the current flows from the power supply VREG, through the resistor element R2 → N-type transistor MN3 → output terminal 22 → N-side transmission line 42 → termination resistor Rx of the receiving circuit 6 → P-side transmission line 41 → output terminal 21 → resistor element R3 → N-type transistor MN4 → ground power supply VSS.

[0027] Here, assume that R2 + MN2 on-resistance, R2 + MN3 on-resistance, R3 + MN4 on-resistance, and R4 + MN5 on-resistance are each designed to be 50Ω. In this case, the total resistance in the current path from the power supply VREG to the ground power supply VSS described above becomes 200Ω including the 100Ω of the termination resistor Rx.

[0028] When the power supply voltage VREG is 0.4V, the current flowing between VREG and VSS becomes 2 (= 0.4×1000 / 200) mA. A differential voltage of 200mV is output to the termination resistor Rt. When the signal INP is high and the signal INN is low, the signal EXP is 300mV and the signal EXN is 100mV. When the signal INP is low and the signal INN is high, the signal EXP is 100mV and the signal EXN is 300mV. In either case, the differential common voltage becomes 200mV.

[0029] Also, when the power supply voltage VREG is 0.2V, the current flowing between VREG and VSS becomes 1 (= 0.2×1000 / 200) mA. A differential voltage of 100mV is output to the termination resistor Rt, and the differential common voltage becomes 100mV.

[0030] <Operation of LPTX Mode> When the signal HS_EN is low and the signal HS_ENB is high, the transmission circuit 10 enters the LPTX mode and the low-speed driver 12 operates. Since both signals INP and INN are low, the high-speed driver 11 does not operate.

[0031] In the LPTX mode, when the signal ALP is high, the P-type transistor MP3 turns off and the N-type transistor MN6 turns on in the low-speed driver 12, so a low level is output as the signal EXP. When the signal ALP is low, the P-type transistor MP3 turns on and the N-type transistor MN6 turns off in the low-speed driver 12, so a high level is output as the signal EXP.

[0032] Also, when the signal ALN is high, the P-type transistor MP5 turns off and the N-type transistor MN8 turns on in the low-speed driver 12, so a low level is output as the signal EXN. When the signal ALN is low, the P-type transistor MP5 turns on and the N-type transistor MN8 turns off in the low-speed driver 12, so a high level is output as the signal EXN.

[0033] (Other Configurations) For ESD protection, diodes D1 and D2 are respectively provided between the output terminals 21, 22 and the power supply VDE, and diodes D3 and D4 are respectively provided between the output terminals 21, 22 and the ground power supply VSS.

[0034] Also, an ESD protection circuit 50 is provided between the power supply VDN and the output terminals 21, 22. The ESD protection circuit 50 includes diodes D5, D6 connected in series between the power supply VDN and the output terminal 21, and diodes D7, D8 connected in series between the power supply VDN and the output terminal 22. In the ESD protection circuit 50, considering the possible voltage difference between the power supply VDN and the output terminals 21, 22 and the threshold voltage of the diodes, the serially connected diodes D5, D6 and the serially connected diodes D7, D8 are provided so that no through current occurs.

[0035] The load fluctuation countermeasure circuit 40 is provided to suppress fluctuations in the power supply voltage VREG when switching from the LPTX mode to the HSTX mode. The load fluctuation countermeasure circuit 40 includes a NOR circuit 41, a resistor element R9, and an N-type transistor MN10. A resistor element R9 and an N-type transistor MN10 are connected in series between the power supply VREG and the ground power supply VSS. Thereby, a current path whose conduction state and non-conduction state are switched by a signal applied to the gate of the N-type transistor MN10 is configured between the power supply VREG and the ground power supply VSS. The NOR circuit 41 receives the signal HS_EN and the signal SUSP as inputs, and the output NG10 is applied to the gate of the N-type transistor MN10.

[0036] FIG. 3 is a signal waveform diagram showing the operation of the transmission circuit 10 when switching from the LPTX mode to the HSTX mode, where (a) shows the case where there is no load fluctuation countermeasure circuit 40, and (b) shows the case where there is a load fluctuation countermeasure circuit 40.

[0037] As shown in FIG. 3(a), in the operation sequence of the MIPI D-PHY-Tx, when switching from the LPTX mode to the HSTX mode, after transitioning from LP-11 → LP-01 → LP-00, it transitions to the HSTX mode. At this time, in the high-speed driver 11, it sharply transitions from a state where no current flows through the current path between VREG and VSS described above to a state where current (for example, 2 mA) flows. Therefore, immediately after transitioning to the HSTX mode, the power supply voltage VREG fluctuates, and as a result, the potentials of the signals EXP and EXN become unstable.

[0038] On the other hand, when the load fluctuation countermeasure circuit 40 is provided, it operates as shown in FIG. 3(b). The signal SUSP is a newly provided signal for the load fluctuation countermeasure circuit 40. When switching from the LPTX mode to the HSTX mode, the signal SUSP transitions from high to low prior to the signal HS_EN transitioning from low to high. At this time, when the output NG10 of the NOR circuit 41 goes high, a current is drawn from the power supply VREG through the resistor element R9 and the N-type transistor MN10. When the signal HS_EN transitions from low to high, the output NG10 of the NOR circuit 41 goes low, and the current path through the resistor element R9 and the N-type transistor MN10 is interrupted. As a result, the potentials of the signals EXP and EXN can be stabilized immediately after transitioning to the HSTX mode.

[0039] Also, a capacitor element C1 is provided between the power supply VREG and the ground power supply VSS. This capacitor element C1 can reduce the impedance of the node of the power supply VREG and stabilize its potential, thereby improving the waveform quality of the output signals EXP and EXN of the high-speed driver 11. The capacitor element C1 is preferably constituted by, for example, a varactor. Thereby, a large-capacity stabilizing capacitor can be realized with a relatively small area and under a low voltage.

[0040] The transmission circuit 10 operates as follows as a whole. The regulator 30 supplies the power supply voltage VREG to the high-speed driver 11. When the signal HS_EN is high (the signal HS_ENB is low), the transmission circuit 10 enters the HSTX mode, the high-speed driver 11 operates, and differential small-amplitude signals EXP and EXN are output in response to the differential input signals INP and INN. At this time, the low-speed driver 12 is in a non-operating state and the output is Hi-Z. On the other hand, when the signal HS_EN is low (the signal HS_ENB is high), the transmission circuit 10 enters the LPTX mode, the low-speed driver 12 operates, and CMOS output signals EXP and EXN are output in response to the single-ended signals ALP and ALN. At this time, the high-speed driver 11 is in a non-operating state and the output is Hi-Z. That is, in the transmission circuit 10, the high-speed driver 11 and the low-speed driver 12 operate exclusively.

[0041] As described above, according to this embodiment, in the transmission circuit 10, the high-speed driver 11 and the low-speed driver 12 are provided in parallel, and the high-speed driver 11 and the low-speed driver 12 are operated by being exclusively switched. Therefore, the power supply VDN of the regulator 30 that supplies the power supply VREG to the high-speed driver 11 can be a power supply having a voltage lower than the power supply VDE of the low-speed driver 12. As a result, the power consumption of the transmission circuit 10 can be reduced. In addition, since the transistors MN2 to MN5 constituting the high-speed driver 11 can be constituted by transistors with low breakdown voltage, the power consumption reduction is facilitated.

[0042] In addition, for ESD protection between the power supply VDN and the output terminals 21 and 22, an ESD protection circuit 50 including serially connected diodes D5 and D6 and serially connected diodes D7 and D8 is provided. In consideration of the potential difference between the power supply VDN and the signals EXP and EXN and the threshold value of the diode, three or more diodes may be provided as necessary, or one diode may be provided.

[0043] Also, by providing the load fluctuation countermeasure circuit 40, fluctuations in the power supply voltage VREG during the switching from the LPTX mode to the HSTX mode can be suppressed. Furthermore, by providing a capacitive element C1 constituted by a varactor between the power supply VREG and the ground power supply VSS, fluctuations in the power supply voltage VREG can be further suppressed.

[0044] Note that in the above-described embodiment, the transmission circuit 10 corresponding to the D-PHY standard of MIPI having the LPTX mode and the HSTX mode is taken as an example for explanation, but the driver circuit according to the present disclosure is not limited thereto, and the present disclosure is applicable to a driver circuit having two signal transmission modes with different amplitudes.

[0045] Note that the present disclosure is not limited to the configurations shown in the above-described embodiments, and many modifications are possible by those having ordinary knowledge in the technical field within the technical idea of the present disclosure. Also, within the scope not departing from the gist of the present disclosure, the components in a plurality of embodiments may be arbitrarily combined.

Industrial Applicability

[0046] In the present disclosure, power consumption reduction of a driver circuit having two signal transmission modes with different amplitudes can be achieved, and thus, for example, it is effective for power saving in a communication system.

Description of Signs

[0047] 1 Communication system 2 Transmitter 3 Receiver 4 Transmission line 10 Transmission circuit (driver circuit) 11 High-speed driver (HSTX, second driver) 12 Low-speed driver (LPTX, first driver) 21, 22 Output terminals 30 Regulator 40 Circuit for countermeasures against load fluctuations 50 ESD protection circuit C1 Capacitive element D5, D6, D7, D8 Diodes R2, R3, R4 Resistive elements MN2, MN3, MN4, MN5 N-type transistors VDE First power supply VDE Second power supply VREG Third power supply

Claims

1. A first driver provided between a first power supply of a first voltage and a ground power supply, receiving a first input signal, and outputting a signal corresponding to the first input signal; A regulator connected to a second power supply of a second voltage lower than the first voltage, and supplying a third power supply of a third voltage lower than the second voltage; A second driver provided between the third power supply and the ground power supply, receiving a second input signal having an amplitude smaller than that of the first input signal, and outputting a signal corresponding to the second input signal; An output terminal to which the output of the first driver and the output of the second driver are commonly connected; A load fluctuation countermeasure circuit for suppressing a fluctuation in the third voltage of the third power supply when transitioning from a first mode in which the first driver operates and the second driver is in a non-operating state to a second mode in which the second driver operates and the first driver is in a non-operating state; The load fluctuation countermeasure circuit is Provided between the third power supply and the ground power supply, and includes a current path whose conduction state and non-conduction state are switched according to a given signal; When transitioning from the first mode to the second mode, a signal is applied to the current path so that the current path is made conductive during the first mode and the current path is cut off when transitioning to the second mode. Driver circuit.

2. In the driver circuit according to Claim 1, A driver circuit provided between the third power supply and the ground power supply and including a capacitive element constituted by a varactor. Driver circuit.

3. In the driver circuit according to Claim 1, The second driver is A first resistor element having one end connected to the third power supply; A first N-type transistor, a second resistor element, and a second N-type transistor connected in series between the other end of the first resistor element and the ground power supply; A third N-type transistor, a third resistor element, and a fourth N-type transistor connected in series in parallel with the first N-type transistor, the second resistor element, and the second N-type transistor between the other end of the first resistor element and the ground power supply; The second input signal is a differential signal, and one signal constituting the differential signal is input to the gates of the first N-type transistor and the fourth N-type transistor, and the other signal is input to the gates of the second N-type transistor and the third N-type transistor. Driver circuit.

4. A transmitter including the driver circuit according to Claim 1.

5. The transmitter according to claim 4, a transmission line connected to the transmitter, and a receiver connected to the transmitter via the transmission line, a communication system.

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