Method for manufacturing a multilayer ceramic capacitor

Abstract

To provide a manufacturing method for a multilayer ceramic capacitor by which a dielectric body can be formed in a flat and proper state on at least a side surface of a multilayer body.SOLUTION: The manufacturing method includes the steps of: printing an internal electrode pattern in a dielectric layer; printing a dielectric body pattern in a region other than the region where the internal electrode pattern is printed; forming a multilayer body by stacking a plurality of dielectric layers; exposing the internal electrode pattern and the dielectric body pattern from a side surface of the multilayer body; removing at least a part of the exposed dielectric body pattern; and forming a dielectric body gap layer in the side surface.SELECTED DRAWING: Figure 25

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a multilayer ceramic capacitor.

Background Art

[0002] In recent years, multilayer ceramic electronic components such as multilayer ceramic capacitors have been miniaturized and increased in capacitance. In order to achieve miniaturization and increased capacitance of a multilayer ceramic capacitor, it is effective to increase the area of the internal electrode layers facing each other by thinning the side margins for each side surface of a laminate in which a plurality of dielectric ceramic layers and a plurality of internal electrode layers are laminated.

[0003] Patent Document 1 discloses a method for manufacturing an electronic component, including a step of preparing a chip including a plurality of laminated dielectric ceramic layers and a plurality of internal electrode layers, where the plurality of internal electrode layers are exposed on the side surfaces; a step of forming a dielectric laminate sheet by laminating a plurality of coating dielectric sheets on each other; and a step of attaching the dielectric laminate sheet to the side surfaces of the chip.

[0004] Further, Patent Document 2 describes that when manufacturing a multilayer ceramic capacitor by laminating a plurality of ceramic green sheets printed with internal electrodes, applying a leveling ceramic slurry to a region where no internal electrode is printed. And when a mother laminate is cut to obtain a plurality of laminates of ceramic capacitor units, it is said that a step difference between a portion where the internal electrodes overlap and a portion where they do not overlap can be suppressed by the leveling ceramic paste layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, the composition of the ceramic dielectric sheet bonded to the side surface of the laminate is not particularly mentioned in Citation Document 1. Also, the composition of the ceramic paste for step difference elimination used in Citation Document 2 is not particularly mentioned. Therefore, there was room for improving the reliability of the multilayer ceramic capacitor by optimizing the composition of the dielectric laminate sheet and the ceramic paste for step difference elimination in Citation Documents 1 and 2. In addition, in the plurality of laminates obtained by cutting the mother laminate described in Citation Document 2, the cut surface is not sufficiently smooth or foreign matter exists. Also, due to the stress during cutting, the ceramic dielectric sheet and the internal electrode may flow and deform in the cutting direction. Therefore, when bonding the ceramic dielectric sheet to the side surface of such a cut surface, there is concern that distortion or the like may occur in the ceramic dielectric sheet.

[0007] An object of the present invention is to provide a method for manufacturing a multilayer ceramic capacitor capable of forming a dielectric on at least the side surface of the laminate in a smooth and clean state.

Means for Solving the Problems

[0008] The method for manufacturing a multilayer ceramic capacitor of the present invention includes a step of printing an internal electrode pattern on a dielectric layer, a step of forming a dielectric pattern in a region other than the region where the internal electrode pattern is printed, a step of laminating a plurality of the dielectric layers to form a laminate, a step of exposing the internal electrode pattern and the dielectric pattern from the side surface of the laminate, a step of removing at least a part of the exposed dielectric pattern, and a step of forming a dielectric gap layer on the side surface.

Effects of the Invention

[0009] An object of the present invention is to provide a method for manufacturing a multilayer ceramic capacitor capable of forming a dielectric on at least a side surface of a laminate in a smooth and clean state.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, the multilayer ceramic capacitor of the present invention will be described. However, the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. In addition, a combination of two or more of the individual desirable configurations described below is also the present invention.

[0012] [Multilayer Ceramic Capacitor] FIG. 1 is a perspective view schematically showing an example of the multilayer ceramic capacitor of the present invention. FIG. 2 is a perspective view schematically showing an example of the laminate constituting the multilayer ceramic capacitor shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line A-A of the multilayer ceramic capacitor shown in FIG. 1. FIG. 4 is a cross-sectional view taken along line C-C of the multilayer ceramic capacitor shown in FIG. 1.

[0013] In this specification, the stacking direction, width direction, and length direction of the multilayer ceramic capacitor and the laminate are defined as the directions indicated by arrows T, W, and L, respectively, in the multilayer ceramic capacitor 1 shown in FIG. 1 and the laminate 10 shown in FIG. 2. Here, the stacking (T) direction, width (W) direction, and length (L) direction are perpendicular to each other. The stacking (T) direction is the direction in which a plurality of dielectric ceramic layers 20 and a plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 are stacked.

[0014] The multilayer ceramic capacitor 1 shown in FIG. 1 includes a laminate 10 and a first external electrode 51 and a second external electrode 52 provided on both end faces of the laminate 10, respectively.

[0015] As shown in FIG. 2, the laminate 10 has a rectangular parallelepiped shape or a substantially rectangular parallelepiped shape, and has a first main surface 11 and a second main surface 12 facing each other in the stacking (T) direction, a first side surface 13 and a second side surface 14 facing each other in the width (W) direction perpendicular to the stacking (T) direction, and a first end surface 15 and a second end surface 16 facing each other in the length (L) direction perpendicular to the stacking (T) direction and the width (W) direction.

[0016] In this specification, the cross-section of the multilayer ceramic capacitor 1 or the laminate 10 that is orthogonal to the first end face 15 and the second end face 16 and parallel to the lamination (T) direction is referred to as the LT cross-section, which is the cross-section in the length (L) direction and the lamination (T) direction. Further, the cross-section of the multilayer ceramic capacitor 1 or the laminate 10 that is orthogonal to the first side face 13 and the second side face 14 and parallel to the lamination (T) direction is referred to as the WT cross-section, which is the cross-section in the width (W) direction and the lamination (T) direction. Moreover, the cross-section of the multilayer ceramic capacitor 1 or the laminate 10 that is orthogonal to the first side face 13, the second side face 14, the first end face 15, and the second end face 16 and orthogonal to the lamination (T) direction is referred to as the LW cross-section, which is the cross-section in the length (L) direction and the width (W) direction. Therefore, FIG. 3 is the LT cross-section of the multilayer ceramic capacitor 1, and FIG. 4 is the WT cross-section of the multilayer ceramic capacitor 1.

[0017] The laminate 10 preferably has rounded corners and ridgelines. A corner is a portion where three faces of the laminate intersect, and a ridgeline is a portion where two faces of the laminate intersect.

[0018] As shown in FIGS. 2, 3, and 4, the laminate 10 has a laminated structure including a plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction and a plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 formed along the interfaces between the dielectric ceramic layers 20. The dielectric ceramic layers 20 extend along the width (W) direction and the length (L) direction, and each of the first internal electrode layers 21 and the second internal electrode layers 22 extends in a flat plate shape along the dielectric ceramic layers 20.

[0019] The first internal electrode layer 21 is drawn out to the first end face 15 of the laminate 10. On the other hand, the second internal electrode layer 22 is drawn out to the second end face 16 of the laminate 10.

[0020] The first internal electrode layer 21 and the second internal electrode layer 22 face each other in the lamination (T) direction with the dielectric ceramic layer 20 interposed therebetween. Capacitance is generated by the portion where the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween.

[0021] Each of the first internal electrode layer 21 and the second internal electrode layer 22 preferably contains a metal such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, Au, etc. Each of the first internal electrode layer 21 and the second internal electrode layer 22 may contain the same dielectric ceramic material as the dielectric ceramic layer 20 in addition to the above metals.

[0022] The dielectric ceramic layer 20 has a first dielectric ceramic layer 20a and a second dielectric ceramic layer 20b. The first dielectric ceramic layer 20a is a dielectric ceramic layer disposed between the first internal electrode layer 21 and the second internal electrode layer 22. The second dielectric ceramic layer 20b is a dielectric ceramic layer disposed in a region where the internal electrode layers (21, 22) are not disposed, between the first dielectric ceramic layers 20a facing each other through the internal electrode layers (21, 22).

[0023] The first external electrode 51 is provided on the first end face 15 of the laminate 10, and in FIG. 1, has a portion that wraps around to a part of each of the first main face 11, the second main face 12, the first side face 13, and the second side face 14. The first external electrode 51 is connected to the first internal electrode layer 21 at the first end face 15.

[0024] The second external electrode 52 is provided on the second end face 16 of the laminate 10, and in FIG. 1, has a portion that wraps around to a part of each of the first main face 11, the second main face 12, the first side face 13, and the second side face 14. The second external electrode 52 is connected to the second internal electrode layer 22 at the second end face 16.

[0025] Each of the first external electrode 51 and the second external electrode 52 preferably includes a Ni layer containing Ni and a ceramic material. The Ni layer is a base electrode layer. Such a Ni layer can be formed by a so-called co-firing method that is fired simultaneously with the first internal electrode layer 21 and the second internal electrode layer 22. The Ni layer is preferably disposed directly on the laminate 10.

[0026] The first external electrode 51 preferably includes, in order from the side of the first end face 15 of the laminate 10, a Ni layer, a first plating layer, and a second plating layer. Similarly, the second external electrode 52 preferably includes, in order from the side of the second end face 16 of the laminate 10, a Ni layer, a first plating layer, and a second plating layer. The first plating layer is preferably formed by Ni plating, and the second plating layer is preferably formed by Sn plating. Each of the first external electrode 51 and the second external electrode 52 may include a conductive resin layer containing conductive particles and resin between the Ni layer and the first plating layer. Examples of the conductive particles in the conductive resin layer include metal particles such as Cu, Ag, and Ni.

[0027] Note that the Ni layer may be formed by a so-called post-fire method in which a conductive paste is applied to the end face of the fired laminate and baked. In this case, the Ni layer may not contain a ceramic material.

[0028] Alternatively, each of the first external electrode 51 and the second external electrode 52 may include a base electrode layer containing a metal such as Cu. The base electrode layer may be formed by a co-fire method or a post-fire method. Also, the base electrode layer may be a plurality of layers.

[0029] For example, the first external electrode 51 may have a four-layer structure including, in order from the side of the first end face 15 of the laminate 10, a Cu layer as a base electrode layer, a conductive resin layer containing conductive particles and resin, a first plating layer, and a second plating layer. Similarly, the second external electrode 52 may have a four-layer structure including, in order from the side of the second end face 16 of the laminate 10, a Cu layer as a base electrode layer, a conductive resin layer containing conductive particles and resin, a first plating layer, and a second plating layer.

[0030] As shown in FIGS. 3 and 4, the dielectric ceramic layer 20 has a first dielectric ceramic layer 20a and a second dielectric ceramic layer 20b. The first dielectric ceramic layer 20a is disposed between the first internal electrode layer 21 and the second internal electrode layer 22. The second dielectric ceramic layer 20b is disposed in a region where no internal electrode layer is disposed, between the first dielectric ceramic layers 20a that face each other via the internal electrode layer.

[0031] As shown in FIGS. 2, 3, and 4, the laminate 10 includes an inner layer portion 30 in which the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 therebetween, outer layer portions 31 and 32 disposed so as to sandwich the inner layer portion 30 in the stacking (T) direction, and third dielectric ceramic layers 41 and 42 disposed so as to sandwich the inner layer portion 30, the outer layer portion 31, and the outer layer portion 32 in the width (W) direction. The third dielectric ceramic layers 41 and 42 are also referred to as side margin portions. In FIGS. 3 and 4, the inner layer portion 30 is a region sandwiched between the first internal electrode layer 21 closest to the first main surface 11 and the first internal electrode layer 21 closest to the second main surface 12 along the stacking (T) direction. Although not shown, each of the outer layer portions 31 and 32 is preferably composed of a plurality of dielectric ceramic layers stacked in the stacking (T) direction, and more preferably composed of the first dielectric ceramic layer 20a.

[0032] The thickness of each of the outer layer portions 31 and 32 is preferably 15 μm or more and 40 μm or less. Note that each of the outer layer portions 31 and 32 may have a single-layer structure instead of a multilayer structure.

[0033] As shown in FIG. 4, each of the third dielectric ceramic layer 41 and the third dielectric ceramic layer 42 may be composed of a plurality of dielectric ceramic layers stacked in the width (W) direction. Of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer, the innermost layer in the width direction is called the inner layer, and the outermost layer is called the outer layer. An interface exists between the inner layer and the outer layer. In FIG. 4, the third dielectric ceramic layer 41 has a two-layer structure including an inner layer 41a disposed innermost in the laminate 10 and an outer layer 41b disposed outermost in the laminate 10 as the dielectric ceramic layer. Similarly, the third dielectric ceramic layer 42 has a two-layer structure including an inner layer 42a disposed innermost in the laminate 10 and an outer layer 42b disposed outermost in the laminate 10 as the dielectric ceramic layer. Note that the third dielectric ceramic layer is not limited to a two-layer structure and may have a structure of three or more layers. When the third dielectric ceramic layer includes three or more dielectric ceramic layers, the dielectric ceramic layer disposed innermost in the width direction is defined as the inner layer, and the dielectric ceramic layer disposed outermost in the width direction is defined as the outer layer. Also, the number of layers of the third dielectric ceramic layer on the first side surface side of the laminate and the third dielectric ceramic layer on the second side surface side may be different.

[0034] When the third dielectric ceramic layer has a two-layer structure including an inner layer and an outer layer, due to the difference in sinterability between the inner layer and the outer layer, it is possible to confirm that it has a two-layer structure and the interface between the layers by observing with an optical microscope in a dark field. The same applies when the third dielectric ceramic layer has a structure of three or more layers.

[0035] The first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 are composed of a dielectric ceramic material mainly containing, for example, BaTiO3 or the like. The dielectric ceramic layer constituting the inner layer portion 30 may further contain a sintering aid element.

[0036] The dielectric ceramic layers constituting the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may contain ceramic grains. Details of the diameter of the ceramic grains will be described later.

[0037] In the multilayer ceramic capacitor of the present invention, the composition of at least one of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is different from the composition of the other dielectric ceramic layers. Since the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer all have different required characteristics in terms of the purpose of arrangement and the manufacturing method, by making the composition of at least one of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer different from the composition of the other dielectric ceramic layers, an optimal composition according to the location where the dielectric ceramic layer is arranged can be realized, and the reliability can be enhanced.

[0038] In the multilayer ceramic capacitor of the present invention, the composition of the first dielectric ceramic layer may be different from the compositions of the second dielectric ceramic layer and the third dielectric ceramic layer, the composition of the second dielectric ceramic layer may be different from the compositions of the first dielectric ceramic layer and the third dielectric ceramic layer, the composition of the third dielectric ceramic layer may be different from the compositions of the first dielectric ceramic layer and the second dielectric ceramic layer, or the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may be different from each other.

[0039] In the multilayer ceramic capacitor of the present invention, it is preferable that the composition of the second dielectric ceramic layer is different from the composition of the third dielectric ceramic layer, and it is more preferable that the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer are all different.

[0040] In addition, when the third dielectric ceramic layer is composed of a plurality of dielectric ceramic layers, the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer may have the same composition as each other or different compositions. If the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the first dielectric ceramic layer, it can be said that the composition of the third dielectric ceramic layer is different from that of the first dielectric ceramic layer. Also, if the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the second dielectric ceramic layer, it can be said that the composition of the third dielectric ceramic layer is different from that of the second dielectric ceramic layer.

[0041] Among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, it is preferable that the dielectric ceramic layers having different compositions have a common main component and different types of additives. Examples of the main component include BaTiO3, CaTiO3, SrTiO3, etc. The additive preferably contains elements such as Si, Mg, Mn, Sn, Cu, rare earths, Ni, and Al. This is preferable. The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may contain two or more of the above elements.

[0042] Note that "the same composition" means that the types of elements contained in the dielectric ceramics constituting each dielectric ceramic layer are the same, and the content ratios (molar ratios) of other elements based on Ti are all within ±0.5%. Note that differences in the diameter of the ceramic grains and the porosity of each dielectric ceramic layer are not included in the differences in the composition of the dielectric ceramic layer.

[0043] Regarding the composition of each dielectric ceramic layer, it can be determined by performing elemental analysis by wavelength-dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (TEM-EDX) on the cut surface where the dielectric ceramic layer is exposed by cutting the multilayer ceramic capacitor. At this time, the composition of each dielectric ceramic layer is measured at five locations and the average value is obtained. Regarding the second dielectric ceramic layer, the average value measured at five locations from the second dielectric ceramic layer exposed on the first end face of the laminate and at five locations from the second dielectric ceramic layer exposed on the second end face of the laminate shall be used. When the third dielectric ceramic layer has a multilayer structure, the sum of the compositions obtained by measuring the compositions of each layer at five locations each, multiplied by the ratio of the thickness occupied by each layer in the third dielectric ceramic layer, shall be used. In addition, when segregation of elements is observed near the interface with other dielectric ceramic layers or internal electrode layers, the locations where segregation of elements is observed shall not be the measurement targets of WDX.

[0044] As the element added to the first dielectric ceramic layer, Mg is preferable. The content of Mg in the first dielectric ceramic layer is preferably 0.05 mol% or more and 3.0 mol% or less with respect to 100 mol of Ti. It is more preferable that the content of Mg in the first dielectric ceramic layer is less than the content of Mg in the second dielectric ceramic layer and the third dielectric ceramic layer. When the content of Mg in the first dielectric ceramic layer is low, the relative permittivity of the first dielectric ceramic layer increases, so that the capacitance of the multilayer ceramic capacitor can be improved. Note that in some cases, it is preferably as low as possible.

[0045] As the element added to the second dielectric ceramic layer, Sn is preferable. The content of Sn in the second dielectric ceramic layer is preferably 0.05 mol% or more and 3.0 mol% or less with respect to 100 mol of Ti. It is preferable that the content of Sn in the second dielectric ceramic layer is more than the content of Sn in the first dielectric ceramic layer and the third dielectric ceramic layer.

[0046] As the element added to the third dielectric ceramic layer, Si is preferable. The Si content in the third dielectric ceramic layer is preferably 0.05 mol% or more and 5.0 mol% or less with respect to 100 mol of Ti. The Si content in the third dielectric ceramic layer is preferably higher than the Si contents in the first and second dielectric ceramic layers. When the Si content in the third dielectric ceramic layer is high, the sinterability of the dielectric ceramic layer is enhanced, so that it is possible to suppress moisture and the like from entering from the first and second side surfaces of the laminate and deteriorating the internal electrode layer.

[0047] As an element added to the third dielectric ceramic layer, Mg is preferable. The Mg content in the third dielectric ceramic layer is preferably 0.05 mol% or more and 5.0 mol% or less with respect to 100 mol of Ti. The Mg content in the third dielectric ceramic layer is preferably higher than the Mg contents in the first and second dielectric ceramic layers. When the Mg content in the third dielectric ceramic layer is high, it is possible to suppress grain growth of ceramic grains contained in the third dielectric ceramic layer and to make it difficult for a short circuit to occur between the internal electrode layers.

[0048] As an element added to the third dielectric ceramic layer, Mn is preferable. The Mn content in the third dielectric ceramic layer is preferably 0.01 mol% or more and 3.0 mol% or less with respect to 100 mol of Ti. The Mn content in the third dielectric ceramic layer is preferably higher than the Mn contents in the first and second dielectric ceramic layers. When the Mn content in the third dielectric ceramic layer is high, it is possible to suppress grain growth of ceramic grains contained in the third dielectric ceramic layer and to make it difficult for a short circuit to occur between the internal electrode layers.

[0049] In the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, it is preferable that elements other than the main components contained in each dielectric ceramic layer diffuse into other dielectric ceramic layers. Moreover, it is preferable that part of the elements contained as additives in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer diffuse into other adjacent dielectric ceramic layers and the internal electrode layers.

[0050] FIG. 5 is a cross-sectional view taken along line B-B of the multilayer ceramic capacitor shown in FIG. 1. Note that FIG. 5 is an LW cross-section of the multilayer ceramic capacitor 1. As shown in FIG. 5, the second internal electrode layer 22 is exposed on the second end face 16 of the laminate 10, and the second dielectric ceramic layer 20b is exposed on the first end face 15 of the laminate 10. Further, a third dielectric ceramic layer 41 and a third dielectric ceramic layer 42 are disposed on the first side face 13 side and the second side face 14 side of the laminate 10, respectively.

[0051] As shown in FIG. 5, an interface 2220b exists between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. Also, interfaces 2241 and 2242 exist between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42. Further, interfaces 20b41 and 20b42 exist between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42.

[0052] Although not shown in FIG. 5, the first dielectric ceramic layer 20a is disposed on both sides in the thickness direction of the second internal electrode layer 22 and the second dielectric ceramic layer 20b. Therefore, it can be said that the first dielectric ceramic layer 20a has interfaces that are in direct contact with the second dielectric ceramic layer 20b, the third dielectric ceramic layers 41 and 42, and the internal electrode layers 21 and 22.

[0053] Furthermore, with respect to the first internal electrode layer 21 as well, similar to the second internal electrode layer 22 shown in FIG. 5, it has interfaces with the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42.

[0054] In the first dielectric ceramic layer 20a, elements derived from the second dielectric ceramic layer 20b may segregate in the vicinity of the interface with the second dielectric ceramic layer 20b. Also, in the first dielectric ceramic layer 20a, elements derived from the third dielectric ceramic layer 41 or 42 may segregate in the vicinity of the interface with the third dielectric ceramic layer 41 or 42.

[0055] In the second dielectric ceramic layer 20b, elements derived from the first dielectric ceramic layer 20a may segregate in the vicinity of the interface with the first dielectric ceramic layer 20a. Also, in the second dielectric ceramic layer 20b, elements derived from the third dielectric ceramic layer 41 or 42 may segregate in the vicinity of the interfaces 20b41, 20b42 with the third dielectric ceramic layer 41 or 42.

[0056] In the third dielectric ceramic layers 41 and 42, elements derived from the first dielectric ceramic layer 20a may segregate in the vicinity of the interface with the first dielectric ceramic layer 20a. Also, in the third dielectric ceramic layers 41 and 42, elements derived from the second dielectric ceramic layer 20b may segregate in the vicinity of the interfaces 20b41, 20b42 with the second dielectric ceramic layer 20b.

[0057] Of the first internal electrode layer 21 and the second internal electrode layer 22, elements derived from the first dielectric ceramic layer 20a may segregate near the interface with the first dielectric ceramic layer 20a. Also, of the first internal electrode layer 21 and the second internal electrode layer 22, elements derived from the second dielectric ceramic layer 20b may segregate near the interface 2220b with the second dielectric ceramic layer 20b. Further, of the first internal electrode layer 21 and the second internal electrode layer 22, elements derived from the third dielectric ceramic layers 41 and 42 may segregate near the interfaces 2241 and 2242 with the third dielectric ceramic layers 41 and 42. Also, in the vicinity of the portion where the interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b and the interface 2241 or 2242 between the second internal electrode layer 22 and the third dielectric ceramic layer 41 or 42 are in contact (the corner portion of the second internal electrode layer 22 on the first end face 15 side), both elements derived from the second dielectric ceramic layer 20b and elements derived from the third dielectric ceramic layer 41 or 42 may segregate.

[0058] The porosity of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may be the same, or they may be different from each other. The laminated ceramic capacitor is cut to expose each dielectric ceramic layer, and the cut surface is observed with a scanning electron microscope (SEM) at a magnification of 20,000 times. Five regions with a field size of 6.3 μm × 4.4 μm are photographed so that the regions do not overlap with each other, and from each obtained SEM image, the ratio of the area occupied by voids to the entire field of view is calculated as the porosity by image analysis, and the average value in the five fields of view is obtained. However, when the third dielectric ceramic layer is composed of a plurality of layers, after individually obtaining the porosity of each layer, the sum of the product of the value obtained by dividing the thickness of the layer by the thickness of the third dielectric ceramic layer and the porosity of each layer is taken as the porosity of the third dielectric ceramic layer.

[0059] The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer preferably contain ceramic grains. When the dielectric ceramic layer contains ceramic grains, interface resistance occurs at the interfaces between the ceramic grains, increasing the insulation resistance between the internal electrode layers and preventing the occurrence of short circuits.

[0060] It is preferable that rare earths are present at the interfaces of the ceramic grains. The presence of rare earths at the interfaces of the ceramic grains can be confirmed by elemental analysis using TEM-EDX. Examples of rare earths include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, etc. The presence of rare earths at the interfaces of the ceramic grains further increases the interface resistance of the dielectric ceramic layer, thereby further improving the reliability of the multilayer ceramic capacitor. Note that Mg, Mn, Si, etc. may also be present.

[0061] It is preferable that the rare earths are present in an amount of 0.2 mol% or more and 5 mol% or less with respect to 100 mol of Ti. The 100 mol of Ti here is determined based on the premise that the dielectric ceramic material constituting the dielectric ceramic layer is mainly composed of a compound having a perovskite structure (a structure represented by ABO3, B = Ti), and is the amount of rare earths present with respect to 100 mol of Ti. The amount of rare earths present can be confirmed by TEM-EDX.

[0062] In the multilayer ceramic capacitor, the thicknesses of the first internal electrode layer and the second internal electrode layer are each preferably 0.4 μm or less. Also, the thicknesses of the first internal electrode layer and the second internal electrode layer are each preferably 0.38 μm or less. Also, the thicknesses of the first internal electrode layer and the second internal electrode layer are each preferably 0.25 μm or more.

[0063] The thickness of the first dielectric ceramic layer is preferably 0.55 μm or less. Further, the thickness of each of the first dielectric ceramic layers is preferably 0.4 μm or more.

[0064] The thickness of the second dielectric ceramic layer is preferably the same as the thickness of the internal electrode layer.

[0065] The thickness of each of the third dielectric ceramic layers 41 and 42 is preferably 5 μm or more and 40 μm or less, and more preferably 5 μm or more and 20 μm or less. The thicknesses of the third dielectric ceramic layers 41 and 42 are preferably the same as each other. However, while the inner layers 41a and the outer layers 41b satisfy the above range, it is preferable that the outer layer 41b is thicker than the inner layer 41a. Similarly, while the inner layers 42a and the outer layers 42b satisfy the above range, it is preferable that the outer layer 42b is thicker than the inner layer 42a.

[0066] From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor 1, the inner layer 41a is preferably thinner than the outer layer 41b. Similarly, the inner layer 42a is preferably thinner than the outer layer 42b.

[0067] The thickness of each of the inner layers 41a and 42a is preferably 0.1 μm or more and 20 μm or less. The thicknesses of the inner layers 41a and 42a are preferably the same as each other.

[0068] The thickness of each of the outer layers 41b and 42b is preferably 5 μm or more and 20 μm or less. The thicknesses of the outer layers 41b and 42b are preferably the same as each other.

[0069] The thickness of each ceramic layer in the side margin portion means the average value when the thickness of the third dielectric ceramic layer is measured at a plurality of locations along the stacking (T) direction.

[0070] [Method for manufacturing a multilayer ceramic capacitor] The manufacturing method of the multilayer ceramic capacitor of the present invention preferably has a laminated structure composed of a plurality of first dielectric ceramic layers, a plurality of second dielectric ceramic layers, and a plurality of pairs of first internal electrode layers and second internal electrode layers in an unfired state, and the first internal electrode layer and the second internal electrode layer are exposed on the first side surface and the second side surface facing each other in the width direction orthogonal to the lamination direction. A step of preparing a green chip; a step of producing an unfired laminate by forming an unfired third dielectric ceramic layer on the first side surface and the second side surface of the green chip; a step of firing the unfired laminate, In the step of preparing the green chip, an unfired first internal electrode layer or a second internal electrode layer is formed on the surface of the unfired first dielectric ceramic layer, and an unfired second dielectric ceramic layer is formed in a region where the first internal electrode layer and the second internal electrode layer are not provided. The ceramic green sheets obtained by laminating are laminated, and in the step of producing the unfired laminate, an unfired inner layer is formed on the first side surface and the second side surface, and an unfired outer layer is formed on the outermost side, whereby the unfired side margin portion is formed. Among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, the composition of at least one dielectric ceramic layer is different.

[0071] Hereinafter, an example of a method for manufacturing the multilayer ceramic capacitor 1 shown in FIG. 1 will be described.

[0072] First, ceramic green sheets to be the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 are prepared. The ceramic green sheet contains, in addition to the ceramic raw material containing the above-described dielectric ceramic material, a binder, a solvent, and the like. Further, an additive containing a rare earth may be added to the ceramic raw material. By changing the elements contained in the additive, the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer can be changed. It is preferable that the ceramic raw material as the main component is the same. The ceramic green sheet is formed, for example, on a carrier film using a die coater, a gravure coater, a micro gravure coater, or the like.

[0073] Figs. 6, 7, and 8 are plan views schematically showing an example of the ceramic green sheet. Figs. 6, 7, and 8 show a first ceramic green sheet 101 for forming the inner layer portion 30, a second ceramic green sheet 102 for forming the inner layer portion 30, and a third ceramic green sheet 103 for forming the outer layer portion 31 or 32, respectively.

[0074] In Figs. 6, 7, and 8, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are not separated for each multilayer ceramic capacitor 1. Figs. 6, 7, and 8 show cutting lines X and Y when separating for each multilayer ceramic capacitor 1. The cutting line X is parallel to the length (L) direction, and the cutting line Y is parallel to the width (W) direction.

[0075] As shown in Fig. 6, in the first ceramic green sheet 101, an unfired first internal electrode layer 121 corresponding to the first internal electrode layer 21 is formed on an unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer 20a. Also, an unfired second dielectric ceramic layer 120b corresponding to the second dielectric ceramic layer 20b is formed in a region where the unfired first internal electrode layer 121 is not formed. The unfired first dielectric ceramic layer 120a and the unfired second dielectric ceramic layer 120b are also an unfired dielectric ceramic layer 120 corresponding to the dielectric ceramic layer 20.

[0076] As shown in FIG. 7, in the second ceramic green sheet 102, an unfired second internal electrode layer 122 corresponding to the second internal electrode layer 22 is formed on an unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer 20a. Also, an unfired second dielectric ceramic layer 120b corresponding to the second dielectric ceramic layer 20b is formed in a region where the unfired second internal electrode layer 122 is not formed. The unfired first dielectric ceramic layer 120a and the unfired second dielectric ceramic layer 120b are also an unfired dielectric ceramic layer 120 corresponding to the dielectric ceramic layer 20.

[0077] The method for producing the first ceramic green sheet 101 shown in FIG. 6 and the second ceramic green sheet shown in FIG. 7 is not particularly limited, but examples include a method of applying, to the surface of the unfired first dielectric ceramic layer 120a, a dielectric paste which is a mixture of a dielectric ceramic that becomes the second dielectric ceramic layer 20b upon firing and a solvent, and a conductive paste that becomes the internal electrode layer 21 or 22 upon firing, to respective predetermined regions. The order of applying the dielectric paste and the conductive paste is not particularly limited, and the conductive paste may be applied after the dielectric paste is applied first, or the dielectric paste may be applied after the conductive paste is applied first. Also, the dielectric paste and the conductive paste may be applied such that a part of the surface of the previously applied paste is covered by a part of the subsequently applied paste.

[0078] As shown in FIG. 8, the third ceramic green sheet 103 corresponding to the outer layer portion 31 or 32 is composed of an unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer, and no unfired internal electrode layer 121 or 122 or unfired second dielectric ceramic layer 120b is formed.

[0079] The first internal electrode layer 121 and the second internal electrode layer 122 can be formed using any conductive paste. For the formation of the first internal electrode layer 121 and the second internal electrode layer 122 with a conductive paste, methods such as a screen printing method, a gravure printing method, etc. can be used, for example.

[0080] The first internal electrode layer 121 and the second internal electrode layer 122 are arranged over two adjacent regions partitioned by the cutting line Y in the length (L) direction and extend in a strip shape in the width (W) direction. Between the first internal electrode layer 121 and the second internal electrode layer 122, the regions partitioned by the cutting line Y are shifted by one row in the length (L) direction. That is, the cutting line Y passing through the center of the first internal electrode layer 121 passes through the region between the second internal electrode layers 122 (i.e., the center of the second dielectric ceramic layer 120b), and the cutting line Y passing through the center of the second internal electrode layer 122 passes through the region between the first internal electrode layers 121 (i.e., the center of the second dielectric ceramic layer 120b).

[0081] Thereafter, a mother block is fabricated by laminating the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103.

[0082] FIG. 9 is an exploded perspective view schematically showing an example of the mother block. In FIG. 9, for convenience of explanation, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are shown separately. In the actual mother block 104, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are pressure-bonded and integrated by means such as hydrostatic pressing.

[0083] In the mother block 104 shown in FIG. 9, a first ceramic green sheet 101 and a second ceramic green sheet 102 corresponding to the inner layer portion 30 are alternately laminated in the lamination (T) direction. Further, a third ceramic green sheet 103 corresponding to the outer layer portions 31 and 32 is laminated on the upper and lower surfaces in the lamination (T) direction of the alternately laminated first ceramic green sheet 101 and second ceramic green sheet 102. In FIG. 9, three third ceramic green sheets 103 are laminated respectively, but the number of the third ceramic green sheets 103 can be appropriately changed.

[0084] By cutting the obtained mother block 104 along the cutting lines X and Y (see FIGS. 6, 7, and 8), a plurality of green chips are produced. For this cutting, for example, methods such as dicing, punching, and laser cutting are applied.

[0085] FIG. 10 is a perspective view schematically showing an example of a green chip. The green chip 110 shown in FIG. 10 has a laminated structure including a plurality of unfired first dielectric ceramic layers 120a and second dielectric ceramic layers 120b and a plurality of pairs of first internal electrode layers 121 and second internal electrode layers 122. The first side surface 113 and the second side surface 114 of the green chip 110 are surfaces appeared by cutting along the cutting line X, and the first end surface 115 and the second end surface 116 are surfaces appeared by cutting along the cutting line Y. The first internal electrode layer 121 and the second internal electrode layer 122 are exposed on the first side surface 113 and the second side surface 114. Further, only the first internal electrode layer 121 and the second dielectric ceramic layer 120b are exposed on the first end surface 115, and only the second internal electrode layer 122 and the second dielectric ceramic layer 120b are exposed on the second end surface 116. The first dielectric ceramic layer 120a is exposed on the first side surface 113, the second side surface 114, the first end surface 115, and the second end surface 116, but the exposed locations of the second dielectric ceramic layer are different in the arranged region. That is, the second dielectric ceramic layer 120b disposed on the first end face 115 side is not exposed on the second end face 116, and the second dielectric ceramic layer 120b disposed on the second end face 116 side is not exposed on the first end face 115.

[0086] An unfired laminate is produced by forming an unfired third dielectric ceramic layer on the first side surface 113 and the second side surface 114 of the obtained green chip 110. The unfired third dielectric ceramic layer is formed, for example, by attaching a ceramic green sheet made of a dielectric ceramic to the first side surface and the second side surface of the green chip.

[0087] For example, when the third dielectric ceramic layer is composed of two layers, an inner layer and an outer layer, first, to produce a ceramic green sheet for the inner layer, in addition to a ceramic raw material containing a dielectric ceramic material mainly composed of BaTiO3 or the like, a ceramic slurry containing a binder, a solvent, and the like is produced. Si, which is a sintering aid, may be added to the ceramic slurry for the inner layer. The inner layer has a role of adhering to the green chip 110. Also, a liquid-phase type metal may be added to the ceramic slurry for the inner layer, and more rare earth elements, Mg, and Mn may be added to the ceramic slurry for the inner layer than to the ceramic green sheet for forming the inner layer portion. By doing so, the grain growth of the ceramic grains contained in the dielectric ceramic layer sandwiched between the widthwise end portions of the internal electrode layer can be suppressed.

[0088] Next, in order to produce a ceramic green sheet for the outer layer, a ceramic slurry containing a dielectric ceramic material mainly composed of BaTiO3 or the like, as well as a binder, a solvent, and the like, is produced. Further, Si, which is a sintering aid, may be added to the ceramic slurry for the outer layer. Also, it is preferable that the Si contained in the ceramic green sheet for the inner layer is more than the Si contained in the ceramic green sheet for the outer layer. The amount of the content is determined by imaging the cross-section with WDX and comparing the areas of the regions where Si is detected.

[0089] The ceramic slurry for the outer layer is applied to the surface of the resin film and dried, whereby a ceramic green sheet for the outer layer is formed. The ceramic slurry for the inner layer is applied to the surface of the ceramic green sheet for the outer layer on the resin film and dried, whereby a ceramic green sheet for the inner layer is formed. Thus, a ceramic green sheet having a two-layer structure is obtained.

[0090] Note that the ceramic green sheet having a two-layer structure can also be obtained, for example, by previously forming each of the ceramic green sheet for the outer layer and the ceramic green sheet for the inner layer and then laminating them together. Also, the ceramic green sheet is not limited to two layers and may be a plurality of layers of three or more layers.

[0091] Thereafter, the ceramic green sheet is peeled off from the resin film.

[0092] Subsequently, the ceramic green sheet for the inner layer of the ceramic green sheet and the first side surface 113 of the green chip 110 are opposed to each other, pressed, and punched to form an unfired side margin portion 41. Further, also with respect to the second side surface 114 of the green chip 110, the ceramic green sheet for the inner layer of the ceramic green sheet is opposed to each other, pressed, and punched to form an unfired side margin portion 42. At this time, it is preferable to previously apply an organic solvent serving as an adhesive to the side surface of the green chip. Thus, an unfired laminate is obtained.

[0093] It is preferable to perform barrel polishing or the like on the unfired laminate obtained by the above method. By polishing the unfired laminate, the corners and ridge lines of the fired laminate 10 are rounded.

[0094] Thereafter, in the unfired laminate, a conductive paste for an external electrode containing Ni and a ceramic material is applied onto each of the first end surface 115 and the second end surface 116 of the green chip 110.

[0095] The conductive paste for an external electrode preferably contains the same dielectric ceramic material as the first dielectric ceramic layer, the second dielectric ceramic layer, or the outer layer as the ceramic material. The content of the ceramic material in the conductive paste for an external electrode is preferably 15% by weight or more. Also, the content of the ceramic material in the conductive paste for an external electrode is preferably 25% by weight or less.

[0096] Next, for the unfired laminate coated with the conductive paste for external electrodes, for example, after degreasing treatment under predetermined conditions in a nitrogen atmosphere, it is fired at a predetermined temperature in a nitrogen-hydrogen-steam mixed atmosphere. As a result, the unfired laminate and the conductive paste for external electrodes are fired simultaneously, and by the so-called co-firing method, the laminate 10, the Ni layer connected to the first internal electrode layer 21, and the Ni layer connected to the second internal electrode layer 22 are formed simultaneously. Then, on the surface of each Ni layer, a first plating layer by Ni plating and a second plating layer by Sn plating are sequentially laminated. Thereby, the first external electrode 51 and the second external electrode 52 are formed.

[0097] Note that the laminate 10, the first external electrode 51, and the second external electrode 52 may be formed at different timings by the so-called post-firing method. Specifically, first, for the unfired laminate, for example, after degreasing treatment under predetermined conditions in a nitrogen atmosphere, it is fired at a predetermined temperature in a nitrogen-hydrogen-steam mixed atmosphere to form the laminate 10. Then, a conductive paste containing Cu powder is applied and baked on each of the first end face 15 and the second end face 16 of the laminate 10. Thereby, a base electrode layer connected to the first internal electrode layer 21 and a base electrode layer connected to the second internal electrode layer 22 are formed. Then, on the surface of each base electrode layer, a conductive resin layer containing conductive particles (for example, metal particles such as Cu, Ag, Ni, etc.) and resin, a first plating layer by Ni plating, and a second plating layer by Sn plating are sequentially laminated. Thereby, the first external electrode 51 and the second external electrode 52 are formed.

[0098] Thus, the multilayer ceramic capacitor 1 is manufactured.

[0099] In the above-described embodiment, after cutting the mother block 104 along the cutting lines X and Y to obtain a plurality of green chips, unfired third dielectric ceramic layers were formed on both side surfaces of the green chips. However, it is also possible to make the following changes.

[0100] That is, by cutting the mother block only along the cutting line X, a plurality of rod-shaped green block bodies are obtained in which the first internal electrode layer and the second internal electrode layer are exposed on the side surfaces appearing by the cutting along the cutting line X. After forming the unfired third dielectric ceramic layer on both side surfaces of the green block body, it may be cut along the cutting line Y to obtain a plurality of unfired laminate bodies, and then the unfired laminate bodies may be fired. After firing, a multilayer ceramic capacitor can be manufactured by performing the same steps as in the above-described embodiment.

[0101] The present invention further includes the following configurations [1] to [7].

[0102] [1] Alloy part between dielectric ceramic layer, internal electrode layer and external electrode In the multilayer ceramic capacitor 1 of the present invention, as shown in FIG. 11, a second alloy part 320 is formed between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and between the second dielectric ceramic layer 20b and the second internal electrode layer 22, respectively. Further, in the multilayer ceramic capacitor 1 of the present invention, a first alloy part 310 is formed between the first dielectric ceramic layer 20a and the first internal electrode layer 21 and between the first dielectric ceramic layer 20a and the second internal electrode layer 22, respectively.

[0103] As shown in FIG. 12, metal element 321a is segregated at the interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. The second alloy portion 320 is formed by a segregation layer 321 which is a layered segregation by the metal element 321a. Similarly, metal element 321a is segregated at the interface 2220b between the first internal electrode layer 21 and the second dielectric ceramic layer 20b, a segregation layer 321 is formed, and the second alloy portion 320 by the segregation layer 321 is formed. Second alloy portions 320 are respectively formed on the surfaces of the first internal electrode layer 21 and the second internal electrode layer 22 on the side of the second dielectric ceramic layer 20b. The second alloy portion 320 will be formed between the first internal electrode layer 21 and the second dielectric ceramic layer 20b and between the second internal electrode layer 22 and the second dielectric ceramic layer 20b.

[0104] Also, as shown in FIG. 12, metal element 311a is segregated at the interface 2220a between the second internal electrode layer 22 and the first dielectric ceramic layer 20a. The first alloy portion 310 is formed by a segregation layer 311 which is a layered segregation by the metal element 311a. Similarly, metal element 311a is segregated at the interface 2220a between the first internal electrode layer 21 and the first dielectric ceramic layer 20a, a segregation layer 311 is formed, and the first alloy portion 310 by the segregation layer 311 is formed. First alloy portions 310 will be respectively formed on the surfaces of the first internal electrode layer 21 and the second internal electrode layer 22 on the side of the first dielectric ceramic layer 20a. The first alloy portion 310 will be formed between the first internal electrode layer 21 and the first dielectric ceramic layer 20a and between the second internal electrode layer 22 and the first dielectric ceramic layer 20a.

[0105] There are multiple types of segregated metal elements 321a that form the second alloy portion 320. The multiple types of metal elements 321a that form the segregation layer 321 include the metal element most contained among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and the elements derived from the second dielectric ceramic layer 20b. The same applies to the segregated metal element 311a that forms the first alloy portion 310. That is, the metal element 311a includes the metal element most contained among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and the elements derived from the first dielectric ceramic layer 20a.

[0106] Examples of the metal element most contained among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22 include one of Ni, Cu, Ag, Pd, Au, and Pt. On the other hand, examples of the elements derived from the second dielectric ceramic layer 20b and the first dielectric ceramic layer 20a include metal elements as additives. Specifically, any one or more metal elements from the metal group of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, Y, and Ge are included, and among these, Sn, Ga, and Ge are particularly preferred. Hereinafter, this metal group may be referred to as metal group M.

[0107] The segregation of the metal element 321a occurs when the metal element contained in the second dielectric ceramic layer 20b moves to the first internal electrode layer 21 and the second internal electrode layer 22 during the firing of the second dielectric ceramic layer 20b. The segregation of the metal element 311a occurs when the metal element contained in the first dielectric ceramic layer 20a moves to the first internal electrode layer 21 and the second internal electrode layer 22 during the firing of the first dielectric ceramic layer 20a.

[0108] When the first dielectric ceramic layer 20a has BaTiO3 as the main component, the second alloy portion 320 has a higher molar ratio of any one or more of the metal elements contained in the second dielectric ceramic layer 20b, that is, the above metal group M, to Ti100 mol in terms of content ratio than the first alloy portion 310.

[0109] FIG. 13 shows a plane including the central portion in the width (W) direction, the length (L) direction, and the stacking (T) direction of the laminate 10. In the multilayer ceramic capacitor 1 of the present invention, on the plane shown in FIG. 13, the first internal electrode layer 21 includes a plurality of first discrete internal electrodes 210 that are discontinuously distributed in the length (L) direction at the end in the length (L) direction that is not connected to the second external electrode 52. Further, the second internal electrode layer 22 includes a plurality of second discrete internal electrodes 220 that are discontinuously distributed in the length (L) direction at the end in the length (L) direction that is not connected to the first external electrode 51. Each of the first discrete internal electrodes 210 and the second discrete internal electrodes 220 is formed inside the second dielectric ceramic layer 20b. The plurality of first discrete internal electrodes 210 may be connected to the first internal electrode layer 21 while extending in the width (W) direction. Also, the plurality of second discrete internal electrodes 220 may be connected to the second internal electrode layer 22 while extending in the width (W) direction.

[0110] A fourth alloy portion 340 is formed around each of the first discrete internal electrodes 210 and the second discrete internal electrodes 220. The fourth alloy portion 340 is formed by a segregation layer 341 that is a layered segregation by a metal element 341a. The metal element 341a includes the most abundant metal element among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and one or more metal elements among the metal group M derived from the second dielectric ceramic layer 20b.

[0111] The segregation of the metal element 341a occurs when the metal elements contained in the second dielectric ceramic layer 20b move to the first discrete internal electrodes 210 and the second discrete internal electrodes 220 during the firing of the second dielectric ceramic layer 20b. Note that the segregation of the metal element 341a occurs around one or more of the first discrete internal electrodes 210 and the plurality of second discrete internal electrodes 220. Alternatively, it may occur around the entire periphery of the first discrete internal electrodes 210 and the entire periphery of the second discrete internal electrodes 220.

[0112] As shown in FIG. 14, in the multilayer ceramic capacitor 1 of the present invention, a third alloy portion 330 is formed between each of the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21, and between each of the third dielectric ceramic layers 41 and 42 and the second internal electrode layer 22.

[0113] As shown in FIG. 14, a metal element 331a is segregated at the interface 2220c between the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21 in the first internal electrode layer 21. Also, a metal element 331a is segregated at the interface 2220c between the third dielectric ceramic layers 41 and 42 and the second internal electrode layer 22 in the second internal electrode layer 22. The third alloy portion 330 is formed by a layered segregation by the metal element 331a, that is, the segregation layer 331. The third alloy portion 330 will be formed on the surfaces of the first internal electrode layer 21 and the second internal electrode layer 22 on the sides of the third dielectric ceramic layers 41 and 42, respectively. The third alloy portion 330 will be formed between each of the first internal electrode layer 21 and the third dielectric ceramic layers 41 and 42, and between each of the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42.

[0114] The metal element 331a includes the most abundant metal element among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and any one or more metal elements among the above metal group M derived from the third dielectric ceramic layers 41 and 42. Examples of the elements derived from the third dielectric ceramic layers 41 and 42 include metal elements as additives. Specifically, any one or more metal elements among the above metal group M can be mentioned.

[0115] The segregation of the metal element 331a occurs when the metal elements contained in the third dielectric ceramic layers 41 and 42 move to the first internal electrode layer 21 and the second internal electrode layer 22 during the firing of the third dielectric ceramic layers 41 and 42.

[0116] In the multilayer ceramic capacitor 1 of the present invention, when the first external electrode 51 and the second external electrode 52 each include a Ni layer as a base electrode layer and are formed by the cofiring method, as shown in FIG. 15, a fifth alloy portion 350 is formed in the Ni layer.

[0117] FIG. 15 shows a state in which a fifth alloy portion 350 is formed at an interface 51b with the second dielectric ceramic layer 20b in the first external electrode 51. The fifth alloy portion 350 is formed by a segregation layer 351 that is a layered segregation by a metal element 351a. Similarly, a fifth alloy portion 350 due to segregation of the metal element 351a is also formed at an interface 51b with the second dielectric ceramic layer 20b in the second external electrode 52. The segregation of the metal element 351a occurs when the metal element contained in the second dielectric ceramic layer 20b moves to the first external electrode 51 and the second external electrode 52 during firing of the second dielectric ceramic layer 20b.

[0118] In the laminate 10 of the multilayer ceramic capacitor 1 of the present invention, the adjacent ends of the first internal electrode layer 21 and the second internal electrode layer 22 and the second dielectric ceramic layer 20b may be in a state of overlapping each other. For example, as shown in FIG. 16, the end of the second dielectric ceramic layer 20b may overlap on the end of the second internal electrode layer 22. Also, as shown in FIG. 17, the end of the second dielectric ceramic layer 20b may overlap on the end of the first internal electrode layer 21. In such a mode where the ends overlap, the first internal electrode layer 21 and the second internal electrode layer 22 may each overlap on the second dielectric ceramic layer 20b.

[0119] In the multilayer ceramic capacitor 1 of the present invention, between the second dielectric ceramic layer 20b and the first internal electrode layer 21, and between the second dielectric ceramic layer 20b and the second internal electrode layer 22, a second alloy portion 320 is formed which contains one metal element most contained among the metal elements constituting the internal electrode layer and any one or more metal elements from the metal group M of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, Y.

[0120] At each end of the first internal electrode layer 21 and the second internal electrode layer 22 in contact with the second dielectric ceramic layer 20b, the electric field tends to concentrate, and thus there was a risk of reducing the reliability as a multilayer ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, by forming the second alloy portion 320 between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and the second internal electrode layer 22, the electric field concentration is suppressed and the reliability can be improved.

[0121] In the multilayer ceramic capacitor 1 of the present invention, when the first dielectric ceramic layer 20a contains Ba and Ti, between the first dielectric ceramic layer 20a and the first internal electrode layer 21, and between the first dielectric ceramic layer 20a and the second internal electrode layer 22, a first alloy portion 310 is formed which contains the metal element most contained among the metal elements constituting the internal electrode layer and any one or more metal elements from the metal group M. The second alloy portion 320 has a higher molar ratio with respect to 100 moles of Ti in the content rate of the metal group M than the first alloy portion 310.

[0122] As a result, in the vicinity of the interfaces between the first internal electrode layer 21 and the second internal electrode layer 22 and the second dielectric ceramic layer 20b, the electric field concentration is suppressed by the second alloy portion 320, and the reliability can be improved. Further, by making the molar ratio of Ti100 mol in the content rate of the metal group M higher for the second alloy portion 320 formed at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 that contact the second dielectric ceramic layer 20b where electric field concentration is likely to occur than for the first alloy portion 310 formed on the first dielectric ceramic layer 20a side, the electric field concentration on the second dielectric ceramic layer 20b side can be effectively suppressed, and the reliability can be further improved.

[0123] By controlling the amount of metal of the metal group M added to each of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b, it becomes possible to control the thicknesses of the first alloy portion 310 and the second alloy portion 320 and the concentration of the metal group M contained therein. For example, when the concentration of the metal group M added to the second dielectric ceramic layer 20b is higher than that of the first dielectric ceramic layer 20a, as shown in FIG. 12, the thickness of the second alloy portion 320 increases as it approaches the second dielectric ceramic layer 20b, or the concentration of the metal group M becomes higher, and in some cases, both of these changes occur.

[0124] In the multilayer ceramic capacitor 1 of the present invention, on the surface of the laminate 10 including the central portion in the width (W) direction, the length (L) direction, and the lamination (T) direction, the first internal electrode layer 21 includes first discrete internal electrodes 210 that are discretely distributed discontinuously in the length (L) direction at the ends in the length (L) direction that are not connected to the second external electrode 52, and the second internal electrode layer 22 includes second discrete internal electrodes 220 that are discretely distributed discontinuously in the length (L) direction at the ends in the length (L) direction that are not connected to the first external electrode 51. A fourth alloy portion 340 including the metal element contained the most among the metal elements constituting the internal electrode layer and one or more metal elements among the metal group M is formed around each of the first discrete internal electrodes 210 and the second discrete internal electrodes 220.

[0125] When the first point internal electrode 210 and the second point internal electrode 220 extend in the width (W) direction and are connected to the first internal electrode layer 21 and the second internal electrode layer 22 respectively, if an electric field concentrates at the connection part, dielectric breakdown may occur and the reliability may decrease. However, in the multilayer ceramic capacitor 1 of the present invention, the fourth alloy part 340 formed around each of the first point internal electrode 210 and the second point internal electrode 220 suppresses dielectric breakdown due to electric field concentration and can improve the reliability.

[0126] In the multilayer ceramic capacitor 1 of the present invention, a third alloy part 330 containing the most abundant metal element among the metal elements constituting the internal electrode layer and at least one metal element among the above metal group M is formed between each of the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21, and between the third dielectric ceramic layers 41 and 42 and the second internal electrode layer 22.

[0127] Thereby, in the vicinity of the interfaces between the first internal electrode layer 21 and the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42, electric field concentration is suppressed by the third alloy part 330, and the reliability can be improved.

[0128] In the multilayer ceramic capacitor 1 of the present invention, the first external electrode 51 and the second external electrode 52 contain Ni, and a fifth alloy part 350 in which at least one metal element among the above metal group M segregates in Ni is formed between the second dielectric ceramic layer 20b and the first external electrode 51 and the second external electrode 52.

[0129] Thereby, even when the intervals between the first internal electrode layer 21 and the second external electrode 52 and between the second internal electrode layer 22 and the first external electrode 51, that is, the distance in the length (L) direction of the second dielectric ceramic layer 20b, are narrow, for example, less than 15 μm, the presence of the fifth alloy part 350 makes it difficult for dielectric breakdown due to electric field concentration to occur between the internal electrode layer and the external electrode, and thus the reliability is improved.

[0130] [Test Example 1] Next, Test Example 1 for verifying the effects of the first alloy portion 310, the second alloy portion 320, and the third alloy portion 330 in the multilayer ceramic capacitor 1 of the present invention will be described.

[0131] ·Regarding TEM analysis In the manufacturing method of the multilayer ceramic capacitor of the present invention described above, without co-firing the first external electrode 51 and the second external electrode 52, for the laminate 10 obtained by firing the green chip 110, polishing is performed from the first side surface 13 side and the second side surface 14 side to obtain a polished body leaving the central portion in the width (W) direction as shown in FIG. 18 as a test body. The types and amounts (metal concentrations) of metal elements contained in the first alloy portion 310 were analyzed as follows. As shown in FIG. 18, at the central portion in the length (L) direction, a virtual line OL1 orthogonal to the length (L) direction was assumed. Then, along the virtual line OL1, the region where the first dielectric ceramic layer 20a related to the acquisition of the capacitance of the polished body, the first internal electrode layer 21, and the second internal electrode layer 22 are laminated was divided into three equal parts in the lamination direction, and divided into three regions: an upper region E1, a central region E2, and a lower region E3. The upper region E1, the central region E2, and the lower region E3 were cut out from the polished body, and each of the upper region E1, the central region E2, and the lower region E3 was thinned by Ar ion milling or the like to obtain three thin film samples from each region.

[0132] For the three thin film samples of the upper region E1, the central region E2, and the lower region E3 of the test body obtained as described above, TEM observation and elemental mapping by EDX attached to the TEM were performed. As a result, since no significant difference was found between the upper region E1 and the lower region E3 and the central region E2, the results obtained from the central region E2 were regarded as the fine structures of the dielectric ceramic layer and the internal electrode layer. As a result, the types and amounts (metal concentrations) of metal elements contained in the first alloy portion 310 were found. Further, the types and amounts (metal concentrations) of metal elements contained in the second alloy portion 320 can be analyzed by obtaining a thin film sample in the same manner as described above in the region at one end in the length (L) direction where the second alloy portion 320 is present. That is, in the polishing body shown in FIG. 18, at one end in the length (L) direction, a virtual line OL2 orthogonal to the length (L) direction is assumed, and thin film samples of three regions, an upper region E4, a central region E5, and a lower region E6, which are equally divided into three in the stacking direction along the virtual line OL2, are obtained. Then, for the three thin film samples of the upper region E4, the central region E5, and the lower region E6, TEM observation and elemental mapping by EDX attached to the TEM are performed to examine the types and amounts (metal concentrations) of metal elements contained in the second alloy portion 320.

[0133] Regarding the second alloy portion and the first alloy portion, the concentration of Sn was examined by analysis using an EDX mapping image based on a TEM observation image. The measurement points of the TEM were measured at intervals of about 5 nm to 10 nm. In the interface between the internal electrode layer and the dielectric ceramic layer, a region where an observed value three times or more greater than other measurement locations was obtained was defined as the alloy portion, and the average value thereof was defined as the metal concentration of the alloy portion.

[0134] Eighteen laminated ceramic capacitors of Test Examples 1-1 to 1-5 shown in Table 1 were prepared respectively. In Test Example 1-2, in the laminated ceramic capacitor of the present invention, the first internal electrode layer 21 and the second internal electrode layer 22 are made of Ni, and the same amount of Sn as an additive is added to the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b. In Test Examples 1-3 to 1-5, the amount of Sn added to the second dielectric ceramic layer 20b is gradually increased compared to Test Example 1-2. Further, Test Example 1-1 was a laminated ceramic capacitor under the same conditions as Test Examples 1-2 to 1-5 except that Sn was not added to the second dielectric ceramic layer 20b.

[0135] Regarding the multilayer ceramic capacitors of Test Examples 1-1 to 1-5, the resistance value (kΩ) was measured under an environment of room temperature to 150°C with a voltage of 6.3 V applied, the MTTF (mean time to failure) was examined, and a determination was made. The MTTF was defined as the time point when the resistance value became 10 kΩ or less. When the MTTF was 15.3 hours (hr) or less, the determination was ×; when it exceeded 15.3 hours (hr) up to 30 hours, the determination was 〇 (good); when it exceeded 30 hours, the determination was ◎ (excellent). The results are also shown in Table 1. Note that when the coverage of the internal electrode layer was less than 80%, it was impossible to measure the capacitance, so it was regarded as unmeasurable.

[0136]

Table 1

[0137] According to Table 1, by forming the second alloy part, the MTTF exceeded the specified time of 15.3 hours in all cases and was good, and it was found that the higher the Sn concentration, the better. On the other hand, in Test Example 1-1 where the second alloy part formed by Sn was not formed, the MTTF could not exceed the specified time. Thus, it was confirmed that the second alloy part enhances the reliability of the multilayer ceramic capacitor.

[0138] Next, in addition to Test Example 1-1, 18 multilayer ceramic capacitors each of Test Examples 1-6 to 1-9 shown in Table 2 were prepared. In Test Example 1-6, in the above Test Example 1-2, Sn as an additive was added to the third dielectric ceramic layer in the same amount as in the first dielectric ceramic layer and the second dielectric ceramic layer. In Test Examples 1-7 to 1-9, the amount of Sn added to the third dielectric ceramic layer was gradually increased compared to Test Example 1-6. In Test Example 1-1, no Sn was added to the third dielectric ceramic layer.

[0139] Regarding Test Examples 1-1 and 1-6 to 1-9, the MTTF determination was performed in the same manner as in Test Examples 1-1 to 1-5 above. The results are shown in Table 2.

[0140]

Table 2

[0141] According to Table 2, when the third alloy part is formed together with the second alloy part, the MTTF is better than the specified time of 15.3 hours in all cases, and it can be seen that the higher the Sn concentration, the better. On the other hand, in Test Example 1-1 where neither the second alloy part nor the third alloy part is formed by Sn, the MTTF could not exceed the specified time. Thus, it was confirmed that the second alloy part and the third alloy part enhance the reliability of the multilayer ceramic capacitor.

[0142] 〔2〕Average particle diameter of dielectric particles included in the vicinity region of the intersection FIG. 19 shows a surface of the multilayer ceramic capacitor 1 of the present invention including the length (L) direction and the width (W) direction, and shows a surface including the second dielectric ceramic layer 20b and the second internal electrode layer 22. As shown in FIG. 19, both sides in the width (W) direction of the end portion on the first end face 15 side in the multilayer ceramic capacitor 1 have an intersection 400 of an interface surrounded by the second dielectric ceramic layer 20b, the second internal electrode layer 22, and the third dielectric ceramic layers 41 and 42. This intersection 400 is an intersection of the interface 2220b between the second dielectric ceramic layer 20b and the second internal electrode layer 22 and the inner surfaces 401 in the width (W) direction in the third dielectric ceramic layers 41 and 42. Similarly, both sides in the width (W) direction of the end portion on the second end face 16 side also have an intersection 400 of an interface surrounded by the second dielectric ceramic layer 20b, the first internal electrode layer 21, and the third dielectric ceramic layers 41 and 42.

[0143] The region inside the circle 400r with a radius of 5 μm centered at the intersection point 400 is defined as the second intersection vicinity region 420. The region inside the circle 400r with a radius of 5 μm centered at the intersection point 400 is defined as the third intersection vicinity region 430. The region inside the circle 400r includes the line of the circle 400r. In the following description, the second intersection vicinity region 420 on the side of the second dielectric ceramic layer 20b and the third intersection vicinity region 430 on the sides of the third dielectric ceramic layers 41 and 42 may be collectively referred to as the intersection vicinity region 440. A part of the second dielectric ceramic layer 20b is included in the region inside the second intersection vicinity region 420. A part of the third dielectric ceramic layers 41 and 42 is included in the region inside the third intersection vicinity region 430.

[0144] In the multilayer ceramic capacitor 1 of the present invention, (A) The average particle diameter of the dielectric particles included in each intersection vicinity region 440 is smaller than the average particle diameters of the dielectric particles included in the first dielectric ceramic layer 20a, the dielectric particles included in the second dielectric ceramic layer 20b, and the dielectric particles included in the third dielectric ceramic layers 41 and 42.

[0145] (B) Further, as the ratio of the smallness, it is preferably 5% or more smaller.

[0146] Note that the average particle diameter of the dielectric particles included in the second dielectric ceramic layer 20b in this case refers to the average particle diameter of the dielectric particles included in the second dielectric ceramic layer 20b in the portion other than the second intersection vicinity region 420, and the average particle diameter of the dielectric particles included in the third dielectric ceramic layers 41 and 42 refers to the average particle diameter of the dielectric particles included in the third dielectric ceramic layers 41 and 42 in the portion other than the third intersection vicinity region 430.

[0147] The multilayer ceramic capacitor 1 of the present invention having the above configuration (A) or (B) preferably further has any one of the following configurations (C) to (I).

[0148] (C) The difference between the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%. The average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a is larger than either the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b or the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. The average particle diameter of the dielectric particles contained in the vicinity of the intersection region 440 is smaller than either the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b or the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0149] (D) The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b is within 5%. The average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is smaller than either the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a or the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b. The average particle diameter of the dielectric particles contained in the vicinity of the intersection region 440 is smaller than the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0150] (E) The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%. The average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than either the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a or the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. The average particle diameter of the dielectric particles contained in the vicinity of the intersection region 440 is smaller than the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b.

[0151] (F) The difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b, the difference between the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, and the difference between the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 are all within 5%. The average particle diameter of the dielectric particles contained in the vicinity region 440 of the intersection is smaller than any of the average particle diameters of the dielectric particles contained in the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42.

[0152] (G) The average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b. The average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is smaller than the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a. The average particle diameter of the dielectric particles contained in the vicinity region 440 of the intersection is smaller than the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

[0153] (H) The average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle diameter of the dielectric particles contained in the third dielectric ceramic layers 41 and 42. The average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a. The average particle diameter of the dielectric particles contained in the vicinity region 440 of the intersection is smaller than the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer 20b.

[0154] (I) The average particle diameter of the dielectric particles included in the vicinity region 440 of the intersection is smaller than the average particle diameter of the dielectric particles included in the first dielectric ceramic layer 20a, and the average particle diameter of the dielectric particles included in the third dielectric ceramic layers 41 and 42 or the average particle diameter of the dielectric particles included in the second dielectric ceramic layer 20b is smaller than the average particle diameter of the dielectric particles included in the vicinity region 440 of the intersection.

[0155] The average particle diameter of the dielectric particles included in the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 can be controlled by adjusting the amount of sintering aids typified by Si, Mn, etc. included in the dielectric ceramic slurry forming each dielectric ceramic layer, and further adjusting the firing temperature.

[0156] As described above, in the multilayer ceramic capacitor 1 of the present invention, the average particle diameter of the dielectric particles included in the vicinity region 440 of the intersection is smaller than the average particle diameter of the dielectric particles included in the first dielectric ceramic layer 20a around the vicinity region 440 of the intersection, the average particle diameter of the dielectric particles included in the second dielectric ceramic layer 20b, and the average particle diameter of the dielectric particles included in the third dielectric ceramic layers 41 and 42.

[0157] In the vicinity region 440 of the intersection, the electric field tends to concentrate, and when the electric field concentration occurs, the reliability as a multilayer ceramic capacitor may be reduced. However, in the multilayer ceramic capacitor 1 of the present invention, the average particle diameter of the dielectric particles included in the vicinity region 440 of the intersection is smaller than the average particle diameter of the dielectric particles included in each of the surrounding first dielectric ceramic layer 20a, second dielectric ceramic layer 20b, and third dielectric ceramic layers 41 and 42. Since the average particle diameter is small in this way, a large number of grain boundaries exist and the electric field concentration is suppressed. As a result, the reliability as a multilayer ceramic capacitor can be improved.

[0158] [Test Example 2] Next, in the multilayer ceramic capacitor 1 of the present invention, a test example 2 will be described to verify that the average particle diameter of the dielectric particles included in the vicinity region 440 of the intersection is preferably smaller than the average particle diameter of the dielectric particles included in each of the surrounding first dielectric ceramic layer 20a and the third dielectric ceramic layers 41 and 42.

[0159] The average particle diameter of the dielectric particles included in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is measured as follows.

[0160] (Average particle diameter of the dielectric particles included in the first dielectric ceramic layer) In the method for manufacturing the multilayer ceramic capacitor of the present invention described above, without co-firing the first external electrode 51 and the second external electrode 52, the laminate 10 obtained by firing the green chip 110 is polished from the first end face 15 side or the second end face 16 side, and as shown in FIG. 20, a polished body leaving the central portion in the length (L) direction is obtained as a test body. As shown in FIG. 20, at the central portion in the width (W) direction, a virtual line OS1 orthogonal to the width (W) direction was assumed. Then, along the virtual line OS1, the region where the first dielectric ceramic layer 20a related to the acquisition of the capacitance of the polished body, the first internal electrode layer 21, and the second internal electrode layer 22 are laminated was divided into three equal parts in the lamination direction, and divided into three regions: an upper region F1, a central region F2, and a lower region F3. Each of the regions F1, F2, and F3 was imaged with the first dielectric ceramic layer 20a with a field size of 4.3 μm × 3.2 μm, and for each of the regions F1, F2, and F3, for 20 dielectric particles, the area was measured by image processing. Then, the equivalent circle diameter was calculated from the measured area and averaged to obtain the average particle diameter. The average particle diameter was measured in each of the upper region F1, the central region F2, and the lower region F3, and since no significant difference was found in the measured values, the average particle diameter of the central region F2 was regarded as the average particle diameter of the first dielectric ceramic layer.

[0161] (Average particle diameter of the dielectric particles included in the third dielectric ceramic layer) In the test piece shown in Fig. 20, assume a virtual line connecting the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the first side surface 13 side or the second side surface 14 side in the stacking (T) direction. In Fig. 20, a virtual line OS3 connecting the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the second side surface 14 side in the stacking (T) direction is shown. As shown in Fig. 21, from the virtual line OS3, the third dielectric ceramic layer 42 was imaged with a field of view size of 4.3 μm × 3.2 μm in a range of 5 μm toward the third dielectric ceramic layer 42 side, and for each of the regions F1, F2, and F3, the area of 20 dielectric particles was measured by image processing. The reference numeral 42F in Fig. 21 indicates the imaging region. Then, the equivalent circle diameter was calculated from the measured area and averaged to obtain the average particle diameter. The average particle diameter was measured in each of the upper region F1, the central region F2, and the lower region F3, and since no significant difference was found in the measured values, the average particle diameter of the central region F2 was regarded as the average particle diameter of the third dielectric ceramic layer.

[0162] (Average particle diameter of dielectric particles contained in the second dielectric ceramic layer) The laminate 10 is polished from the first end face 15 side or the second end face 16 side until just before at least one of the internal electrode layers appears. For example, as shown in Fig. 22, it is polished from the second end face 16 side to the surface J just before the second internal electrode layer 22 appears. As shown in Fig. 23, a virtual line OS2 orthogonal to the width (W) direction was assumed at the center in the width (W) direction. Then, along the virtual line OS2, the second dielectric ceramic layer 20b was divided into three equal parts in the stacking direction and divided into three regions: an upper region G1, a central region G2, and a lower region G3. Each of the regions G1, G2, and G3 was imaged with the second dielectric ceramic layer with a field of view size of 4.3 μm × 3.2 μm, and for each of the regions G1, G2, and G3, the area of 20 dielectric particles was measured by image processing. Then, the equivalent circle diameter was calculated from the measured area and averaged to obtain the average particle diameter. The average particle diameter was measured in each of the upper region G1, the central region G2, and the lower region G3, and since no significant difference was found in the measured values, the average particle diameter of the central region G2 was regarded as the average particle diameter of the second dielectric ceramic layer.

[0163] (Average particle diameter of dielectric particles included in the vicinity of the intersection) In the test piece shown in FIG. 23, assume a virtual line OS4 that connects the ends of a plurality of first internal electrode layers 21 and a plurality of second internal electrode layers 22 on the second side surface 14 side in the stacking (T) direction. Then, along the virtual line OS4, the regions on both sides in the width (W) direction of the virtual line OS4 including the vicinity region 440 of the intersection are equally divided into three regions in the stacking direction, and divided into three regions: an upper region H1, a central region H2, and a lower region H3. As shown in FIG. 24, the second dielectric ceramic layer 20b and the third dielectric ceramic layer 42 are imaged with a field of view size of 4.3 μm × 3.2 μm in a range of 5 μm on both sides in the width (W) direction of the virtual line OS4, and for each of the regions F1, F2, and F3, the area of 20 dielectric particles is measured by image processing. The reference numeral 42H in FIG. 24 indicates the imaging region. Then, the equivalent circle diameter is calculated from the measured area and averaged to obtain the average particle diameter. The average particle diameter was measured in each of the upper region H1, the central region H2, and the lower region H3, and since no significant difference was found in the measured values, the average particle diameter of the central region H2 was regarded as the average particle diameter of the vicinity region 440 of the intersection.

[0164] As the multilayer ceramic capacitors corresponding to the above (C) to (I), test examples 2-1 to 2-24 shown in Table 3 were prepared. Also, in test examples 2-25 to 2-27, the average particle diameter of the dielectric particles included in the vicinity region 440 of the intersection was made larger than any of the average particle diameters of the dielectric particles included in the first dielectric ceramic layer 20a, the average particle diameter of the dielectric particles included in the second dielectric ceramic layer 20b, and the average particle diameters of the dielectric particles included in the third dielectric ceramic layers 41 and 42. For these test examples 2-1 to 2-27, the average particle diameter was examined by the above-described measurement method.

[0165] In Table 3, in the item of comparison of average particle diameter, "First" is the average particle diameter of the dielectric particles contained in the first dielectric ceramic layer, "Second" is the average particle diameter of the dielectric particles contained in the second dielectric ceramic layer, "Third" is the average particle diameter of the dielectric particles contained in the third dielectric ceramic layer, and "Intersection" is the average particle diameter of the dielectric particles contained in the vicinity of the intersection.

[0166] On the other hand, for the multilayer ceramic capacitors of Test Examples 2-25 to 2-27, the resistance value (kΩ) was measured in an environment at room temperature of 150° with a voltage of 6.3 V applied, the MTTF (mean time to failure) was examined, and a determination was made. The MTTF was set at the time when the resistance value became 10 kΩ or less. When the MTTF was 15.3 hours (hr) or less, the determination was marked as ×; when it exceeded 15.3 hours (hr) and was up to 30 hours, the determination was marked as 〇 (good); when it exceeded 30 hours, the determination was marked as ◎ (excellent). The results are also shown in Table 3. Note that when the coverage of the internal electrode layer was less than 80%, it was impossible to measure the capacitance, so the measurement was not performed.

[0167]

Table 3

[0168] According to Table 3, it was confirmed that when the average particle diameter of the dielectric particles contained in the vicinity of the intersection was smaller than the average particle diameter of the dielectric particles contained in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, the MTTF increased and the reliability of the multilayer ceramic capacitor was enhanced.

[0169] 〔3〕Manufacturing method with an additional step of removing the side surface of the laminate In the method for manufacturing the multilayer ceramic capacitor 1 of the present invention described above, in obtaining the green chip 110 which is the unfired laminate 10, a step of printing the unfired first internal electrode layer 121 and the second internal electrode layer 122 on the unfired first dielectric ceramic layer 120a; a step of forming the unfired second dielectric ceramic layer 120b in a region of the first dielectric ceramic layer 120a other than the regions where the first internal electrode layer 121 and the second internal electrode layer 122 are printed; a step of laminating a plurality of first dielectric ceramic layers 120a to form the green chip 110; a step of exposing the first internal electrode layer 121, the second internal electrode layer 122, the first dielectric ceramic layer 120a, and the second dielectric ceramic layer 120b from the first side surface 113 and the second side surface 114 of the individual green chips 110 by cutting the mother block 104; and a step of forming by bonding the unfired third dielectric ceramic layer (side margin portions 41 and 42) to the first side surface 113 and the second side surface 114 of the individual green chips 110. Here, the green chip 110 is an example of a laminate. The first dielectric ceramic layer 120a is an example of a dielectric layer. The first internal electrode layer 121 and the second internal electrode layer 122 are examples of internal electrode patterns. The second dielectric ceramic layer 120b is an example of a dielectric pattern. The first side surface 113 and the second side surface 114 are examples of side surfaces. The side margin portions 41 and 42 which are the unfired third dielectric ceramic layer are examples of dielectric gap layers.

[0170] In this manufacturing method, after the step of exposing the first internal electrode layer 121, the second internal electrode layer 122, the first dielectric ceramic layer 120a, and the second dielectric ceramic layer 120b from the first side surface 113 and the second side surface 114 of the green chip 110 by cutting the mother block 104, and before the step of forming by bonding a third dielectric ceramic layer to the first side surface 113 and the second side surface 114 of the green chip 110 respectively, a removing step of removing a certain thickness can be added to the first side surface 113 and the second side surface 114. Thereby, the side surfaces of the first dielectric ceramic layer 120a, the second dielectric ceramic layer 120b, the first internal electrode layer 121, and the second internal electrode layer 122 exposed on the first side surface 113 and the second side surface 114 are removed.

[0171] FIG. 25 shows a state in which the first side surface 113 and the second side surface 114 of the green chip 110 are removed by a certain thickness (for example, 1 μm or less) and flattened. In FIG. 25, the left side shows before the removing step, and the right side shows after the removing step. When the mother block 104 is cut to obtain a plurality of green chips 110, the first side surface 113 and the second side surface 114 of the green chip 110 may be plastically deformed with the side surfaces flowing slightly downward as shown in FIG. 25 due to the stress applied to the lower side in the drawing in the cutting direction. Also, the cutting surface may not be sufficiently smooth or foreign matter may be present on the cutting surface. Therefore, a thickness is removed to the extent that the deformed portion disappears. The means for removing the first side surface 113 and the second side surface 114 in this way is not limited, but for example, polishing by appropriate polishing means is preferably suitable.

[0172] As shown in FIG. 26, the first side surface 113 and the second side surface 114 after the above removing step are formed into smooth surfaces and surfaces from which foreign matter has been removed. A third dielectric ceramic layer (side margin portions 41 and 42) is bonded to the first side surface 113 and the second side surface 114 after this removing step to form.

[0173] In the present invention, each of the second dielectric ceramic layer 20b, the first internal electrode layer 21, and the second internal electrode layer 22 may contain a resin. The resin can be contained by adding it to the materials during manufacturing. That is, in the second dielectric ceramic layer 20b, the dielectric paste contains the resin, and in the first internal electrode layer 21 and the second internal electrode layer 22, the conductive paste contains the resin.

[0174] The resins contained in the dielectric paste and the conductive paste are added for the purpose of functions such as acting as a binder and improving the viscosity of the materials. Examples of such resins include polyvinyl acetal resins such as polyvinyl butyral and polyvinyl acetoacetal, polyvinyl alcohol-based resins such as polyvinyl alcohol, cellulose-based resins such as methyl cellulose, ethyl cellulose, and cellulose acetate phthalate, (meth)acrylic resins such as (meth)acrylate, imide-based resins such as polyamideimide and polyimide, ethylene-based resins such as polyethylene oxide, nitrile-based resins such as polyacrylonitrile and polymethacrylonitrile, urethane-based resins such as polyurethane, vinyl-based resins such as polyethylene, polypropylene, and vinyl acetate, and rubber-based resins such as styrene-butadiene rubber, but are not limited thereto.

[0175] Also, as the resin content, it is preferable that the content contained in the second dielectric ceramic layer 20b is different from the content contained in the first dielectric ceramic layer 20a. The resin contents of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b are preferably, for example, 30 wt% or more and 50 wt% or less. It is preferable that the resin contents of the first dielectric ceramic layer and the second dielectric ceramic layer 20b are different from each other within this range.

[0176] In the method for manufacturing the multilayer ceramic capacitor of the present invention, the thickness of the first dielectric ceramic layer 120a is preferably 0.4 μm or more and 0.8 μm or less. Also, in the method for manufacturing the multilayer ceramic capacitor of the present invention, the thicknesses of the first internal electrode layer 121 and the second internal electrode layer 122 are preferably 0.4 μm or more and 0.8 μm or less.

[0177] Also, when forming the green chip 110, a part of the second internal electrode layer 122 may be in a state of overlapping with a part of the first internal electrode layer 121 and the second internal electrode layer 122. Specifically, the end portions adjacent to each other in the length (L) direction of the second dielectric ceramic layer 120b and the first internal electrode layer 121 and the second internal electrode layer 122 may overlap with each other. For example, as shown in FIG. 27, in the length (L) direction, the end portion of the second dielectric ceramic layer 120b may overlap on the end portion of the first internal electrode layer 121. Similarly, the end portion of the second dielectric ceramic layer 120b may overlap on the end portion of the second internal electrode layer 122. In the mode where the end portions in the length (L) direction overlap in this way, the end portion of the first internal electrode layer 121 and the end portion of the second dielectric ceramic layer 120b may overlap on the end portion of the second dielectric ceramic layer 120b.

[0178] In the method for manufacturing the multilayer ceramic capacitor of the present invention, after removing a certain thickness from the first side surface 113 and the second side surface 114 of the green chip 110 which is the unfired laminate 10, an unfired third dielectric ceramic layer is pasted and formed on the first side surface 113 and the second side surface 114. Thereby, an unfired third dielectric ceramic layer can be formed on the first side surface 113 and the second side surface 114 in a smooth and clean state.

[0179] In the method for manufacturing the multilayer ceramic capacitor of the present invention, by removing the first side surface 113 and the second side surface 114 by polishing, the first side surface 113 and the second side surface 114 can be easily and accurately removed with a predetermined removal amount.

[0180] In the method for manufacturing a multilayer ceramic capacitor of the present invention, the second dielectric ceramic layer 120b contains resin, and the amount of the resin is preferably larger than the amount of the resin contained in the first internal electrode layer 121 and the second internal electrode layer 122. Thereby, the viscosity of the second dielectric ceramic layer 120b is relatively increased, and it is possible to suppress the occurrence of defects such as cracks and chips on the cut surface of the second dielectric ceramic layer 20b when the mother block 104 is cut.

[0181] Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thickness of the first dielectric ceramic layer 120a is preferably 0.4 μm or more and 0.8 μm or less. Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thicknesses of the first internal electrode layer 121 and the second internal electrode layer 122 are preferably 0.4 μm or more and 0.8 μm or less. By having such thicknesses in the unfired dielectric layer and internal electrode layer, the first dielectric ceramic layer 20a, the first internal electrode layer 21, and the second internal electrode layer 22 after firing can be formed to have appropriate thicknesses.

[0182] Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, a part of the second internal electrode layer 122 may overlap with the first internal electrode layer 121 and the second internal electrode layer 122. Thereby, after firing, the second dielectric ceramic layer 20b can be arranged with sufficient thickness without a gap.

[0183] 〔4〕Defective portion of the second dielectric ceramic layer In the multilayer ceramic capacitor 1 of the present invention, as shown in FIGS. 28 and 29, between at least one second dielectric ceramic layer 20b and one third dielectric ceramic layer 42, there is a defective portion 520 in which a part of the second dielectric ceramic layer 20b is missing. Similarly, between at least one second dielectric ceramic layer 20b and the other third dielectric ceramic layer 41, there is a defective portion 520 in which a part of the second dielectric ceramic layer 20b is missing.

[0184] The defective portion 520 is located in the region where the second dielectric ceramic layer 20b is disposed, that is, in the length (L) direction of the laminate 10, between the end portion of the first internal electrode layer 21 that is not connected to the second external electrode 52 and the second external electrode 52, and between the end portion of the second internal electrode layer 22 that is not connected to the first external electrode 51 and the first external electrode 51. In the plane including the lamination (T) direction and the width (W) direction, the position in the lamination (T) direction is between the first dielectric ceramic layers 20a, and the position in the width (W) direction is formed between the second dielectric ceramic layer 20b and the third dielectric ceramic layer 41 or 42.

[0185] When manufacturing the green chip 110 which is the unfired laminate 10, the side surface of the unfired second dielectric ceramic layer 120b is processed and then fired, whereby the laminate 10 having the defective portion 520 on the side surface of the second dielectric ceramic layer 20b is obtained. The processing method for obtaining the defective portion 520 is arbitrary. For example, it can be formed by drilling with an appropriate tool or the like.

[0186] Also, in the above-mentioned "manufacturing method with an additional step of removing the side surface of the laminate", when the first side surface 113 or the second side surface 114 of the unfired green chip 110 is removed by means such as polishing, a part of the side surface of the second dielectric ceramic layer 20b may be missing and a fine hole may be formed. When such a hole is formed, it is also possible to use the hole as the defective portion 520. The defective portion 520 does not have to be formed on the side surfaces of all the second internal electrode layers 22, and one or more may be formed on each of the first side surface 13 side and the second side surface 14 side at both end portions in the length (L) direction.

[0187] Also, as shown in FIGS. 28 and 29, a Si segregation 530 may be disposed in the defective portion 520. The Si segregation 530 is a segregation of Si added as an additive to the second dielectric ceramic layer 20b.

[0188] The size of the segregation 530 of Si is preferably larger than 1 / 3 of the thickness of the second dielectric ceramic layer 20b in terms of the diameter of the equivalent circle diameter. Further, it may be 100 nm or more and 600 nm or less.

[0189] The defective portion 520 is preferably disposed close to the first internal electrode layer 21 or the second internal electrode layer 22. In FIG. 29, the defective portion 520 is disposed close to the end portion in the length (L) direction of the second internal electrode layer 22. Similarly, it is preferable that the defective portion 520 is disposed close to the end portion in the length (L) direction of the first internal electrode layer 21.

[0190] The dimension of the segregation 530 of Si is preferably 0.1% or more and 5% or less of the dimensions of the third dielectric ceramic layers 41 and 42 in the width (W) direction.

[0191] The multilayer ceramic capacitor 1 of the present invention has a defective portion 520 in at least one of the regions where the second dielectric ceramic layer 20b is disposed, that is, in the length (L) direction of the laminate 10, between the second external electrode 52 and the end portion and the second external electrode 52 in the first internal electrode layer 21, and between the end portion not connected to the first external electrode 51 and the first external electrode 51 in the second internal electrode layer 22. In the plane including the lamination (T) direction and the width (W) direction, the position in the lamination (T) direction is between the first dielectric ceramic layers 20a, and in the position in the width (W) direction, it is between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42.

[0192] Thereby, the stress generated in the second dielectric ceramic layer 20b during firing can be relaxed by the defective portion 520. As a result, it is possible to suppress cracks and chipping from occurring in the second dielectric ceramic layer 20b.

[0193] In the multilayer ceramic capacitor 1 of the present invention, segregation 530 of Si may be disposed in the defective portion 520. When the segregation 530 exists in the defective portion 520, the ingress of moisture is suppressed by the segregation 530. The presence of the segregation 530 in the defective portion 520 improves the moisture resistance of the multilayer ceramic capacitor 1. The segregation 530 may exist in all of the defective portion 520 or may exist in a part of the defective portion 520. The defective portion 520 in which the segregation 530 exists can suppress the occurrence of cracks and chips in the second dielectric ceramic layer 20b, and the moisture resistance of the multilayer ceramic capacitor 1 can also be improved.

[0194] In the multilayer ceramic capacitor 1 of the present invention, the segregation 530 of Si is 1 / 3 or more (or less) of the thickness of the second dielectric ceramic layer 20b.

[0195] In the multilayer ceramic capacitor 1 of the present invention, the defective portion 520 is disposed in proximity to the first internal electrode layer 21 and the second internal electrode layer 22. The regions in proximity to the first internal electrode layer 21 and the second internal electrode layer 22 have relatively large stress generated during firing, but the stress is relaxed by the defective portion 520, so that the occurrence of cracks and chips can be effectively suppressed.

[0196] In the multilayer ceramic capacitor 1 of the present invention, in the width direction, the dimension of the segregation 530 of Si is preferably 0.1% or more and 5% or less of the dimensions of the third dielectric ceramic layers 41 and 42. When the segregation 530 of Si exists in the defective portion 520, the occurrence of cracks and chips can be effectively suppressed, and the moisture resistance of the multilayer ceramic capacitor 1 can also be improved.

[0197] 〔5〕Segregation formed at the end portion on the internal electrode layer side of the second dielectric ceramic layer As shown in FIG. 30, in the multilayer ceramic capacitor 1 of the present invention, a first segregation 610 may exist at an end portion in the length (L) direction that is not connected to the second external electrode 52 in the first internal electrode layer 21. Further, a first segregation 610 may exist at an end portion in the length (L) direction that is not connected to the first external electrode 51 in the second internal electrode layer 22.

[0198] As shown in FIG. 31, the first segregation 610 is caused by the layered segregation of a metal element 610a derived from the second dielectric ceramic layer 20b. Examples of the metal element 610a include at least one of Mg, Mn, and Si. The segregation 610 caused by the metal element 610a occurs when the metal element contained in the second dielectric ceramic layer 20b moves to the first internal electrode layer 21 and the second internal electrode layer 22 during the firing of the second dielectric ceramic layer 20b.

[0199] On the other hand, as shown in FIG. 32, a second segregation 620 may exist at an end portion in the width (W) direction of the first internal electrode layer 21. Further, a second segregation 620 may exist at an end portion in the width (W) direction of the second internal electrode layer 22.

[0200] The second segregation 620 is caused by the layered segregation of a metal element 620a derived from the third dielectric ceramic layers 41 and 42 that contact the first internal electrode layer 21 and the second internal electrode layer 22. Examples of the metal element 620a are the same as those of the first segregation 610, and include at least one of Mg, Mn, and Si. The segregation 620 caused by the metal element 620a occurs when the metal element contained in the third dielectric ceramic layers 41 and 42 moves to the first internal electrode layer 21 and the second internal electrode layer 22 during the firing of the third dielectric ceramic layers 41 and 42.

[0201] In the multilayer ceramic capacitor 1 of the present invention, it is preferable that at least one set of the segregation including the first segregation 610 segregated in the first internal electrode layer 21, the first segregation 610 segregated in the second internal electrode layer 22, the second segregation 620 segregated in the first internal electrode layer 21, and the second segregation 620 segregated in the second internal electrode layer 22 has a metal element different from that included in other segregation.

[0202] When the first dielectric ceramic layer 20a contains BaTiO3 as a main component, the content of the metal element contained in the first segregation 610 with respect to the first internal electrode layer 21 and the second internal electrode layer 22 is 0.3 mol% or more with respect to 100 mol of Ti. Similarly, the content of the metal element contained in the second segregation 620 with respect to the first internal electrode layer 21 and the second internal electrode layer 22 is 0.3 mol% or more with respect to 100 mol of Ti.

[0203] In the present invention, it is preferable that the length of the region where the first segregation 610 exists in the first internal electrode layer 21 along its length (L) direction is 0.1 μm or more. Also, it is preferable that the length of the region where the first segregation 610 exists in the second internal electrode layer 22 along its length (L) direction is 0.1 μm or more. Also, it is preferable that the length of the region where the second segregation 620 exists in the first internal electrode layer 21 along its width (W) direction is 0.1 μm or more. Also, it is preferable that the length of the region where the second segregation 620 exists in the second internal electrode layer 22 along its width (W) direction is 0.1 μm or more. By having these lengths, the effect of suppressing electric field concentration due to segregation and improving reliability can be surely obtained.

[0204] Regarding the lengths of the first segregation 610 and the second segregation 620, if they are less than the above lengths, it becomes difficult to suppress electric field concentration. Also, in the first segregation 610, when it exceeds 0.5% in the length (L) direction, and in the second segregation 620, when it exceeds 1.0% in the width (W) direction, the metal element (at least one of Mg, Mn, Si) that segregates becomes excessive, and the function of storing charges in the internal electrode layer deteriorates.

[0205] The length in the length (L) direction of the first segregation 610 can be controlled by adjusting the content of the metal element 610a contained in the second dielectric ceramic layer 20b and moving and segregating to the first internal electrode layer 21 and the second internal electrode layer 22. Also, the length in the width (W) direction of the second segregation 620 can be controlled by adjusting the content of the metal element 620a contained in the third dielectric ceramic layers 41 and 42 and moving and segregating to the first internal electrode layer 21 and the second internal electrode layer 22.

[0206] In the multilayer ceramic capacitor 1 of the present invention, at each of the ends in the length (L) direction of the first internal electrode layer 21 not connected to the second external electrode 52 and the ends in the length (L) direction of the second internal electrode layer 22 not connected to the first external electrode 51, there is a first segregation 610 of at least one kind of metal element among Mg, Mn, and Si.

[0207] At each of the ends in the length (L) direction of the first internal electrode layer 21 and the second internal electrode layer 22 in contact with the second dielectric ceramic layer 20b, an electric field tends to concentrate. When electric field concentration occurs, the reliability as a multilayer ceramic capacitor may be reduced. However, in the multilayer ceramic capacitor 1 of the present invention, the electric field concentration is suppressed by the first segregation 610, and the reliability can be improved.

[0208] In the multilayer ceramic capacitor 1 of the present invention, at each of the ends in the width (W) direction of the first internal electrode layer 21 and the ends in the width (W) direction of the second internal electrode layer 22, there is a second segregation 620 of at least one kind of metal element among Mg, Mn, and Si.

[0209] At the ends in the width (W) direction of the first internal electrode layer 21 and the second internal electrode layer 22 that are in contact with the third dielectric ceramic layers 41 and 42, an electric field is likely to concentrate. When electric field concentration occurs, it may reduce the reliability of the multilayer ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, since the electric field concentration is suppressed by the second segregation 620, the reliability can be improved.

[0210] In the multilayer ceramic capacitor 1 of the present invention, the first segregation 610 segregated in the first internal electrode layer 21, the first segregation 610 segregated in the second internal electrode layer 22, the second segregation 620 segregated in the first internal electrode layer 21, and the second segregation 620 segregated in the second internal electrode layer 22 are such that at least one set of the segregation contains a metal element different from the metal element contained in the other segregation.

[0211] Thereby, an optimal metal element corresponding to the location where the first segregation 610 and the second segregation 620 are arranged can be arranged, and the reliability can be enhanced.

[0212] In the multilayer ceramic capacitor 1 of the present invention, the first dielectric ceramic layer 20a contains Ba and Ti, and the content of the metal element 610a contained in the first segregation 610 and the content of the metal element 620a contained in the second segregation 620 with respect to each internal electrode layer are 0.3 mol% or more with respect to 100 mol of Ti.

[0213] Thereby, the above-described electric field concentration can be effectively suppressed, and the reliability can be further improved.

[0214] In the multilayer ceramic capacitor 1 of the present invention, the region where the first segregation 610 exists in the first internal electrode layer 21 has a length (L) of 0.3 μm or more, the region where the first segregation 610 exists in the second internal electrode layer 22 has a length (L) of 0.3 μm or more, and the region where the second segregation 620 exists in the first segregation 610 preferably has a width (W) of 0.3 μm or more, and the region where the second segregation 620 exists in the second segregation 620 preferably has a width (W) of 0.3 μm or more.

[0215] Thereby, the effect that the electric field concentration is suppressed by the segregation and the reliability is improved can be surely obtained.

[0216] [Test Example 3] Next, Test Example 3 for verifying the effects of the first segregation 610 and the second segregation 620 in the multilayer ceramic capacitor 1 of the present invention will be described.

[0217] As shown in Table 4, Test Examples 3-1 to 3-18 of multilayer ceramic capacitors provided with the second dielectric ceramic layer 20b, the third dielectric ceramic layers 41 and 42 containing any one of the elements Mg, Mn, and Si were prepared. Then, for each test example, the concentration of the element of the first segregation generated at the end in the length (L) direction of the first internal electrode layer 21 and the second internal electrode layer 22, the length in the length (L) direction, and the length in the width (W) direction were examined. The concentrations of the metal elements of the first segregation and the second segregation were examined using the same method as the concentrations of the second alloy part and the third alloy part in the above-described "Test Example 1". Also, the lengths of the first segregation and the second segregation were measured by EDX analysis.

[0218] For the multilayer ceramic capacitors of Test Examples 3-1 to 3-18, after heating in an environment at a temperature of 150° for 1 hour and then cooling to room temperature, the resistance value (kΩ) was measured with a voltage of 6.3 V applied, and the MTTF (mean time to failure) was examined. Also, the presence or absence of a decrease in capacitance was examined using an LCR meter (manufactured by Keysight: E4980). Those with a capacitance decrease of 3% or more, or an MTTF of 15.3 hours or less are marked as ×. When the capacitance decrease is less than 3% and the MTTF exceeds 15.3 hours and is 30 hours or less, it is judged as 〇 (good). When the capacitance decrease is less than 3% and the MTTF exceeds 30 hours, it is judged as ◎ (excellent). The results are also shown in Table 4.

[0219]

Table 4

[0220] By incorporating Mg, Mn, and Si into the second dielectric layer, segregation parts are created at the ends in the length and width directions of the internal electrode, thereby eliminating the reliability degradation factors that tend to occur at the ends. However, if the content is too high, the region functioning as the metal of the internal electrode becomes narrow, resulting in a decrease in capacitance.

[0221] 〔6〕Segregation formed in the corner region on the side of the internal electrode layer of the second dielectric ceramic layer When having the above-mentioned first segregation 610 and second segregation 620, furthermore, as shown in Fig. 33, it is preferable that a third segregation 630 exists. The third segregation 630 exists in each of the first corner region 710 and the second corner region 720.

[0222] The first corner region 710 is a region where the length (L) direction in which the first segregation 610 exists and the width (W) direction of the second segregation 620 overlap in the first internal electrode layer 21. Also, the second corner region 720 is a region where the length (L) direction in which the first segregation 610 exists and the width (W) direction of the second segregation 620 overlap in the second internal electrode layer 22. The third segregation 630 is caused by the segregation of the metal element 610a of the first segregation 610 and the metal element 620a of the second segregation 620.

[0223] In the present invention, the metal element 610a included in the first segregation 610 and the metal element 620a included in the second segregation 620 are different from each other, and the metal element 630a of the third segregation 630 preferably includes both the metal element 610a included in the first segregation 610 and the metal element 620a included in the second segregation 620.

[0224] Further, in the present invention, the region where the first segregation 610 exists is preferably 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is preferably 0.1 μm or more in the width (W) direction.

[0225] FIG. 33 shows a surface including the length (L) direction and the width (W) direction in the multilayer ceramic capacitor 1 of the present invention. The third segregation 630 preferably segregates in a substantially right-angled triangular shape such that its existing region becomes larger as it goes toward the end in the length (L) direction on the surface including the length (L) direction and the width (W) direction. Part or all of the third segregation 630 is included in the vicinity region 440 of the intersection in FIG. 19.

[0226] Further, in the multilayer ceramic capacitor 1 of the present invention, a part of the second dielectric ceramic layer 20b is preferably arranged so as to overlap the existing region of the third segregation 630 in the lamination (T) direction with respect to the first internal electrode layer 21 and the second internal electrode layer 22. Specifically, as shown in FIG. 34, in the length (L) direction, a form in which the end of the second dielectric ceramic layer 120b overlaps the end of the second internal electrode layer 22 in the region including the third segregation 630 can be mentioned. Similarly, the end of the second dielectric ceramic layer 20b may overlap the end of the first internal electrode layer 21. In the aspect where the ends in the length (L) direction overlap in this way, the end of the first internal electrode layer 121 or the end of the second dielectric ceramic layer 120b may overlap on the end of the second dielectric ceramic layer 20b.

[0227] In the multilayer ceramic capacitor 1 of the present invention, at each of the ends in the length (L) direction not connected to the second external electrode 52 in the first internal electrode layer 21 and the ends in the length (L) direction not connected to the first external electrode 51 in the second internal electrode layer 22, there is a first segregation 610 of at least one metal element among Mg, Mn, and Si. At each of the ends in the width (W) direction of the first internal electrode layer 21 and the ends in the width (W) direction of the second internal electrode layer 22, there is a second segregation 620 of at least one metal element among Mg, Mn, and Si. In the first internal electrode layer 21, a first corner region 710 where the end in the length (L) direction where the first segregation 610 exists overlaps with the width (W) direction where the second segregation 620 exists, and in the second internal electrode layer 22, a second corner region 720 where the end in the length (L) direction where the first segregation 610 exists overlaps with the width (W) direction where the second segregation 620 exists, there is a third segregation 630 of each metal element of the first segregation 610 and the second segregation 620.

[0228] In the first corner region 710 and the second corner region 720, the electric field tends to concentrate. When electric field concentration occurs, the reliability of the multilayer ceramic capacitor may be reduced. However, in the multilayer ceramic capacitor 1 of the present invention, since the electric field concentration in the first corner region 710 and the second corner region 720 is suppressed by the third segregation 630, the reliability can be improved.

[0229] In the multilayer ceramic capacitor 1 of the present invention, the metal element 610a included in the first segregation 610 and the metal element 620a included in the second segregation 620 are different from each other, and the metal element included in the third segregation 630 includes both the metal element 610a included in the first segregation 610 and the metal element 620a included in the second segregation 620.

[0230] Thereby, the electric field concentration in the first corner region 710 and the second corner region 720 is suppressed by the third segregation 630, and the reliability can be improved.

[0231] In the third segregation 630, Mg is preferably used as the metal element disposed on the side close to the third dielectric ceramic layers 41 and 42. On the other hand, in the third segregation 630, Si is preferably used as the metal element disposed on the side close to the second dielectric ceramic layer 20b from the viewpoint of possible improvement in moisture resistance. Therefore, it is preferable that both Mg and Si are segregated in the first corner region 710 and the second corner region 720. Further, short-circuit recovery may be performed due to the first segregation 610 at the ends in the width (W) direction of the first internal electrode layer 21 and the second internal electrode layer 22. Furthermore, it is more preferable that Sn is dissolved in the first internal electrode layer 21 and the second internal electrode layer 22.

[0232] In the multilayer ceramic capacitor 1 of the present invention, the region where the first segregation 610 exists is 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is 0.1 μm or more in the width (W) direction. Thereby, the effect that the electric field concentration is suppressed by the segregation and the reliability is improved can be surely obtained.

[0233] In the multilayer ceramic capacitor 1 of the present invention, in the plane including the length (L) direction and the width (W) direction, the existence region of the third segregation 630 becomes larger as it goes toward the end in the length (L) direction.

[0234] As a result, the area of the third segregation 630 in the portion of the end in the length (L) direction of the second dielectric ceramic layer 20b where electric field concentration is likely to occur increases, and the suppression of the electric field concentration by the third segregation 630 becomes more effective, and the reliability can be further improved.

[0235] In the multilayer ceramic capacitor 1 of the present invention, a part of the second dielectric ceramic layer 20b is arranged so as to overlap the existence region of the third segregation 630 in the stacking (T) direction with respect to the first internal electrode layer 21 and the second internal electrode layer 22.

[0236] As a result, it becomes easier to form the third segregation 630 such that the existence region thereof increases as it goes toward the end in the length (L) direction on the plane including the length (L) direction and the width (W) direction.

[0237] [Test Example 4] Next, Test Example 4 for verifying the effect of the third segregation 630 in the multilayer ceramic capacitor 1 of the present invention will be described.

[0238] As shown in Table 5, Test Examples 4-1 to 4-18 of multilayer ceramic capacitors including a second dielectric ceramic layer containing any one of the metal elements Mg, Mn, and Si and a third dielectric ceramic layer containing any one of Mg, Mn, and Si were prepared. Then, the concentration of the metal element contained in the third segregation generated in the first corner region and the second corner region of each multilayer ceramic capacitor, and the length in the length (L) direction and the length in the width (W) direction were examined. The concentration of the metal element of the third segregation was examined using the same method as the concentration of the second alloy part and the concentration of the third alloy part in the above-described "Test Example 1". Also, the length of each of the third segregations was measured by EDX analysis.

[0239] For the multilayer ceramic capacitors of Test Examples 4-1 to 4-14, the resistance value (kΩ) was measured in a state where a voltage of 6.3 V was applied in an environment at room temperature of 150°, the MTTF (mean time to failure) was examined, and a determination was made. The MTTF was defined as the time point when the resistance value became 10 kΩ or less. When the MTTF was 15.3 hours (hr) or less, the determination was marked as ×, when it exceeded 15.3 hours (hr) and was up to 30 hours, the determination was marked as ○ (good), and when it exceeded 30 hours, the determination was marked as ⊚ (excellent). The results are also shown in Table 5. Also, the presence or absence of a decrease in capacitance was examined using an LCR meter (manufactured by Keysight Technologies: E4980), and those showing a capacitance decrease of 3% or more were marked as ×. In addition, when the coverage of the internal electrode layer was less than 80%, it was impossible to measure the capacitance because it became difficult to obtain the capacitance.

[0240]

Table 5

[0241] By incorporating Si, Mg, and Mn into the second and third ceramic dielectric layers, many segregation regions can be created at the corners. In particular, electric field concentration occurs at the corners, which tends to reduce reliability. However, by creating segregation regions, reliability can be improved. However, if the content is too high, the region that functions as the metal of the internal electrode becomes narrow, resulting in a decrease in capacitance.

[0242] 〔7〕Thickness of the second dielectric ceramic layer FIG. 35 schematically shows a WT cross-section at the center in the length (L) direction of the laminate 10 in the multilayer ceramic capacitor 1 of the present invention. In this cross-section, the thickness of the first dielectric ceramic layer 20a is indicated by T1, and the thickness at the end in the width (W) direction is indicated by T2.

[0243] Further, FIG. 36 shows a part of the LT cross-section of the multilayer ceramic capacitor 1 of the present invention. T3 is the thickness of the second dielectric ceramic layer 20b. In FIG. 36, the second dielectric ceramic layer 20b in contact with the second internal electrode layer 22 is shown, but the thickness of the second dielectric ceramic layer 20b in contact with the first internal electrode layer 21 is also regarded as T3. In other words, the thickness T3 of the second dielectric ceramic layer 20b is the thickness between the end in the length (L) direction not connected to the second external electrode 52 and the second external electrode 52 in the first internal electrode layer 21, and the thickness between the end in the length (L) direction not connected to the first external electrode 51 and the second external electrode 52 in the second internal electrode layer 22.

[0244] In the present invention, the difference in thickness between T1 and T2 is relatively small and is within 10% of T1. On the other hand, the thickness of T3 is larger than T1 and T2, and the difference is preferably 10% or more of T1 and T2.

[0245] There is no limitation on the means for making the thickness T3 of the second dielectric ceramic layer 20b thicker than the thicknesses T1 and T2 of the first dielectric ceramic layer 20a as described above. For example, when producing the green chip 110 before firing, the end portions in the length (L) direction of the unfired second dielectric ceramic layer 120b and the end portions in the length (L) direction of the unfired first internal electrode layer 121 and the second internal electrode layer 122 are overlapped, and then the green chip 110 is fired, which makes it possible.

[0246] Among T1, T2, and T3, the thickness T1 at the central portion of the first dielectric ceramic layer 20a is preferably 0.7 μm or less. Also, the thickness T3 of the second dielectric ceramic layer 20b is preferably 0.4 μm or more.

[0247] In the multilayer ceramic capacitor 1 of the present invention, when the thickness at the central portion in the stacking (T) direction on the surface including the central portion in the length (L) direction, the stacking (T) direction, and the width (W) direction of the first dielectric ceramic layer 20a is T1, the thickness at the end portion in the width (W) direction of the first dielectric ceramic layer 20a is T2, the thickness between the end portion in the length (L) direction of the first internal electrode layer 21 that is not connected to the second external electrode 52 and the second external electrode 52, and the thickness between the end portion in the length (L) direction of the second internal electrode layer 22 that is not connected to the first external electrode 51 and the first external electrode 51 are each T3, the difference in thickness between T1 and T2 is within 10% of T1, the thickness of T3 is larger than T1 and T2, and the difference is 10% or more of T1 and T2.

[0248] As a result, the element thickness due to the second dielectric ceramic layer 20b disposed for step elimination has a sufficient thickness between the first dielectric ceramic layers 20a sandwiching the first internal electrode layer 21 and the second internal electrode layer 22, and as a result, the reliability can be improved.

Description of Reference Numerals

[0249] 41, 42 Margin portion (dielectric gap layer) 110 Green chip (laminated body) 120a First dielectric ceramic layer (dielectric layer) 120b Second dielectric ceramic layer (dielectric pattern) 121 First internal electrode layer (internal electrode pattern) 122 Second internal electrode layer (internal electrode pattern)

Claims

1. A step of printing an internal electrode pattern on a dielectric layer; A step of forming a dielectric pattern in a region other than the region where the internal electrode pattern is printed; A step of laminating a plurality of the dielectric layers to form a laminate; A step of exposing the internal electrode pattern and the dielectric pattern from a side surface of the laminate; A step of removing a thickness such that a deformed portion disappears from the exposed internal electrode pattern and the dielectric pattern; A step of forming a dielectric gap layer on the side surface, and includes: A method for manufacturing a multilayer ceramic capacitor, wherein the dielectric pattern contains resin, and the amount of the resin is larger than the amount of resin contained in the internal electrode pattern.

2. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein the step of removing a part of the dielectric pattern is by polishing.

3. The method for manufacturing a multilayer ceramic capacitor according to claim 1 or 2, wherein the thickness of the dielectric layer is 0.4 μm or more and 0.8 μm or less.

4. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the thickness of the internal electrode pattern is 0.4 μm or more and 0.8 μm or less.

5. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 4, wherein a part of the dielectric pattern overlaps with a part of the internal electrode pattern.

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