Transmitting device, and electronic device

Abstract

A transmission apparatus according to the present disclosure has a plurality of output circuits each of which has a plurality of transistors. The transmission apparatus comprises: a driver circuit that, on the basis of a plurality of driver input signals inputted to the respective ones of the plurality of transistors, outputs a plurality of output signals constituting differential signals and having mutually different signal levels from the plurality of output circuits; a plurality of timing adjustment circuits that, on the basis of timing setting signals, adjust the input timings of the plurality of driver input signals to the driver circuit; and a control circuit that changes the setting values of the timing setting signals for the respective ones of the plurality of timing adjustment circuits to values that are suitable for a plurality of transition states of the signal levels that can be exhibited by the respective ones of the plurality of output signals to be outputted from the driver circuit.

Description

Technical Field

[0001] The present disclosure relates to a transmission device that transmits differential signals and an electronic device.

Background Art

[0002] When transmitting a differential signal having two or more differential signal levels from a transmission device using a plurality of transmission lines, common-mode noise is generated due to the loss of signal balance between the transmission lines. To suppress this, there is a technique of adjusting the timing of the driver input signal to the driver circuit of the differential signal in the transmission device using a timing adjustment circuit (see Patent Document 1). In this case, the set value of the timing adjustment is constant (fixed).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] When the set value of the timing adjustment is constant, for example, when transmitting a differential signal having four or more differential signal levels, the number of transition states of the differential signal levels that the differential signal can take increases, and it becomes difficult to suppress common-mode noise in all transition states.

[0005] It is desirable to provide a transmission device and an electronic device capable of improving communication performance.

[0006] A transmission device according to an embodiment of the present disclosure includes a plurality of output circuits each having a plurality of transistors, and based on a plurality of driver input signals input to each of the plurality of transistors, outputs, from the plurality of output circuits, a plurality of output signals having different signal levels that constitute a differential signal; a plurality of timing adjustment circuits that adjust the input timing of the plurality of driver input signals to the driver circuit based on a timing setting signal; and a control circuit that changes the setting value of the timing setting signal for each of the plurality of timing adjustment circuits to a value corresponding to a plurality of transition states of signal levels that each of the plurality of output signals output from the driver circuit can take. The control circuit has a state determination circuit that changes the set value of the timing setting signal to a value corresponding to a plurality of transition states based on a plurality of first input signals corresponding to a plurality of output signals and a plurality of second input signals obtained by delaying the plurality of first input signals.

[0007] An electronic device according to an embodiment of the present disclosure includes a transmission device that transmits a differential signal and a reception device that receives the differential signal transmitted from the transmission device. The transmission device includes a plurality of output circuits each having a plurality of transistors, and based on a plurality of driver input signals input to each of the plurality of transistors, outputs, from the plurality of output circuits, a plurality of output signals having different signal levels that constitute a differential signal; a plurality of timing adjustment circuits that adjust the input timing of the plurality of driver input signals to the driver circuit based on a timing setting signal; and a control circuit that changes the setting value of the timing setting signal for each of the plurality of timing adjustment circuits to a value corresponding to a plurality of transition states of signal levels that each of the plurality of output signals output from the driver circuit can take. The control circuit has a state determination circuit that changes the set value of the timing setting signal to a value corresponding to a plurality of transition states based on a plurality of first input signals corresponding to a plurality of output signals and a plurality of second input signals obtained by delaying the plurality of first input signals.

[0008] In the transmission device or the electronic device according to an embodiment of the present disclosure, the setting value of the timing setting signal for each of the plurality of timing adjustment circuits is changed to a value corresponding to a plurality of transition states of signal levels that each of the plurality of output signals output from the driver circuit can take.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 0. Comparative Example (Figs. 1 to 15) 1. First Embodiment (Figs. 16 to 35) 1.1 Configuration Example and Operation Example of Transmission Device 1.2 Application Example to Electronic Devices 1.3 Modification 1.4 Effects 2. Second Embodiment (Figs. 36 to 37) 3. Third Embodiment (Fig. 38) 4. Other Embodiments

[0011] <0. Comparative Example> (Outline and Problems of Transmission Device According to Comparative Example) When transmitting a differential signal via a transmission line formed on a printed circuit board or the like, the common-mode noise generated by the differential signal becomes radiated noise, which is a factor deteriorating EMI (Electro Magnetic Interference). When EMI generated from the differential signal becomes a problem, it is effective to suppress this common-mode noise. As a means for suppressing this common-mode noise, there is a method of attenuating the common-mode noise by arranging a common-mode choke filter with respect to the differential signal transmission line wired on the printed circuit board. However, when adding a new mounting component to the printed circuit board or the like in this way, there is a demerit that the component cost thereof is incurred. This common-mode noise is mainly generated in an LSI (Large Scale Integration) serving as a transmission circuit of the differential signal. Regarding the common-mode noise generated on the transmission circuit side, it is desirable to suppress it on the transmission circuit side. If this can be realized, the surplus cost due to the common-mode choke filter as described above can be avoided.

[0012] When driving the differential signal output from the LSI, in order to reduce the common-mode noise, the rise time and the fall time of a plurality of output signals constituting the differential signal may be made the same. At this time, if the driving ability of each rise and the driving ability of each fall in a plurality of output circuits that output a plurality of output signals are exactly the same, the input timing of the input signal to each output circuit may be made the same timing.

[0013] FIG. 1 shows a configuration example of a transmission device according to a comparative example that outputs a binary differential signal.

[0014] The transmission device according to this comparative example outputs output signal SIGA and output signal SIGB with different signal levels from each other, which constitute a binary differential signal. The transmission device according to the comparative example includes a driver circuit 150 and a pre-driver circuit 140 arranged in front of the driver circuit 150. The pre-driver circuit 140 and the driver circuit 150 constitute an output circuit 101A that outputs the output signal SIGA and an output circuit 101B that outputs the output signal SIGB.

[0015] The pre-driver circuit 140 in the output circuit 101A has a rising circuit 141U and a falling circuit 141D. The driver circuit 150 in the output circuit 101A has a rising circuit 151U and a falling circuit 151D. Similarly, the pre-driver circuit 140 in the output circuit 101B has a rising circuit 141U and a falling circuit 141D. The driver circuit 150 in the output circuit 101B has a rising circuit 151U and a falling circuit 151D.

[0016] The rising circuit 151U has a MOS transistor M1 and a resistance element R1. The falling circuit 151D has a MOS transistor M2 and a resistance element R2. The MOS transistors M1 and M2 are each composed of an N-ch MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The power supply voltage VDDH is supplied to the drain of the MOS transistor M1. The source of the MOS transistor M2 is grounded.

[0017] The current driving capabilities of the rising circuit 151U and the falling circuit 151D in the driver circuit 150 are ideally the same.

[0018] FIG. 2 is a timing chart showing an example of the ideal operation timing of a plurality of input / output signals and the generation timing of common-mode noise in the driver circuit 150 shown in FIG. 1. FIG. 2(A) shows the operation timing of the driver input signal UIN_A input to the MOS transistor M1 and the driver input signal DIN_A input to the MOS transistor M2 in the output circuit 101A of the driver circuit 150. FIG. 2(B) shows the operation timing of the driver input signal UIN_B input to the MOS transistor M1 and the driver input signal DIN_B input to the MOS transistor M2 in the output circuit 101B of the driver circuit 150. FIG. 2(C) shows the operation timing of the output signal SIGA and the output signal SIGB. FIG. 2(D) shows the generation timing of the common-mode noise.

[0019] In the ideal state shown in FIG. 2, no common-mode noise is generated. However, considering manufacturing variations of the LSI, voltage fluctuations, etc., it is difficult to make the above-mentioned rising driver driving ability and falling driver driving ability in the driver circuit 150 the same under certain conditions, and there are cases where they are slightly different. Similarly, a timing difference between a plurality of driver input signals is likely to occur. For these reasons, there are cases where a difference occurs in the rising time and the falling time between the output signal SIGA and the output signal SIGB, and as a result, it is difficult to reduce the common-mode noise.

[0020] FIG. 3 is a timing chart showing an example of the operation timing of input / output signals and the generation timing of common-mode noise when a timing difference occurs between a plurality of driver input signals in the driver circuit 150 shown in FIG. 1. FIGS. 3(A) to 3(D) show the same timings as FIGS. 2(A) to 2(D).

[0021] When a timing difference occurs between a plurality of driver input signals as shown in FIGS. 3(A) and 3(B), a difference occurs in the rise time and fall time between the output signal SIGA and the output signal SIGB as shown in FIG. 3(C). As a result, common mode noise occurs as shown in FIG. 3(D).

[0022] As a means for suppressing the common mode noise generated by such a timing difference between a plurality of driver input signals, there is a method of adjusting the timing of the driver input signal or the output signals SIGA and SIGB.

[0023] FIG. 4 shows a configuration example in which timing adjustment circuits 160U and 160D are arranged in front of the pre-driver circuit 140 in the transmission device shown in FIG. 1.

[0024] In the configuration example shown in FIG. 4, timing adjustment circuits 160U and 160D are arranged in front of the rising circuit 141U and the falling circuit 141D, respectively, in each of the output circuits 101A and 101B. The timing adjustment circuits 160U and 160D are composed of, for example, a delay element and a circuit for selecting a signal delayed by the delay element. Examples of the delay element include a CMOS inverter and a capacitive element. The timing adjustment circuits 160U and 160D operate based on the set values of the input timing setting signals T_D and T_U.

[0025] FIG. 5 is a timing chart showing an example of the operation timing of the input / output signals and the generation timing of the common mode noise before and after timing adjustment by the timing adjustment circuits 160U and 160D in the transmission device shown in FIG. 4. (A1) to (D1) in FIG. 5 show the same timings as (A) to (D) in FIG. 2 before timing adjustment. (A2) to (D2) in FIG. 5 show the same timings as (A) to (D) in FIG. 2 after timing adjustment.

[0026] The timing differences that occur between a plurality of driver input signals (Figs. 5(A1) and (B1)) are adjusted by the timing adjustment circuits 160U and 160D as shown in Figs. 5(A2) and (B2). As a result, the differences that occur in the rise time and fall time between the output signal SIGA and the output signal SIGB (Fig. 5(C1)) are corrected as shown in Fig. 5(C2). As a result, the common mode noise that has occurred (Fig. 5(D1)) is suppressed as shown in Fig. 5(D2).

[0027] Fig. 6 shows an example of the transition state of the signal levels of each part of the transmission device shown in Fig. 4.

[0028] In Fig. 6, the driver driving capabilities of the output circuits 101A and 101B of the driver circuit 150 are set to 50 Ω, and resistor elements Ra and Rb of 50 Ω are connected as termination resistors to the respective transmission lines of the plurality of output signals SIGA and SIGB to show the transition state of the signal levels of each part. The output level of the pre-driver circuit 140 is set from 0 V (Low level) to 1 V (High level), and the power supply voltage VDDH of the MOS transistor M1 of the driver circuit 150 is set to 0.4 V. One end of the load capacitor Ca is connected between the resistor elements Ra and Rb.

[0029] Fig. 7 shows an example of the operation timings of a plurality of input / output signals in the driver circuit 150 shown in Fig. 6. Fig. 7(A) shows the operation timings of the driver input signal UIN_A input to the MOS transistor M1 and the driver input signal DIN_A input to the MOS transistor M2 in the output circuit 101A of the driver circuit 150. Fig. 7(B) shows the operation timings of the driver input signal UIN_B input to the MOS transistor M1 and the driver input signal DIN_B input to the MOS transistor M2 in the output circuit 101B of the driver circuit 150. Fig. 7(C) shows the operation timings of the output signal SIGA and the output signal SIGB.

[0030] For example, in FIG. 7, when the transition state of the signal is transition (2), the driver input signal UIN_A and the driver input signal DIN_B transition from the Low level (0V) to the High level (1V). At the same time, when it is transition (2), the driver input signal UIN_B and the driver input signal DIN_A transition from the High level to the Low level. When it is this transition (2), the output signal SIGA transitions from the Low level (0.1V) to the High level (0.3V), and the output signal SIGB transitions from the High level (0.3V) to the Low level (0.1V).

[0031] Strictly speaking, even during the transition of each driver input signal, the plurality of output signals SIGA and SIGB transition. However, due to the influence of the parasitic capacitance held by each MOS transistor in the driver circuit 150 and the wiring capacitance held by the wiring after each MOS transistor, the plurality of output signals SIGA and SIGB cannot make an immediate and steep transition. Therefore, in FIG. 7, immediately after the transition of each driver input signal, the operation timing at which the plurality of output signals SIGA and SIGB transition is schematically shown.

[0032] FIG. 8 shows an example of the gate-source voltage Vgs and the drain-source voltage Vds of the MOS transistors M1 and M2 in the on state in the driver circuit 150 in each transition state shown in FIG. 7.

[0033] As shown in FIG. 8, whether it is transition (1) or transition (2), at the time of transition, the gate-source voltage Vgs and the drain-source voltage Vds of each of the MOS transistors M1 and M2 do not change. Therefore, if, hypothetically, a difference occurs between the rising driver driving ability and the falling driver driving ability in the driver circuit 150 described above, or a timing difference occurs between the plurality of driver input signals, when performing timing adjustment by the timing adjustment circuits 160U and 160D, the timing setting signals T_D and T_U in FIG. 6 may only be set to a certain set value.

[0034] FIG. 9 shows a configuration example of a transmission device according to a comparative example that outputs a four-valued differential signal. The transmission device according to the comparative example shown in FIG. 9 schematically shows an example of a circuit that outputs a four-valued differential signal, which is used in, for example, PAM4 (Pulse Amplitude Modulation 4) or MIPI (Mobile Industry Processor Interface) C-PHY.

[0035] The transmission device according to this comparative example outputs a plurality of output signals SIGA, SIGB, and SIGC that have different signal levels from each other and constitute a four-valued differential signal. The transmission device according to the comparative example includes a driver circuit 50 and a pre-driver circuit 40 arranged in front of the driver circuit 50. The pre-driver circuit 40 and the driver circuit 50 constitute an output circuit 1A that outputs the output signal SIGA, an output circuit 1B that outputs the output signal SIGB, and an output circuit 1C that outputs the output signal SIGC.

[0036] The pre-driver circuit 40 in the output circuit 1A includes a High-level circuit 41A1, a Mid (middle)-level circuit 41A2, and a Low-level circuit 41A3. The pre-driver circuit 40 in the output circuit 1B includes a High-level circuit 41B1, a Mid-level circuit 41B2, and a Low-level circuit 41B3. The pre-driver circuit 40 in the output circuit 1C includes a High-level circuit 41C1, a Mid-level circuit 41C2, and a Low-level circuit 41C3.

[0037] The driver circuit 50 in the output circuit 1A includes a High-level MOS transistor M_A1 and a resistor element R_A1, a Mid-level MOS transistor M_A2 and a resistor element R_A2, and a Low-level MOS transistor M_A3 and a resistor element R_A3. A driver input signal A_up is input to the MOS transistor M_A1. A driver input signal A_mid is input to the MOS transistor M_A2. A driver input signal A_dn is input to the MOS transistor M_A3.

[0038] The driver circuit 50 in the output circuit 1B includes the MOS transistor M_B1 and the resistor element R_B1 for High level, the MOS transistor M_B2 and the resistor element R_B2 for Mid level, and the MOS transistor M_B3 and the resistor element R_B3 for Low level. The driver input signal B_up is input to the MOS transistor M_B1. The driver input signal B_mid is input to the MOS transistor M_B2. The driver input signal B_dn is input to the MOS transistor M_B3.

[0039] The driver circuit 50 in the output circuit 1C includes the MOS transistor M_C1 and the resistor element R_C1 for High level, the MOS transistor M_C2 and the resistor element R_C2 for Mid level, and the MOS transistor M_C3 and the resistor element R_C3 for Low level. The driver input signal C_up is input to the MOS transistor M_C1. The driver input signal C_mid is input to the MOS transistor M_C2. The driver input signal C_dn is input to the MOS transistor M_C3.

[0040] FIG. 10 is a timing chart showing an example of the operation timing of a plurality of output signals SIGA, SIGB, and SIGC output from the driver circuit 50 of the transmission device shown in FIG. 9.

[0041] In the transmission device according to the comparative example shown in FIG. 9, when any one of the plurality of output signals SIGA, SIGB, and SIGC is output, any one of the driver input signals *_up, *_mid, and *_dn becomes High level to drive the driver circuit 50. Here, *_up indicates any one of the driver input signals A_up, B_up, and C_up. *_mid indicates any one of the driver input signals A_mid, B_mid, and C_mid. *_dn indicates any one of the driver input signals A_dn, B_dn, and C_dn.

[0042] As the plurality of output signals SIGA, SIGB, and SIGC, when outputting a High level, the driver input signal *_up becomes High level, when outputting a Mid level, the driver input signal *_mid becomes High level, and when outputting a Low level, the driver input signal *_dn becomes High level.

[0043] In FIG. 9, each MOS transistor in the driver circuit 50 is an N-ch MOSFET. In FIG. 9, as an example, the power supply voltage connected to the MOS transistors M_A1, M_B1, and M_C1 for High level is set to 0.4V, and the power supply voltage connected to the MOS transistors M_A2, M_B2, and M_C2 for Mid level is set to 0.2V. Also, the driver driving ability of each of the output circuits 1A, 1B, and 1C of the driver circuit 50 is set to 50Ω, and one end of the resistance elements Ra, Rb, and Rc of 50Ω resistors as termination resistors is connected to each output terminal of the plurality of output signals SIGA, SIGB, and SIGC. The other ends of the resistance elements Ra, Rb, and Rc are commonly connected, and one end of the load capacitor Ca is connected.

[0044] With such a configuration, as shown in FIG. 10, it becomes possible to output the plurality of output signals SIGA, SIGB, and SIGC with a High level of 0.3V, a Mid level of 0.2V, and a Low level of 0.1V.

[0045] As shown in FIG. 10, according to the signal levels that each of the plurality of output signals SIGA, SIGB, and SIGC output from the driver circuit 50 can take, there are a plurality of transition states. The types of transitions include transitions (1), (2), (3), (4), and (5), and the states of the signal levels after the transitions are also five types: states (1), (2), (3), (4), and (5). In FIG. 10, the plurality of output signals SIGA, SIGB, and SIGC are arranged from top to bottom in this order, but even if the order of each output signal is changed, the transition states of the signal levels are all covered by this.

[0046] Strictly speaking, even during the transition of each driver input signal, the multiple output signals SIGA, SIGB, and SIGC transition. However, due to the influence of the parasitic capacitance held by each MOS transistor in the driver circuit 50 and the wiring capacitance held by the wiring after each MOS transistor, the multiple output signals SIGA, SIGB, and SIGC cannot immediately make a steep transition. Therefore, in FIG. 10, the operation timing at which the multiple output signals SIGA, SIGB, and SIGC are transitioning immediately after the transition of each driver input signal is schematically shown.

[0047] FIG. 11 shows an example of the differential signal levels of the differential signals output from the transmission device shown in FIG. 9. In FIG. 11, the differential signal levels in the states (1), (2), (3), (4), and (5) of FIG. 10 are shown. Here, A represents the output signal SIGA, B represents the output signal SIGB, and C represents the output signal SIGC. The differential signals are of three types: (SIGA - SIGB), (SIGB - SIGC), and (SIGC - SIGA), and in each state, they show four values such as -0.1V / 0.1V / -0.2V / 0.2V. That is, the transmission device according to the comparative example in FIG. 9 outputs a four - value differential signal.

[0048] FIG. 12 is a circuit diagram showing an example of the transition state of the signal levels of the driver input signals in the transmission device shown in FIG. 9. Note that FIG. 12 shows an example in the case where the transition state is the transition (1) shown in FIG. 10. The output level of the pre - driver circuit 40 is such that the Low level is 0V and the High level is 1V.

[0049] FIG. 13 shows an example of the gate - source voltage Vgs and the drain - source voltage Vds of the MOS transistor M_* in the on state of the driver circuit 50 in each of the transition states (1), (2), (3), (4), and (5) shown in FIG. 10. Here, M_* represents an arbitrary MOS transistor in the driver circuit 50.

[0050] First, pay attention to the case where the signal level transitions to the Mid level. When comparing the output signal SIGA of transition (1) with the output signal SIGB of transition (3), it can be seen that when outputting a signal at the Mid level, the gate-source voltage Vgs applied to the MOS transistor M_* is different.

[0051] Next, pay attention to the case where the signal level transitions to the High level. When comparing the output signal SIGA of transition (4) with the output signal SIGB of transition (1), it can be seen that when outputting a signal at the High level, the gate-source voltage Vgs and the drain-source voltage Vds applied to the MOS transistor M_* are different.

[0052] Finally, pay attention to the case where the signal level transitions to the Low level. When comparing the output signal SIGA of transition (3) with the output signal SIGB of transition (2), it can be seen that when outputting a signal at the Low level, the drain-source voltage Vds applied to the MOS transistor M_* is different.

[0053] FIG. 14 shows a configuration example in which a timing adjustment circuit is arranged in front of the pre-driver circuit 40 in the transmission device according to the comparative example shown in FIG. 9.

[0054] The transmission device according to the comparative example shown in FIG. 14 is of the same concept as the configuration example (FIG. 4) in which timing adjustment circuits 160U and 160D are arranged in front of the pre-driver circuit 140 in the transmission device according to the comparative example that outputs a binary differential signal.

[0055] In the transmission device according to the comparative example shown in FIG. 14, a timing adjustment circuit 60A1 is arranged in front of the High-level circuit 41A1 in the pre-driver circuit 40, a timing adjustment circuit 60A2 is arranged in front of the Mid-level circuit 41A2, and a timing adjustment circuit 60A3 is arranged in front of the Low-level circuit 41A3.

[0056] Also, a timing adjustment circuit 60B1 is arranged in front of the High level circuit 41B1 in the pre-driver circuit 40, a timing adjustment circuit 60B2 is arranged in front of the Mid level circuit 41B2, and a timing adjustment circuit 60B3 is arranged in front of the Low level circuit 41B3.

[0057] Also, a timing adjustment circuit 60C1 is arranged in front of the High level circuit 41C1 in the pre-driver circuit 40, a timing adjustment circuit 60C2 is arranged in front of the Mid level circuit 41C2, and a timing adjustment circuit 60C3 is arranged in front of the Low level circuit 41C3.

[0058] Hereinafter, any one or any plurality of the plurality of timing adjustment circuits 60A1, 60A2, 60A3, 60B1, 60B2, 60B3, 60C1, 60C2, 60C3 are collectively referred to as the timing adjustment circuit 60.

[0059] The timing adjustment circuit 60 is composed of, for example, a delay element and a circuit for selecting a signal delayed by the delay element. Examples of the delay element include a CMOS inverter and a capacitive element. The timing adjustment circuits 60A1, 60B1, 60C1 operate based on the set value of the input timing setting signal T_up. The timing adjustment circuits 60A2, 60B2, 60C2 operate based on the set value of the input timing setting signal T_mid. The timing adjustment circuits 60A3, 60B3, 60C3 operate based on the set value of the input timing setting signal T_dn.

[0060] If there is a difference between the rising driver driving ability and the falling driver driving ability in the driver circuit 50, or if a timing difference occurs between a plurality of driver input signals, the timing adjustment circuit 60 can reduce the common mode noise of the differential signal output by adjusting the input timing of the driver input signal. In that case, appropriate setting values are given to the timing setting signals T_dn, T_mid, and T_up to adjust the operation timing and reduce the common mode noise.

[0061] As described above, in the case of the driver circuit 150 that outputs a binary differential signal, when the signal level transitions, since the gate-source voltage Vgs and the drain-source voltage Vds of each of the MOS transistors that output the High level and the MOS transistor that outputs the Low level do not change in the signal level transition state, the setting values of the timing setting signals T_U and T_D can be set to constant values to adjust the timing.

[0062] However, in the case of the driver circuit 50 that outputs a quaternary differential signal, it is difficult to reduce the common mode noise even if timing adjustment is performed by the same method as in the binary case. Depending on the signal level transition state, the drain-source voltage Vds and the gate-source voltage Vgs applied to each MOS transistor of the driver circuit 50 are different. The fact that the gate-source voltage Vgs and the drain-source voltage Vds are different means that the signal level transition speed of the signal output from the driver circuit 50 is different. Therefore, for example, in the transition (1) of FIG. 10, the speed at which the signal level of the output signal SIGA transitions to the Mid level (0.2V) is different from the speed at which the signal level of the output signal SIGB transitions to the Mid level (0.2V) in the transition (3).

[0063] In the above-described timing adjustment method, regardless of the transition state of the signal level, since the set values of the timing setting signals T_dn, T_mid, and T_up are constant values, a timing difference occurs between a plurality of output signals in this way. As a result, it becomes difficult to reduce common-mode noise using this adjustment circuit.

[0064] FIG. 15 is a timing chart showing an example of the operation timing of a plurality of input / output signals in the driver circuit 50 and the generation timing of common-mode noise when timing adjustment is performed by the timing adjustment circuit 60 in the transmission apparatus according to the comparative example shown in FIG. 14. FIG. 15(A) shows the operation timing of the driver input signal A_up input to the MOS transistor M_A1 in the output circuit 1A of the driver circuit 50 and the driver input signal A_mid input to the MOS transistor M_A2. FIG. 15(B) shows the operation timing of the driver input signal B_up input to the MOS transistor M_B1 in the output circuit 1B of the driver circuit 50 and the driver input signal B_mid input to the MOS transistor M_B2. FIG. 15(C) shows the operation timing of each of the plurality of output signals SIGA, SIGB, and SIGC. FIG. 15(D) shows the generation timing of common-mode noise.

[0065] FIG. 15 shows a case where the timing is adjusted so that the common-mode noise in the transition (1) is minimized. After the timing adjustment, the transition time from when the signal level of the driver input signal of the MOS transistor that outputs the Mid level changes until immediately before the signal levels between the plurality of output signals change is defined as T_mid_rise. In this case, in the transitions (1) and (3), the transition time T_mid_rise is the same for both. As shown in FIG. 13, since the gate-source voltage Vgs applied to the MOS transistor M_A2 that outputs the Mid level in the transition (3) is 0.1 V higher than that of the MOS transistor M_B2 that outputs the Mid level in the transition (1), its transition speed is also faster. For this reason, common-mode noise occurs in the transition (3).

[0066] In the configuration example of FIG. 14, as shown in FIGS. 10 to 13, the signal levels of the plurality of output signals SIGA, SIGB, and SIGC are three types: Low level (0.1V), Mid level (0.2V), and High level (0.3V). And the driver input signal when turning on each MOS transistor of the driver circuit 50 is 1V.

[0067] When transitioning any of the signal levels of the plurality of output signals SIGA, SIGB, and SIGC to the Mid level, since the original signal level is either the Low level (0.1V) or the High level (0.3V), there are two ways to apply the gate-source voltage Vgs for driving the Mid level, which are 1V - 0.1V = 0.9V or 1V - 0.2V = 0.8V. Here, the reason why it is 1V - 0.2V and not 1V - 0.3V is that the power supply voltage of the MOS transistor at the Mid level = 0.2V is smaller than 0.3V, and the 0.2V side becomes the source.

[0068] In the case of the driver circuit 150 that outputs the binary differential signal shown in FIG. 6, such a phenomenon does not occur. Since the output signal levels are two types: Low level (0.1V) and High level (0.3V), when the driver input signal for turning on the MOS transistor is 1V, when transitioning to the Low level, Vgs = 1V - 0V = 1.0V, and when transitioning to the High level, Vgs = 1V - 0.1V = 0.9V, and there are only two types. Here, the reason why Vgs is not 1V - 0.3V when transitioning to the Low level is that when transitioning to the Low level, the source of the MOS transistor becomes the GND level.

[0069] Thus, when there are three or more states of the signal levels of the plurality of output signals SIGA, SIGB, and SIGC, even when transitioning to the same signal level, the gate-source voltage Vgs applied to the MOS transistor will be different due to the difference in the state of the previous signal level.

[0070] <1. First Embodiment> [1.1 Configuration Example and Operation Example of Transmission Device] First, a configuration example and an operation example of a transmission device according to the first embodiment of the present disclosure will be described. Hereinafter, for parts that are substantially the same as the components of the transmission device according to the above comparative example, the same reference numerals will be given, and the description will be omitted as appropriate.

[0071] FIG. 16 shows an overall configuration example of a transmission device according to the first embodiment of the present disclosure.

[0072] The transmission device according to the first embodiment includes a signal generation unit 15, a flip-flop (F / F) 16, an output unit 30A, and a plurality of output terminals ToutA, ToutB, and ToutC.

[0073] The transmission device transmits a plurality of symbols CS as transmission data using a plurality of output signals SIGA, SIGB, and SIGC that constitute a differential signal. The plurality of output signals SIGA, SIGB, and SIGC are respectively output from the plurality of output terminals ToutA, ToutB, and ToutC.

[0074] The signal generation unit 15 obtains a symbol NS based on the symbol CS, a plurality of signals TxF, TxR, TxP, and a clock signal CLK. The symbol CS is the currently transmitted symbol (current symbol), and the symbol NS is the next symbol to be transmitted (next symbol).

[0075] The flip-flop 16 delays the signal S1 by one clock of the clock signal CLK and outputs it as a 3-bit signal S2. That is, the flip-flop 16 generates the current symbol CS by delaying the next symbol NS indicated by the signal S1 by one clock of the clock signal CLK. Then, the flip-flop 16 supplies the signal S2 to the signal generation unit 15 and the output unit 30A.

[0076] The output unit 30A generates a plurality of output signals SIGA, SIGB, and SIGC based on the signal S2. The operation of the output unit 30A is controlled by the control signal IT1.

[0077] The control signal IT1 includes timing setting signals T_i_up, T_i_mid, and T_i_dn, which will be described later. The signal S2 includes a plurality of input data DinA, DinB, and DinC, which will be described later.

[0078] FIG. 17 shows a configuration example of a main part of the transmission device according to the first embodiment.

[0079] FIG. 17 shows a configuration example of the output unit 30A as a main part of the transmission device shown in FIG. 16. The configuration example shown in FIG. 17 is a configuration in which a synchronization circuit 61 and a state determination circuit 63 are added as control circuits for controlling the setting values of a plurality of timing adjustment signals T_up, T_mid, and T_dn with respect to the circuit configuration of the transmission device according to the comparative example of FIG. 14. In FIG. 17, the configuration after the pre-driver circuit 40 is omitted, but the configuration after the pre-driver circuit 40 is the same as that in FIG. 14. A driver circuit 50 is connected to the subsequent stage of the pre-driver circuit 40, and a plurality of output signals SIGA, SIGB, and SIGC are output from the driver circuit 50.

[0080] The synchronization circuit 61 and the state determination circuit 63 are control circuits that change the setting values of the timing setting signals T_up, T_mid, and T_dn to values corresponding to a plurality of transition states of signal levels that each of the plurality of output signals SIGA, SIGB, and SIGC output from the driver circuit 50 can take. The plurality of transition states mentioned here refer to, for example, the transitions (1), (2), (3), (4), and (5) shown in FIG. 10 described above.

[0081] The synchronization circuit 61 has a plurality of first synchronization circuits 61A, 61B, and 61C and a plurality of second synchronization circuits 62A, 62B, and 62C.

[0082] The plurality of first synchronization circuits 61A, 61B, and 61C each delay each of the plurality of first input signals based on the clock signal CLK and output a plurality of second input signals. Here, as shown in FIG. 17, the plurality of first input signals are the plurality of input data DinA, DinB, and DinC. Also, as shown in FIG. 17, the plurality of second input signals are the plurality of output signals Dout1A, Dout1B, and Dout1C.

[0083] The plurality of second synchronization circuits 62A, 62B, and 62C each delay each of the plurality of second input signals based on the clock signal CLK and output a third input signal to each of the plurality of timing adjustment circuits 60. Here, as shown in FIG. 17, the plurality of third input signals are the plurality of output signals Dout2A, Dout2B, and Dout2C.

[0084] The state determination circuit 63 changes the set values of the plurality of timing setting signals T_up, T_mid, and T_dn to values corresponding to the plurality of transition states based on the plurality of first input signals (DinA, DinB, DinC) corresponding to the plurality of output signals SIGA, SIGB, and SIGC and the plurality of second input signals (Dout1A, Dout1B, Dout1C) obtained by delaying the plurality of first input signals.

[0085] (Configuration example of the synchronization circuit 61) FIG. 18 shows a specific configuration example of the synchronization circuit 61 shown in FIG. 17.

[0086] FIG. 18 shows a configuration example of the first synchronization circuit 61A and the second synchronization circuit 62A corresponding to the output signal SIGA. Note that the first synchronization circuit 61B and the second synchronization circuit 62B corresponding to the output signal SIGB, and the first synchronization circuit 61C and the second synchronization circuit 62C corresponding to the output signal SIGC may have the same configuration.

[0087] The configuration example shown in FIG. 18 is an example using a D-FlipFlop as the synchronization circuit 61. In a D-FlipFlop, by synchronizing the input signal with the clock signal CLK, an output signal synchronized with the clock signal CLK can be obtained. Here, two stages of D-FlipFlops are connected. The first-stage D-FlipFlop corresponds to the first synchronization circuit 61A, and the second-stage D-FlipFlop corresponds to the second synchronization circuit 62A.

[0088] FIG. 19 is a timing chart showing an example of the output timing of signals in the configuration example of the synchronization circuit 61 shown in FIG. 18.

[0089] As shown in FIG. 19, the first synchronization circuit 61A outputs an output signal Dout1A that delays the input data DinA by synchronizing the input data DinA with the clock signal CLK. The second synchronization circuit 62A outputs an output signal Dout2A that delays the output signal Dout1A by synchronizing the output signal Dout1A from the first synchronization circuit 61A with the clock signal CLK.

[0090] (Configuration example of the state determination circuit 63) FIG. 20 shows a specific configuration example of the state determination circuit 63 shown in FIG. 17.

[0091] The state determination circuit 63 includes a matching circuit 64 and an addition / subtraction circuit 65. The state determination circuit 63 is a circuit that changes the signal output from the state determination circuit 63 according to the logical state of the signal input to the state determination circuit 63. The input signals of the state determination circuit 63 are the signal group Sx, the signal group Sy, and a plurality of timing setting signals T_i_dn, T_i_up, T_i_mid. The output signals of the state determination circuit 63 are the timing setting signals T_dn, T_up, T_mid. As shown in FIG. 17, the signal group Sx includes a plurality of input data DinA, DinB, DinC input to the first synchronization circuits 61A, 61B, 61C. As shown in FIG. 17, the signal group Sy includes a plurality of output signals Dout1A, Dout1B, Dout1C output from the first synchronization circuits 61A, 61B, 61C.

[0092] The plurality of timing setting signals T_i_dn, T_i_up, and T_i_mid each have a fixed set value that serves as the basis for timing setting. For example, if each signal is 3 bits, then T_i_dn<2:0>=3’b011 and so on.

[0093] The signals input to the matching circuit 64 are the signal group Sx and the signal group Sy. This matching circuit 64 performs a specific output when the signal group Sx and the signal group Sy match a specific logical state. The specific logic corresponds to the logic of states (1) to (5) shown in FIG. 10 described above. An example of the circuit of the matching circuit 64 is a decode circuit. The output of the matching circuit 64 may be 1 bit or may have a large number of bits.

[0094] The addition / subtraction circuit 65 receives the output of the matching circuit 64 and adds or subtracts the respective values of the plurality of timing setting signals T_i_dn, T_i_up, and T_i_mid according to the above-described logical state. The plurality of timing setting signals T_up, T_mid, and T_dn after this addition or subtraction are taken as the output of the addition / subtraction circuit 65. For example, when the addition / subtraction is "1" and subtracting T_i_dn<2:0>=3’b011, the addition / subtraction circuit 65 outputs T_dn<2:0>=3’b010, and when adding, it outputs T_dn=3’b100.

[0095] Depending on the logical state of the output of the matching circuit 64, the addition / subtraction number may be an integer larger than "1". Regarding the specific value of this addition / subtraction number, a set value derived in advance by circuit simulation or the like that can optimize the common mode noise may be used, or later, the addition / subtraction value may be made changeable with a register, and the addition / subtraction value that minimizes the common mode noise may be derived by actual machine measurement.

[0096] The plurality of timing setting signals \(T_{i\_dn}\), \(T_{i\_up}\), \(T_{i\_mid}\) input to the state determination circuit 63 are each subjected to appropriate addition and subtraction according to the states of the signal group \(Sx\) and the signal group \(Sy\). Finally, the state determination circuit 63 outputs a plurality of timing setting signals \(T_{dn}\), \(T_{up}\), \(T_{mid}\) having optimal timing settings corresponding to the five transition states shown in FIG. 10.

[0097] The circuit configurations shown in FIGS. 17 and 20 are merely examples. Any other configuration may be adopted as long as it is a circuit that determines the transition states of the plurality of output signals \(SIGA\), \(SIGB\), \(SIGC\) and dynamically changes to a desired setting from the existing timing settings according to this state.

[0098] FIG. 21 is a timing chart showing a series of operation flows from when input data is given to the transmission device shown in FIG. 17 until a plurality of output signals \(SIGA\), \(SIGB\), \(SIGC\) whose transition state becomes transition (1) (see FIG. 10) are output from the driver circuit 50. FIG. 22 is a timing chart showing a series of operation flows from when input data is given to the transmission device shown in FIG. 17 until a plurality of output signals \(SIGA\), \(SIGB\), \(SIGC\) whose transition state becomes transition (3) (see FIG. 10) are output from the driver circuit. In FIGS. 21 and 22, only the timing setting signals \(T_{i\_mid}\), \(T_{mid}\) for the Mid level are illustrated for the timing setting signals.

[0099] In FIGS. 21 and 22, the input data \(DinA\), \(DinB\), \(DinC\) each have a bit width of 3 bits. These 3 bits correspond to signals of High level, Mid level, and Low level driven by the driver circuit 50 from the upper bit to the lower bit.

[0100] A plurality of timing setting signals T_mid, T_up, T_dn indicating the setting values of the timing adjustment circuit 60 must each determine the setting value before the transitions of the plurality of output signals SIGA, SIGB, SIGC from the driver circuit 50 are completed. To satisfy such timing constraints, in some cases, a delay circuit may be arranged at an appropriate position in the signal path after the synchronization circuit 61, for example. As the delay circuit, for example, one that intentionally delays a signal, such as an inverter chain, may be used.

[0101] The setting value of each of the plurality of timing setting signals T_mid, T_up, T_dn is set so that the common mode noise is minimized in each transition state of the transitions (1) to (5) shown in FIG. 10. That is, the setting value of each of the plurality of timing setting signals T_mid, T_up, T_dn is a setting value that sets the input timing of each of the plurality of driver input signals to the driver circuit 50 such that the common mode noise caused by the plurality of output signals SIGA, SIGB, SIGC can be minimized.

[0102] For example, when driving the output signal SIGA to the Mid level in transition (1), the setting of the timing adjustment circuit 60 that determines the operation timing of the driver input signal A_mid is T_mid<2:0>=3’b011 as shown in FIG. 21. On the other hand, when driving the output signal SIGB to the Mid level in transition (3), the setting of the timing adjustment circuit 60 that determines the operation timing of the driver input signal B_mid is T_mid<2:0>=3’b010 as shown in FIG. 22.

[0103] In this way, the technology of the present disclosure sets the optimal input timing of the driver input signal according to the transition state for each of the plurality of output signals SIGA, SIGB, SIGC from the driver circuit 50, even if the signal levels to be transitioned are the same. Therefore, the technology of the present disclosure changes the timing setting dynamically rather than to a fixed value. In this way, the common mode noise in each transition state is minimized.

[0104] (Configuration example of the timing adjustment circuit 60) FIG. 23 shows a specific configuration example of the timing adjustment circuit 60 shown in FIG. 17.

[0105] The timing adjustment circuit 60 appropriately delays the output data from the input data according to its timing setting. For example, it is composed of an inverter delay circuit 71 and a 1 / 8 select circuit 72.

[0106] The inverter delay circuit 71 is a delay circuit that generates a plurality of delayed signals obtained by delaying a signal corresponding to the driver input signal. The inverter delay circuit 71 has a configuration in which a plurality of inverters INV1 and INV2 are connected in a chain. One end of each of a plurality of load capacitors C1 and C2 is connected to each of the plurality of inverters INV1 and INV2. The plurality of inverters INV1 and INV2 are each composed of MOS transistors.

[0107] The 1 / 8 select circuit 72 is a select circuit that selects one of the plurality of delayed signals from the inverter delay circuit 71 based on the timing setting signal and outputs it as the driver input signal.

[0108] By adjusting the size of the MOS transistors used in the plurality of inverters INV1 and INV2 that make up the inverter delay circuit 71, or the magnitude of each of the plurality of load capacitors C1 and C2 connected to the plurality of inverters INV1 and INV2, the processing delay of the inverter delay circuit 71 can be controlled. By any of these means, a timing adjustment circuit 60 capable of controlling the delay amount can be configured. A plurality of delayed signals from the inverter delay circuit 71 can be selected by the 1 / 8 select circuit 72, and a signal with an appropriate delay amount can be selected.

[0109] FIG. 24 is a timing chart showing an example of the operation timing of the timing adjustment circuit 60 shown in FIG. 23.

[0110] The timing chart of FIG. 24 shows an example of the operation timing when using timing setting signals each having a bit width of 3 bits as a plurality of timing setting signals T_up, T_mid, and T_dn. As an example, for each of the plurality of timing setting signals T_up, T_mid, and T_dn, the operation timing in the case where the delay is the shortest, the case where the delay is the longest, and the case approximately in the middle thereof is shown.

[0111] FIG. 25 shows a modified example of the timing adjustment circuit 60.

[0112] Each of the plurality of timing setting signals T_up, T_mid, and T_dn may include a rising-edge timing setting signal T_set_rise and a falling-edge timing setting signal T_set_fall. Each of the plurality of timing adjustment circuits 60 may be able to adjust the rising-edge timing and the falling-edge timing of each of the plurality of driver input signals based on the rising-edge timing setting signal T_set_rise and the falling-edge timing setting signal T_set_fall. The synchronization circuit 61 and the state determination circuit 63 as control circuits may change the setting values of the rising-edge timing setting signal T_set_rise and the falling-edge timing setting signal T_set_fall to values corresponding to a plurality of transition states.

[0113] When the timing adjustment circuit 60 is provided with a function of adjusting the rising-edge timing and the falling-edge timing, the configuration as shown in FIG. 25 may be adopted. In FIG. 25, the falling-edge timing setting signal T_set_fall and the rising-edge timing setting signal T_set_rise are each a signal having a bit width of 8 bits as an example.

[0114] In the configuration shown in FIG. 25, in order to adjust the fall timing, there are a plurality of MOS transistors Mp1, Mp2, Mp3, Mp4, Mp5, Mp6, Mp7, Mp8 each consisting of a P-ch MOSFET. Also, in order to adjust the rise timing, there are a plurality of MOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, Mn7, Mn8 each consisting of an N-ch MOSFET. Since the fall timing setting signal T_set_fall and the rise timing setting signal T_set_rise are each 8-bit signals, 8 P-ch MOSFETs and 8 N-ch MOSFETs are each used. Among the plurality of MOS transistors Mp1, Mp2, Mp3, Mp4, Mp5, Mp6, Mp7, Mp8 and the plurality of MOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, Mn7, Mn8, one or more are in the on state at any timing setting. By changing the size of the MOSFET according to the fall timing setting signal T_set_fall and the rise timing setting signal T_set_rise, the processing delay of the inverters INV1 and INV2 can be controlled, and the rise timing and fall timing of the signal can be controlled individually. At this time, either a plurality of MOSFETs may be in the on state or only one may be in the on state. It is important here to adjust the size of the MOSFET in the on state according to the fall timing setting signal T_set_fall and the rise timing setting signal T_set_rise.

[0115] (Common mode noise simulation) FIG. 26 is a timing chart showing an example of the result of simulating the operation timings of a plurality of output signals SIGA, SIGB, and SIGC from driver circuit 50 and the generation timing of common-mode noise before the timing adjustment by timing adjustment circuit 60 in the transmission apparatus according to the first embodiment. FIG. 27 is a timing chart showing an example of the result of simulating the operation timings of a plurality of output signals SIGA, SIGB, and SIGC from driver circuit 50 and the generation timing of common-mode noise after the timing adjustment by timing adjustment circuit 60 in the transmission apparatus according to the first embodiment. In FIGS. 26 and 27, the upper row shows the operation timings of the plurality of output signals SIGA, SIGB, and SIGC, and the lower row shows the generation timing of common-mode noise.

[0116] FIG. 26 shows the simulation result when the input timing of each of the plurality of driver input signals is set to a constant value regardless of the transition states of the plurality of output signals SIGA, SIGB, and SIGC. FIG. 27 shows the simulation result in which the set values of the input timings of the plurality of driver input signals are dynamically varied according to the transition states of the plurality of output signals SIGA, SIGB, and SIGC to optimize the input timing. It was confirmed that the common-mode noise can be reduced to less than half in the optimized case (FIG. 27) compared to the case where the input timing was not optimized (FIG. 26).

[0117] [1.2 Application Examples to Electronic Devices] (Application Example 1) FIG. 28 shows an application example of the transmission apparatus according to the first embodiment to an electronic device. FIG. 28 shows a configuration example of an electronic device system 80 having a wireless function as an example of an electronic device.

[0118] The electronic device system 80 includes a transmission device 82, a reception device 83, and an antenna 91. The transmission device 82 and the reception device 83 are connected by a differential signal transmission line 84 that transmits a differential signal between the transmission device 82 and the reception device 83, and a control signal transmission line 85 that transmits a control signal from the reception device 83 to the transmission device 82. The reception device 83 and the antenna 91 are connected by an antenna reception signal wiring 86 and a cable, connector, etc. 87.

[0119] The transmission device 82, the reception device 83, the differential signal transmission line 84, the control signal transmission line 85, and the antenna reception signal wiring 86 are formed on a mother board 81.

[0120] The antenna 91 receives a radio signal and outputs it as a reception signal to the reception device 83. The transmission device 82 transmits a differential signal. The reception device 83 receives the differential signal transmitted from the transmission device 82 and the reception signal from the antenna 91. The transmission device 82 has a circuit CHIP A as a circuit that transmits a differential signal. The reception device 83 has a circuit CHIP B as a circuit that receives a differential signal. In the circuit CHIP A, the circuit of the transmission device according to the above-described first embodiment is formed.

[0121] In the electronic device system 80, due to the common-mode noise of the differential signal transmitted from the circuit CHIP A of the transmission device 82, the radiation noise radiated from the differential signal transmission line 84 becomes EMI and couples to the antenna 91. Since the antenna 91 receives the radio wave of a weak external radio signal, if the EMI from the differential signal transmission line 84 couples, it becomes difficult to receive the external radio wave. That is, the radio sensitivity deteriorates.

[0122] By applying the technology of the transmission device according to the above-described first embodiment to the electronic device system 80, the above-described problem can be solved.

[0123] The receiving device 83 transmits, via the control signal transmission line 85, a timing control signal for controlling the set value of the above-described timing setting signal in the transmitting device 82 so that the state of the reception signal from the antenna 91 becomes a desired state. The receiving device 83 generates a timing control signal based on the level of the antenna coupling noise generated by the radiation noise radiated from the transmission line 85 coupling to the antenna 91, or the state (such as magnitude) of the radio sensitivity of the antenna 91.

[0124] In the transmitting device 82, based on the timing control signal from the receiving device 83, the set value of the timing setting signal of the timing adjustment circuit 60 for suppressing common mode noise is changed. The timing setting signal referred to here is the plurality of timing setting signals T_i_dn, T_i_mid, T_i_up shown in FIG. 17.

[0125] After the timing setting of the timing adjustment circuit 60 is changed in the transmitting device 82, again, the receiving device 83 determines the level of the antenna coupling noise or the state of the radio sensitivity of the antenna 91. Every time the timing setting of the timing adjustment circuit 60 is changed in the transmitting device 82 in this way, the receiving device 83 makes the above determination and derives the set value of the timing setting that optimizes the state of the reception signal from the antenna 91. Then, finally, the transmitting device 82 is made to apply this optimal setting according to the command indicated by the timing control signal from the receiving device 83.

[0126] FIG. 29 is a flowchart showing an example of the operation of controlling the set value of the timing setting signal of the transmitting device 82 in the electronic device according to the first embodiment.

[0127] First, common mode noise is emitted from the transmitting device 82 (step S11). Next, EMI is radiated from the differential signal transmission line 84 and coupled to the antenna 91 (step S12). Next, the receiving device 83 determines the state of the antenna coupling noise (or radio sensitivity degradation) (step S13).

[0128] Next, the receiving device 83 determines whether the antenna coupling noise is minimized or whether the wireless sensitivity degradation is minimized (step S14). If it is determined that the antenna coupling noise is not minimized or the wireless sensitivity degradation is not minimized (step S14; N), the receiving device 83 controls to change the timing setting of the transmitting device 82 by transmitting a timing control signal to the transmitting device 82 (step S15), and returns to the process of step S11. If it is determined that the antenna coupling noise is minimized or the wireless sensitivity degradation is minimized (step S14; Y), the receiving device 83 transmits a timing control signal to the transmitting device 82 to set the minimum setting to the transmitting device 82 (step S16), and ends the process.

[0129] By applying the technology of the transmitting device according to the above-described first embodiment to the electronic device system 80 as described above, it is possible to apply the automatic minimization of EMI in the actual operation of the electronic device system 80.

[0130] (Application Example 2) FIG. 30 shows an example of a radio band used in the electronic device according to the first embodiment. FIG. 31 shows an example of the relationship between the radio band used in the electronic device according to the first embodiment and the spectral characteristics of EMI generated in the electronic device.

[0131] Generally, as shown in FIG. 30, a wireless system often uses a plurality of radio bands A, B, and C. Hereinafter, in the electronic device system 80 having the configuration shown in FIG. 28 described above, a case where a plurality of radio bands A, B, and C as shown in FIG. 30 are used will be described.

[0132] When EMI occurs due to the operation of the transmitting device 82 in the electronic device system 80, if this has the spectral characteristics as shown in FIG. 31, for example, the spectral B' of EMI and the spectral C' of EMI overlap with the radio band B and the radio band C, respectively. Due to this spectral B' and spectral C', the sensitivity of the antenna 91 as a wireless device using the radio band B and the radio band C may be deteriorated.

[0133] To avoid this, the transmission device 82 may be provided with a function capable of changing the operating frequency. The change in the operating frequency may be performed by transmitting an operation control signal from the receiving device 83 via the control signal transmission line 85.

[0134] The transmission device 82 may be provided with a function capable of changing the operating frequency of the transmission device 82 based on the operation control signal from the receiving device 83 so that the state of the received signal from the antenna 91 becomes a desired state. The receiving device 83 may generate an operation control signal based on the level of the antenna coupling noise generated by the radiation noise caused by the operation of the transmission device 82 coupling to the antenna 91, or the state (such as magnitude) of the radio sensitivity of the antenna 91, and transmit it to the transmission device 82. Thereby, the change to the operating frequency at which the radio characteristics become optimal is performed.

[0135] FIG. 32 shows an example of the relationship between the spectrum characteristics of EMI after the operating frequency of the transmission device 82 is changed and the radio bands in the electronic device according to the first embodiment. By changing the operating frequency of the transmission device 82, it becomes easy to prevent, for example, as shown in FIG. 32, the EMI spectrum caused by the operation of the transmission device 82 from overlapping with each radio band. In some cases, although the radio band A and the radio band B do not overlap with the EMI spectrum, there is also a possibility that the radio band C overlaps with the EMI spectrum, but whether this is acceptable or not is a decision on the radio system side. For example, it may be determined based on the radio sensitivity characteristics.

[0136] Incidentally, examples of the EMI caused by the operation of the transmission device 82 include the following. · Common mode noise generated during transmission of the differential signal of the transmission device 82. · The switching noise generated when the circuit CHIP A of the transmission device 82 operates. This is caused by a steep current flowing through the power supply line for supplying the circuit CHIP A due to switching, and EMI radiates from this power supply line. This power supply line refers to the power distribution lines within the circuit CHIP A, the semiconductor package, and all the power supply lines wired on the printed circuit board.

[0137] FIG. 33 shows an example of the settable frequencies of the operating frequency of the transmission device 82 in the electronic device according to the first embodiment.

[0138] In FIG. 33, 82 the circuit CHIP A of the transmission device has circuit block A and circuit block B, and the case where the operating frequencies of each circuit block are represented by multiples of the basic operating frequency is taken as an example. When the settable frequencies held by the circuit CHIP A of the transmission device 82 are as shown in FIG. 33, for example, the operating frequency settings of circuit block A and circuit block B can be performed respectively, and the setting with the best radio characteristics can be selected and used.

[0139] For example, assuming that setting 24 has the best radio characteristics. When the basic operating frequencies are circuit block A = 200 MHz and circuit block B = 300 MHz, with this setting, the operating frequency of circuit block A is 240 MHz and the operating frequency of circuit block B is 330 MHz. Note that the change in the operating frequency in circuit CHIP A can be specifically achieved by using a frequency division circuit or the like.

[0140] FIG. 34 is a flowchart showing an example of the operation for controlling the operating frequency of the transmission device 82 in the electronic device according to the first embodiment. 。

[0141] First, the circuit CHIP A of the transmission device 82 operates, generating noise (step S21). Next, EMI radiates from the differential signal transmission line 84 and couples to the antenna 91 (step S22). Next, the receiving device 83 determines the state of the antenna-coupled noise (or radio sensitivity degradation) (step S23).

[0142] Next, the receiving device 83 determines whether the antenna-coupled noise is minimized or whether the radio sensitivity degradation is minimized (step S24). If it is determined that the antenna-coupled noise is not minimized or the radio sensitivity degradation is not minimized (step S24; N), the receiving device 83 controls the transmission device 82 to change the operating frequency setting of the circuit CHIP A of the transmission device 82 by transmitting an operation control signal to the transmission device 82 (step S25), and returns to the process of step S21. If it is determined that the antenna-coupled noise is minimized or the radio sensitivity degradation is minimized (step S24; Y), the receiving device 83 sets the minimum setting to the transmission device 82 by transmitting an operation control signal to the transmission device 82 (step S26), and ends the process.

[0143] Note that since the receiving device 83 can grasp the radio characteristics, in the above description, it is assumed that the receiving device 83 determines whether the radio characteristics are in an optimal state. However, it may be determined on the transmission device 82 side whether the radio characteristics are in an optimal state. In this case, information on the radio characteristics may be transmitted from the receiving device 83 to the transmission device 82, and the transmission device 82 side may determine whether the radio characteristics are in an optimal state.

[0144] [1.3 Modification Example] FIG. 35 shows a configuration example of a main part of a transmission device according to a modification example of the first embodiment.

[0145] In the above description, as the transmission device according to the first embodiment, the case of outputting a 4-value differential signal is taken as an example. However, the technology according to the present disclosure is also applicable to the case of outputting a differential signal other than 4 values. FIG. 35 shows a configuration example of a transmission device that outputs a 2-value differential signal.

[0146] The transmission device shown in FIG. 35 is the transmission device according to the comparative example shown in FIG. 1, in which a timing adjustment circuit 160UA is arranged in front of the rising circuit 141U of the pre-driver circuit 140 in the output circuit 101A, and a timing adjustment circuit 160DA is arranged in front of the falling circuit 141D. Also, in the output circuit 101B, a timing adjustment circuit 160UB is arranged in front of the rising circuit 141U of the pre-driver circuit 140, and a timing adjustment circuit 160DB is arranged in front of the falling circuit 141D.

[0147] The timing adjustment circuit 160UA adjusts the input timing of the driver input signal UIN_A based on the timing setting signal T_UA. The timing adjustment circuit 160DA adjusts the input timing of the driver input signal DIN_A based on the timing setting signal T_DA. The timing adjustment circuit 160UB adjusts the input timing of the driver input signal UIN_B based on the timing setting signal T_UB. The timing adjustment circuit 160DB adjusts the input timing of the driver input signal DIN_B based on the timing setting signal T_DB.

[0148] Also, in the driver circuit 150, in the output circuit 101A, the rising circuit 151U has an MOS transistor M_UA and a resistance element R1. fall The falling circuit 151D has an MOS transistor M_DA and a resistance element R2. In the driver circuit 150, in the output circuit 101B, the rising circuit 151U has an MOS transistor M_UB and a resistance element R1. fall The falling circuit 151D has an MOS transistor M_DB and a resistance element R2. The MOS transistors M_UA, M_DA, M_UB, and M_DB are each N-ch MOSFETs.

[0149] In the driver circuit 150 shown in FIG. 35, for example, when manufacturing variations occur in each of the MOS transistors M_UA, M_DA, M_UB, and M_DB, a difference occurs in the operating speed of the MOSFETs. At this time, a timing difference occurs between the output signals SIGA and SIGB, and as a result, the common-mode noise increases.

[0150] Therefore, by independently controlling the timing setting by each of the plurality of timing adjustment circuits 160UA, 160DA, 160UB, and 160DB based on each of the plurality of timing setting signals T_UA, T_DA, T_UB, and T_DB, even when manufacturing variations occur in each of the MOS transistors M_UA, M_DA, M_UB, and M_DB, the common-mode noise can be minimized.

[0151] [1.4 Effects] As described above, according to the transmission device and the electronic device according to the first embodiment, the setting value of the timing setting signal for each of the plurality of timing adjustment circuits 60 is changed to a value corresponding to the plurality of transition states of the signal levels that each of the plurality of output signals output from the driver circuit can take. Therefore, it is possible to minimize the common-mode noise in each of the plurality of transition states and improve the communication performance.

[0152] Further, according to the electronic device according to the first embodiment, by applying the technology of the present disclosure to the electronic device system 80 having a wireless function, it is also possible to minimize the common-mode noise output from the transmission device in the actual machine state.

[0153] Note that the effects described in this specification are merely examples and are not limited, and there may be other effects. The same applies to the effects of the following other embodiments.

[0154] <2. Second Embodiment> Next, a transmission device according to a second embodiment of the present disclosure will be described. In the following, components that are substantially the same as those of the transmission device according to the first embodiment described above are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0155] FIG. 36 shows a configuration example of a main part of a transmission device according to the second embodiment. FIG. 37 shows an example of symbol transitions transmitted by the transmission device according to the second embodiment.

[0156] FIG. 36 shows a configuration example of the output unit 30A as the main part of the transmission device shown in FIG. 16. The output unit 30A shown in FIG. 36 includes an output control unit 31, drivers 32A, 32B, 32C, delay units 33A, 33B, 33C, and a control unit 39.

[0157] The transmission device shown in FIG. 16 may transmit six symbols “+x”, “-x”, “+y”, “-y”, “+z”, “-z” using three output signals SIGA, SIGB, SIGC. For example, when transmitting the symbol “+x”, the transmission device sets the output signal SIGA to the high-level voltage VH, the output signal SIGB to the low-level voltage VL, and the output signal SIGC to the middle-level voltage VM. When transmitting the symbol “-x”, the transmission device sets the output signal SIGA to the low-level voltage VL, the output signal SIGB to the high-level voltage VH, and the output signal SIGC to the middle-level voltage VM. When transmitting the symbol “+y”, the transmission device sets the output signal SIGA to the middle-level voltage VM, the output signal SIGB to the high-level voltage VH, and the output signal SIGC to the low-level voltage VL. When transmitting the symbol “-y”, the transmission device sets the output signal SIGA to the middle-level voltage VM, the output signal SIGB to the low-level voltage VL, and the output signal SIGC to the high-level voltage VH. When transmitting the symbol “+z”, the transmission device sets the output signal SIGA to the low-level voltage VL, the output signal SIGB to the middle-level voltage VM, and the output signal SIGC to the high-level voltage VH. When transmitting the symbol “-z”, the transmission device sets the output signal SIGA to the high-level voltage VH, the output signal SIGB to the middle-level voltage VM, and the output signal SIGC to the low-level voltage VL.

[0158] Figure 37 shows an example of the operation of the signal generation unit 15 in the transmission device shown in FIG. 16. In the example of this Figure 37, six symbols, namely, “+x”, “-x”, “+y”, “-y”, “+z”, “-z” and the transitions between them are shown.

[0159] In the transmission device shown in FIG. 16, the signal TxF causes symbol transitions between “+x” and “-x”, between “+y” and “-y”, and between “+z” and “-z”. Specifically, when the signal TxF is “1”, it transitions so as to change the polarity of the symbol (for example, from “+x” to “-x”), and when the signal TxF is “0”, such a transition is not made.

[0160] The signals TxR and TxP cause symbol transitions between other than “+x” and “+x”, between other than “+y” and “+y”, and between other than “+z” and “+z” when the signal TxF is “0”. Specifically, when the signals TxR and TxP are “1” and “0”, they transition clockwise in FIG. 37 while maintaining the symbol polarity (for example, from “+x” to “+y”), and when the signals TxR and TxP are “1” and “1”, they change the symbol polarity and transition clockwise in FIG. 37 (for example, from “+x” to “-y”). Also, when the signals TxR and TxP are “0” and “0”, they transition counterclockwise in FIG. 37 while maintaining the symbol polarity (for example, from “+x” to “+z”), and when the signals TxR and TxP are “0” and “1”, they change the symbol polarity and transition counterclockwise in FIG. 37 (for example, from “+x” to “-z”).

[0161] In this way, in the signal generation unit 15, the directions of symbol transitions are specified by the signals TxF, TxR, and TxP. Therefore, the signal generation unit 15 can obtain the next symbol NS based on the current symbol CS and these signals TxF, TxR, and TxP. Then, the signal generation unit 15 supplies this symbol NS to the flip-flop 16 using, in this example, a 3-bit signal S1.

[0162] The output unit 30A shown in FIG. 37 generates a plurality of output signals SIGA, SIGB, and SIGC based on the signal S2. The operation of the output unit 30A is controlled by the control signal IT1.

[0163] The driver 32A sets the voltage state of the output signal SIGA to any one of three voltage levels (high-level voltage VH, middle-level voltage VM, and low-level voltage VL) based on the control signal supplied from the output control unit 31 via the delay unit 33A. The driver 32B sets the voltage state of the output signal SIGB to any one of the three voltage levels based on the control signal supplied from the output control unit 31 via the delay unit 33B. The driver 32C sets the voltage state of the output signal SIGC to any one of the three voltage levels based on the control signal supplied from the output control unit 31 via the delay unit 33C.

[0164] With this configuration, the output unit 30A can set the output signals SIGA, SIGB, and SIGC to three voltage levels corresponding to the symbol CS based on the symbol CS indicated by the signal S2.

[0165] Next, the driver 32A of the output unit 30 will be described in more detail. Note that the same applies to the drivers 32B and 32C.

[0166] Driver 32A has transistors 35 and 36, and resistor elements 37 and 38. Transistors 35 and 36 are N-ch MOSFETs. A control signal is supplied from output control unit 31 to the gate of transistor 35 via delay unit 33A, voltage V1 is supplied to the drain, and the source is connected to one end of resistor element 37. A control signal is supplied from output control unit 31 to the gate of transistor 36 via delay unit 33A, the drain is connected to one end of resistor element 38, and the source is grounded. Resistor elements 37 and 38 function as termination resistors. One end of resistor element 37 is connected to the source of transistor 35, the other end is connected to the other end of resistor element 38 and to output terminal ToutA. One end of resistor element 38 is connected to the drain of transistor 36, the other end is connected to the other end of resistor element 37 and to output terminal ToutA.

[0167] For example, when setting output signal SIGA to high-level voltage VH, output control unit 31 supplies a high-level control signal to transistor 35 and a low-level control signal to transistor 36. As a result, transistor 35 turns on and transistor 36 turns off, an output current flows through transistor 35, and output signal SIGA is set to high-level voltage VH. Also, for example, when setting output signal SIGA to low-level voltage VL, output control unit 31 supplies a low-level control signal to transistor 35 and a high-level control signal to transistor 36. As a result, transistor 35 turns off and transistor 36 turns on, an output current flows through transistor 36, and output signal SIGA is set to low-level voltage VL. Also, for example, when setting output signal SIGA to mid-level voltage VM, output control unit 31 supplies a low-level control signal to transistors 35 and 36. As a result, transistors 35 and 36 turn off.

[0168] Based on control signal IT1, control unit 39 controls the delay amounts of delay units 33A, 33B, and 33C.

[0169] The delay unit 33A is inserted between the output control unit 31 and the driver 32A, delays the two control signals supplied from the output control unit 31 based on the delay control signal supplied from the control unit 39, and supplies them to the driver 32A.

[0170] The delay unit 33B is inserted between the output control unit 31 and the driver 32B, delays the two control signals supplied from the output control unit 31 based on the delay control signal supplied from the control unit 39, and supplies them to the driver 32B.

[0171] The delay unit 33C is inserted between the output control unit 31 and the driver 32C, delays the two control signals supplied from the output control unit 31 based on the delay control signal supplied from the control unit 39, and supplies them to the driver 32C.

[0172] Note that the delay units 33A, 33B, and 33C respectively correspond to the timing adjustment circuits in the transmission device according to the first embodiment. In the transmission device according to the second embodiment shown in FIG. 36, the control unit 39 controls the delay amounts of the delay units 33A, 33B, and 33C by the same technology as that of the transmission device according to the first embodiment, and performs control according to the transition states of the output signals SIGA, SIGB, and SIGC, thereby adjusting the skew of the output signals SIG1A, SIG1B, and SIG1C and suppressing the common mode. noise can be suppressed.

[0173] Other configurations, operations, and effects may be substantially the same as those of the transmission device according to the first embodiment.

[0174] <3. Third Embodiment> Next, a transmission device according to the third embodiment of the present disclosure will be described. In the following, components that are substantially the same as those of the transmission device according to the first or second embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0175] FIG. 38 shows a configuration example of a main part of a transmission device according to the third embodiment.

[0176] The transmission device according to the third embodiment has two operation modes MA and MB. The operation mode MA is a single-phase mode for transmitting a single-phase signal, and the operation mode MB is a differential mode for transmitting a differential signal. The transmission device transmits data in either of the two operation modes MA and MB based on the mode signal Smode.

[0177] The transmission device includes four serializers 21 (serializers 21A, 21B, 21C, 21D), four multiplexers (MUX) 22 (multiplexers 22A, 22B, 22C, 22D), four selectors (SEL) 23 (selectors 23A, 23B, 23C, 23D), two drivers 24 (drivers 24A, 24B), and a control unit 25.

[0178] The transmission device also has a plurality of timing adjustment circuits 160AA, 160AB, 160BA, 160BB at the subsequent stage of each of the multiplexers 22A, 22B, 22C, 22D.

[0179] The serializer 21A generates signals S21AP and S21AN by serializing the signals DI10, DI12, DI14, DI16 based on the clock signals P0, P2, P4, P6. The signals S21AP and S21AN are inverted signals with respect to each other. Similarly, the serializer 21B generates signals S21BP and S21BN by serializing the signals DI20, DI22, DI24, DI26 based on the clock signals P0, P2, P4, P6. The signals S21BP and S21BN are inverted signals with respect to each other. The serializer 21C generates signals S21CP and S21CN by serializing the signals DI11, DI13, DI15, DI17 based on the clock signals P1, P3, P5, P7. The signals S21CP and S21CN are inverted signals with respect to each other. The serializer 21D generates signals S21DP and S21DN by serializing the signals DI21, DI23, DI25, DI27 based on the clock signals P1, P3, P5, P7. The signals S21DP and S21DN are inverted signals with respect to each other.

[0180] In operation mode MA, signals DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17 are transmitted using signal SIG1, and signals DI20, DI21, DI22, DI23, DI24, DI25, DI26, DI27 are transmitted using signal SIG2.

[0181] Also, in operation mode MB, signals DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17 are transmitted using signals SIGP and SIGN. Also, in this operation mode MB, signals DI20, DI21, DI22, DI23, DI24, DI25, DI26, DI27 are used to perform an emphasis operation. The data indicated by these signals DI20 to DI27 is set to be offset by one bit from the data indicated by signals DI10 to DI17, as will be described later.

[0182] Multiplexer 22A alternately selects one of signals S21AP and S21CP based on the clock signal CLK, and outputs the selected signal as signal S22A. Multiplexer 22B alternately selects one of signals S21AN and S21CN based on the clock signal CLK, and outputs the selected signal as signal S22B. Multiplexer 22C alternately selects one of signals S21BP and S21DP based on the clock signal CLK, and outputs the selected signal as signal S22C. Multiplexer 22D alternately selects one of signals S21BN and S21DN based on the clock signal CLK, and outputs the selected signal as signal S22D.

[0183] Multiplexer 22A selects signal S21AP during the period when the clock signal CLK is at a high level, and selects signal S21CP during the period when the clock signal CLK is at a low level.

[0184] In this way, multiplexer 22A selects signal S21AP during the period when clock signal CLK is at a high level, and selects signal S21CP during the period when clock signal CLK is at a low level. Also, multiplexer 22B selects signal S21AN during the period when clock signal CLK is at a high level, and selects signal S21CN during the period when clock signal CLK is at a low level. Since signals S21AP and S21AN are inverted signals of each other, and signals S21CP and S21CN are inverted signals of each other, output signal S22A of multiplexer 22A and output signal S22B of multiplexer 22B become inverted signals of each other.

[0185] Similarly, multiplexer 22C selects signal S21BP during the period when clock signal CLK is at a high level, and selects signal S21DP during the period when clock signal CLK is at a low level. Also, multiplexer 22D selects signal S21BN during the period when clock signal CLK is at a high level, and selects signal S21DN during the period when clock signal CLK is at a low level. As described above, since signals S21BP and S21BN are inverted signals of each other, and signals S21DP and S21DN are inverted signals of each other, output signal S22C of multiplexer 22C and output signal S22D of multiplexer 22D become inverted signals of each other.

[0186] Selector 23A selects signal S22A when the operation mode is operation mode MA (single-phase mode) based on signal Ssel, selects signal S22D when the operation mode is operation mode MB (differential mode), and outputs the selected signal as signal S23A.

[0187] Selector 23B selects signal S22B when the operation mode is operation mode MA based on signal Ssel, selects signal S22C when the operation mode is operation mode MB, and outputs the selected signal as signal S23B.

[0188] Selector 23C selects signal S22C when the operation mode is operation mode MA based on signal Ssel, selects signal S22B when the operation mode is operation mode MB, and outputs the selected signal as signal S23C.

[0189] Selector 23D selects signal S22D when the operation mode is operation mode MA based on signal Ssel, selects signal S22A when the operation mode is operation mode MB, and outputs the selected signal as signal S23D.

[0190] Driver 24A sets the voltage at output terminal Tout1 based on signals S22A, S22B, S23A, S23B, and signal CTL. Driver 24B sets the voltage at output terminal Tout2 based on signals S23C, S23D, S22C, S22D, and signal CTL.

[0191] Driver 24A has M sub-drivers AA and N sub-drivers AB. Driver 24B has M sub-drivers BA and N sub-drivers BB. "M" and "N" are configured to be changeable by signal CTL.

[0192] Each of sub-drivers AA, AB, BA, and BB has a resistance element and a transistor. The transistor is an N-ch MOSFET. In FIG. 38, these transistors are drawn inside drivers 24A and 24B. Also, in FIG. 38, the illustration of the resistance element is omitted.

[0193] With this configuration, for example, in operation mode MA (single-phase mode), when signal S22A is set to a high level and signal S22B is set to a low level, signal S23A becomes a high level and signal S23B becomes a low level. As a result, driver 24A can set the voltage at output terminal Tout1 to high-level voltage VH and set the output impedance to, for example, about 50 [Ω].

[0194] Also, for example, in operation mode MA, when signal S22B is set to a high level and signal S22A is set to a low level, signal S23B becomes a high level and signal S23A becomes a low level. As a result, driver 24A can set the voltage at output terminal Tout1 to a low-level voltage VL and set the output impedance to, for example, approximately 50 [Ω].

[0195] Also, for example, in operation mode MB (differential mode), when signals S22A and S22D are both set to a high level and signals S22B and S22C are both set to a low level, signals S23A and S23D both become high levels and signals S23B and S23C both become low levels. As a result, driver 24A can set the voltage at output terminal Tout1 to a high-level voltage VH and set the output impedance to, for example, approximately 50 [Ω]. Similarly, driver 24B can set the voltage at output terminal Tout2 to a low-level voltage VL and set the output impedance to, for example, approximately 50 [Ω].

[0196] Also, for example, in operation mode MB, when signals S22B and S22C are both set to a high level and signals S22A and S22D are both set to a low level, signals S23B and S23C both become high levels and signals S23A and S23D both become low levels. As a result, driver 24A can set the voltage at output terminal Tout1 to a low-level voltage VL and set the output impedance to, for example, approximately 50 [Ω]. Similarly, driver 24B can set the voltage at output terminal Tout2 to a high-level voltage VH and set the output impedance to, for example, approximately 50 [Ω].

[0197] Also, for example, in operation mode MB, when both signals S22A and S22C are set to high level and both signals S22B and S22D are set to low level, both signals S23B and S23D become high level and both signals S23A and S23C become low level. As a result, driver 24A can set the voltage at output terminal Tout1 to a voltage (VH - ΔV) that is lower than the high-level voltage VH by voltage ΔV, and can set the output impedance to, for example, about 50 [Ω]. Similarly, driver 24B can set the voltage at output terminal Tout2 to a voltage (VL + ΔV) that is higher than the low-level voltage VL by voltage ΔV, and can set the output impedance to, for example, about 50 [Ω].

[0198] Also, for example, in operation mode MB, when both signals S22B and S22D are set to high level and both signals S22A and S22C are set to low level, both signals S23A and S23C become high level and both signals S23B and S23D become low level. As a result, driver 24A can set the voltage at output terminal Tout1 to a voltage (VL + ΔV) that is higher than the low-level voltage VL by voltage ΔV, and can set the output impedance to, for example, about 50 [Ω]. Similarly, driver 24B can set the voltage at output terminal Tout2 to a voltage (VH - ΔV) that is lower than the high-level voltage VH by voltage ΔV, and can set the output impedance to, for example, about 50 [Ω].

[0199] This voltage ΔV changes according to "M" and "N". That is, for example, when "M" is increased and "N" is decreased, voltage ΔV can be decreased. Also, for example, when "M" is decreased and "N" is increased, voltage ΔV can be increased.

[0200] Based on the mode signal Smode, control unit 25 generates clock signals P0 to P7, CLK and signals Ssel, CTL.

[0201] The timing adjustment circuits 160AA, 160AB, 160BA, and 160BB each control the input timing of the signals input to the drivers 24A and 24B based on the respective timing setting signals Tset_AA, Tset_AB, Tset_BA, and Tset_BB by the same technology as the transmission device according to the first embodiment in the operation mode MB (differential mode). Thereby, the common mode noise of the differential signals in the operation mode MB can be suppressed.

[0202] Other configurations, operations, and effects may be substantially the same as those of the transmission device according to the first embodiment.

[0203] <4. Other Embodiments> The technology according to the present disclosure is not limited to the descriptions of the above embodiments, and various modifications can be made.

[0204] For example, the present technology can also have the following configuration. According to the present technology having the following configuration, the setting values of the timing setting signals for each of the plurality of timing adjustment circuits are changed to values corresponding to the plurality of transition states of the signal levels that each of the plurality of output signals output from the driver circuit can take. Therefore, it is possible to improve the communication performance.

[0205] (1) A driver circuit having a plurality of output circuits each having a plurality of transistors, and outputting a plurality of output signals having different signal levels that constitute a differential signal from the plurality of output circuits based on a plurality of driver input signals input to each of the plurality of transistors, a plurality of timing adjustment circuits that adjust the input timing of the plurality of driver input signals to the driver circuit based on a timing setting signal, and a control circuit that changes the setting value of the timing setting signal for each of the plurality of timing adjustment circuits to a value corresponding to the plurality of transition states of the signal levels that each of the plurality of output signals output from the driver circuit can take Comprising A transmission device (2) The timing setting signal includes a rising-edge timing setting signal and a falling-edge timing setting signal, Each of the plurality of timing adjustment circuits can adjust the rising-edge timing and the falling-edge timing of each of the plurality of driver input signals based on the rising-edge timing setting signal and the falling-edge timing setting signal, The control circuit changes the setting values of the rising-edge timing setting signal and the falling-edge timing setting signal to values corresponding to the plurality of transition states The transmission device according to (1) above (3) Each of the plurality of timing adjustment circuits, A delay circuit that generates a plurality of delay signals obtained by delaying the signal corresponding to the driver input signal, A select circuit that selects one of the plurality of delay signals based on the timing setting signal and outputs it as the driver input signal Having The transmission device according to (1) or (2) above (4) The control circuit, A state determination circuit that changes the setting value of the timing setting signal to a value corresponding to the plurality of transition states based on a plurality of first input signals corresponding to the plurality of output signals and a plurality of second input signals obtained by delaying the plurality of first input signals, having The transmission device according to any one of (1) to (3) above (5) The control circuit, A plurality of first synchronization circuits that delay each of the plurality of first input signals based on a clock signal and output the plurality of second input signals, A plurality of second synchronization circuits that delay each of the plurality of second input signals based on the clock signal and output a third input signal to each of the plurality of timing adjustment circuits Further having The transmission device according to the above (4). (6) The differential signal has a differential signal level of 4 or more values. The transmission device according to any one of the above (1) to (5). (7) A transmission device that transmits a differential signal, A receiving device that receives the differential signal transmitted from the transmission device, and The transmission device includes a plurality of output circuits each having a plurality of transistors, and based on a plurality of driver input signals input to each of the plurality of transistors, outputs a plurality of output signals having different signal levels that constitute a differential signal from the plurality of output circuits; a driver circuit, a plurality of timing adjustment circuits that adjust the input timing of the plurality of driver input signals to the driver circuit based on a timing setting signal, a control circuit that changes the setting value of the timing setting signal for each of the plurality of timing adjustment circuits to a value corresponding to a plurality of transition states of signal levels that each of the plurality of output signals output from the driver circuit can take and is provided with (8) further includes an antenna that receives a radio signal and outputs it as a received signal to the receiving device, The receiving device transmits a timing control signal for controlling the setting value of the timing setting signal in the transmission device to the transmission device so that the state of the received signal from the antenna becomes a desired state. The electronic device according to the above (7). (9) further includes a transmission line that transmits the differential signal between the transmission device and the receiving device, The receiving device generates the timing control signal based on the level of antenna-coupled noise generated by the radiation noise radiated from the transmission line coupling to the antenna, or the state of the radio sensitivity of the antenna. The electronic device according to the above (8). (10) The transmission device can change the operating frequency of the transmission device so that the state of the received signal from the antenna becomes a desired state based on an operation control signal. The receiving device generates the operation control signal based on the level of antenna-coupled noise generated by the radiation noise caused by the operation of the transmission device coupling to the antenna, or based on the state of the wireless sensitivity of the antenna, and transmits it to the transmission device. The electronic device according to the above (8) or (9).

[0206] This application claims priority based on Japanese Patent Application No. 2020-209036 filed with the Japan Patent Office on December 17, 2020, and incorporates all the contents of this application by reference.

[0207] Those skilled in the art can conceive various modifications, combinations, sub-combinations, and changes according to design requirements and other factors, but it is understood that they are included within the scope of the appended claims and their equivalents.

Claims

1. A driver circuit having a plurality of output circuits each having a plurality of transistors, and outputting a plurality of output signals having different signal levels that constitute a differential signal from the plurality of output circuits based on a plurality of driver input signals input to each of the plurality of transistors; A plurality of timing adjustment circuits that adjust the input timing of the plurality of driver input signals to the driver circuit based on a timing setting signal; A control circuit that changes the setting value of the timing setting signal for each of the plurality of timing adjustment circuits to a value corresponding to a plurality of transition states of signal levels that each of the plurality of output signals output from the driver circuit can take; Comprising; The control circuit is; A state determination circuit that changes the setting value of the timing setting signal to a value corresponding to the plurality of transition states based on a plurality of first input signals corresponding to the plurality of output signals and a plurality of second input signals obtained by delaying the plurality of first input signals; A transmission device.

2. The timing setting signal includes a rising-edge timing setting signal and a falling-edge timing setting signal, Each of the plurality of timing adjustment circuits can adjust the rising-edge timing and the falling-edge timing of each of the plurality of driver input signals based on the rising-edge timing setting signal and the falling-edge timing setting signal, The control circuit changes the setting value of each of the rising-edge timing setting signal and the falling-edge timing setting signal to a value corresponding to the plurality of transition states. The transmission device according to claim 1.

3. Each of the plurality of timing adjustment circuits is; A delay circuit that generates a plurality of delay signals obtained by delaying a signal corresponding to the driver input signal; A select circuit that selects one of the plurality of delay signals based on the timing setting signal and outputs it as the driver input signal. Having; The transmission device according to claim 1.

4. The control circuit is; A plurality of first synchronization circuits that delay each of the plurality of first input signals based on a clock signal and output the plurality of second input signals; A plurality of second synchronization circuits that delay each of the plurality of second input signals based on the clock signal and output a third input signal to each of the plurality of timing adjustment circuits. Further having; The transmission device according to claim 1.

5. The differential signal has a differential signal level of 4 values or more The transmission device according to claim 1.

6. A transmission device that transmits a differential signal, A receiving device that receives the differential signal transmitted from the transmission device and includes The transmission device is It has a plurality of output circuits each having a plurality of transistors, and based on a plurality of driver input signals input to each of the plurality of transistors, from the plurality of output circuits, a plurality of output signals having different signal levels that constitute the differential signal are output. A driver circuit, A plurality of timing adjustment circuits that adjust the input timing of the plurality of driver input signals to the driver circuit based on a timing setting signal, A control circuit that changes the set value of the timing setting signal for each of the plurality of timing adjustment circuits to a value corresponding to a plurality of transition states of signal levels that each of the plurality of output signals output from the driver circuit can take and includes The control circuit is Based on a plurality of first input signals corresponding to the plurality of output signals and a plurality of second input signals obtained by delaying the plurality of first input signals, it has a state determination circuit that changes the set value of the timing setting signal to a value corresponding to the plurality of transition states Electronic device.

7. It further includes an antenna that receives a radio signal and outputs it as a received signal to the receiving device, The receiving device transmits a timing control signal that controls the set value of the timing setting signal in the transmission device so that the state of the received signal from the antenna becomes a desired state to the transmission device. The electronic device according to claim 6.

8. It further includes a transmission line that transmits the differential signal between the transmission device and the receiving device, The receiving device generates the timing control signal based on the level of antenna coupling noise generated by the radiation noise radiated from the transmission line coupling to the antenna, or the state of the radio sensitivity of the antenna. The electronic device according to claim 7.

9. The transmission device can change the operating frequency of the transmission device based on an operation control signal so that the state of the received signal from the antenna becomes a desired state. The receiving device generates the operation control signal based on the level of antenna-coupled noise generated by the coupling of radiated noise caused by the operation of the transmitting device to the antenna, or based on the state of the wireless sensitivity of the antenna, and transmits the operation control signal to the transmitting device. The electronic device according to claim 7.

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