Wake detection in a controller for a physical layer of a single pair Ethernet network, and related systems, methods, and devices

Abstract

Circuits for detecting valid signals on single-pair Ethernet buses and related systems are described. Circuits and related systems for wake detection at the physical layer of a network segment are also described, and in some embodiments, the wake detection circuitry may include or use signal detection circuitry. In some cases, a low-frequency clock generator may be used to clock the wake detection circuitry, including during low-power modes of operation. In some cases, the low-frequency clock generator may be selectively enabled or disabled to limit power consumption.

Description

Technical Field

[0001] (Claim of Priority) This application claims the benefit of the filing date of Chinese Patent Application No. 201910784580.0, filed on August 23, 2019, for "Wake Detection at Controller for Physical Layer of Single Pair Ethernet Network, and Related Systems, Methods and Devices", and also claims the benefit of the filing date of U.S. Patent Application No. 16 / 591,294, filed on October 2, 2019, for "Wake Detection at Controller for Physical Layer of Single Pair Ethernet Network, and Related Systems, Methods and Devices". The entire disclosure of each of these is hereby incorporated by reference in its entirety.

[0002] (Technical Field) The embodiments described herein generally relate to single pair Ethernet, and more specifically, some embodiments relate to systems, methods, and devices for wake detection in the physical layer of a network segment.

Background Art

[0003] Interconnection is widely used to facilitate communication between network devices. Generally speaking, electrical signals are transmitted on a physical medium (such as a bus, coaxial cable, or twisted pair - and sometimes simply referred to as a "line") by devices coupled to that physical medium.

[0004] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., electrical signals are discrete electrical pulses) to transmit data packets and ultimately messages that are communicated between network devices. According to the OSI model, a special circuit called a physical layer (PHY) device or controller is used to interface between the analog domain of the line and the digital domain of the data link layer (or simply the "link layer") that operates according to packet signaling. The data link layer may include one or more sublayers, but in Ethernet-based computer networking, the data link layer typically includes at least one media access control (MAC) layer that provides control abstraction of the physical layer. As an example, when transmitting data to another device on the network, the MAC controller may prepare a frame for the physical media, add error correction elements, and perform collision avoidance. Further, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare a frame for a higher layer.

[0005] There are various network topologies that implement the physical layer and the link layer (and, without limitation, may include other layers). The Peripheral Component Interconnect (PCI) standard and Parallel Advanced Technology Attachment (Parallel ATA), which have existed since the early 1990s, may implement a multi-drop bus topology. The trend since the early 2000s has been to use a point-to-point bus topology. For example, the PCI Express standard and Serial ATA (SATA) standard implement a point-to-point topology.

[0006] A typical point-to-point bus topology can implement a line between each device (e.g., a dedicated point-to-point) or a line between a device and a switch (e.g., a switched point-to-point without limitation). In a multi-drop topology, the physical medium is a shared bus, and each network device is coupled to the shared bus via a circuit selected based on, for example, the type of physical medium (e.g., coaxial or twisted pair without limitation).

[0007] Point-to-point bus topologies, such as dedicated point-to-point topologies or switched point-to-point topologies, require more wires and more expensive materials than multi-drop topologies, partly due to the increased number of links between devices. In certain applications, such as in automobiles, there may be physical constraints that make it difficult to directly connect devices, and thus topologies that do not require direct connections or do not require the same number of direct connections within a network or subnet (e.g., multi-drop topologies without limitation) may be less affected by such constraints.

[0008] Devices in a baseband network (e.g., but not limited to, a multi-drop network) share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (i.e., the digital signals used in baseband transmission occupy the entire bandwidth of the medium). As a result, only one device on the baseband network can transmit at a given instant. The present disclosure concludes with claims that specifically point out and distinctly claim certain embodiments, but various features and advantages of embodiments within the scope of the present disclosure can be more readily ascertained from the following description when read in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0009]

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[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which illustrate, by way of example, specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, other embodiments may be utilized and structural, material, and process changes may be made without departing from the scope of the disclosure.

[0011] The examples presented herein are not intended to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to illustrate embodiments of the disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in the various drawings may retain the same or similar reference numerals for the convenience of the reader. However, similarity in reference numerals does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0012] The following description may include examples to assist those skilled in the art in implementing the disclosed embodiments. The use of the terms "exemplary," "as an example," and "for example" means that the associated description is illustrative, and the scope of the present disclosure is intended to include the examples and legal equivalents, and the use of such terms is not intended to limit the embodiments or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0013] It will be readily understood that the components of the embodiments generally described herein and illustrated in the drawings can be arranged and designed in a wide variety of different configurations. Accordingly, the following description of the various embodiments is not intended to limit the scope of the present disclosure, but merely represents the various embodiments. Although the various aspects of the embodiments can be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0014] Furthermore, the specific implementation forms illustrated and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions can be shown in the form of block diagrams so as not to obscure the present disclosure by unnecessary details. Conversely, the specific implementation forms illustrated and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Moreover, the logical block definitions and partitioning between the various blocks are examples of specific implementation forms. It will be readily apparent to those skilled in the art that the present disclosure can be implemented by a number of other partitioning solutions. For the most part, details regarding timing considerations, etc. are omitted, and such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0015] One of ordinary skill in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. In some of the drawings, signals may be illustrated as a single signal for clarity of presentation and description. One of ordinary skill in the art will understand that a signal can represent a bus of signals, which can have various bit widths, and that the present disclosure can be implemented with any number of data signals including a single data signal.

[0016] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed with a general purpose processor, a dedicated processor, a Digital Signal Processor (DSP), an integrated circuit (IC), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (referred to herein as a host processor or simply a host) can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration of combinations. A general purpose computer including a processor is considered a dedicated computer, and the general purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0017] Embodiments may be described with respect to processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. A flowchart may describe operational acts as sequential processes, although many of these acts may be executed in another order, in parallel, or substantially simultaneously. Additionally, the order of the acts may be re-adjusted. A process may correspond to a method, thread, function, procedure, subroutine, subprogram, but is not limited thereto. Further, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium. A computer-readable medium includes both a computer storage medium and a communication medium such as any medium that facilitates transfer of a computer program from one place to another.

[0018] Any reference in this specification to elements using the notations “first,” “second,” etc. does not limit the quantity or order of those elements unless such a limitation is explicitly stated. Rather, these notations may be used as a convenient way to distinguish between two or more elements or instances of an element in this specification. Thus, a reference to a first element and a second element does not mean that only two elements may be used or that the first element must precede the second element in any way. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0019] As used herein, the term “substantially” when referring to a given parameter, characteristic, or condition means and includes that the given parameter, characteristic, or condition meets variations that are small, such as within acceptable manufacturing tolerances, for example, as would be understood by one of ordinary skill in the art. As an example, depending on the particular parameter, characteristic, or condition being substantially met, the parameter, characteristic, or condition may be met at least 90%, at least 95%, or even at least 99%.

[0020] Mobile machines such as automobiles, trucks, buses, ships, and / or aircraft may include a mobile machine communication network. The complexity of the mobile machine communication network can vary depending on the number of electronic devices and subsystems within the network. For example, an advanced mobile machine communication network may include various control modules for engine control, transmission control, safety control (e.g., antilock brakes), and emissions control. As another non-limiting example, an advanced mobile machine communication network may include, without limitation, connectivity for voice and other information and entertainment systems, on-board charging, external cameras, external devices (e.g., universal serial bus connectivity), and door control (e.g., locks, windows, side view mirrors), as well as modules to support vehicle diagnostics. Similar considerations arise, without limitation, for communication networks used in industrial control, building operation systems, building management systems, residential utility systems, and connected lighting systems.

[0021] To support these modules, the automotive industry relies on various communication protocols. 10SPE (i.e., 10 Mbps Single Pair Ethernet) is a network technology specification currently being developed by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE 802.3cg™. Using 10SPE, deterministic transmission without collisions on a multi-drop network can be provided. The 10SPE specification provides PHY requirements for normal operation but does not have requirements for low power mode or sleep mode (low power mode, power saving mode, and sleep mode are collectively referred to herein as "sleep mode").

[0022] FIG. 1 shows a functional block diagram of a network segment 100 that includes a link layer device, MAC 106, and a physical layer (PHY) device, PHY 104. By way of non-limiting example, network segment 100 can be a segment of a multi-drop network, a segment of a multi-drop sub-network, a multi-drop bus that is a segment of a hybrid media network, or a combination or sub-combination thereof. By way of non-limiting example, network segment 100 can be, but is not limited to, a microcontroller-based embedded system, a user-type computer, a computer server, a notebook computer, a tablet, a handheld device, a mobile device, a wireless earphone device or a headphone device, a wired earphone device or a headphone device, an electrical product subsystem, a lighting subsystem, a voice subsystem, a building management system, a residential monitoring system (e.g., for security or utility use of the stem )、 an elevator system or subsystem, a mass transit control system (e.g., in the case of an overground train, subway, trolley, or bus), an automotive system or automotive subsystem, or an industrial control system, or can be part of them, or can include one or more of them. By way of non-limiting example, PHY 104 and MAC 106 can be part of an endpoint or a switch.

[0023] PHY 104 is generally configured to interface with MAC 106. By way of non-limiting example, PHY 104 and / or MAC 106 can be a chip package that includes memory and / or logic configured to execute all or part of the embodiments described herein. By way of non-limiting example, PHY 104 and MAC 106 can each be implemented as a separate chip package or circuit (e.g., an integrated circuit) within a single chip package (e.g., a system-in-a-package (SIP)).

[0024] PHY104 is generally configured to interface with a network including a shared transmission medium 102, such as a physical medium that is a communication path of a node that is part of network segment 100, or a network of which network segment 100 is a part that includes nodes each including an instance of PHY104 and MAC106. By way of non-limiting example, the shared transmission medium 102 can be a single twisted pair such as used for single pair Ethernet.

[0025] In some cases, it may be useful to operate network segment 100 in sleep mode and then transition it to normal operation mode in response to a control signal (e.g., a wake signal from a master node without limitation) or in response to activity on shared transmission medium 102. By way of non-limiting example, it may be desirable for network segment 100 to be in sleep mode while waiting for a scheduled transmission opportunity. However, due to power limitations during sleep mode, the amount of power available to circuits that monitor control signals or bus activity can be severely limited.

[0026] Some embodiments generally relate to providing wake-up detection (i.e., detecting conditions for transitioning from sleep mode to normal operation mode) in physical layer device 104 of network segment 100. FIG. 2 shows a diagram of an embodiment of a system 200 configured for various wake-up detection functions. System 200 can be implemented, for example, in PHY104. In various embodiments, system 200 is configured to generate a signal, wake-up 214, to indicate that a PHY, node, or more generally an endpoint should transition to a power mode associated with normal operation mode from sleep mode (normal operation mode can also be characterized as being “awake”).

[0027] In one or more embodiments, system 200 may include modules for activity detector 204 and power manager 202. As a non-limiting example, system 200 may be configured to provide signal, wakeup 214 to node power control responsible for powering one or more components of the node and / or to the core logic of the PHY in which system 200 is implemented. For example, the core logic of PHY104 may be implemented in the interruptible power domain of PHY104, and system 200 may be implemented in the uninterruptible power domain 216 of PHY104. As a non-limiting example, the interruptible power domain may be supplied by an interruptible power source (e.g., a switched voltage regulator that is turned off during sleep mode), and the uninterruptible power domain 216 may be supplied by a continuous power source (e.g., one that is not interrupted during sleep mode). In one embodiment, the uninterruptible power domain 216 may be powered only by a continuous power source; in other words, the circuits and digital logic within the uninterruptible power domain 216 may operate only on power supplied by a continuous power source. In the case of a 10SPE network used in an automobile, the uninterruptible power domain 216 may operate, as a non-limiting example, based on a 3.3V power source.

[0028] In one or more embodiments, system 200 may include activity detector 204 and power manager 202. Activity detector 204 may be configured to detect bus activity 212 on bus 206 and to detect signal, wake-in 210 on a dedicated input pin (not shown) of system 200. Activity detector 204 may be configured to generate signal, activity detect 208 in response to signal, wake-in 210 and / or bus activity 212. Activity detection and related circuitry are more fully described with reference to FIGS. 3, 4, 5, and 6.

[0029] In one or more embodiments, the power manager 202 may be configured to receive a signal, activity detection 208 and, in response to the signal, activity detection 208, generate a signal, wake-up 214. In an envisioned use case, the wake-up 214 may be asserted by node power control or an interrupt in core logic.

[0030] The signals of wake-in 210 and / or bus activity 212 may contain noise, particularly in environments where noise is especially likely to occur (e.g., but not limited to, automotive environments, commercial buildings, and lighting systems). In fact, not only can noise be mistaken for a valid signal, but a valid signal can also be mistaken for noise. In some cases, it may be useful to provide means for distinguishing between valid and invalid signals (e.g., noise) as part of the operation of the signal, activity detector 204.

[0031] FIG. 3 shows a block diagram of a sleep mode controller 300 configured to distinguish between valid and invalid signals for wake detection purposes while executing one or more of the functions of the system 200 of FIG. 2 according to one or more embodiments.

[0032] In one or more embodiments, the sleep mode controller 300 may include a wake signal input 312 and a bus signal detector 302. The wake signal input 312 is a dedicated input pin assigned to receive a wake-in signal (not shown) such as the wake-in 210 of FIG. 2. The bus activity 318 may be measured at n and p terminals (not shown) coupled to respective n and p cables of the type typically used in a single pair Ethernet cable.

[0033] In the embodiment of FIG. 3, the wake signal input 312 is configured to propagate the wake signal 308 to the valid activity detector 306 in response to the received wake-in signal (e.g., wake-in 210). In other words, in such an embodiment, the wake signal 308 is substantially the signal received at the wake signal input 312 (e.g., wake-in 210 of FIG. 2). In some cases, the wake signal input 312 may include a signal detector arranged to measure the signal level of the wake signal input 312 and generate the wake signal 308 in response to observing the signal amplitude of the wake signal input 312 indicative of a potential valid signal.

[0034] The bus signal detector 302 may be configured to provide a bus signal 328 in response to detecting the signal level of the bus activity 318 indicative of a potential valid signal.

[0035] In one embodiment, the bus signal detector 302 may include a comparator circuit that generates an output signal, the bus signal 328, in response to detecting that the signal level of the bus activity 212 is within a specified threshold. By way of non-limiting example, such a comparator circuit may be configured as a threshold circuit or a Schmitt trigger, without limitation.

[0036] In one embodiment, the specified threshold may be the minimum voltage value of the measured signal level of the bus activity 318 that is considered potentially valid. In one embodiment, the specified threshold may be a range including an upper threshold limit and a lower threshold limit, and the bus activity 318 may be determined to be potentially valid in response to the measured signal level of the bus activity 318 being within the upper threshold limit and the lower threshold limit.

[0037] As described above, the signal and / or signal level of the wake signal input 312 or bus activity 318 may be due to noise. Further, the signal levels of other valid wake signals 308 and / or bus activity 318 may be affected by interference caused by, as a non-limiting example, electromagnetic radiation (EME).

[0038] In some cases, it may be beneficial to consider not only the signal level but also other characteristics of the valid signal. One such characteristic is the signal duration, i.e., the period during which the activity signaling persists. In particular, time can be measured in units of time, units of clock cycles, or units of data, as non-limiting examples.

[0039] In one or more embodiments, the valid activity detector 306 may be configured to generate an activity signal 326 in response to detecting that the wake signal 308 or bus signal 328 is a valid signal. In one embodiment, the valid activity detector 306 may be configured to detect that these signals are valid signals in response to the measured duration of the wake signal 308 or bus signal 328 meeting a specified threshold in some cases.

[0040] In one embodiment, the valid activity detector 306 may be configured to measure the signal duration of potential valid signals detected at the wake input and / or bus by measuring the signal duration of the wake signal 308 and the signal duration of the bus signal 328. In one embodiment, the valid activity detector 306 may include a digital counter configured to count the number of clock cycles during which the wake signal 308 and / or bus signal 328 is asserted. In the contemplated use cases, the digital counter counts the number of clock cycles corresponding to the duration of the wake signal 308 and the bus signal 328. If the counted number of clock cycles exceeds a specified threshold, the valid activity detector 306 is configured to generate an activity signal 326.

[0041] Figure 4 shows a flowchart of an embodiment of process 400 for detecting valid activity. Process 400 can be used to determine whether a potential valid signal detected by wake signal input 312 is a valid signal and whether a potential valid signal detected by bus activity 318 is a valid signal.

[0042] In operation 402, a clock is generated for executing the activity detection process, and more specifically, for executing operations 404 - 412 of process 400. As described above, the clock can be a low-frequency clock generated during sleep mode.

[0043] In operation 404, process 400 observes one or more signals on a shared transmission medium or at a signal input (e.g., without limitation, a dedicated input for receiving a wake signal). The one or more signals can be valid signals from which to exit sleep mode based on them, but they can also be noise.

[0044] In operation 406, process 400 observes a single amplitude indicative of the presence of one or more potential valid signals present at the input or on the shared transmission medium. In one embodiment, a signal among the one or more signals can be a signal propagated from the input, and another signal can be a signal generated in response to detecting activity (e.g., without limitation, bus activity above a specified level) on the shared transmission medium. In another embodiment, instead of propagating a signal from the input, the signal can be generated in response to detecting the signal level of a potential valid signal at the input.

[0045] In operation 408, process 400 counts the number of clock cycles of the signal duration of the first signal corresponding to the potential valid signal. In the disclosed embodiments, the first signal can be a signal propagated from an input or a signal generated in response to detecting activity in a shared transmission medium. In one embodiment, the first signal includes one or more pulses, and each pulse corresponds to the duration of the potential valid signal.

[0046] In operation 410, process 400 compares the counted number of clock cycles of operation 408 with a threshold. The threshold can, in some cases, be associated with the input or the shared transmission medium. In other words, a first threshold number of clock cycles can be associated with the input, a second threshold number of clock cycles can be associated with the shared transmission medium, and one of the first and second thresholds can be compared with the counted number of clock cycles. These thresholds can be associated with the pulse duration of the valid signal.

[0047] In operation 412, process 400 generates a signal indicating that valid activity has been detected in one of the input or the shared transmission medium. In one embodiment, the signal is generated in response to the comparison of operation 410, and more specifically, in response to determining that the counted number of clock cycles meets or exceeds the threshold.

[0048] FIG. 5 shows a timing diagram 500 of an example of a valid signal detection process using wake signal 308 by process 400. In the use case contemplated by FIG. 5, wake signal 308 is determined to be a valid signal if the measured duration is at least six clock cycles. The duration of signal pulse 502 is three clock cycles, which is less than six clock cycles and is too short to be considered a valid signal in this example. However, the duration of signal pulse 504 is greater than six clock cycles (here, at least ten clock cycles), which is long enough to be considered a valid signal in this example.

[0049] Figure 6 shows a timing diagram 600 of an example of an active signal detection process using the bus signal 328 by the process 400. In the use case contemplated by Figure 6, the bus signal 328 is determined to be valid if the measured duration is at least 99 clock cycles. The duration of the pulse 602 is less than 99 clock cycles, which is too short to be considered a valid signal in this example. However, the duration of 604 is greater than 99 clock cycles, which is long enough to be considered a valid signal in this example, and in response thereto, the activity signal 326 is asserted as the signal pulse 606.

[0050] Returning to Figure 3, in some cases, operating the active activity detector 306 while in the sleep mode may be too power - intensive for the power available in the uninterruptible power domain 216. In some embodiments, a clock 324 that is a low frequency (as described below) may be included and used to clock the active activity detector 306. Further, in some embodiments, the clock generator 310 that generates the clock 324 may be operably coupled to the clock enable 314 and configured to be selectively enabled / disabled in response to the on / off signal 320 generated by the clock enable 314. In one or more embodiments, the clock 324 may be periodically enabled and then disabled by the clock enable 314, more specifically by the on / off signal 320, during the measurement period.

[0051] The clock enable 314 can be configured to provide an on / off signal 320 in response to a power mode (e.g., sleep mode, off mode, normal operation mode) indicated by a mode signal 322 provided by the power mode logic 304. The clock enable 314 can be configured to provide an on / off signal 320 in response to a mode or state indicated by the mode signal 322. As a non-limiting example, when the mode signal 322 indicates the normal operation mode or the off mode, the clock enable 314 can be configured to disable the clock generator 310, and more generally, the activity detector 330. When the mode signal 322 indicates the sleep mode, the clock enable 314 can be configured to enable / disable the clock generator 310, and more generally, the activity detector 330, according to a specified frequency for a specified measurement period.

[0052] The occurrence frequency and duration of the measurement period can be selected, as a non-limiting example, based on an acceptable trade-off between, on the one hand, the sensitivity to wake-up conditions for a given application and, on the other hand, the power limit of the uninterruptible power domain. As a non-limiting example, the occurrence frequency and duration of the measurement can be selected such that the power consumption of the clock generator 310 while it is enabled is below the power limit of the uninterruptible power domain 216.

[0053] The oscillator of the clock generator 310 can be selected, as a non-limiting example, based on an acceptable trade-off between, on the one hand, the need to perform the operations described herein for a given application and, on the other hand, the power limit of the uninterruptible power domain. As a non-limiting example, when the uninterruptible power domain 216 has a maximum supply limit of 35 μA, the oscillator of the clock generator 310 can be selected to generate a signal having a frequency of substantially about 290 kHz to 330 kHz.

[0054] In response to the activity signal 326, the low power mode logic 304 can be configured to generate a wake-up signal 316 for, as a non-limiting example, core logic and / or node power control (not shown).

[0055] FIG. 7 shows a circuit diagram of an embodiment of a signal detection circuit 700 that can be used, for example, to implement the bus signal detector 302 of FIG. 3. In the embodiment shown in FIG. 7, the signal detection circuit 700 includes a signal conditioning stage 702, a comparison stage 708, and a combination stage 722.

[0056] In one or more embodiments, the signal conditioning stage 702 is configured to receive a p-terminal input signal 724 and an n-terminal input signal 726 and, in response, provide a conditioned p-signal 706 and a conditioned n-signal 704. The p-terminal input signal 724 and the n-terminal input signal 726 can be received from respective p and n terminals of a twisted pair cable used for single pair Ethernet.

[0057] In one or more embodiments, the signal conditioning stage 702 includes a 1 / N block 728 and an amplification block 730. In particular, the common mode voltage during some interference cases (e.g., without limitation, bulk current injection, injection molding by gas injection) can be large enough to damage the circuit or chip. The division of the differential voltage and the common mode voltage should theoretically prevent some of these interface cases. The 1 / N block 728 is configured to divide the differential voltage and the common mode voltage of the p-terminal input signal 724 and the n-terminal input signal 726 by N. As a non-limiting example, N can be selected based at least in part on the expected signal characteristics of the twisted pair bus to which the signal detection circuit 700 is operatively coupled. The amplification block 730 is configured to receive the n and p signals divided from the 1 / N block 728, amplify the input differential voltage, adjust the output common mode voltage to a suitable level for the comparison stage 708, thereby obtaining a conditioned p-signal 706 and a conditioned n-signal 704.

[0058] The comparison stage 708 is generally configured to detect a differential signal amplitude and output a detection result. Any suitable differential comparator known to those skilled in the art may be used in the comparison stage 708. In one or more embodiments, the comparison stage 708 may include a comparator 712 and a comparator 710. The comparator 712 and the comparator 710 are each arranged to detect a positive signal amplitude and a negative signal amplitude, respectively. In the embodiment shown in FIG. 7, the output of the signal adjustment stage 702 that becomes the adjusted p signal 706 is operably coupled to the positive input of the comparator 712 and the negative input of the comparator 710. Further, the output of the signal adjustment stage 702 that becomes the adjusted n signal 704 is operably coupled to the negative input of the comparator 712 and the positive input of the comparator 710.

[0059] Each of the comparator 712 and the comparator 710 is configured to detect a differential signal amplitude in response to a threshold voltage 718. In various embodiments, the threshold voltage 718 may be selected based on a particular application. In one embodiment, a value of the threshold voltage 718 lower than the ideal differential signal expected for a particular application may be selected, where the difference between the threshold voltage 718 and the expected value is selected to account for noise and / or generation corners. As a non-limiting example, in a 10 SPE network, the expected differential signal amplitude may be substantially 1V and the threshold voltage 718 may be substantially 400mV.

[0060] In one embodiment, the threshold voltage 718 may be set based on control bits stored in a control register (not shown) of the sleep mode controller 300.

[0061] As described above, the comparator 710 can be used to detect whether a positive differential signal has reached a threshold value. If it has reached, the comparator 710 outputs a "1". Similarly, the comparator 712 can be used to detect whether a negative differential signal has reached a threshold value. If it has reached, the comparator 712 outputs a "1". Since the differential signal toggles continuously between its positive and negative amplitudes, the outputs of the two comparators 710 and 712 do not necessarily result in consecutive "1"s. In order for the circuit 700 to output consecutive "1"s, the combination stage 722 is provided to combine the outputs of the comparators and send out consecutive "1"s when both the positive and negative differential signals have reached the threshold value.

[0062] In FIG. 7, the combination stage 722 is configured to receive a positive differential signal detection 714 and a negative differential signal detection 716 and output a combined differential signal detection 720. In one embodiment, the combination stage 722 can be an OR gate that provides a combined (i.e., substantially continuous signal) differential signal detection 720 in response to the positive differential signal detection 714 and the negative differential signal detection 716. In other words, when the positive differential signal detection 714 is "high" and / or the negative differential signal detection 716 is "high", the combined differential signal detection 720 becomes "high".

[0063] As described elsewhere in this specification, the combined differential signal detection 720 can be used as the bus signal 328 that is used, for example, by the valid activity detector 306 to detect whether the bus signal 328 is a valid signal.

[0064] The terms used in this disclosure, and in particular the terms used in the appended claims (e.g., the body of the appended claims), are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least", the term "comprising" should be interpreted as "comprising but not limited to", etc.).

[0065] In addition, if a specific number of introduced claim recitations are intended, such intent will be explicitly recited in the claim, and if there is no such recitation, such intent does not exist. For example, by way of illustration, the following appended claims may include the use of introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to limit any particular claim that includes such an introduced claim recitation to an embodiment that includes only one of such recitations, even if the same claim includes an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should be interpreted to mean "at least one" or "one or more"). The same is true for the use of definite articles used to introduce claim recitations.

[0066] In addition, even when a specific number recited in an introduced claim is explicitly recited, one of ordinary skill in the art will recognize that such a recitation should be construed to mean at least the recited number (e.g., an explicit recitation of "two XXs" without other modifiers means "at least two XXs" or "two or more XXs"). Further, when a convention similar to "at least one of A, B, and C" or "one or more of A, B, and C" is used, generally, such a construction is intended to include only A, only B, only C, A and B together, A and C together, B and C together, or A, B, and C together.

[0067] Further, any disjunctive word or phrase presenting two or more alternative terms should be understood to contemplate including one of the terms, any of the terms, or both terms in any of the description, claims, or drawings. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B".

[0068] Further non-limiting embodiments of the present disclosure are as follows.

[0069] Embodiment 1: A sleep mode controller for a physical layer of a network segment, wherein the physical layer is an attachment layer between a single pair Ethernet bus and a portion of the network segment, and the controller is an activity detector configured to observe signal levels on the bus and on dedicated inputs and provide an activity detection signal in response to an observed signal level exceeding a specified threshold, and a power manager configured to provide a wake-up signal in response to the activity detection signal.

[0070] Embodiment 2: The sleep mode controller according to Embodiment 1, further comprising an uninterruptible power domain including an activity detector and a power manager.

[0071] Embodiment 3: The sleep mode controller according to any one of Embodiments 1 and 2, comprising a first circuit configured such that an activity detector identifies one or more of a valid wake signal and valid bus activity in a bus.

[0072] Embodiment 4: The sleep mode controller according to any one of Embodiments 1 to 3, wherein the first circuit is a valid signal detector configured to provide an activity detection signal in response to one or more of the signal duration of the wake signal exceeding a first threshold and the signal duration of the bus activity exceeding a second threshold.

[0073] Embodiment 5: The sleep mode controller according to any one of Embodiments 1 to 4, wherein the first threshold is a first number of clock cycles, the second threshold is a second number of clock cycles, and the second number is different from the first number.

[0074] Embodiment 6: The sleep mode controller according to any one of Embodiments 1 to 5, further comprising a bus signal detector configured to detect bus activity having a first signal level and provide a bus signal in response to detecting the bus activity.

[0075] Embodiment 7: The sleep mode controller according to any one of Embodiments 1 to 6, wherein the bus signal detector comprises a signal detection circuit configured to be operably coupled to a single pair of buses and detect a differential signal amplitude in response to a specified threshold.

[0076] Embodiment 8: The sleep mode controller according to any one of Embodiments 1 to 7, wherein the signal detection circuit comprises a comparison stage configured to compare the amplitude of one or more of a positive signal and a negative signal with a specified threshold and provide one or more differential detection signals in response to the comparison.

[0077] Embodiment 9: The sleep mode controller according to any one of Embodiments 1 to 8, wherein the signal detection circuit further includes an adjustment stage configured to adjust an input signal to a specified level for the comparison stage.

[0078] Embodiment 10: The sleep mode controller according to any one of Embodiments 1 to 9, wherein the adjustment stage is configured to adjust the input signal to a specified level by performing one or more of dividing the differential voltage of the input signal, dividing the differential voltage of the input signal, dividing the common mode voltage of the input signal, amplifying the differential voltage of the input signal, and amplifying the common mode voltage of the input signal.

[0079] Embodiment 11: The sleep mode controller according to any one of Embodiments 1 to 10, further comprising a clock generator configured to generate a clock at a first frequency and a clock enable configured to selectively enable and disable the oscillation of the clock generator in response to a power mode.

[0080] Embodiment 12: The sleep mode controller according to any one of Embodiments 1 to 11, wherein the first frequency is selected to enable the operation of the active signal detector in the uninterruptible power supply.

[0081] Embodiment 13: The bus is a single twisted pair Ethernet cable story The sleep mode controller according to any one of Embodiments 1 to 12, which is a shared transmission medium.

[0082] Embodiment 14: The sleep mode controller according to any one of Embodiments 1 to 13, wherein the bus is a single twisted pair Ethernet cable.

[0083] Embodiment 15: A method, comprising: generating a clock; in response to the clock, executing an activity detection process, the activity detection process including observing a signal amplitude indicative of a potential valid signal present on a shared transmission medium, counting a number of clock cycles of at least a portion of a signal duration of the potential valid signal, and generating a signal indicative of valid activity in response to detecting that the counted number of clock cycles exceeds a specified threshold; and executing the steps including the above steps.

[0084] Although the present disclosure has been described herein with respect to specific exemplary embodiments, those skilled in the art will recognize and understand that the invention is not so limited. Rather, numerous additional, deletions, and modifications may be made to the exemplary and illustrative embodiments without departing from the scope of the invention as claimed hereinafter together with their legal equivalents. Additionally, features of one embodiment may be combined with features of another embodiment as contemplated by the inventors, and still be encompassed within the scope of the present disclosure.

Claims

1. An Ethernet network device, a sleep mode controller for a physical layer device of a network segment, the network segment including at least a data link layer device and a media access control device, the physical layer device providing an interface between a single pair Ethernet bus and a portion of the network segment, the sleep mode controller including an activity detector, observing signal levels on the single pair Ethernet bus and on dedicated input pins, and providing an activity detection signal in response to the observed signal levels exceeding a specified threshold, and an activity detector, and a power manager that provides a wake-up signal in response to the activity detection signal. An Ethernet network device comprising.

2. The apparatus according to claim 1, wherein the sleep mode controller comprises an uninterruptible power domain including the activity detector and the power manager.

3. The apparatus according to claim 1, wherein the activity detector comprises a first circuit that distinguishes a valid signal and an invalid signal from one or more of a wake signal and a bus signal on the single pair Ethernet bus.

4. The first circuit comprises a valid signal detector, wherein the valid signal detector provides the activity detection signal in response to one or more of the signal duration of the wake signal exceeding a first threshold and the signal duration of the bus signal exceeding a second threshold. The apparatus according to claim 3.

5. The apparatus according to claim 4, wherein the first threshold is a first number of clock cycles, the second threshold is a second number of clock cycles, and the second number is different from the first number.

6. The sleep mode controller comprises a bus activity detector that detects bus activity having a first signal level, and a bus signal detector that provides the bus signal in response to the detection of the bus activity. The apparatus according to claim 4.

7. The bus signal detector comprises a signal detection circuit operably coupled to a single pair of buses and detecting a differential signal amplitude in response to a specified threshold. The apparatus according to claim 6.

8. The signal detection circuit comprises ​ comparing the amplitude of one or more of the positive and negative signals with the specified threshold value; The apparatus according to claim 7, comprising a comparison stage that provides one or more differential detection signals in response to the comparison.

9. The apparatus according to claim 8, wherein the signal detection circuit comprises an adjustment stage that adjusts an input signal to a specified level for the comparison stage.

10. The adjustment stage divides the differential voltage of the input signal; divides the common mode voltage of the input signal; amplifies the differential voltage of the input signal; amplifies the common mode voltage of the input signal; and adjusts the input signal to the specified level by performing one or more of the above, the apparatus according to claim 9.

11. a clock generator that generates a clock at a first frequency; The apparatus according to claim 6, comprising a clock enable that selectively enables and disables the oscillation of the clock generator in response to a power mode.

12. The apparatus according to claim 11, wherein the first frequency is selected to enable operation of the active signal detector in an uninterruptible power domain.

13. The apparatus according to claim 1, wherein the single pair Ethernet bus is a shared transmission medium.

14. The apparatus according to claim 13, wherein the shared transmission medium is a twisted pair Ethernet cable.

15. A wake detection method, comprising: generating a clock by a sleep mode controller of a physical layer device of a network segment; performing an activity detection process in response to the generated clock by an activity detector of the sleep mode controller, the activity detection process comprising: observing a signal amplitude indicative of a potential active signal present on a shared transmission medium; counting the number of clock cycles of at least a portion of the signal duration of the potential active signal; generating a signal indicative of valid activity in response to detecting that the counted number of clock cycles exceeds a specified threshold; and a wake detection method comprising performing the steps.

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