Bidirectional Variable Gain Amplification

Abstract

An apparatus for bidirectional variable gain amplification is disclosed. In an exemplary aspect, the apparatus includes an antenna element of an antenna array and a wireless transceiver. The wireless transceiver includes a transmit path coupled to the antenna element, a receive path coupled to the antenna element, and a phase shifter disposed in both the transmit path and the receive path. The phase shifter is configured to operate in an active mode and includes a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier.

Description

Technical Field

[0001] Priority

[0001] This patent application claims priority to U.S. Non-Provisional Application No. 16 / 557,974, entitled "BIDIRECTIONAL VARIABLE GAIN AMPLIFICATION," filed on August 30, 2019, which is assigned to the assignee of this specification and is hereby incorporated by reference in its entirety.

[0002]

[0002] The present disclosure generally relates to a wireless transceiver, and more particularly, to a bidirectional variable gain amplifier (VGA) disposed in both the transmit path and the receive path of a wireless transceiver.

Background Art

[0003]

[0003] Electronic devices communicate information using radio frequency (RF) signals. These RF signals enable a user to have conversations with friends, download information, share images, remotely control home devices, receive global positioning information, listen to radio stations, and so on. When communicating over longer distances, it can be difficult to distinguish RF signals from background noise. To address this problem, some electronic devices implement beam steering using an antenna array and a plurality of phase shifters. Beam steering enables an electronic device to increase the transmit signal strength or receive sensitivity in a particular spatial direction. In this way, the electronic device can communicate with other devices over longer distances.

[0004]

[0004] To improve spatial coverage or increase dynamic range, it may be desirable to increase the number of antenna elements in one or more antenna arrays of an electronic device. However, due to the presence of multiple antenna elements, the transceiver of the electronic device may become somewhat large and complex in order to condition and route the signals provided to and received from each of the antenna elements. Thus, depending on the wireless transceiver architecture, it may be difficult to support a large number of antenna elements without degrading system performance or increasing cost and still fit within the size constraints of a given electronic device. The size constraints are particularly relevant for portable electronic devices such as smartphones and wearable devices.

SUMMARY OF THE INVENTION

[0005]

[0005] An apparatus implementing bidirectional variable gain amplification is disclosed. The described technique implements a bidirectional variable gain amplifier that can be placed in both the transmit and receive paths of a wireless transceiver. Thus, both the transmit and receive paths can share the bidirectional variable gain amplifier to save space within the wireless transceiver. As a result, the wireless transceiver can include a relatively smaller number of amplifiers compared to other wireless transceiver designs that utilize separate amplifiers for the transmit and receive paths. By sharing the bidirectional variable gain amplifier between the transmit and receive paths, it is possible to reduce the routing length and routing complexity, which can improve performance through increased isolation, reduced cross talk, reduced coupling, etc.

[0006]

[0006] The bidirectional variable gain amplifier includes a plurality of ports and a T-network having three branch circuits commonly coupled at a common node. Each branch circuit includes a set of transistors, which can include one or more common-gate amplifiers. At least two of the branch circuits include switches, which dynamically bias the channel terminals of the set of transistors to propagate signals between different ones of the plurality of ports of the bidirectional variable gain amplifier. Using the set of transistors and the switches, the bidirectional variable gain amplifier can provide isolation, duplexing, amplification (with a gain greater than or less than one), or some combination thereof. In some cases, the bidirectional variable gain amplifier operates in an active transmit configuration or an active receive configuration to improve beamsteering or dynamic range of a wireless transceiver. Alternatively, the bidirectional variable gain amplifier can operate in a passive configuration to conserve power within the wireless transceiver.

[0007]

[0007] One or more bidirectional variable gain amplifiers can be used to implement various different components within a wireless transceiver. In one example, the bidirectional variable gain amplifier implements a stand-alone amplifier within the transmit path and receive path of the wireless transceiver. If the wireless transceiver includes a plurality of amplifiers coupled to different antenna elements of an antenna array, the plurality of amplifiers are combined and equalize the gain across different transmit and receive paths associated with the antenna elements, compensate for performance differences between individual antenna elements, compensate for differences in routing losses experienced across each of the transmit or receive paths, and can gradually reduce the antenna gain across different antenna elements.

[0008]

[0008] In another example, two bidirectional variable gain amplifiers implement a vector modulator of a phase shifter. Since the two bidirectional variable gain amplifiers can be arranged in both the transmit path and the receive path, the vector modulator can be implemented using a relatively smaller number of variable gain amplifiers (e.g., half the number of variable gain amplifiers) compared to other vector modulators that use separate variable gain amplifiers for transmission and reception. Due to the isolation and duplexing characteristics inherent in the bidirectional variable gain amplifiers described herein, the phase shifter can be bidirectional without using switches to route signals from a shared transceiver path to the transmit path or from the receive path to the shared transceiver path. In this way, the wireless transceiver can achieve improved linearity performance and noise figure performance relative to other transceivers that use switches within the signal propagation path. Further, depending on the operating mode of the bidirectional variable gain amplifier, the phase shifter can operate in an active mode to achieve a higher bit resolution, operate in a passive mode to conserve power, or dynamically switch between the active mode and the passive mode to balance both performance and power consumption.

[0009]

[0009] In an exemplary aspect, an apparatus for bidirectional phase shift is disclosed. The apparatus includes an antenna element of an antenna array and a wireless transceiver. The wireless transceiver includes a transmit path coupled to the antenna element, a receive path coupled to the antenna element, and a phase shifter disposed in both the transmit path and the receive path. The phase shifter is configured to operate in an active mode and includes a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier.

[0010]

[0010] In an exemplary aspect, an apparatus for bidirectional phase shift is disclosed. The apparatus includes an antenna element of an antenna array and a wireless transceiver. The antenna element is configured to transmit a phase-shifted transmit signal and receive an input receive signal. The wireless transceiver includes a transmit path coupled to the antenna element, a receive path coupled to the antenna element, and a phase shifter disposed in both the transmit path and the receive path. The phase shifter is configured to operate in an active mode to generate a phase-shifted transmit signal based on an input transmit signal and generate a phase-shifted receive signal based on an input receive signal. The phase shifter includes vector modulation means for adjusting the amplitude of two split transmit signals related to the input transmit signal and for adjusting the amplitude of two split receive signals related to the input receive signal during a second time period.

[0011]

[0011] In an exemplary aspect, a method for bidirectional phase shift is disclosed. The method comprises operating a phase shifter in an active mode during a first time period and during a second time period. The method also comprises receiving an input transmission signal at a shared node of the phase shifter during the first time period. The method further comprises generating a phase-shifted transmission signal at a transmit node of the phase shifter using a first bidirectional variable gain amplifier of the phase shifter and a second bidirectional variable gain amplifier of the phase shifter during the first time period. The phase-shifted transmission signal is based on the input transmission signal. During the second time period, the method comprises receiving an input reception signal at a receive node of the phase shifter. The method also comprises generating a phase-shifted reception signal at the shared node using the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier during the second time period. The phase-shifted reception signal is based on the input reception signal.

[0012]

[0012] In an exemplary aspect, an apparatus for bidirectional variable gain amplification is disclosed. The apparatus comprises at least one bidirectional variable gain amplifier having two or more ports and a T-shaped circuit network. The two or more ports comprise a first port and a third port. The T-shaped circuit network is coupled between the two or more ports and comprises a common node, a first branch circuit, a second branch circuit, and a third branch circuit. The first branch circuit is coupled between the first port and the common node and comprises a first set of transistors. The second branch circuit is coupled between a supply voltage and the common node and comprises a second set of transistors. The third branch circuit is coupled between the third port and the common node and comprises a third set of transistors.

[0013]

[0013] In an exemplary aspect, a method for bidirectional variable gain amplification is disclosed. The method comprises operating a bidirectional variable gain amplifier in an active transmission configuration during a first time period. The bidirectional variable gain amplifier comprises a first port and a third port. The method also comprises amplifying a first signal propagating from the first port to the third port in the active transmission configuration. Additionally, the method comprises operating the bidirectional variable gain amplifier in an active reception configuration during a second time period. The method further comprises amplifying a second signal propagating from the third port to the first port in the active reception configuration.

Brief Description of the Drawings

[0014]

Figure 1

[0014] A diagram showing an exemplary operating environment for bidirectional variable gain amplification.

Figure 2-1

[0015] A diagram showing an exemplary wireless transceiver including a plurality of phase shifters for performing bidirectional variable gain amplification.

Figure 2-2

[0016] A diagram showing an exemplary wireless transceiver including a plurality of 3-port amplifiers for performing bidirectional variable gain amplification.

Figure 2-3

[0017] A diagram showing an exemplary wireless transceiver including at least one 2-port amplifier for performing bidirectional variable gain amplification.

Figure 3

[0018] A diagram showing an exemplary phase shifter or an exemplary amplifier disposed in both the transmission path and the reception path of a wireless transceiver for bidirectional variable gain amplification.

Figure 4

[0019] A diagram showing an exemplary implementation form of a phase shifter for bidirectional variable gain amplification.

Figure 5

[0020] A diagram showing an exemplary operation of a phase shifter for bidirectional variable gain amplification.

Figure 6-1

[0021] A diagram showing an exemplary implementation form of a bidirectional variable gain amplifier.

Figure 6-2

[0022] Figure showing another exemplary implementation of a bidirectional variable gain amplifier.

Figure 7-1

[0023] Figure showing the active transmission configuration of an exemplary three-port bidirectional variable gain amplifier.

Figure 7-2

[0024] Figure showing the active reception configuration of an exemplary three-port bidirectional variable gain amplifier.

Figure 7-3

[0025] Figure showing the passive configuration of an exemplary three-port bidirectional variable gain amplifier.

Figure 7-4

[0026] Figure showing an exemplary two-port bidirectional variable gain amplifier.

Figure 8

[0027] Exemplary sequence flow diagram regarding switching between different configurations of a bidirectional variable gain amplifier for bidirectional variable gain amplification.

Figure 9

[0028] Flow diagram showing an exemplary process for bidirectional variable gain amplification.

Figure 10

[0029] Another flow diagram showing an exemplary process for bidirectional variable gain amplification. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0030] Designing a wireless transceiver architecture that supports a large number of antenna elements associated with one or more antenna arrays and fits within the size constraints of a given electronic device without adversely affecting system performance or increasing cost can be difficult. This is particularly relevant for portable electronic devices such as smartphones and wearable devices. To address this difficulty, some wireless transceiver designs use passive components that can be bidirectional. Due to the bidirectionality, the passive components can be shared by both the transmission path and the reception path, making it possible to save space within the wireless transceiver. However, some passive components may have limited performance or occupy a larger area relative to their active counterparts. The use of passive components can also increase losses within the wireless transceiver, thereby degrading the signal-to-noise performance of the wireless transceiver. Other wireless transceiver designs use switches to enable the transmission path and the reception path to reuse components. However, switches can add losses, increase routing complexity, degrade linearity performance, and reduce the isolation between the transmission path and the reception path.

[0016]

[0031] In contrast, this specification describes a technique for implementing a bidirectional variable gain amplifier. The described technique implements a bidirectional variable gain amplifier that can be disposed in both the transmission path and the reception path of a wireless transceiver. Thus, both the transmission path and the reception path can share the bidirectional variable gain amplifier to save space within the wireless transceiver. As a result, the wireless transceiver can include a relatively smaller number of amplifiers compared to other wireless transceiver designs that utilize separate amplifiers for the transmission path and the reception path. By sharing the bidirectional variable gain amplifier between the transmission path and the reception path, it is possible to reduce the routing length and routing complexity, which can improve performance through increased isolation, reduced leakage, and reduced coupling.

[0017]

[0032] A bidirectional variable gain amplifier includes a plurality of ports and a T-shaped circuit network having three branch circuits commonly coupled at a common node. Each branch circuit includes a set of transistors, which can include one or more common gate amplifiers. At least two of the branch circuits include switches that dynamically bias the channel terminals of the set of transistors to propagate signals between different ports among the plurality of ports of the bidirectional variable gain amplifier. Using the set of transistors and the switches, the bidirectional variable gain amplifier can provide isolation, duplexing, amplification (with a gain greater than or less than 1), or some combination thereof. In some cases, the bidirectional variable gain amplifier operates in an active transmit configuration or an active receive configuration to improve beam steering or dynamic range of a wireless transceiver. Alternatively, the bidirectional variable gain amplifier can operate in a passive configuration to conserve power within the wireless transceiver.

[0018]

[0033] One or more bidirectional variable gain amplifiers can be used to implement various different components within a wireless transceiver. In one example, the bidirectional variable gain amplifier implements a stand-alone amplifier within the transmit path and the receive path of the wireless transceiver. If the wireless transceiver includes a plurality of amplifiers coupled to different antenna elements of an antenna array, the plurality of amplifiers can be identical and equalize gain across different transmit paths and receive paths associated with the antenna elements, compensate for performance differences between individual antenna elements, compensate for differences in routing losses experienced across each of the transmit paths or receive paths, and taper antenna gain across different antenna elements, among other things.

[0019]

[0034] In another example, two bidirectional variable gain amplifiers implement the vector modulator of the phase shifter. Since the two bidirectional variable gain amplifiers can be placed in both the transmit path and the receive path, the vector modulator can be implemented using a relatively smaller number of variable gain amplifiers (e.g., half the number of variable gain amplifiers) compared to other vector modulators that use separate variable gain amplifiers for transmission and reception. Due to the isolation and duplexing characteristics inherent in the bidirectional variable gain amplifier described herein, the phase shifter can be bidirectional without routing signals through switches from the shared transceiver path to the transmit path or from the receive path to the shared transceiver path. In this way, the wireless transceiver can achieve improved linearity performance and noise figure performance relative to other transceivers that use switches within the signal propagation path. Further, depending on the operating mode of the bidirectional variable gain amplifier, the phase shifter can operate in an active mode to achieve a higher bit resolution, operate in a passive mode to conserve power, or dynamically switch between the active mode and the passive mode to balance both performance and power consumption.

[0020]

[0035] FIG. 1 shows an exemplary operating environment 100 for bidirectional variable gain amplification. In environment 100, computing device 102 communicates with base station 104 via wireless communication link 106 (wireless link 106). In this example, computing device 102 is depicted as a smartphone. However, computing device 102 can be implemented as any suitable computing or electronic device, such as a modem, cellular base station, broadband router, access point, cellular phone, gaming device, navigation device, media device, laptop computer, desktop computer, tablet computer, wearable computer, server, network-attached storage (NAS) device, smart appliance or other Internet of Things (IoT) device, medical device, sensor or security device, vehicle-based communication system, wireless device, etc.

[0021]

[0036] Base station 104 communicates with computing device 102 via wireless link 106, and wireless link 106 can be implemented as any suitable type of wireless link. Base station 104 is depicted as a tower of a cellular network, but can represent or be implemented as another device, such as a satellite, server device, terrestrial television broadcast tower, access point, peer-to-peer device, mesh network node, fiber optic line, etc. Thus, computing device 102 can communicate with base station 104 or another device via a wired connection, wireless connection, or a combination thereof.

[0022]

[0037] Wireless link 106 can include a downlink for data or control information communicated from base station 104 to computing device 102, or an uplink for other data or control information communicated from computing device 102 to base station 104. Wireless link 106 can be implemented using any suitable communication protocol or standard, such as second generation (2G), third generation (3G), fourth generation (4G), or fifth generation (5G) cellular, IEEE 802.11 (e.g., Wi-Fi (registered trademark)), IEEE 802.15 (e.g., Bluetooth (registered trademark)), IEEE 802.16 (e.g., WiMAX (registered trademark)), and the like. In some implementations, wireless link 106 provides power wirelessly, and base station 104 includes a power source.

[0023]

[0038] As shown, computing device 102 includes an application processor 108 and a computer-readable storage medium (CRM) 110. Application processor 108 can include any type of processor that executes processor-executable code stored by CRM 110, such as a multi-core processor. CRM 110 can include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., disks), and the like. In the context of the present disclosure, CRM 110 is implemented to store instructions 112, data 114, and other information of computing device 102, and thus does not include transient propagated signals or carrier waves.

[0024]

[0039] Computing device 102 may also include an input / output port 116 (I / O port 116) and a display 118. The I / O port 116 enables data exchange or interaction with other devices, networks, or users. The I / O port 116 may include a serial port (e.g., a Universal Serial Bus (USB) port), a parallel port, an audio port, an infrared (IR) port, a user interface port such as a touch screen, etc. The display 118 presents the graphics of the computing device 102, such as a user interface related to an operating system, program, or application. Alternatively or additionally, the display 118 may be implemented as a display port or a virtual interface through which the graphical content of the computing device 102 is presented.

[0025]

[0040] The wireless transceiver 120 of the computing device 102 provides connectivity to respective networks and other electronic devices connected to the network. Alternatively or additionally, the computing device 102 may also include a wired transceiver such as an Ethernet (registered trademark) or fiber optic interface for communication via a local network, intranet, or the Internet. The wireless transceiver 120 may facilitate communication via any suitable type of wireless network, such as a Wireless Local Area Network (WLAN), a Peer-to-Peer (P2P) network, a mesh network, a cellular network, a Wireless Wide Area Network (WWAN), and / or a Wireless Personal Area Network (WPAN). In the context of the exemplary environment 100, the wireless transceiver 120 enables the computing device 102 to communicate with the base station 104 and the network connected to the base station 104. However, the wireless transceiver 120 can also enable the computing device 102 to communicate "directly" with other devices or networks.

[0026]

[0041] The wireless transceiver 120 includes circuitry and logic for transmitting and receiving communication signals via the antenna array 132. The components of the wireless transceiver 120 can include amplifiers, switches, mixers, analog-to-digital converters, filters, etc. for conditioning the communication signals (e.g., for generating or processing the signals). The wireless transceiver 120 can also include logic for performing in-phase / quadrature (I / Q) operations such as synthesis, encoding, modulation, decoding, demodulation, etc. In some cases, the components of the wireless transceiver 120 are implemented as separate receiver and transmitter entities. Additionally or alternatively, the wireless transceiver 120 can be implemented using multiple or different sections (e.g., separate transmit and receive paths) to implement the respective receive and transmit operations. Generally, the wireless transceiver 120 processes data and / or signals related to communicating the data of the computing device 102 using the antenna array 132.

[0027]

[0042] To employ bidirectional variable gain amplification, the wireless transceiver 120 can operate, for example, as a time-division duplex wireless transceiver. Thus, the wireless transceiver 120 can generate an uplink signal during one time slot and process a downlink signal during another time slot.

[0028]

[0043] The wireless transceiver 120 includes at least one phase shifter 122, at least one three-port amplifier 124, or at least one two-port amplifier 138. The phase shifter 122 adjusts the phase of the signal transmitted and received via the antenna array 132. Using the phase shifter 122, the wireless transceiver 120 can adopt beam steering techniques to improve the dynamic range performance. Although the vector modulator of the phase shifter 122 is shown in FIGS. 4 and 5, this vector modulator can be implemented using at least two bidirectional variable gain amplifiers 126-1 and 126-2. In this example, the two bidirectional variable gain amplifiers 126-1 and 126-2 include two three-port bidirectional variable gain amplifiers, and examples of these are shown in FIGS. 7-1 to 7-3.

[0029]

[0044] The phase shifter 122 can operate in the active mode 134 or the passive mode 136 based on the configuration of the bidirectional variable gain amplifiers 126-1 and 126-2. Generally, the bit resolution performance of the phase shifter 122 depends on the active mode 134 or the passive mode 136. In the active mode 134, the phase shifter 122 can achieve a resolution of, for example, at least about 5 bits. However, in the passive mode 136, the phase shifter 122 can achieve a resolution of about 3 bits or less. The phase shifter 122 can also operate using a resolution of less than 5 bits in the active mode 134, but the active mode 134 consumes relatively more power compared to the passive mode 136.

[0030]

[0045] The 3-port amplifier 124 and the 2-port amplifier 138 adjust the amplitude of the signals transmitted and received via the antenna array 132. In other words, the 3-port amplifier 124 and the 2-port amplifier 138 are components that can increase the magnitude of a signal (e.g., provide amplification by a factor greater than 1), decrease the magnitude of a signal (e.g., provide attenuation or amplification by a factor less than 1 but greater than 0), or pass the signal without changing its magnitude (e.g., provide buffering or amplification by a factor equal to 1).

[0031]

[0046] The 3-port amplifier 124 can be implemented using at least one bidirectional variable gain amplifier 126-3. In this example, the bidirectional variable gain amplifier 126-3 includes a 3-port bidirectional variable gain amplifier, and this example is shown in FIGS. 7-1 to 7-3. Similarly, the 2-port amplifier 138 can be implemented using at least one other bidirectional variable gain amplifier 126-4. An exemplary implementation of the bidirectional variable gain amplifier 126-4 includes a 2-port bidirectional variable gain amplifier, which is further described with respect to FIG. 7-4.

[0032]

[0047] Similar to the phase shifter 122, the 3-port amplifier 124 and the 2-port amplifier 138 can operate in the active mode 134 or the passive mode 136 based on the configurations of their respective bidirectional variable gain amplifiers 126-3 and 126-4. In the active mode 134, the 3-port amplifier 124 and the 2-port amplifier 138 operate as an amplifier that amplifies the signal or as a buffer for passing the signal. While operating in the active mode 134, the 3-port amplifier 124 and the 2-port amplifier 138 have a gain of 0 dB or more. However, in the passive mode 136, the 3-port amplifier 124 and the 2-port amplifier 138 operate as an attenuator and attenuate the amplitude of the signal. While operating in the passive mode 136, the 3-port amplifier 124 and the 2-port amplifier 138 have an effective gain of less than 0 dB.

[0033]

[0048] By means of the bidirectional variable gain amplifiers 126-1 to 126-4, the phase shifter 122, the 3-port amplifier 124, and the 2-port amplifier 138 can be operated bidirectionally, and thus can be arranged in the transmission path and the reception path of the wireless transceiver 120 as further described with respect to FIGS. 2-1 to 3. Therefore, the wireless transceiver 120 can condition signals for both transmission and reception using the phase shifter 122, the 3-port amplifier 124, or the 2-port amplifier 138. By sharing the phase shifter 122, the 3-port amplifier 124, or the 2-port amplifier 138 between the transmission path and the reception path, the overall footprint of the wireless transceiver 120 can be made relatively smaller compared to other wireless transceivers including separate phase shifters and / or amplifiers within the transmission path and within the reception path.

[0034]

[0049] In an exemplary implementation, each of the bidirectional variable gain amplifiers 126-1 to 126-4 includes a T-shaped circuit network including three sets of transistors. Each set of transistors includes at least one transistor. Generally, the three sets of transistors operate as a set of input transistors, a set of output transistors, and a set of current-steering transistors, respectively. The operation of one or more of the three sets of transistors may vary based on the configuration of the bidirectional variable gain amplifier 126. For example, during the transmission configuration, the first set of transistors operates as a set of input transistors. However, during the reception configuration, the first set of these transistors operates as a set of output transistors. An exemplary implementation of the bidirectional variable gain amplifier 126 is further described with respect to FIGS. 6-1 and 6-2, and an exemplary configuration of the bidirectional variable gain amplifier 126 is further described with respect to FIGS. 7-1 to 7-4.

[0035]

[0050] Using three sets of transistors, the bidirectional variable gain amplifier 126 provides isolation, duplexing, amplification, or some combination thereof. Since the bidirectional variable gain amplifier 126 enables both an active mode 134 and a passive mode 136, the term amplification can, unless the context otherwise specifies, represent amplification, attenuation, or buffering. The bidirectional variable gain amplifier 126 can support wideband (e.g., broadband) operation and process signals having radio frequencies on the order of gigahertz (GHz) including signals within the extremely-high frequency (EHF) spectrum (e.g., for signals having frequencies between approximately 24 GHz and 44 GHz). Generally, the bidirectional variable gain amplifier 126 can implement bidirectional variable gain as described herein for amplifiers, phase shifters, and other components, at least in part.

[0036]

[0051] The wireless transceiver 120 also includes a control circuit 130, which can be implemented within the wireless transceiver 120 or separately from the wireless transceiver 120, such as a modem, a general-purpose processor, a controller, fixed logic circuitry, hard-coded logic, some combination thereof, and the like. The components of the control circuit 130 can be localized in one module (e.g., an integrated circuit chip) or distributed across multiple modules. Although not explicitly shown, the control circuit 130 can also include at least one CRM (e.g., CRM 110), can include a portion of CRM 110, or can access CRM 110 to obtain computer-readable instructions (e.g., instructions 112). The control circuit 130 controls the wireless transceiver 120, at least in part, and enables wireless communication to be performed.

[0037]

[0052] The control circuit 130 is coupled to the bidirectional variable gain amplifiers 126-1 to 126-4 and controls the respective configurations of the bidirectional variable gain amplifiers 126-1 to 126-4. Through the configurations of the bidirectional variable gain amplifiers 126-1 to 126-4, the control circuit 130 controls the operating modes of the phase shifter 122, the three-port amplifier 124, and the two-port amplifier 138. In some cases, the control circuit 130 causes the phase shifter 122, the three-port amplifier 124, and / or the two-port amplifier 138 to dynamically switch between the active mode 134 and the passive mode 136 based on the current operating mode of the wireless transceiver 120. The various types of operating modes may include a transmit mode, a receive mode, various spatial coverage modes, various frequency modes (e.g., a high-frequency mode or a low-frequency mode), various power modes (e.g., a low-output mode or a high-output mode), various resource control states (e.g., a connected mode, an inactive mode, or an idle mode), various modulation modes (e.g., a low-order modulation mode such as a quadrature phase shift keying (QPSK) mode, or a high-order modulation mode such as 64 quadrature amplitude modulation (QAM) or 256QAM), and the like.

[0038]

[0053] In some cases, the control circuit 130 specifies the relative phase offsets between the plurality of phase shifters 122 respectively associated with different antenna elements of the antenna array 132. By controlling the relative phase offsets, the control circuit 130 can use beam steering techniques to increase the transmit power or enhance the receive sensitivity along a specific direction. In other cases, the control circuit 130 specifies the relative amplitude offsets between the plurality of three-port amplifiers 124 coupled to the plurality of antenna elements. By controlling the relative amplitude offsets, the control circuit 130 can equalize the gains across different transmit and receive paths associated with the antenna elements, compensate for performance differences between individual antenna elements, compensate for differences in routing losses experienced across each of the transmit or receive paths, gradually reduce the antenna gain across different antenna elements, and the like.

[0039]

[0054] FIG. 2-1 shows an exemplary wireless transceiver 120 that includes a plurality of phase shifters 122-1 to 122-N that perform bidirectional variable gain amplification, where N represents a positive integer. In the depicted configuration, the antenna array 132 includes a plurality of antenna elements 202-1 to 202-N. The number of antenna elements 202-1 to 202-N is shown as being equal to the number of phase shifters 122-1 to 122-N. In other implementations, these numbers may be different. The antenna elements 202-1 to 202-N are each coupled to antenna nodes 204-1 to 204-N of the wireless transceiver 120. Both the antenna array 132 and the wireless transceiver 120 transmit uplink signals and receive downlink signals during different time slots.

[0040]

[0055] The wireless transceiver includes a plurality of transmission paths in which a plurality of power amplifiers 206-1 to 206-N are each coupled to antenna nodes 204-1 to 204-N. The wireless transceiver 120 also includes a plurality of reception paths in which a plurality of low noise amplifiers 208-1 to 208-N are each coupled to antenna nodes 204-1 to 204-N. The phase shifters 122-1 to 122-N are each coupled (e.g., indirectly or directly) to the power amplifiers 206-1 to 206-N and the low noise amplifiers 208-1 to 208-N.

[0041]

[0056] The wireless transceiver 120 also includes a combining circuit 210, and the combining circuit 210 is coupled to the phase shifters 122-1 to 122-N. The combining circuit 210 operates as a splitter or a combiner based on the operating mode of the wireless transceiver 120. The combining circuit 210 may be coupled to other components within the wireless transceiver 120 not shown in FIG. 2, such as mixers, filters, other amplifiers, analog-to-digital converters, digital-to-analog converters, etc. In some cases, the combining circuit 210 comprises a single stage that combines N signals together into a single signal or splits a single signal into N signals. In other cases, the combining circuit 210 comprises multiple stages that incrementally combine N signals together to produce a single signal or incrementally split a single signal into N signals.

[0042]

[0057] The control circuit 130 is coupled to the phase shifters 122-1 to 122-N and generates an offset signal 212 and a configuration signal 214. The offset signal 212 or the configuration signal 214 can comprise a plurality of signals that are sent to the respective phase shifters 122-1 to 122-N. Alternatively, the offset signal 212 or the configuration signal 214 can also comprise a multi-bit signal, and each bit or each group of bits controls the respective phase shifters 122-1 to 122-N.

[0043]

[0058] Using the offset signal 212, the control circuit 130 controls, for example, the relative phase offsets applied across the phase shifters 122-1 to 122-N. The control circuit 130 can determine the relative phase offset based on a target direction selected to increase the transmission power or enhance the sensitivity. In some cases, the target direction is based on a known direction to the base station 104 in FIG. 1.

[0044]

[0059] Using the configuration signal 214, the control circuit 130 operates the phase shifters 122-1 to 122-N in the active mode 134 or the passive mode 136. The control circuit 130 can determine the mode at a particular point in time based on the number of antenna elements 202-1 to 202-N, which can vary across different types of computing devices 102. The control circuit 130 can also determine the mode based on the available power based on the target dynamic range performance, which can vary based on the selected carrier frequency, the current distance between the computing device 102 and the base station 104, etc. Generally, the active mode 134 improves the performance of the wireless transceiver 120 and consumes relatively more power compared to the passive mode 136.

[0045]

[0060] During the transmission operation, the wireless transceiver 120 generates an input signal (not shown), and the combining circuit 210 divides this input signal into a plurality of input transmission signals 216-1 to 216-N. The plurality of input transmission signals 216-1 to 216-N may have similar amplitudes and similar phases. The phase shifters 122-1 to 122-N each generate modified transmit signals 218-1 to 218-N based on the input transmission signals 216-1 to 216-N. The modified transmit signals 218-1 to 218-N may have relatively different phases or different amplitudes compared to the input transmission signals 216-1 to 216-N. The power amplifiers 206-1 to 206-N amplify the modified transmit signals 218-1 to 218-N for transmission via the antenna elements 202-1 to 202-N. The signal to be transmitted can represent an uplink signal.

[0046]

[0061] During the reception operation, the antenna array 132 can receive a downlink signal (not shown). The low-noise amplifiers 208-1 to 208-N generate input received signals 220-1 to 220-N based on the downlink signal. The relative phases of the input received signals 220-1 to 220-N may differ depending on the location difference between the antenna elements 202-1 and 202-N and the angle of arrival of the downlink signal. Similarly, the relative amplitudes of the input received signals 220-1 to 220-N may also differ depending on the location difference between the antenna elements 202-1 and 202-N, the routing length difference between the antenna elements 202-1 to 202-N and the antenna nodes 204-1 to 204-N, or the performance difference of the antenna elements 202-1 to 202-N.

[0047]

[0062] The phase shifters 122-1 to 122-N generate corrected received signals 222-1 to 222-N based on the input received signals 220-1 to 220-N. For example, the phase shifters 122-1 to 122-N can compensate for the relative phase difference between the input received signals 220-1 to 220-N by making the corrected received signals 222-1 to 222-N have substantially similar phases. In other words, the corrected received signals 222-1 to 222-N generally have a smaller relative phase offset compared to the relative phase offset between the input received signals 220-1 to 220-N. In this way, the corrected received signals 222-1 to 222-N can be constructively combined via the combining circuit 210 to enhance sensitivity. By these phase-shifting adjustments, the computing device 102 can communicate with other devices at a greater distance.

[0048]

[0063] FIG. 2-2 shows an exemplary wireless transceiver 120 that includes a plurality of three-port amplifiers 124-1 to 124-N that perform bidirectional variable gain amplification. The wireless transceiver 120 of FIG. 2-2 is similar to the wireless transceiver 120 of FIG. 2-1, except that the wireless transceiver 120 of FIG. 2-2 includes three-port amplifiers 124-1 to 124-N and passive phase shifters 224-1 to 224-N instead of phase shifters 122-1 to 122-N. The number of antenna elements 202-1 to 202-N is shown as being equal to the number of three-port amplifiers 124-1 to 124-N. In other implementations, these numbers may be different.

[0049]

[0064] The three-port amplifiers 124-1 to 124-N are each coupled (e.g., indirectly or directly coupled) to a power amplifier 206-1 to 206-N and a low-noise amplifier 208-1 to 208-N. The passive phase shifters 224-1 to 224-N are each coupled between the respective three-port amplifier 124-1 to 124-N and a coupling circuit 210.

[0050]

[0065] The control circuit 130 is coupled to the three-port amplifiers 124-1 to 124-N and generates an offset signal 212 and a configuration signal 214. The offset signal 212 or the configuration signal 214 can comprise a plurality of signals that are sent to the respective three-port amplifiers 124-1 to 124-N. Alternatively, the offset signal 212 or the configuration signal 214 can comprise a multi-bit signal, with each bit or each group of bits controlling the respective three-port amplifiers 124-1 to 124-N. Using the offset signal 212, the control circuit 130 controls, for example, the relative amplitude offset applied across the amplifiers 124-1 to 124-N. The control circuit 130 can determine the relative amplitude offset based on a look-up table or based on a selected radiation pattern of the antenna array 132.

[0051]

[0066] Using the configuration signal 214, the control circuit 130 operates the three-port amplifiers 124-1 to 124-N in the active mode 134 or the passive mode 136. The control circuit 130 can determine the mode at a particular point in time based on the number of antenna elements 202-1 to 202-N, which can vary across different types of computing devices 102. The control circuit 130 can also determine the mode based on the available power based on the target dynamic range performance, which can vary based on, for example, the selected carrier frequency and the current distance between the computing device 102 and the base station 104. Generally, the active mode 134 improves the performance of the wireless transceiver 120 and consumes relatively more power compared to the passive mode 136.

[0052]

[0067] In some implementations, the three-port amplifiers 124-1 to 124-N operate in the passive mode 136. Thus, the three-port amplifiers 124-1 to 124-N act as switches that allow the power amplifiers 206-1 to 206-N and the low-noise amplifiers 208-1 to 208-N to be coupled to the respective passive phase shifters 224-1 to 224-N and separated from each other. By using the three-port amplifiers 124-1 to 124-N instead of switches to provide this duplexing capability, the wireless transceiver 120 can experience relatively less loss compared to implementations that use switches.

[0053]

[0068] In other implementations, the three-port amplifiers 124-1 to 124-N operate in the active mode 134 as will be described further below. By operating in the active mode 134, the three-port amplifiers 124-1 to 124-N can compensate for at least some of the losses introduced by the passive phase shifters 224-1 to 224-N. In some cases, the three-port amplifiers 124-1 to 124-N are implemented as part of the first (e.g., driver) stage of the power amplifiers 206-1 to 206-N and the last stage of the low-noise amplifiers 208-1 to 208-N.

[0054]

[0069] During the transmission operation, each of the 3-port amplifiers 124-1 to 124-N generates a modified transmission signal 218-1 to 218-N based on the input transmission signals 216-1 to 216-N. The modified transmission signals 218-1 to 218-N may have different amplitudes relative to the input transmission signals 216-1 to 216-N.

[0055]

[0070] During the reception operation, the relative amplitudes of the input reception signals 220-1 to 220-N may be different due to differences in the locations of the antenna elements 202-1 and 202-N, differences in the routing lengths between the antenna elements 202-1 to 202-N and the antenna nodes 204-1 to 204-N, or differences in the performance of the antenna elements 202-1 to 202-N. The 3-port amplifiers 124-1 to 124-N generate modified reception signals 222-1 to 222-N based on the input reception signals 220-1 to 220-N. For example, the 3-port amplifiers 124-1 to 124-N can compensate for the relative amplitude differences between the input reception signals 220-1 to 220-N by adjusting the amplitudes of the modified reception signals 222-1 to 222-N. In some cases, the modified reception signals 222-1 to 222-N may have a smaller relative amplitude offset compared to the relative amplitude offset between the input reception signals 220-1 to 220-N. By adapting the amplitudes of the modified reception signals 222-1 to 222-N, the amplifiers 124-1 to 124-N can also increase the sensitivity of the wireless transceiver 120. Using these phase shifts or amplitude adjustments, the computing device 102 can communicate with other devices at a greater distance.

[0056]

[0071] FIG. 2-3 shows an exemplary wireless transceiver 120 that includes at least one 2-port amplifier 138 that performs bidirectional variable gain amplification. The 2-port amplifier 138 is coupled to the coupling circuit 210 of FIG. 2-1 or FIG. 2-2. In other words, the components between the antenna nodes 204-1 to 204-N and the coupling circuit 210 can include the phase shifters 122-1 to 122-N of FIG. 2-1 or the 3-port amplifiers 124-1 to 124-N of FIG. 2-2.

[0057]

[0072] In the described configuration, the wireless transceiver 120 includes at least one switching circuit 226, at least one transmission path 228, and at least one reception path 230. The switching circuit 226 is coupled to the two-port amplifier 138, the transmission path 228, and the reception path 230. An exemplary implementation of the switching circuit 226 includes at least one switch or at least one multiplexer. The switching circuit 226 selectively connects the transmission path 228 or the reception path 230 to the two-port amplifier 138.

[0058]

[0073] The transmission path 228 can include at least one up-conversion mixer, at least one filter, or at least one digital-to-analog converter. Similarly, the reception path 230 can include at least one down-conversion mixer, at least one filter, or at least one analog-to-digital converter. Generally, the transmission path 228 and the reception path 230 include components designed for this particular path or components specific to this particular path. In some cases, one or more of these components are not bidirectional.

[0059]

[0074] The control circuit 130 is coupled to the two-port amplifier 138 and generates a configuration signal 214. Using the configuration signal 214, the control circuit 130 operates the two-port amplifier 138 in the active mode 134 or the passive mode 136. The control circuit 130 can determine the mode, for example, based on the available power.

[0060]

[0075] During the transmission operation, the transmission path 228 generates an input transmission signal 216. The switching circuit 226 connects the transmission path 228 to the input port of the two-port amplifier 138. In response to the configuration signal 214, the two-port amplifier 138 amplifies, passes, or attenuates the input transmission signal 216. The combining circuit 210 divides the input transmission signal 216 into input transmission signals 216-1 to 216-N.

[0061]

[0076] During the receiving operation, the combining circuit 210 combines the modified received signals 222-1 to 222-N to generate a modified received signal 222. The two-port amplifier 138 amplifies, passes, or attenuates the modified received signal 222. The switching circuit 226 connects the output port of the two-port amplifier 138 to the receiving path 230 and passes the modified received signal 222 to the receiving path 230.

[0062]

[0077] Although not shown, other implementations of the wireless transceiver 120 can include a plurality of two-port amplifiers 138-1 to 138-N coupled in series to the phase shifters 122-1 to 122-N. In general, the two-port amplifier 138 can be implemented as part of the transmitting path 228 (not shown), as part of the receiving path 230 (not shown), or as part of both the transmitting path 228 and the receiving path 230 (e.g., within a shared transceiver path) (shown in FIGS. 2-3). Within the transmitting path 228, the two-port amplifier 138 conditions the signal for transmission. Similarly, within the receiving path 230, the two-port amplifier 138 conditions the signal for reception. However, within the shared transceiver path, the two-port amplifier 138 conditions the signal for both transmission and reception (e.g., conditions both the input transmission signal 216 and the modified received signal 222). The relationship between the transmitting path, the receiving path, and the shared transceiver path will be further described later with respect to FIG. 3.

[0063]

[0078] Figure 3 shows an exemplary phase shifter 122 or an exemplary three-port amplifier 124 that is disposed in both the transmit path 302 and the receive path 304 of the wireless transceiver 120 for bidirectional variable gain amplification. In the depicted configuration, the phase shifter 122 or the three-port amplifier 124 represents one of the phase shifters 122-1 through 122-N or the three-port amplifiers 124-1 through 124-N shown in FIG. 2. Each of the transmit path 302 and the receive path 304 includes a power amplifier 206 (e.g., one of the power amplifiers 206-1 through 206-N of FIG. 2) and a low noise amplifier 208 (e.g., one of the low noise amplifiers 208-1 through 208-N of FIG. 2). Both the power amplifier 206 and the low noise amplifier 208 are coupled to one of the antenna nodes 204-1 through 204-N (of FIG. 2). Although not shown, the transmit path 302 and the receive path 304 may also each include the transmit path 228 and the receive path 230 of FIGS. 2-3.

[0064]

[0079] The phase shifter 122 or the three-port amplifier 124 is shown as being disposed in both the transmit path 302 and the receive path 304. In other words, the phase shifter 122 or the three-port amplifier 124 is electrically coupled to other components within the transmit path 302 and the receive path 304, such as the power amplifier 206 and the low noise amplifier 208. In this way, a signal propagating through the transmit path 302 propagates through the phase shifter 122 or the three-port amplifier 124. Additionally, a signal propagating through the receive path 304 also propagates through the phase shifter 122 or the three-port amplifier 124.

[0065]

[0080] The phase shifter 122 or the three-port amplifier 124 includes a shared node 306 disposed in both the transmit path 302 and the receive path 304, a transmit node 308 disposed in the transmit path 302, and a receive node 310 disposed in the receive path 304. Although not shown, the shared node 306 may be coupled to other components within the transmit path 302 and / or the receive path 304, such as mixers or the coupling circuit 210 (of FIG. 2).

[0066]

[0081] Of at least a portion of the phase shifter 122 or the 3-port amplifier 124, the transmission path 302 and the reception path 304 share common components along the shared transceiver path 312. This is shown by the fact that a dashed-line portion of the transmission path 302 and a dotted-line portion of the reception path 304 are included within the dashed lines of the shared transceiver path 312. In this way, the shared transceiver path 312 represents a common path shared by both the transmission path 302 and the reception path 304 (e.g., the shared transceiver path 312 includes at least a portion of both the transmission path 302 and the reception path 304).

[0067]

[0082] Although not shown, the 2-port amplifier 138 of FIGS. 2-3 can be implemented as part of the shared transceiver path 312. The bidirectional variable gain amplifiers 126-1 and 126-2 of the phase shifter 122, the bidirectional variable gain amplifier 126-3 of the 3-port amplifier 124, and the bidirectional variable gain amplifier 126-4 of the 2-port amplifier 138 (e.g., of FIGS. 1 and / or 3) are exemplary components arranged in the shared transceiver path 312.

[0068]

[0083] FIG. 4 shows an exemplary implementation of the phase shifter 122 for bidirectional variable gain amplification. In the depicted configuration, the phase shifter 122 includes a quadrature coupling circuit 402, a vector modulator 404, a combiner 406, and a splitter 408. The vector modulator 404 includes the bidirectional variable gain amplifiers 126-1 and 126-2 of FIG. 1. Using the bidirectional variable gain amplifiers 126-1 and 126-2, the phase shifter 122 can occupy less space compared to other phase shifter designs that use separate variable gain amplifiers for transmission and reception.

[0069]

[0084] The phase shifter 122 includes components arranged along the transmission path 302, components arranged along the reception path 304, and components arranged along the shared transceiver path 312 (e.g., components shared by both the transmission path 302 and the reception path 304). In particular, the transmission path 302 includes a combiner 406, and the reception path 304 includes a splitter 408. The vector modulator 404 provides an interface that merges the transmission path 302 and the reception path 304 into the shared transceiver path 312 and splits the transmission path 302 and the reception path 304 from the shared transceiver path 312. The shared transceiver path 312 includes the vector modulator 404 and the quadrature coupling circuit 402, and both of these can be bi-directional components.

[0070]

[0085] The quadrature coupling circuit 402 includes a shared port 410 coupled to the shared node 306 and two orthogonal ports 412-1 and 412-2. In some implementations, the quadrature coupling circuit 402 is implemented using passive components such as a quadrature coupler (e.g., a 3 decibel (3 dB) 90-degree hybrid coupler). Generally, the quadrature coupling circuit 402 provides a phase delta of approximately 90 degrees between the orthogonal ports 412-1 and 412-2. During transmission, the quadrature coupling circuit 402 generates orthogonal signals at the orthogonal ports 412-1 and 412-2 respectively based on the input signal received at the shared port 410. Due to the 90-degree phase delta, the phases of the orthogonal signals differ by approximately 90 degrees. During reception, the quadrature coupling circuit 402 generates an output signal at the shared port 410 based on the in-phase signals received at the orthogonal ports 412-1 and 412-2 respectively. Due to the 90-degree phase delta, the output signal has a phase that represents the sum of the phase of one of the in-phase signals and the phase of another signal that is shifted by 90 degrees from the in-phase signals.

[0071]

[0086] Combiner 406 and splitter 408 are respectively coupled to transmission node 308 and reception node 310. In contrast to the orthogonal coupling circuit 402, combiner 406 and splitter 408 substantially maintain the relative phase offset between the signals received or generated respectively. In other words, combiner 406 combines a plurality of signals at the combined output without substantially shifting the phases of the plurality of signals relative to each other, and splitter 408 generates a plurality of signals that are approximately in phase with each other.

[0072]

[0087] Types of components that can implement combiner 406 or splitter 408 include Wilkinson circuits (e.g., Wilkinson combiners or splitters), T-junctions, transformers, current addition nodes, matching circuit networks, and the like. In an exemplary implementation of combiner 406 using a current addition node, the output of vector modulator 404 coupled to combiner 406 may be a current mode output from a transistor within vector modulator 404, and combiner 406 provides a load impedance to each output of vector modulator 404. In an exemplary implementation of splitter 408 using a matching circuit network, the input to vector modulator 404 from splitter 408 may have an impedance Z1, and splitter 408 provides an impedance transformation from Z1 to Z2*2. In this way, the two amplifiers within vector modulator 404 provide the combined impedance Z2 to reception node 310 through splitter 408. Impedance Z2 can be matched to the output impedance of low noise amplifier 208 coupled to reception node 310.

[0073]

[0088] The vector modulator 404 is coupled between the quadrature combining circuit 402, the combiner 406, and the splitter 408. The vector modulator 404 adjusts the amplitude of a signal provided by the quadrature combining circuit 402 for a transmission operation or by the splitter 408 for a reception operation. The vector modulator 404 includes two bidirectional variable gain amplifiers 126-1 and 126-2, both of which are disposed in the transmission path 302 and the reception path 304. Using the bidirectional variable gain amplifiers 126-1 and 126-2, the vector modulator 404 can amplify, attenuate, or invert the amplitude of an incoming signal. In other words, the vector modulator 404 maintains the amplitude of one or more of the signals to remain relatively unchanged (e.g., provides buffering). In other words, the vector modulator 404 can increase the amplitude of an incoming signal, reduce the amplitude of the incoming signal, or keep the amplitude of the incoming signal relatively unchanged.

[0074]

[0089] During transmission, the quadrature coupler 402 receives the input transmission signal 216 and generates split transmission signals 414-1 and 414-2 at the quadrature ports 412-1 and 412-2, respectively. The split transmission signals 414-1 and 414-2 are approximately 90 degrees out of phase with respect to each other. Depending on the design of the quadrature coupler 402, the split transmission signals 414-1 and 414-2 may have relatively similar amplitudes or relatively different amplitudes. The vector modulator 404 adjusts the amplitudes of the split transmission signals 414-1 and 414-2 to generate amplified split transmission signals 416-1 and 416-2. The amplitudes of the amplified split transmission signals 416-1 and 416-2 can be made larger than, smaller than, or approximately equal to the amplitudes of the corresponding split transmission signals 414-1 and 414-2 to facilitate the phase shift by the phase shifter 122. The combiner 406 combines the amplified split transmission signals 416-1 and 416-2 to generate a phase-shifted transmission signal 418 at the transmission node 308. In this way, the phase of the phase-shifted transmission signal 418 is based on the relative amplitude difference between the amplified split transmission signals 416-1 and 416-2 and the 90-degree phase offset between the amplified split transmission signals 416-1 and 416-2 by the quadrature coupler 402.

[0075]

[0090] While receiving, splitter 408 splits input received signal 220 to generate split received signals 420-1 and 420-2. Split received signals 420-1 and 420-2 are substantially in phase with each other (e.g., have relatively similar phases). Vector modulator 404 adjusts the amplitudes of split received signals 420-1 and 420-2 to generate amplified split receive signals 422-1 and 422-2. Similar to amplified split transmit signals 416-1 and 416-2, the amplitudes of amplified split receive signals 422-1 and 422-2 can be made larger than, smaller than, or approximately equal to the amplitudes of the corresponding split received signals 420-1 and 420-2 according to the desired phase shift. Orthogonal coupling circuit 402 generates phase-shifted received signal 424 at shared node 306 based on amplified split receive signals 422-1 and 422-2. In this way, the phase of phase-shifted received signal 424 is based on the relative amplitude difference between amplified split receive signals 422-1 and 422-2 and a 90-degree phase offset applied to one of amplified split receive signals 422-1 and 422-2 via orthogonal coupling circuit 402. As shown above, phase shifter 122 performs phase shift for both transmission and reception and is thus bidirectional.

[0076]

[0091] FIG. 5 shows an exemplary operation of phase shifter 122 for bidirectional variable gain amplification. In the depicted configuration, orthogonal coupling circuit 402 is implemented as an orthogonal coupler 502 having a shared port 410 (e.g., an input or output (IO) port), a through port 504, a coupled port 506, and an isolated port 508. The signal passing between shared port 410 and through port 504 has a relatively unchanged phase, and another signal passing between shared port 410 and coupled port 506 has a phase shifted by approximately 90 degrees. Through port 504 and coupled port 506 correspond to orthogonal ports 412-1 and 412-2 in FIG. 4.

[0077]

[0092] The bidirectional variable gain amplifiers 126-1 and 126-2 each include a respective first port 510-1 and 510-2, a respective second port 512-1 and 512-2, and a respective third port 514-1 and 514-2. The first ports 510-1 and 510-2 are disposed in the shared transceiver path 312 (of FIG. 4) and are coupled to the through port 504 and the coupling port 506, respectively. The second ports 512-1 and 512-2 are disposed in the transmission path 302 (of FIG. 4) and are coupled to the combiner 406. In contrast, the third ports 514-1 and 514-2 are disposed in the reception path 304 (of FIG. 4) and are coupled to the splitter 408.

[0078]

[0093] The amplitude adjustment performed by the bidirectional variable gain amplifiers 126-1 and 126-2 is individually controlled by the control circuit 130 via the offset signal 212. The control circuit 130 also controls the configuration of the bidirectional variable gain amplifiers 126-1 and 126-2 via the configuration signal 214. The different configurations of the bidirectional variable gain amplifiers 126-1 and 126-2 enable a signal to propagate from the first ports 510-1 and 510-2 to the second ports 512-1 and 512-2, or from the third ports 514-1 and 514-2 to the first ports 510-1 and 510-2.

[0079]

[0094] FIG. 5 also shows an exemplary vector diagram of the signals received or generated by the phase shifter 122. The signals related to transmission are shown within the solid circle, and the signals related to reception are shown within the dashed circle. During transmission, the quadrature coupler 502 receives the input transmission signal 216 at the shared port 410 and generates split transmission signals 414-1 and 414-2 at the through port 504 and the coupling port 506, respectively. Due to the phase shift that occurs between the shared port 410 and the coupling port 506, the split transmission signal 414-2 has a phase that is approximately 90 degrees different from the phase of the split transmission signal 414-1. In other words, the split transmission signals 414-1 and 414-2 represent orthogonal signals.

[0080]

[0095] In this example, the bidirectional variable gain amplifier 126-1 increases the amplitude of the split transmission signal 414-1 to generate an amplified split transmission signal 416-1, and the bidirectional variable gain amplifier 126-2 reduces and inverts the amplitude of the split transmission signal 414-2 to generate an amplified split transmission signal 416-2. These adjustments to the amplitudes of the split transmission signals 414-1 and 414-2 are specified by the control circuit 130 via the offset signal 212 so as to effectively shift the phase of the input transmission signal 216 by a target amount. The combiner 406 combines the amplified split transmission signals 416-1 and 416-2 to generate a phase-shifted transmission signal 418, which is shown as the vector sum of the amplified split transmission signals 416-1 and 416-2.

[0081]

[0096] During reception, the splitter 408 receives the input received signal 220 and generates split received signals 420-1 and 420-2, which are substantially in phase with each other. In other words, the split received signals 420-1 and 420-2 represent in-phase signals. In this example, the bidirectional variable gain amplifier 126-1 generates an amplified split received signal 422-1 having an amplitude relatively similar to that of the split received signal 420-1 (for example, the gain of the bidirectional variable gain amplifier 126-1 is about 0 decibels). In contrast, the bidirectional variable gain amplifier 126-2 increases the amplitude of the split received signal 420-2 to generate an amplified split received signal 422-2. These adjustments, or lack thereof, to the amplitudes of the split received signals 420-1 and 420-2 are specified by the control circuit 130 via the offset signal 212 so as to effectively shift the phase of the input received signal 220 by a target amount.

[0082]

[0097] The quadrature coupler 502 receives the amplified split received signal 422-1 at the through port 504 and receives the amplified split received signal 422-2 at the combined port 506. The quadrature coupler 502 shifts the phase of the amplified split received signal 422-2 by approximately 90 degrees to produce a phase-shifted amplified split received signal (not explicitly shown). At the common port 410, the quadrature coupler 502 combines the amplified split received signal 422-1 with the phase-shifted amplified split received signal to generate the phase-shifted received signal 424. This is shown as the vector sum of these signals. The bidirectional variable gain amplifier 126 is further described with respect to FIG. 6-1.

[0083]

[0098] FIG. 6-1 shows an exemplary implementation of a bidirectional variable gain amplifier 126 that can be used to implement each of the bidirectional variable gain amplifiers 126-1 to 126-4 of FIG. 1. The bidirectional variable gain amplifier 126 includes a T-shaped circuit network 602 coupled to ports 510 and 514 and, in a three-port implementation, coupled to port 512. The T-shaped circuit network 602 includes three branch circuits 604-1, 604-2, and 604-3 and a common node 606. The first branch circuit 604-1 is coupled between the first port 510 and the common node 606. The second branch circuit 604-2 is coupled between the second port 512 and the common node 606. Similarly, the third branch circuit 604-3 is coupled between the third port 514 and the common node 606.

[0084]

[0099] Each of the branch circuits 604-1 to 604-3 includes a respective set of transistors 608-1, 608-2, and 608-3. Each of the sets of transistors 608-1 to 608-3 includes one or more n-channel metal oxide semiconductor field effect transistors (NMOSFETs) or one or more p-channel metal oxide semiconductor field effect transistors (PMOSFETs). When one or more of the sets of transistors 608-1 to 608-3 includes a plurality of transistors, the plurality of transistors are all connected in parallel. To achieve a target amount of amplification, a different number of transistors within each of the sets of transistors 608-1 to 608-3 can be enabled or disabled. The sets of transistors 608-1 to 608-3 can have a similar or different number of transistors.

[0085]

[0100] The branch circuits 604-1 and 604-3 include respective switches 610-1 and 610-3, which enable the bidirectional variable gain amplifier 126 to operate dynamically in an active transmit configuration or an active receive configuration. The branch circuit 604-2 can optionally include a second switch 610-2 as shown via a dashed line to enable the bidirectional variable gain amplifier 126 to operate dynamically in an active configuration (e.g., an active transmit configuration or an active receive configuration) or a passive configuration. Various configurations are further described with respect to FIGS. 7-1 to 7-4.

[0086]

[0101] Each of switches 610-1 to 610-3 can be implemented using an inverter, a multiplexer, one or more transistors, etc. Based on the configuration signal 214 (of FIG. 5), switches 610-1 to 610-3 connect the corresponding sets 608-1 to 608-3 of transistors to the supply voltage or ground. To enable the active mode 134, two of switches 610-1 to 610-3 are connected to the supply voltage and another one of switches 610-1 to 610-3 is connected to ground. This allows a direct current (DC) to flow from the supply voltage to ground through at least two of the sets 608-1 to 608-3 of transistors. To enable the passive mode 136, switches 610-1 to 610-3 connect the corresponding sets 608-1 to 608-3 of transistors to ground.

[0087]

[0102] Various configurations of switches 610-1 to 610-3 operate sets of transistors 608-1 to 608-3 as a set of input transistors 612, a set of output transistors 614, and a set of current steering transistors 616. In the active configuration, the input set of transistors 612 generates a current based on an input voltage. The output set of transistors 614 operates as a cascode stage and generates an output voltage based on at least a portion of the current. The current steering set of transistors 616 optionally steers another portion of the current, whereby another portion of the current flows through the corresponding branch circuit and affects the magnitude of the portion of the current flowing through the output set of transistors 614. In other words, the current steering set of transistors 616 controls the current distribution through the output set of transistors 614 by adjusting the amount of current flowing through the current steering set of transistors 616. The current distribution can vary dynamically to achieve a specific amount of amplification. In the passive configuration, the input set of transistors 612 and the output set of transistors 614 operate as series resistors, and the set of current steering transistors 616 operates as a shunt resistor.

[0088]

[0103] The operations of the sets 608-1 to 608-3 of transistors may vary based on the configuration of the bidirectional variable gain amplifier 126. For example, during transmission, the first set 608-1 of transistors operates as the set 612 of input transistors, the second set 608-2 of transistors operates as the set 614 of output transistors, and the third set 608-3 of transistors operates as the set 616 of current steering transistors. However, during reception, the third set 608-3 of transistors operates as the set 612 of input transistors, the first set 608-1 of transistors operates as the set 614 of output transistors, and the second set 608-2 of transistors operates as the set 616 of current steering transistors. The possible communication signal flows during transmission and reception are represented by the directions of the arrows shown in FIG. 6-1. The components of the bidirectional variable gain amplifier 126 are further described with respect to FIG. 6-2.

[0089]

[0104] FIG. 6-2 shows another exemplary implementation of the bidirectional variable gain amplifier 126 that can be used to implement each of the bidirectional variable gain amplifiers 126-1 to 126-4 of FIG. 1. In the depicted configuration, the branch circuits 604-1 to 604-3 include sets of transistors 608-1 to 608-3, switches 610-1 to 610-3, respective inductors 618-1 to 618-3, and respective capacitors 620-1 to 620-3. Each of the switches 610-1 to 610-3 includes a pole and two throws. The pole is coupled to the inductors 618-1 to 618-3 respectively, and each of the two throws is coupled to the supply voltage 622 and ground 624 respectively. The switches 610-1 to 610-3 are each configured to selectively connect the corresponding sets of transistors 608-1 to 608-3 to the supply voltage 622 or ground 624. As shown in FIG. 6-2, the individual switches 610-1 to 610-3 are not serially coupled between two of the ports 510, 512, or 514, and thus are not in the signal propagation path related to the transmission path 302 or the reception path 304. In this way, it is possible to avoid the losses associated with the switches disposed in the propagation path.

[0090]

[0105] Inductors 618-1 to 618-3 are each coupled between respective poles of switches 610-1 to 610-3 and sets 608-1 to 608-3 of transistors. Inductors 618-1 to 618-3 are configured to resonate at a desired frequency to provide a band response. In particular, inductors 618-1 to 618-3 are configured to pass higher frequencies to the output and attenuate lower frequencies. Each of inductors 618-1 to 618-3 also operates as a dummy load when the corresponding sets 608-1 to 608-3 of transistors operate as sets 616 of current steering transistors. Capacitors 620-1 to 620-3 are coupled between respective poles of switches 610-1 to 610-3 and ground 624. In this way, capacitors 620-1 to 620-3 comprise bypass capacitors that allow high-frequency signals to "see" a low impedance at switches 610-1 to 610-3. Capacitors 620-1 to 620-3 can be optional components that may not be included depending on the implementation form.

[0091]

[0106] Each of sets 608-1 to 608-3 of transistors includes respective gate terminals 626-1, 626-2, and 626-3, respective channel terminals 628-1, 628-2, 628-3, and other respective channel terminals 630-1, 630-2, 630-3. In addition, each of sets 608-1 to 608-3 of transistors includes at least one common gate amplifier 632. If one or more of sets 608-1 to 608-3 of transistors includes multiple common gate amplifiers 632, the multiple common gate amplifiers 632 are connected in parallel with each other. Generally, common gate amplifier 632 is symmetric, and thus, DC current can flow from channel terminal 628 to channel terminal 630 or from channel terminal 630 to channel terminal 628 based on the bias voltage provided via switch 610. This enables the bidirectional operation of bidirectional variable gain amplifier 126.

[0092]

[0107] The gate terminals 626-1 to 626-3 are coupled to a voltage generator (not shown), which can be implemented within the wireless transceiver 120 and generates individual gate voltages. When the sets of transistors 608-1 to 608-3 each include a plurality of transistors, each of the gate terminals 626-1 to 626-3 can comprise a plurality of gate terminals coupled to the individual transistors within the sets of transistors 608-1 to 608-3. In this way, the voltage generator can generate different gate voltages to enable different numbers of transistors within the sets of transistors 608-1 to 608-3 to operate (e.g., operate either in the saturation region or the linear region) or to disable them (e.g., operate in the cutoff region). In the enabled state, current flows through the transistors. In the disabled state, current does not substantially flow through the transistors. Based on the gate voltage, the transistors within the sets of transistors 608-1 to 608-3 can operate as amplifiers or switches. The gate voltage can be related to an analog or digital signal generated by the voltage generator. Generally, the voltage generator generates a set of gate voltages for the set of input transistors 612 and another set of gate voltages for the set of output transistors 614 and the set of current steering transistors 616. In the active configuration, the gate voltage is a bias voltage that causes the transistors to operate as amplifiers. In the passive configuration, the gate voltage is a ground voltage, a supply voltage, or a combination thereof that causes the transistors to operate as switches.

[0093]

[0108] Each of the channel terminals 628-1 to 628-3 and 630-1 to 630-3 is connected to the terminals of transistors having the same doping type within the sets of transistors 608-1 to 608-3. The switches 610-1 to 610-3 provide a bias voltage at the channel terminals 630-1 to 630-3, whereby the channel terminals 630-1 to 630-3 represent source terminals or drain terminals. For example, when the transistors are NMOSFETs and the switches 610-1 to 610-3 connect the channel terminals 630-1 to 630-3 to the ground 624, the channel terminals 630-1 to 630-3 represent source terminals and the channel terminals 628-1 to 628-3 represent drain terminals. Alternatively, when the switches 610-1 to 610-3 connect the channel terminals 630-1 to 630-3 to the supply voltage 622, the channel terminals 630-1 to 630-3 represent drain terminals. T

[0109] Various configurations of the exemplary three-port bidirectional variable gain amplifier 126 are further described with respect to FIGS. 7-1 through 7-3. The three-port bidirectional variable gain amplifier 126 can be used to implement the bidirectional variable gain amplifiers 126-1 and 126-2 of the phase shifter 122, or the bidirectional variable gain amplifier 126-3 of the three-port amplifier 124. An example of the two-port bidirectional variable gain amplifier 126 is further described with respect to FIG. 7-4. The two-port bidirectional variable gain amplifier 126 can be used to implement the bidirectional variable gain amplifier 126-4 of the two-port amplifier 138.

[0094]

[0110] FIG. 7-1 shows an active transmission configuration 700-1 of an exemplary three-port bidirectional variable gain amplifier 126. In this configuration, the control circuit 130 causes the first switch 610-1 to connect the first set of transistors 608-1 to ground 624 via a configuration signal 214 (not shown). The control circuit 130 also causes both the second switch 610-2 and the third switch 610-3 to connect the sets of transistors 608-2 and 608-3 to the supply voltage 622 via the configuration signal 214. In the active transmission configuration 700-1, a voltage generator provides bias voltages to the gate terminals 626-1, 626-2, and 626-3, and the transistors within the sets of transistors 608-1~608-3 operate as amplifiers within the T-shaped circuit network 602.

[0095]

[0111] In the active transmission configuration 700-1, a signal propagates from the first port 510 to the second port 512 through the first set of transistors 608-1 and the second set of transistors 608-2. Accordingly, the first set of transistors 608-1 operates as the set of input transistors 612, and the second set of transistors 608-2 operates as the set of output transistors 614. In particular, the first set of transistors 608-1 receives an input voltage 702 at the first port 510 and generates a current 704 based on the input voltage 702. At least a portion of the current 704 flows through the second set of transistors 608-2 as indicated by the current 706. The second set of transistors 608-2 generates an output voltage 708 at the second port 512 based on the current 706. In some situations, all of the transistors within the set of input transistors 612 are in an enabled state.

[0096]

[0112] When at least a part of the transistors in the third set 608-3 of transistors is in an enabled state, as represented by current 710, another part of current 704 flows through the third set 608-3 of transistors. The directions of the arrows shown for currents 704, 706, and 710 represent the direction of DC current. Thus, the third set 608-3 of transistors can operate as a set 616 of current steering transistors to allocate the amount of current 706 flowing through the second set 608-2 of transistors. In this way, the gain of the bidirectional variable gain amplifier 126 is relatively reduced with respect to a configuration in which all the transistors in the set 616 of current steering transistors are in a disabled state. Based on current 710, a current steering voltage 712 is generated at the third port 514. In some cases, the control circuit 130 causes the transceiver component (such as the low noise amplifier 208) coupled to the third port 514 to be in a disabled state during the active transmission configuration 700-1.

[0097]

[0113] The set 614 of output transistors and the set 616 of current steering transistors both control the amplitude of the output voltage 708. Generally, the gain of the bidirectional variable gain amplifier 126 is based on the number of enabled transistors in the set 614 of output transistors and the number of enabled transistors in the set 616 of current steering transistors. In particular, this ratio controls the amounts of currents 706 and 710 flowing through the set 614 of output transistors and the set 616 of current steering transistors, respectively. Generally, the amplitude of the output voltage 708 increases as the number of enabled transistors in the set 614 of output transistors increases.

[0098]

[0114] In some cases, the total number of enabled transistors across both the set 614 of output transistors and the set 616 of current steering transistors is based on a predetermined number. For example, if the total number of transistors in the set 614 of output transistors is equal to the total number of transistors in the set 616 of current steering transistors, the predetermined number can represent this number. To adjust the gain of the bidirectional variable gain amplifier 126 and keep the total number of enabled transistors across both the set 614 of output transistors and the set 616 of current steering transistors equal to the predetermined number, it can be assumed that as the number of enabled transistors in the set 614 of output transistors increases, the number of enabled transistors in the set 616 of current steering transistors decreases similarly, or vice versa.

[0099]

[0115] FIG. 7-2 shows an active receive configuration 700-2 of an exemplary three-port bidirectional variable gain amplifier 126. In this configuration, the control circuit 130 causes the third switch 610-3 to connect the third set 608-3 of transistors to the ground 624 via a configuration signal 214 (not shown). The control circuit 130 also causes both the first switch 610-1 and the second switch 610-2 to connect the sets 608-1 and 608-2 of transistors to the supply voltage 622 via the configuration signal 214. In the active receive configuration 700-2, the voltage generator provides bias voltages to the gate terminals 626-1, 626-2, and 626-3, and the transistors in the sets 608-1 to 608-3 of transistors operate as amplifiers in the T-shaped circuit network 602.

[0100]

[0116] In the active receive configuration 700-2, the signal propagates from the third port 514 to the first port 510 through the third set 608-3 of transistors and the first set 608-1 of transistors. Accordingly, the third set 608-3 of transistors operates as the set 612 of input transistors, and the first set 608-1 of transistors operates as the set 614 of output transistors. When at least a part of the transistors in the second set 608-2 of transistors is in an enabled state, the second set 608-2 of transistors operates as the set 616 of current steering transistors. The respective operations of the set 612 of input transistors, the set 614 of output transistors, and the set 616 of current steering transistors are the same as those described above with respect to FIG. 7-1. In some cases, the control circuit 130 causes the transceiver component (e.g., the power amplifier 206) coupled to the second port 512 to be in a disabled state during the active receive configuration 700-2.

[0101]

[0117] FIG. 7-3 shows a passive configuration 700-3 of an exemplary three-port bidirectional variable gain amplifier 126. In this configuration, the control circuit 130 causes the switches 610-1 to 610-3 to connect the sets 608-1 to 608-3 of transistors to the ground 624 via a configuration signal 214 (not shown). In the passive configuration 700-3, the voltage generator connects the supply voltage 622 or the ground 624 to the gate terminals 626-1, 626-2, and 626-3, whereby the transistors in the sets 608-1 to 608-3 of transistors act as switches. Accordingly, the sets 608-1 to 608-3 of transistors operate as variable resistors in the T-shaped network 602. By changing the number of enabled transistors in the sets 608-1 to 608-3 of transistors, the effective resistance of the sets 608-1 to 608-3 of transistors changes.

[0102]

[0118] During transmission in the passive configuration 700-3, the signal propagates from the first port 510 to the second port 512 through the first set 608-1 of transistors and the second set 608-2 of transistors, similar to the active transmission configuration 700-1 in FIG. 7-1. Thus, the sets 608-1 and 608-2 of transistors operate as series resistors, and the third set 608-3 of transistors operates as a shunt resistor. By adjusting the effective resistance of the sets 608-1 to 608-3 of transistors, the signal is attenuated by a target amount at the second port 512.

[0103]

[0119] During reception in the passive configuration 700-3, the signal propagates from the third port 514 to the first port 510 through the third set 608-3 of transistors and the first set 608-1 of transistors, similar to the active reception configuration 700-2 in FIG. 7-2. Thus, the sets 608-1 and 608-3 of transistors operate as series resistors, and the second set 608-2 of transistors operates as a shunt resistor. By adjusting the effective resistance of the sets 608-1 to 608-3 of transistors, the signal is attenuated by a target amount at the first port 510.

[0104]

[0120] FIG. 7-4 shows an exemplary two-port bidirectional variable gain amplifier 126 that can be disposed within the shared transceiver path 312. Thus, the wireless transceiver 120 can use the bidirectional variable gain amplifier 126 to provide variable gain amplification for both transmission and reception. Thereby, the wireless transceiver 120 can save area relative to other designs that utilize separate variable gain amplifiers for transmission and reception. The bidirectional variable gain amplifier 126 can implement the two-port amplifier 138 of FIG. 2-3, and this two-port amplifier 138 can operate as an amplifier, an attenuator, or a buffer within the shared transceiver path 312.

[0105]

[0121] In FIGS. 7-1 to 7-3, different ports of the 3-port bidirectional variable gain amplifier 126 behave as input ports or output ports according to the operating mode. However, in FIG. 7-4, ports 510 and 514 of the 2-port bidirectional variable gain amplifier 126 behave as an input port and an output port, respectively, during transmission, and behave as an output port and an input port, respectively, during reception. For example, in the active transmission configuration 700-1, the first port 510 behaves as an input port, and the third port 514 behaves as an output port. However, in the active reception configuration 700-2, the third port behaves as an input port, and the first port behaves as an output port. Therefore, the first set 608-1 of transistors operates as the set 612 of input transistors, and the third set 608-3 of transistors operates as the set 614 of output transistors, or vice versa. The second set 608-2 of transistors operates as the set 616 of current steering transistors. The operations of each of the set 612 of input transistors, the set 614 of output transistors, and the set 616 of current steering transistors are the same as those described above with respect to FIGS. 7-1 to 7-3.

[0106]

[0122] For example, in the active transmission configuration 700-1, a signal propagates from the first port 510 to the third port 514 through the first set 608-1 of transistors and the third set 608-3 of transistors. To achieve this, the first switch 610-1 connects the first set 608-1 of transistors to the ground 624, and the first set 608-1 of transistors operates as the set 612 of input transistors. The third switch 610-3 connects the third set 608-3 of transistors to the supply voltage 622, and the third set 608-3 of transistors operates as the set 614 of output transistors.

[0107]

[0123] In the active reception configuration 700-2, the signal propagates from the third port 514 to the first port 510 through the third set 608-3 of transistors and the first set 608-1 of transistors. To achieve this, the third switch 610-3 connects the third set 608-3 of transistors to the ground 624, and the third set 608-3 of transistors operates as the set 612 of input transistors. The first switch 610-1 connects the first set 608-1 of transistors to the supply voltage 622, and the first set 608-1 of transistors operates as the set 614 of output transistors.

[0108]

[0124] In both the active transmission configuration 700-1 and the active reception configuration 700-2, the second set 608-2 of transistors operates as the set 616 of current steering transistors and apportions the amount of current flowing through the set 614 of output transistors. To achieve this, the second switch 610-2 connects the second set 608-2 of transistors to the supply voltage 622.

[0109]

[0125] Between both transmission and reception in the passive configuration 700-3, the first and third sets 608-1 and 608-3 of transistors operate as series resistors, and the second set 608-2 of transistors operates as a shunt resistor. The first switch 610-1 connects the first set 608-1 of transistors to the ground 624, the second switch 610-2 connects the second set 608-2 of transistors to the ground 624, and the third switch 610-3 connects the third set 608-3 of transistors to the ground 624.

[0110]

[0126] Although the above circuits in FIGS. 2 to 7-4 are shown as single-ended circuits, at least some of the circuits can alternatively be implemented as differential circuits. Also, when a bidirectional variable gain amplifier 126 is implemented such that the second branch circuit 604-2 does not include the switch 610-2, the channel terminal 630-2 can be coupled to the supply voltage 622. In this implementation, the inductor 618-2 can optionally be removed so that the channel terminal 630-2 is directly coupled to the supply voltage 622.

[0111]

[0127] FIG. 8 shows an exemplary sequence flow diagram 800 regarding switching between different operating modes of a phase shifter 122, a 3-port amplifier 124, or a 2-port amplifier 138 that includes at least one bidirectional variable gain amplifier 126, with time progressing downward. At 802 and 804, the phase shifter 122, the 3-port amplifier 124, or the 2-port amplifier 138 operates in the active mode 134. The active mode 134 consumes power and enables the phase shifter 122, the 3-port amplifier 124, or the 2-port amplifier 138 to improve the performance of the wireless transceiver 120.

[0112]

[0128] During the active mode 134, the bidirectional variable gain amplifier 126 (e.g., the 3-port bidirectional variable gain amplifier shown in FIGS. 7-1 and 7-2, or the 2-port bidirectional variable gain amplifier shown in FIG. 7-4) can operate in the active transmit (TX) configuration 700-1 (of FIG. 7-1) or the active receive (RX) configuration 700-2 (of FIG. 7-2). For example, in 802, the bidirectional variable gain amplifier 126 operates in the active transmit configuration 700-1 based on the first switch 610-1 connecting the first port 510 to the ground 624 and the second and third switches 610-2 and 610-3 connecting the ports 512 and 514 to the supply voltage 622, respectively, as shown. In 804, the bidirectional variable gain amplifier 126 operates in the active receive configuration 700-2 based on the third switch 610-3 connecting the third port 514 to the ground 624 and the first and second switches 610-1 and 610-2 connecting the ports 510 and 512 to the supply voltage 622, respectively, as shown.

[0113]

[0129] The control circuit 130 can cause the bidirectional variable gain amplifier 126 to dynamically switch between the active transmit configuration 700-1 and the active receive configuration 700-2 based on the operating mode (e.g., transmit mode or receive mode) of the wireless transceiver 120 at a particular point in time. In this way, it is possible to achieve performance improvement in the active mode 134 both during transmission and reception using the bidirectional variable gain amplifier 126.

[0114]

[0130] At 806, the phase shifter 122, 3-port amplifier 124, or 2-port amplifier 138 operates in the passive mode 136. The passive mode 136 saves power (e.g., substantially consumes no power from the DC current), but realizes relatively lower performance compared to the active mode 134. During the passive mode 136, the bidirectional variable gain amplifier 126 (e.g., the 3-port bidirectional variable gain amplifier 126 of FIG. 7-3, or the 2-port bidirectional variable gain amplifier 126 of FIG. 7-4) operates in the passive configuration 700-3 based on the switches 610-1 to 610-3 connecting the ports 510, 512, and 514 to the ground 624 as shown in FIG. 8.

[0115]

[0131] In some implementations, the control circuit 130 can cause the phase shifter 122, 3-port amplifier 124, or 2-port amplifier 138 to dynamically switch between the active mode 134 and the passive mode 136 to balance power consumption and performance. In some cases, when the wireless transceiver 120 is coupled to a relatively larger antenna array having four or more antenna elements 202, the active mode 134 can be used, and when the wireless transceiver 120 is coupled to a relatively smaller antenna array having less than four antenna elements 202, the passive mode 136 can be used.

[0116]

[0132] FIG. 9 is a flowchart showing an exemplary process 900 for bidirectional variable gain amplification. The process 900 is described in the form of a set of blocks 902 to 910 specifying the operations that can be implemented. However, since the operations can be implemented in an alternative order or in a fully or partially overlapping manner, the operations are not necessarily limited to the order shown in FIG. 9 or described herein. The operations represented by the illustrated blocks of the process 900 can be implemented by the wireless transceiver 120 (e.g., of FIG. 1 or FIG. 2), or by the phase shifter 122 (e.g., of FIGS. 2 to 5). More specifically, the operations of the process 900 can be implemented, at least in part, by the bidirectional variable gain amplifier 126 shown in FIGS. 6-1 to 7-4.

[0117]

[0133] In block 902, during the first time period and during the second time period, the phase shifter is operated in the active mode. For example, during the first time period associated with identifier 802 in FIG. 8, and during the second time period associated with identifier 804 in FIG. 8, the phase shifter 122 operates in the active mode 134. During the active mode 134, the bidirectional variable gain amplifiers 126-1 and 126-2 in the phase shifter 122 can be assumed to be in the active transmission configuration 700-1 (in FIG. 7-1) or the active reception configuration 700-2 (in FIG. 7-2).

[0118]

[0134] In block 904, during the first time period, an input transmission signal is received at the shared node of the phase shifter. For example, the phase shifter 122 receives the input transmission signal 216 at the shared node 306. The quadrature coupling circuit 402 can generate split transmission signals 414-1 and 414-2 based on the input transmission signal 216, as shown in FIG. 4.

[0119]

[0135] At block 906, during a first time period, a phase-shifted transmission signal is generated at a transmission node of the phase shifter using a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier of the phase shifter. The phase-shifted transmission signal is based on an input transmission signal. For example, as shown in FIG. 4, phase shifter 122 uses bidirectional variable gain amplifiers 126-1 and 126-2 to generate a phase-shifted transmission signal 418 at transmission node 308. The phase-shifted transmission signal 418 may have a different phase and / or a different amplitude relative to the input transmission signal 216 based on the input transmission signal 216. In particular, bidirectional variable gain amplifiers 126-1 and 126-2 can adjust the respective amplitudes of split transmission signals 414-1 and 414-2 related to the input transmission signal 216 to generate amplified split transmission signals 416-1 and 416-2. Combiner 406 combines the amplified split transmission signals 416-1 and 416-2 to generate the phase-shifted transmission signal 418. During transmission, the two bidirectional variable gain amplifiers 126-1 and 126-2 are respectively related to an in-phase channel and a quadrature channel within the phase shifter 122.

[0120]

[0136] At block 908, during a second time period, an input reception signal is received at a reception node of the phase shifter. For example, phase shifter 122 receives an input reception signal 220 at reception node 310. Splitter 408 can generate split reception signals 420-1 and 420-2 based on the input reception signal 220 as shown in FIG. 4.

[0121]

[0137] At block 910, during a second time period, a phase-shifted received signal is generated at a shared node using a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier. The phase-shifted received signal is based on an input received signal. For example, as shown in FIG. 4, phase shifter 122 generates a phase-shifted received signal 424 at shared node 306 using bidirectional variable gain amplifiers 126-1 and 126-2. The phase-shifted received signal 424 may have a different phase and / or a different amplitude relative to the input received signal 220 based on the input received signal 220. In particular, bidirectional variable gain amplifiers 126-1 and 126-2 can adjust the respective amplitudes of split received signals 420-1 and 420-2 related to the input received signal 220 to generate amplified split received signals 422-1 and 422-2. During reception, the two bidirectional variable gain amplifiers 126-1 and 126-2 are each related to two in-phase channels within phase shifter 122. Orthogonal coupling circuit 402 can generate a phase-shifted received signal 424 based on the amplified split received signals 422-1 and 422-2 as shown in FIG. 4.

[0122]

[0138] FIG. 10 is another flowchart showing an exemplary process 1000 for bidirectional variable gain amplification. Process 1000 is described in the form of a set of blocks 1002-1008 that specify operations that can be implemented. However, the operations can be implemented in an alternative order or in a manner that is fully or partially overlapping, so the operations are not necessarily limited to the order shown in FIG. 10 or described herein. The operations represented by the illustrated blocks of process 1000 can be implemented by a wireless transceiver 120 (e.g., of FIG. 1 or FIG. 2) or a phase shifter 122 (e.g., of FIGS. 2-5). More specifically, the operations of process 1000 can be implemented, at least in part, by bidirectional variable gain amplifier 126 shown in FIGS. 6-1 through 7-4.

[0123]

[0139] At 1002, during a first time period, the bidirectional variable gain amplifier is operated in an active transmission configuration. The bidirectional variable gain amplifier includes a first port and a third port. For example, during the first time period, the bidirectional variable gain amplifier 126 operates in the active transmission configuration 700-1. The bidirectional variable gain amplifier 126 includes a first port 510 and a third port 514 as shown in FIGS. 6-1 through 7-4.

[0124]

[0140] At 1004, a first signal propagating from the first port to the third port in the active transmission configuration is amplified. For example, the bidirectional variable gain amplifier 126 in FIG. 7-4 amplifies a first signal propagating from the first port 510 to the third port 514 in the active transmission configuration 700-1.

[0125]

[0141] At 1006, during a second time period, the bidirectional variable gain amplifier operates in an active reception configuration. For example, during the second time period, the bidirectional variable gain amplifier 126 operates in the active reception configuration 700-2.

[0126]

[0142] At 1008, a second signal propagating from the third port to the first port in the active reception configuration is amplified. For example, the bidirectional variable gain amplifier 126 amplifies a second signal propagating from the third port 514 to the first port 510 in the active reception configuration 700-2.

[0127]

[0143] Elements or circuits described herein may sometimes be referred to as means for achieving a particular property or function. With respect to the described aspects, the apparatus comprises an antenna element of an antenna array configured to transmit a phase-shifted transmission signal and receive an input received signal, and a wireless transceiver. The wireless transceiver comprises a transmission path coupled to the antenna element, a reception path coupled to the antenna element, and a phase shifter disposed in both the transmission path and the reception path, the phase shifter being configured to operate in an active mode to generate a phase-shifted transmission signal based on an input transmission signal and to generate a phase-shifted reception signal based on an input received signal, the phase shifter comprising vector modulation means for adjusting the amplitudes of two split transmission signals related to the input transmission signal and for adjusting the amplitudes of two split reception signals related to the input received signal. For example, the vector modulation means may correspond to vector modulator 404.

[0128]

[0144] In some embodiments, the phase shifter comprises a quadrature coupling circuit, the quadrature coupling circuit comprising a first quadrature port and a second quadrature port, the vector modulation means being coupled to the first quadrature port and the second quadrature port, the two split transmission signals comprising quadrature signals having phases approximately 90 degrees different from each other, and the two split reception signals comprising in-phase signals having approximately equal other phases with respect to each other.

[0129]

[0145] In some embodiments, the vector modulation means includes a first bidirectional amplification means for amplifying a first split transmit signal of two split transmit signals and a first split receive signal of two split receive signals, and a second bidirectional amplification means for amplifying a second split transmit signal of two split transmit signals and a second split receive signal of two split receive signals. For example, the first bidirectional amplification means may correspond to a first bidirectional amplifier 126-1, and the second bidirectional amplification means may correspond to a second bidirectional amplifier 126-2.

[0130]

[0146] In some embodiments, the first bidirectional amplification means includes: a first port disposed in both the transmission path and the reception path; a second port disposed in the transmission path, configured such that the first port receives a first split transmission signal; a third port disposed in the reception path, configured such that the third port receives a first split reception signal; first duplexing means for selectively providing a first amplified split transmission signal at the second port based on the first split transmission signal and providing a first amplified split reception signal at the first port based on the first split reception signal; and the first duplexing means coupled to the first port, the second port, and the third port. The second bidirectional amplification means includes: another first port disposed in both the transmission path and the reception path; another second port disposed in the transmission path, configured such that the another first port receives a second split transmission signal; another third port disposed in the reception path, configured such that the another third port receives a second split reception signal; second duplexing means for selectively providing a second amplified split transmission signal at the another second port based on the second split transmission signal and providing a second amplified split reception signal at the another first port based on the second split reception signal; and the second duplexing means coupled to the another first port, the another second port, and the another third port. For example, the first duplexing means may correspond to an instance of a first branch circuit 604-1, a second branch circuit 604-2, and a third branch circuit 604-3, and the second duplexing means may correspond to another instance of the first branch circuit 604-1, the second branch circuit 604-2, and the third branch circuit 604-3.

[0131]

[0147] In some embodiments, the first duplexing means comprises: a first input means for generating respective first currents based on a first input voltage; the first input voltage being selectively related to a first split transmission signal and a first split reception signal; a first output means for generating respective first output voltages based on at least a portion of the first currents; the first output voltage being selectively related to a first amplified split transmission signal and a first amplified split reception signal. The second duplexing means comprises: a second input means for generating respective second currents based on a second input voltage; the second input voltage being selectively related to a second split transmission signal and a second split reception signal; a second output means for generating respective second output voltages based on at least a portion of the second currents; the second output voltage being selectively related to a second amplified split transmission signal and a second amplified split reception signal. For example, the first input means may correspond to an instance of a set of input transistors 612, and the first output means may correspond to an instance of a set of output transistors 614. The second input means may correspond to another instance of the set of input transistors 612, and the second output means may correspond to another instance of the set of output transistors 614.

[0132]

[0148] In some embodiments, the first duplexing means comprises first current-steering means for allocating the amount of a first current flowing through the first output means, and the second duplexing means comprises second current-steering means for allocating the amount of a second current flowing through the second output means. For example, the first current-steering means may correspond to an instance of a set 616 of current-steering transistors, and the second current-steering means may correspond to another instance of the set 616 of current-steering transistors.

[0133]

[0149] In some embodiments, the first duplexing means comprises first switching means for connecting the first input means to ground and for connecting the first output means and the first current-steering means to a supply voltage, and the second duplexing means comprises second switching means for connecting the second input means to ground and for connecting the second output means and the second current-steering means to a supply voltage. For example, the first switching means may correspond to a first switch 610-1, a second switch 610-2, and a third switch 610-3 in the configuration shown in FIG. 7-1, and the second switching means may correspond to a first switch 610-1, a second switch 610-2, and a third switch 610-3 in the configuration shown in FIG. 7-2.

[0134]

[0150] Unless the context otherwise specifies, the use of the word "or" in this specification may be regarded as the use of an "inclusive disjunction", or the use of a term that permits the inclusion or application of one or more of the items linked by the word "or" (e.g., the phrase "A or B" may be interpreted as permitting only "A", only "B", or both "A" and "B"). Further, the items represented in the accompanying drawings and the terms discussed in this specification may represent one or more items or terms, and thus, in the description in this writing, reference may be made interchangeably to the singular or plural forms of items and terms. Finally, although the subject matter has been described in language specific to structural features or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above, including that the subject matter is not necessarily limited to the composition in which the features are arranged or the order in which the acts are performed. The invention described in the claims of the present application at the time of filing is appended below. [C1] An apparatus comprising an antenna element of an antenna array and a wireless transceiver, wherein the wireless transceiver has a transmission path coupled to the antenna element and a reception path coupled to the antenna element, and a phase shifter disposed in both the transmission path and the reception path, and the phase shifter is configured to operate in an active mode, and the phase shifter comprises a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier. [C2] Based on the phase shifter being in the active mode, in the transmission mode, using both the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier to amplify a first signal propagating in the transmission path, and in the reception mode, using both the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier to amplify a second signal propagating in the reception path, and being configured to selectively perform the above, the apparatus according to C1. [C3] The apparatus according to C2, wherein the phase shifter is configured to amplify the first signal and the second signal by a coefficient greater than 1. [C4] The apparatus according to C1, wherein the phase shifter comprises a vector modulator, and the vector modulator comprises the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier. [C5] The apparatus according to C1, wherein the phase shifter comprises a quadrature coupling circuit, and the quadrature coupling circuit comprises a first quadrature port coupled to the first bidirectional variable gain amplifier and a second quadrature port coupled to the second bidirectional variable gain amplifier. [C6] The apparatus according to C5, wherein the first quadrature port and the second quadrature port are related to a phase delta of about 90 degrees. [C7] The first bidirectional variable gain amplifier and the first quadrature port are related to a first in-phase channel of the transmission path and a second in-phase channel of the reception path, and the second bidirectional variable gain amplifier and the second quadrature port are related to a quadrature channel of the transmission path and a third in-phase channel of the reception path, the apparatus according to C5. [C8] The first bidirectional variable gain amplifier is configured to operate as a first set of input transistors based on an active transmission configuration, and comprises a first set of transistors configured to selectively operate as a first set of output transistors based on an active reception configuration, The second bidirectional variable gain amplifier is configured to operate as a second set of input transistors based on the active transmission configuration, and comprises a second set of transistors configured to selectively operate as a second set of output transistors based on the active reception configuration, the apparatus according to C1. [C9] The first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier each comprise a first port disposed in both the transmission path and the reception path, a second port disposed in the transmission path, a third port disposed in the reception path, and different sets of a T-shaped circuit network coupled to the first port, the second port, and the third port, the T-shaped circuit network comprising a common node, a first branch circuit coupled between the first port and the common node, the first branch circuit comprising a first set of transistors, the first set of transistors comprising at least one first common-gate amplifier, a second branch circuit coupled between the second port and the common node, the second branch circuit comprising a second set of transistors, the second set of transistors comprising at least one second common-gate amplifier, a third branch circuit coupled between the third port and the common node, the third branch circuit comprising a third set of transistors, the third set of transistors comprising at least one third common-gate amplifier, the apparatus according to C1. [C10] The first branch circuit comprises a first switch, the first switch being configured to selectively connect a first channel terminal of the first set of transistors to a supply voltage, and selectively connect the first channel terminal of the first set of transistors to ground, The second branch circuit is configured to connect the second channel terminal of the second set of transistors to the supply voltage, The third branch circuit includes a third switch, and the third switch is configured to selectively connect the third channel terminal of the third set of transistors to the supply voltage and connect the third channel terminal of the third set of transistors to the ground, the apparatus according to C9. [C11] The first branch circuit includes a first inductor coupled between the first switch and the first channel terminal of the first set of transistors, The third branch circuit includes a third inductor coupled between the third switch and the third channel terminal of the third set of transistors, the apparatus according to C10. [C12] The first switch is configured to connect the first channel terminal of the first set of transistors to the ground in an active transmission configuration, the active transmission configuration being based on the active mode of the phase shifter, The third switch is configured to connect the third channel terminal of the third set of transistors to the supply voltage in the active transmission configuration, the apparatus according to C10. [C13] The first set of transistors is configured to receive an input voltage at the first port in the active transmission configuration, the input voltage being related to a split transmission signal, and generate a current based on the input voltage in the active transmission configuration, The second set of transistors is configured to generate an output voltage at the second port based on at least a portion of the current in the active transmission configuration, the output voltage being related to an amplified split transmission signal, the apparatus according to C12. [C14] The third set of transistors is configured to allocate the amount of the current flowing through the second set of transistors in the active transmission configuration, the apparatus according to C13. [C15] The first switch is configured to connect the first channel terminal of the first set of transistors to the supply voltage in an active reception configuration, the active reception configuration being based on the active mode of the phase shifter, The device according to C12, wherein the third switch is configured to connect the third channel terminal of the third set of transistors to the ground in the active reception configuration. [C16] The third set of transistors is configured to receive an input voltage at the third port in the active reception configuration, wherein the input voltage is related to a divided reception signal, and configured to generate a current based on the input voltage in the active reception configuration. The device according to C15, wherein the first set of transistors is configured to generate an output voltage at the first port based on at least a part of the current, and the output voltage is related to an amplified divided reception signal. [C17] The device according to C16, wherein the second set of transistors is configured to allocate an amount of the current flowing through the first set of transistors in the active reception configuration. [C18] The second branch circuit includes a second switch, and the second switch is configured to selectively connect the second channel terminal of the second set of transistors to the supply voltage, and configured to selectively connect the second channel terminal of the second set of transistors to the ground. The device according to C10. [C19] The device according to C18, wherein the second switch is configured to connect the second channel terminal of the second set of transistors to the supply voltage in the active transmission configuration and the active reception configuration. [C20] The phase shifter is configured to operate selectively in the active mode and the passive mode. The first switch is configured to connect the first channel terminal of the first set of transistors to the ground in the passive configuration, and the passive configuration is based on the passive mode of the phase shifter. The second switch is configured to connect the second channel terminal of the second set of transistors to the ground in the passive configuration. The device according to C18, wherein the third switch is configured to connect the third channel terminal of the third set of transistors to the ground in the passive configuration. [C21] The passive mode includes a passive transmit mode and a passive receive mode. The first set of transistors is configured to operate as a first series resistor in both the passive transmission mode and the passive reception mode, The second set of transistors, selectively operate as a second series resistor in the passive transmission mode and as a shunt resistor in the passive reception mode, The third set of transistors is configured to selectively operate as the shunt resistor in the passive transmission mode and as the second series resistor in the passive reception mode, the apparatus according to C20. The wireless transceiver comprises a time-division duplex wireless transceiver, the apparatus according to C1. An antenna element of an antenna array, and the antenna element is configured to transmit a phase-shifted transmission signal and receive an input reception signal, [C22] comprising a wireless transceiver, the wireless transceiver comprising [C23] a transmission path coupled to the antenna element, a reception path coupled to the antenna element, and a phase shifter disposed in both the transmission path and the reception path, the phase shifter being configured to generate the phase-shifted transmission signal based on an input transmission signal and generate a phase-shifted reception signal based on the input reception signal in an active mode, The phase shifter comprises vector modulation means for adjusting the amplitudes of two split transmission signals related to the input transmission signal and for adjusting the amplitudes of two split reception signals related to the input reception signal, an apparatus. The phase shifter comprises a quadrature coupling circuit, the quadrature coupling circuit comprising a first quadrature port and a second quadrature port, the vector modulation means is coupled to the first quadrature port and the second quadrature port, the two split transmission signals comprise orthogonal signals having phases different from each other by approximately 90 degrees, the two split reception signals comprise in-phase signals having approximately equal phases to each other, the apparatus according to C23. The vector modulation means comprises [C24] a first bidirectional amplification means for amplifying a first split transmission signal of the two split transmission signals and for amplifying a first split reception signal of the two split reception signals, ​ ​ ​ [C25] ​ ​ The apparatus according to C23, comprising second bi-directional amplification means for amplifying a second split transmission signal among the two split transmission signals and for amplifying a second split reception signal among the two split reception signals. [C26] The first bi-directional amplification means is a first port arranged in both the transmission path and the reception path, and the first port is configured to receive the first split transmission signal, a second port arranged in the transmission path, a third port arranged in the reception path, and the third port is configured to receive the first split reception signal, first duplexing means for selectively providing a first amplified split transmission signal at the second port based on the first split transmission signal and providing a first amplified split reception signal at the first port based on the first split reception signal, and the first duplexing means is coupled to the first port, the second port, and the third port. The second bi-directional amplification means is another first port arranged in both the transmission path and the reception path, and the another first port is configured to receive the second split transmission signal, another second port arranged in the transmission path, another third port arranged in the reception path, and the another third port is configured to receive the second split reception signal, second duplexing means for selectively providing a second amplified split transmission signal at the another second port based on the second split transmission signal and providing a second amplified split reception signal at the another first port based on the second split reception signal, and the second duplexing means is coupled to the another first port, the another second port, and the another third port. The apparatus according to C25. [C27] The first duplexing means is first input means for generating first currents respectively based on a first input voltage, and the first input voltage is selectively related to the first split transmission signal and the first split reception signal, first output means for generating first output voltages respectively based on at least a part of the first currents, and the first output voltages are selectively related to the first amplified split transmission signal and the first amplified split reception signal. The second duplexing means, a second input means for generating respective second currents based on a second input voltage, wherein the second input voltage is selectively related to the second split transmission signal and the second split reception signal, a second output means for generating respective second output voltages based on at least a part of the second currents, wherein the second output voltage is selectively related to the second amplified split transmission signal and the second amplified split reception signal, the apparatus according to C26. [C28] The first duplexing means includes a first current steering means for allocating the amount of the first current flowing through the first output means, The second duplexing means includes a second current steering means for allocating the amount of the second current flowing through the second output means, the apparatus according to C27. [C29] The first duplexing means includes a first switching means for connecting the first input means to ground and for connecting the first output means and the first current steering means to a supply voltage, The second duplexing means includes a second switching means for connecting the second input means to the ground and for connecting the second output means and the second current steering means to the supply voltage, the apparatus according to C28. [C30] operating the phase shifter in an active mode during a first time period and during a second time period, receiving an input transmission signal at a shared node of the phase shifter during the first time period, generating a phase-shifted transmission signal at a transmission node of the phase shifter using a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier of the phase shifter during the first time period, wherein the phase-shifted transmission signal is based on the input transmission signal, receiving an input reception signal at a reception node of the phase shifter during the second time period, generating a phase-shifted reception signal at the shared node using the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier during the second time period, wherein the phase-shifted reception signal is based on the input reception signal, a method comprising. [C31] Generating the phase-shifted transmission signal, amplifying a first split transmission signal related to the input transmission signal using the first bidirectional variable gain amplifier to generate a first amplified split transmission signal, To generate the second amplified split transmission signal, amplifying a second split transmission signal related to the input transmission signal using the second bidirectional variable gain amplifier; combining the first amplified split transmission signal and the second amplified split transmission signal to generate the phase-shifted transmission signal, the phase-shifted transmission signal having a first phase different from a second phase of the input transmission signal; generating the phase-shifted received signal; To generate a first amplified split received signal, amplifying a first split received signal related to the input received signal using the first bidirectional variable gain amplifier; To generate a second amplified split received signal, amplifying a second split received signal related to the input received signal using the second bidirectional variable gain amplifier; combining the first amplified received transmission signal and the second amplified split received signal to generate the phase-shifted received signal, the phase-shifted received signal having a third phase different from a fourth phase of the input received signal, the method according to C30. [C32] amplifying the first split transmission signal; receiving a first input voltage based on the first split transmission signal through a first branch circuit of the first bidirectional variable gain amplifier; generating a first current based on the first input voltage through the first branch circuit; generating a first output voltage based on at least a part of the first current through a second branch circuit of the first bidirectional variable gain amplifier; allocating an amount of the first current flowing through the second branch circuit through a third branch circuit of the first bidirectional variable gain amplifier; amplifying the second split transmission signal; receiving a second input voltage based on the second split transmission signal through another first branch circuit of the second bidirectional variable gain amplifier; generating a second current based on the second input voltage through the another first branch circuit; generating a second output voltage based on at least a part of the second current through another second branch circuit of the second bidirectional variable gain amplifier; allocating an amount of the second current flowing through the second branch circuit through another third branch circuit of the second bidirectional variable gain amplifier, the method according to C31. [C33] amplifying the first divided received signal includes receiving a third input voltage based on the first divided received signal via the third branch circuit of the first bidirectional variable gain amplifier; generating a third current based on the third input voltage via the third branch circuit of the first bidirectional variable gain amplifier; generating a third output voltage based on at least a part of the third current via the first branch circuit of the first bidirectional variable gain amplifier; allocating an amount of the second current flowing through the first branch circuit via the second branch circuit of the first bidirectional variable gain amplifier; amplifying the second divided received signal includes receiving a fourth input voltage based on the second divided received signal via another third branch circuit of the second bidirectional variable gain amplifier; generating a fourth current based on the fourth input voltage via another third branch circuit of the second bidirectional variable gain amplifier; generating a fourth output voltage based on at least a part of the fourth current via another first branch circuit of the second bidirectional variable gain amplifier; allocating an amount of the fourth current flowing through the another first branch circuit via the second branch circuit of the second bidirectional variable gain amplifier, the method according to C32. [C34] An apparatus comprising at least one bidirectional variable gain amplifier, wherein the at least one bidirectional variable gain amplifier comprises two or more ports, and the two or more ports include a first port and a third port; comprises a T-shaped circuit network coupled between the two or more ports, and the T-shaped circuit network comprises a common node; a first branch circuit coupled between the first port and the common node, and the first branch circuit comprises a first set of transistors; a second branch circuit coupled between a supply voltage and the common node, and the second branch circuit comprises a second set of transistors; a third branch circuit coupled between the third port and the common node, and the third branch circuit comprises a third set of transistors, the apparatus. [C35] The first set of transistors comprises a first common gate amplifier, or a plurality of first common gate amplifiers connected in parallel together; The second set of transistors comprises a second common gate amplifier, or a plurality of second common gate amplifiers connected in parallel together; wherein the third set of transistors comprises a third common gate amplifier, or a plurality of third common gate amplifiers connected in parallel together, the apparatus according to C34. [C36] wherein the first branch circuit selectively connects the first channel terminal of the first set of transistors to the supply voltage in an active receive configuration, and comprises a first switch configured to selectively connect the first channel terminal of the first set of transistors to ground in an active transmit configuration, wherein the third branch circuit selectively connects the third channel terminal of the third set of transistors to the supply voltage in the active transmit configuration, and comprises a third switch configured to selectively connect the third channel terminal of the third set of transistors to ground in the active receive configuration, the apparatus according to C34. [C37] wherein the second branch circuit selectively connects the second channel terminal of the second set of transistors to the supply voltage in both the active transmit configuration and the active receive configuration, and comprises a second switch configured to selectively connect the second channel terminal of the second set of transistors to ground in a passive configuration, wherein the first branch circuit is configured to connect the first channel terminal of the first set of transistors to ground in the passive configuration, wherein the third branch circuit is configured to connect the third channel terminal of the third set of transistors to ground in the passive configuration, the apparatus according to C36. [C38] wherein the at least one bidirectional variable gain amplifier amplifies a first signal propagating from the first port to the third port in the active transmit configuration, and amplifies a second signal propagating from the third port to the first port in the active receive configuration, and attenuates a third signal propagating from the first port to the third port in the passive configuration, and attenuates a fourth signal propagating from the third port to the first port in the passive configuration, the apparatus according to C37. [C39] wherein the two or more ports comprise the first port, the second port, and the third port, wherein the second branch circuit is coupled between the common node and the second port, wherein the at least one bidirectional variable gain amplifier propagates a first signal from the first port to the second port, The apparatus according to C34, configured to selectively perform propagating a second signal from the third port to the first port. [C40] Further comprising a wireless transceiver, wherein the wireless transceiver a transmission path, a reception path, the at least one bidirectional variable gain amplifier, the at least one bidirectional variable gain amplifier being disposed in both the transmission path and the reception path, the first port being disposed in both the transmission path and the reception path, the second port being disposed in the transmission path, and the third port being disposed in the reception path, the apparatus according to C39. [C41] The at least one bidirectional variable gain amplifier includes a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier, The wireless transceiver includes a phase shifter disposed in both the transmission path and the reception path, the phase shifter including the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier, the apparatus according to C40. [C42] An antenna array including a plurality of antenna elements, the at least one bidirectional variable gain amplifier being coupled to at least one of the plurality of antenna elements, A wireless transceiver coupled to the antenna array, the wireless transceiver including the at least one bidirectional variable gain amplifier and being configured to process a signal communicated via the antenna array, the apparatus according to C34 further comprising. [C43] A display screen, A processor operably coupled to the display screen and the wireless transceiver, the processor being configured to present one or more graphical images on the display screen based on the signal communicated by the wireless transceiver using the at least one bidirectional variable gain amplifier, the apparatus according to C42 further comprising. [C44] Operating the bidirectional variable gain amplifier in an active transmission configuration during a first time period, the bidirectional variable gain amplifier including a first port and a third port, Amplifying a first signal propagating from the first port to the third port in the active transmission configuration, Operating the bidirectional variable gain amplifier in an active reception configuration during a second time period, Amplifying a second signal propagating from the third port to the first port in the active reception configuration, the method comprising. [C45] Amplifying the first signal comprises amplifying the first signal by a first coefficient greater than 1. The method according to C44, wherein amplifying the second signal comprises amplifying the second signal by a second coefficient greater than 1. [C46] Operating the bidirectional variable gain amplifier in a passive configuration during a third time period; Attenuating a third signal propagating from the first port to the third port in the passive configuration; The method according to C44, further comprising attenuating a fourth signal propagating from the third port to the first port in the passive configuration. [C47] The bidirectional variable gain amplifier comprises a first set of transistors coupled between the first port and a common node, a second set of transistors coupled to the common node, and a third set of transistors coupled between the third port and the common node. Operating the bidirectional variable gain amplifier in the active transmission configuration comprises: Operating the first set of transistors as a first set of input transistors; Operating the second set of transistors as a set of current steering transistors; Operating the third set of transistors as a second set of output transistors. Operating the bidirectional variable gain amplifier in the active reception configuration comprises: Operating the first set of transistors as a first set of output transistors; The method according to C44, further comprising operating the second set of transistors as the set of current steering transistors and operating the third set of transistors as a second set of input transistors. [C48] The bidirectional variable gain amplifier comprises a second port. The method comprises: Operating the bidirectional variable gain amplifier in the active transmission configuration during a third time period; Propagating a third signal from the first port to the second port during the third time period; The method according to C44, further comprising amplifying the third signal in the active transmission configuration. [C49] The bidirectional variable gain amplifier comprises a first set of transistors coupled between the first port and a common node, a second set of transistors coupled to the common node, and a third set of transistors coupled between the third port and the common node. operating the bidirectional variable gain amplifier in the active transmission configuration during the third time period comprises operating the first set of transistors as a set of input transistors, operating the second set of transistors as a set of output transistors, and operating the third set of transistors as a set of current steering transistors, the method of claim C48.

Claims

1. An apparatus comprising one antenna element of an antenna array and a wireless transceiver, wherein the wireless transceiver comprises: a transmission path coupled to the one antenna element; a reception path coupled to the one antenna element; one phase shifter disposed in both the transmission path and the reception path, and the one phase shifter is configured to operate in an active mode, the one phase shifter comprising: a first bidirectional variable gain amplifier; a second bidirectional variable gain amplifier. An apparatus.

2. Based on the one phase shifter being in the active mode, the apparatus according to claim 1, wherein the one phase shifter is configured to selectively: in a transmission mode, amplify a first signal propagating in the transmission path by using both the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier; and in a reception mode, amplify a second signal propagating in the reception path by using both the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier.

3. The apparatus according to claim 2, wherein the one phase shifter is configured to amplify the first signal and the second signal by a factor greater than 1.

4. The apparatus according to claim 1, wherein the one phase shifter comprises a vector modulator, and the vector modulator comprises the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier.

5. The apparatus according to claim 1, wherein the one phase shifter comprises a quadrature coupling circuit, and the quadrature coupling circuit comprises: a first quadrature port coupled to the first bidirectional variable gain amplifier; and a second quadrature port coupled to the second bidirectional variable gain amplifier.

6. The apparatus according to claim 5, wherein the first quadrature port and the second quadrature port are related by a phase delta of approximately 90 degrees.

7. The first bidirectional variable gain amplifier and the first quadrature port are related to a first in-phase channel of the transmission path and a second in-phase channel of the reception path; and The second bidirectional variable gain amplifier and the second quadrature port are related to a quadrature channel of the transmission path and a third in-phase channel of the reception path.

8. The first bidirectional variable gain amplifier, configured to selectively operate as a first set of input transistors based on an active transmission configuration, comprising a first set of transistors configured to selectively operate as a first set of output transistors based on an active reception configuration, wherein the second bidirectional variable gain amplifier, is configured to selectively operate as a second set of input transistors based on the active transmission configuration, The apparatus according to claim 1, further comprising a second set of transistors configured to selectively operate as a second set of output transistors based on the active reception configuration.

9. Each of the first bidirectional variable gain amplifier and the second bidirectional variable gain amplifier, a first port disposed in both the transmission path and the reception path, a second port disposed in the transmission path, a third port disposed in the reception path, and a different set of a T-shaped circuit network coupled to the first port, the second port, and the third port, the T-shaped circuit network including: a common node, a first branch circuit coupled between the first port and the common node, the first branch circuit including a first set of transistors, the first set of transistors including at least one first common-gate amplifier, a second branch circuit coupled between the second port and the common node, the second branch circuit including a second set of transistors, the second set of transistors including at least one second common-gate amplifier, a third branch circuit coupled between the third port and the common node, the third branch circuit including a third set of transistors, the third set of transistors including at least one third common-gate amplifier, The apparatus according to claim 1, comprising:

10. The first branch circuit includes a first switch, the first switch being configured to: selectively connect a first channel terminal of the first set of transistors to a supply voltage, selectively connect the first channel terminal of the first set of transistors to ground, The second branch circuit is configured to connect the second channel terminal of the second set of transistors to the supply voltage, The third branch circuit includes a third switch, and the third switch, selectively connects the third channel terminal of the third set of transistors to the supply voltage and, selectively connects the third channel terminal of the third set of transistors to the ground, wherein, with respect to the first set, the second set, and the third set of transistors, the channel terminals of each transistor are source terminals and drain terminals, the first channel terminal is the channel terminal that connects to the first port among the two channel terminals of each transistor in the first set of transistors, the second channel terminal is the channel terminal that connects to the second port among the two channel terminals of each transistor in the second set of transistors, and the third channel terminal is the channel terminal that connects to the third port among the two channel terminals of each transistor in the third set of transistors, the apparatus according to claim 9. **Claim 11** The first branch circuit includes a first inductor coupled between the first switch and the first channel terminal of the first set of transistors, The third branch circuit includes a third inductor coupled between the third switch and the third channel terminal of the third set of transistors, the apparatus according to claim 10. **Claim 12** The first switch is configured to connect the first channel terminal of the first set of transistors to the ground in an active transmission configuration, the active transmission configuration being based on the active mode of the one phase shifter, The third switch is configured to connect the third channel terminal of the third set of transistors to the supply voltage in the active transmission configuration, the apparatus according to claim 10. **Claim 13** The first set of transistors, receives an input voltage at the first port in the active transmission configuration, the input voltage being related to a split transmission signal, configured to perform generating a current based on the input voltage in the active transmission configuration, The apparatus according to claim 12, wherein the second set of transistors is configured to generate an output voltage at the second port based on at least a portion of the current in the active transmission configuration, and the output voltage is related to the amplified split transmission signal. **Claim 14** The apparatus according to claim 13, wherein the third set of transistors is configured to allocate an amount of the current flowing through the second set of transistors in the active transmission configuration. **Claim 15** The first switch is configured to connect the first channel terminal of the first set of transistors to the supply voltage in the active reception configuration, and the active reception configuration is based on the active mode of the one phase shifter. The apparatus according to claim 12, wherein the third switch is configured to connect the third channel terminal of the third set of transistors to the ground in the active reception configuration. **Claim 16** The third set of transistors is receiving an input voltage at the third port in the active reception configuration, wherein the input voltage is related to the split reception signal, configured to perform generating a current based on the input voltage in the active reception configuration, The apparatus according to claim 15, wherein the first set of transistors is configured to generate an output voltage at the first port based on at least a portion of the current, and the output voltage is related to the amplified split reception signal. **Claim 17** The apparatus according to claim 16, wherein the second set of transistors is configured to allocate an amount of the current flowing through the first set of transistors in the active reception configuration. **Claim 18** The second branch circuit includes a second switch, and the second switch is configured to selectively connect the second channel terminal of the second set of transistors to the supply voltage, The apparatus according to claim 10, configured to selectively connect the second channel terminal of the second set of transistors to the ground. **Claim 19** The apparatus according to claim 18, wherein the second switch is configured to connect the second channel terminal of the second set of transistors to the supply voltage in the active transmission configuration and the active reception configuration. **Claim 20** The one phase shifter is configured to selectively operate in the active mode and the passive mode, the first switch is configured to connect the first channel terminal of the first set of transistors to the ground in a passive configuration, the passive configuration being based on the passive mode of the one phase shifter, the second switch is configured to connect the second channel terminal of the second set of transistors to the ground in the passive configuration, the third switch is configured to connect the third channel terminal of the third set of transistors to the ground in the passive configuration, the apparatus according to claim 18.

21. the passive mode includes a passive transmit mode and a passive receive mode, the first set of transistors is configured to operate as a first series resistor in both the passive transmit mode and the passive receive mode, the second set of transistors, is configured to selectively operate as a second series resistor in the passive transmit mode, and operate as a shunt resistor in the passive receive mode, the third set of transistors, is configured to selectively operate as the shunt resistor in the passive transmit mode, and operate as the second series resistor in the passive receive mode, the apparatus according to claim 20.

22. The wireless transceiver includes a time-division duplex wireless transceiver, the apparatus according to claim 1.

Images