Light-emitting substrate, driving method thereof, and display device

Abstract

The present invention provides a light-emitting substrate including a plurality of light-emitting units arranged in an array, a driving method thereof, and a display device. Each light-emitting unit includes a driving circuit, a plurality of light-emitting elements, and a driving voltage terminal. The plurality of light-emitting elements are connected in series sequentially and connected between the driving voltage terminal and an output terminal of the driving circuit. The driving circuit is configured to output a relay signal via the output terminal during a first period and supply a drive signal via the output terminal during a second period to the plurality of light-emitting elements connected in series sequentially, based on a first input signal received via a first input terminal and a second input signal received via a second input terminal. The light-emitting substrate can achieve independent control of light-emitting brightness by area, has low power consumption, is highly integrated, and has a simple control configuration, and can be combined with a liquid crystal display device to achieve a high-contrast display.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a light-emitting substrate, a driving method thereof, and a display device.

Background Art

[0002] With the development of light-emitting diode technology, backlights using light-emitting diodes on the order of submillimeters or even micrometers are widely applied. Thereby, not only can the screen contrast of, for example, transmissive display products using the backlight reach the level of organic light-emitting diode (OLED) display products, but also the technical advantages of liquid crystal display (LCD) can be retained in the products, and further, the display effect of the screen can be improved, and a better visual experience can be provided to users.

Summary of the Invention

[0003] A light-emitting substrate according to at least one embodiment of the present disclosure includes a plurality of light-emitting units arranged in an array, each light-emitting unit including a driving circuit, a plurality of light-emitting elements, and a driving voltage terminal. The driving circuit includes a first input terminal, a second input terminal, and an output terminal. The plurality of light-emitting elements are connected in series in sequence and are connected between the driving voltage terminal and the output terminal. The driving circuit is configured to output a relay signal through the output terminal during a first period and supply a driving signal to the plurality of light-emitting elements connected in series in sequence through the output terminal during a second period based on a first input signal received by the first input terminal and a second input signal received by the second input terminal.

[0004] For example, in the light-emitting substrate according to an embodiment of the present disclosure, the driving circuit further includes a demodulation circuit, a physical layer interface circuit, a data processing control circuit, a pulse width modulation circuit, a driving signal generation circuit, and a relay signal generation circuit. The demodulation circuit is electrically connected to the second input terminal and the physical layer interface circuit, configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit. The physical layer interface circuit is further electrically connected to the data processing control circuit, configured to process the communication data to obtain a data frame, and transmit the data frame to the data processing control circuit. The data processing control circuit is further electrically connected to the first input terminal, the pulse width modulation circuit, and the relay signal generation circuit, configured to generate a pulse width control signal based on the data frame, transmit the pulse width control signal to the pulse width modulation circuit, generate a relay control signal based on the first input signal, and transmit the relay control signal to the relay signal generation circuit. The pulse width modulation circuit is further electrically connected to the driving signal generation circuit, configured to generate a pulse width modulation signal in response to the pulse width control signal, and transmit the pulse width modulation signal to the driving signal generation circuit. The driving signal generation circuit is further electrically connected to the output terminal, configured to generate the driving signal in response to the pulse width modulation signal, and output the driving signal from the output terminal. The relay signal generation circuit is further electrically connected to the output terminal, configured to generate the relay signal based on the relay control signal, and output the relay signal from the output terminal.

[0005] For example, in the light-emitting substrate according to an embodiment of the present disclosure, the second input signal is a power line carrier communication signal, and the power line carrier communication signal includes information corresponding to the communication data.

[0006] For example, a light-emitting substrate according to an embodiment of the present disclosure further includes a plurality of address patch codes. The plurality of address patch codes extend along a first direction and are configured to transmit the first input signal. The plurality of light-emitting units are arranged in N rows and M columns and are divided into a plurality of groups. Each group of light-emitting units includes a total of X*M light-emitting units in X rows and M columns. The plurality of address patch codes correspond one-to-one to the plurality of groups of light-emitting units. In the light-emitting units of the same group, the X*M light-emitting units are sequentially numbered according to their row and column distribution positions. The first input terminal of the driving circuit of the light-emitting unit numbered 1 is electrically connected to the address patch code corresponding to the light-emitting units of the group. The output terminal of the driving circuit of the light-emitting unit numbered P is electrically connected to the first input terminal of the driving circuit of the light-emitting unit numbered P+1. The first input terminal of the driving circuit of the light-emitting unit numbered P+1 receives the relay signal output by the output terminal of the driving circuit of the light-emitting unit numbered P as the first input signal. N is an integer greater than 0, M is an integer greater than 0, 0<X≦N, X is an integer, 0<P<X*M, and P is an integer.

[0007] For example, in a light-emitting substrate according to an embodiment of the present disclosure, in the light-emitting units of the same group, the X*M light-emitting units are numbered row by row and column by column according to a Z shape, or are numbered row by row and column by column according to an S shape.

[0008] For example, a light-emitting substrate according to an embodiment of the present disclosure further includes a plurality of voltage patch codes. The plurality of voltage patch codes extend along the first direction and are configured to transmit the second input signal. The plurality of voltage patch codes correspond one-to-one to the light-emitting units in N rows. The second input terminal of the driving circuit is electrically connected to the voltage patch code corresponding to the row where the light-emitting unit including the driving circuit is located.

[0009] For example, a light-emitting substrate according to an embodiment of the present disclosure further includes a plurality of source address lines and a plurality of source voltage lines extending along a second direction, wherein the plurality of source address lines are electrically connected in a one-to-one correspondence with the plurality of address patch codes and are configured to transmit the first input signal, and the plurality of source voltage lines are in a one-to-one correspondence with the plurality of groups of light-emitting units, and each source voltage line is electrically connected to a plurality of voltage patch codes corresponding to the light-emitting units of the corresponding group and is configured to transmit the second input signal, and the first direction intersects the second direction.

[0010] For example, in a light-emitting substrate according to an embodiment of the present disclosure, the source address lines and the source voltage lines are located in the same layer, the voltage patch codes and the address patch codes are located in the same layer, and the source address lines and the address patch codes are located in different layers.

[0011] For example, a light-emitting substrate according to an embodiment of the present disclosure further includes a plurality of first test points, a plurality of second test points, a plurality of third test points, and a plurality of fourth test points. The plurality of first test points are located at ends of the source address lines and the source voltage lines away from the light-emitting units. The plurality of second test points are located at connection portions between the source address lines and the address patch codes, and are located at connection portions between the source voltage line and the voltage patch code connected to the source voltage line that is farthest from the first test point among the voltage patch codes. The plurality of third test points are located at both ends of the voltage patch codes and at ends of the address patch codes away from the light-emitting units. The plurality of fourth test points are located at connection portions other than the position of the second test point at the connection portion between the source voltage line and the voltage patch code.

[0012] For example, in a light-emitting substrate according to an embodiment of the present disclosure, the plurality of source address lines are arranged along the first direction, the lengths of the plurality of source address lines along the second direction are different from each other, and among the two source address lines that are farthest along the first direction, the length of the source address line close to the gate driving circuit on the light-emitting substrate is shorter than the length of the source address line far from the gate driving circuit. The plurality of source voltage lines are arranged along the first direction, the lengths of the plurality of source voltage lines along the second direction are different from each other, and among the two source voltage lines that are farthest along the first direction, the length of the source voltage line close to the gate driving circuit is shorter than the length of the source voltage line far from the gate driving circuit.

[0013] For example, in a light-emitting substrate according to an embodiment of the present disclosure, the plurality of source address lines are parallel to each other, and the lengths of the plurality of source address lines sequentially arranged along the first direction change monotonically. The plurality of source voltage lines are parallel to each other, and the lengths of the plurality of source voltage lines sequentially arranged along the first direction change monotonically.

[0014] For example, in a light-emitting substrate according to an embodiment of the present disclosure, the source address line and the source voltage line corresponding to the same group of light-emitting units are installed adjacent to each other.

[0015] For example, in a light-emitting substrate according to an embodiment of the present disclosure, the source voltage line does not overlap with the address patch code.

[0016] For example, in a light-emitting substrate according to an embodiment of the present disclosure, the source address line and the source voltage line are located in the gaps between the plurality of rows of light-emitting units.

[0017] For example, the light-emitting substrate according to an embodiment of the present disclosure further includes a plurality of first driving voltage lines and a plurality of first common voltage lines extending along the second direction. The first driving voltage lines are electrically connected to the driving voltage terminals of each light-emitting unit and are configured to transmit a driving voltage. The driving circuit further includes a common voltage terminal. The first common voltage lines are electrically connected to the common voltage terminals of the driving circuits of each light-emitting unit and are configured to transmit a common voltage.

[0018] For example, in the light-emitting substrate according to an embodiment of the present disclosure, the first driving voltage lines and the first common voltage lines are located in the same layer, and are located in the same layer as the source address lines and the source voltage lines.

[0019] For example, the light-emitting substrate according to an embodiment of the present disclosure further includes a plurality of second driving voltage lines and a plurality of second common voltage lines extending along the first direction. The second driving voltage lines are electrically connected to the first driving voltage lines and form a grid-like wiring. The second common voltage lines are electrically connected to the first common voltage lines and form a grid-like wiring. The second driving voltage lines and the second common voltage lines are located in the same layer, and are located in the same layer as the address patch codes and the voltage patch codes.

[0020] For example, in the light-emitting substrate according to an embodiment of the present disclosure, in the same light-emitting unit, the plurality of light-emitting elements are arranged in an array, and the driving circuit is arranged in the gap of the array formed by the plurality of light-emitting elements.

[0021] For example, in the light-emitting substrate according to an embodiment of the present disclosure, the light-emitting element is a micro light-emitting diode.

[0022] For example, the light-emitting substrate according to an embodiment of the present disclosure further includes a flexible printed circuit board. The flexible printed circuit board overlaps with and is electrically connected to the source address lines and the source voltage lines. The first test point is located on the side of the flexible printed circuit board away from the light-emitting unit.

[0023] A display device according to at least one embodiment of the present disclosure includes a display panel and a light-emitting substrate described in any embodiment of the present disclosure. The display panel has a display side and a non-display side facing the display side, and the light-emitting substrate is provided on the non-display side of the display panel as a backlight unit.

[0024] A driving method of a light-emitting substrate described in any embodiment of the present disclosure according to at least one embodiment of the present disclosure includes supplying the first input signal and the second input signal, outputting the relay signal at the output terminal during the first period, and supplying the driving signal to the plurality of light-emitting elements connected in series in sequence at the output terminal during the second period, so as to cause the plurality of light-emitting elements to emit light under the action of the driving signal within the second period.

[0025] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the accompanying drawings of the embodiments are briefly introduced below. Obviously, the accompanying drawings in the following description relate only to some embodiments of the present disclosure and are not intended to limit the present disclosure.

Brief Description of the Drawings

[0026]

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Mode for Carrying Out the Invention

[0027] In order to further clarify the objectives, technical solutions and advantages of the embodiments of the present disclosure, hereinafter, with reference to the drawings of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor shall fall within the protection scope of the present disclosure.

[0028] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings understood by those skilled in the art to which this disclosure pertains. The terms "first", "second" and the like used in this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components. Similarly, similar terms such as "comprising" or "included" mean that the element or thing that appears before this term includes the element or thing listed after this term and their equivalents, but does not exclude other elements or things. Similar terms such as "connected" or "connected to each other" are not limited to physical or mechanical connections, and may include electrical connections whether direct or indirect. Terms such as "above", "below", "left", "right" are merely for indicating relative positional relationships, and when the absolute position of the object to be described changes, the relative positional relationship may also change accordingly.

[0029] In display products using light-emitting diodes, mini light-emitting diodes (Mini-LED) or micro light-emitting diodes (Micro-LED) are small in size, high in brightness, widely applied to the backlight module of a display device, and can finely adjust the backlight to realize the display of high-dynamic range images (HDR). For example, the typical size (e.g., length) of a Micro-LED is less than 50 microns, for example, from 10 microns to 50 microns, and the typical size (e.g., length) of a Mini-LED is 50 microns to 150 microns, for example, 80 microns to 120 microns. Since the size of the light-emitting diode is small, when applying the light-emitting diode to the backlight module, a huge number of light-emitting diodes are required. Furthermore, since the light-emitting diode is a current-driven element, the signal line needs to transmit the current signal from the driving chip to the light-emitting diode. If each light-emitting diode in the backlight module is to be independently controlled, a corresponding number of driving chips and dense signal lines need to be provided, resulting in a high product cost. Also, the chip area of the driving circuit is usually large, occupying more space and increasing the difficulty of product design and processing.

[0030] At least one embodiment of the present disclosure provides a light-emitting substrate, its driving method, and a display device. The light-emitting substrate can achieve independent control by area over the light-emitting brightness, has low power consumption, high integration, a simple control form, and can realize high-contrast display in combination with a liquid crystal display device.

[0031] The embodiments of the present disclosure will be described in detail below with reference to the drawings. It should be noted that the same reference numerals in different drawings are used to refer to the same elements described.

[0032] At least one embodiment of the present disclosure provides a light-emitting substrate including a plurality of light-emitting units arranged in an array. Each light-emitting unit includes a driving circuit, a plurality of light-emitting elements, and a driving voltage terminal. The driving circuit includes a first input terminal, a second input terminal, and an output terminal. The plurality of light-emitting elements are connected in series in sequence and are connected between the driving voltage terminal and the output terminal. The driving circuit outputs a relay signal via the output terminal during a first period and supplies a driving signal to the plurality of light-emitting elements connected in series in sequence via the output terminal during a second period based on a first input signal received by the first input terminal and a second input signal received by the second input terminal.

[0033] FIG. 1 is a schematic diagram of a light-emitting substrate according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram of the arrangement of the light-emitting units of the light-emitting substrate shown in FIG. 1. As shown in FIGS. 1 and 2, the light-emitting substrate 10 includes a base substrate 101 and a plurality of light-emitting units 100 arranged in an array on the base substrate 101. For example, the plurality of light-emitting units 100 are arranged in N rows and M columns, where N is an integer greater than 0 and M is an integer greater than 0. For example, the number of light-emitting units 100 may be determined according to actual needs, for example, according to the size of the light-emitting substrate 10 and the required luminance. Although only the light-emitting units of 3 rows and 5 columns are shown in FIG. 1, it should be understood that the number of light-emitting units 100 is not limited thereto. For example, the base substrate 01 may be a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, a quartz substrate, etc., and the base substrate 01 includes a single-layer or multi-layer circuit, but the embodiments of the present disclosure are not limited thereto.

[0034] For example, the light-emitting units 100 in each row are arranged along the first direction, and the light-emitting units 100 in each column are arranged along the second direction. For example, the first direction is the row direction, and the second direction is the column direction. Naturally, the embodiments of the present disclosure are not limited thereto, and the first direction and the second direction may be any direction, and it is only necessary to intersect the first direction and the second direction. Further, the plurality of light-emitting units 100 are not limited to being arranged along a straight line, and may be arranged along a curve, arranged along an annular shape, or arranged according to any form, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0035] FIG. 3 is a schematic diagram of one light-emitting unit in the light-emitting substrate shown in FIG. 1. FIG. 4 is a schematic diagram of the pins of the drive circuit in the light-emitting unit of the light-emitting substrate shown in FIG. 1. As shown in FIGS. 1, 3, and 4, each light-emitting unit 100 includes a drive circuit 110, a plurality of light-emitting elements 120, and a drive voltage terminal Vled.

[0036] The drive circuit 110 includes a first input terminal Di, a second input terminal Pwr, an output terminal OT, and a common voltage terminal GND. The first input terminal Di receives a first input signal, which is, for example, an address signal for strobbing the drive circuit 110 of the corresponding address. For example, the addresses of different drive circuits 110 may be the same or different. The first input signal may be an 8-bit address signal, and by analyzing the address signal, the address waiting to be transmitted can be known. The second input terminal Pwr receives a second input signal, which is, for example, a power line carrier communication signal. For example, the second input signal not only supplies power to the drive circuit 110 but also transmits communication data to the drive circuit 110, and the communication data can be used to control the emission time length of the corresponding light-emitting unit 100 and further control its visual emission luminance. The output terminal OT outputs different signals at different periods, and for example, can output a relay signal and a drive signal respectively. For example, the relay signal is an address signal supplied to another drive circuit 110, that is, the first input terminal Di of another drive circuit 110 receives the relay signal as the first input signal, thereby obtaining the address signal. For example, the drive signal may be a drive current for driving the light-emitting element 120 to emit light. The common voltage terminal GND receives a common voltage signal such as a ground signal.

[0037] The drive circuit 110 outputs a relay signal via the output terminal OT during a first period based on a first input signal received by the first input terminal Di and a second input signal received by the second input terminal Pwr, and supplies a drive signal via the output terminal OT to a plurality of light-emitting elements 120 connected in series in sequence during a second period. During the first period, the output terminal OT outputs a relay signal, and the relay signal is supplied to other drive circuits 110 so that the other drive circuits 110 can acquire an address signal. During the second period, the output terminal OT outputs a drive signal, and the drive signal is supplied to a plurality of light-emitting elements 120 connected in series in sequence. As a result, the light-emitting elements 120 emit light during the second period. For example, the first period and the second period are different periods, and the first period may be earlier than the second period, for example. The first period can continuously follow the second period, and the end point of the first period is the start point of the second period, or there may be other periods between the first period and the second period. The other periods may be used to implement other necessary functions, or the other periods may be used only to separate the first period and the second period so as to avoid interference between the signals of the output terminal OT in the first period and the second period. The operating principle of the drive circuit 110 will be described in detail later, and the description is omitted here.

[0038] Note that when the drive signal is a drive current, the drive current can flow from the output terminal OT to the light-emitting element 120, and can also flow from the light-emitting element 120 to the output terminal OT. The flowing direction of the drive current may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto. In this specification, "the output terminal OT outputs a drive signal" means that the output terminal OT supplies a drive signal, and the direction of the drive signal can flow from the output terminal OT and can also flow into the output terminal OT.

[0039] For example, as shown in FIGS. 1 and 3, a plurality of light-emitting elements 120 are connected in series sequentially and are connected in series between a drive voltage terminal Vled and an output terminal OT. For example, the light-emitting element 120 may be a micro light-emitting diode (Micro-LED) or a mini light-emitting diode (Mini-LED). For example, each light-emitting element 120 includes a positive electrode (+) and a negative electrode (-) (also called an anode and a cathode), and the positive and negative electrodes of the plurality of light-emitting elements 120 are connected in series sequentially from end to end. As a result, a current path is formed between the drive voltage terminal Vled and the output terminal OT. The drive voltage terminal Vled supplies a drive voltage that becomes a high voltage during a period (second period) when it is necessary to cause the light-emitting element 120 to emit light and becomes a low voltage during other periods. Thereby, in the second period, a drive signal (for example, a drive current) flows sequentially through the plurality of light-emitting elements 120 from the drive voltage terminal Vle and then flows into the output terminal OT of the drive circuit 110. The plurality of light-emitting elements 120 emit light when a drive current flows, and by controlling the duration of the drive current, the emission time length of the light-emitting element 120 can be controlled, and thereby the visual emission luminance can be controlled.

[0040] For example, as shown in FIGS. 1 and 3, in some examples, one light-emitting unit 100 includes six light-emitting elements 120, and the six light-emitting elements 120 are arranged in two rows and three columns. For example, the six light-emitting elements 120 are sequentially numbered (1, 1), (1, 2), (1, 3), (2, 1), (2, 2), and (2, 3) from left to right and from top to top, as shown in FIG. 3. For example, when the six light-emitting elements 120 are connected in series, the light-emitting element 120 at position (2, 1) is used as the starting point of the series connection, and the light-emitting elements 120 at positions (1, 1), (2, 2), (1, 2), (2, 3), and (1, 3) are sequentially connected, and the light-emitting element 120 at position (1, 3) is used as the end point of the series connection. For example, the positive electrode of the light-emitting element 120 at position (2, 1) is connected to the drive voltage terminal Vled, and the negative electrode of the light-emitting element 120 at position (1, 3) is connected to the output terminal OT of the drive circuit 110. By adopting this distribution form and series connection form, the overlap of wiring can be effectively avoided, the design and manufacturing become easy, and furthermore, the bending shape and length of the wiring between any two adjacent light-emitting elements 120 on the series circuit are substantially the same. As a result, the resistance of the circuit itself becomes more balanced, so that the load balance can be improved and the stability of the circuit can be enhanced.

[0041] FIG. 5 is a schematic diagram of the arrangement of the light-emitting elements and the drive circuit in the light-emitting unit of the light-emitting substrate shown in FIG. 1. As shown in FIG. 5, in the same light-emitting unit 100, a plurality (for example, six) of light-emitting elements 120 are arranged in an array, for example, arranged in a plurality of rows and a plurality of columns, whereby the light emission can be made more uniform. The drive circuit 110 is located within the gaps of the array formed by the plurality of light-emitting elements 120.

[0042] In addition, in the embodiments of the present disclosure, the number of light-emitting elements 120 in each light-emitting unit 100 is not limited and may be any number such as 4, 5, 7, 8, etc., and is not limited to six. The plurality of light-emitting elements 120 can adopt any array form. For example, they may be arranged according to a required pattern and are not limited to a matrix array form. The installation position of the drive circuit 110 is not limited and may be installed in any gap between the light-emitting elements 120, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0043] The operating principle of the drive circuit 110 will be briefly described below.

[0044] FIG. 6A is a schematic block diagram of the principle of a drive circuit in a light-emitting unit of a light-emitting substrate according to some embodiments of the present disclosure. As shown in FIG. 6A, the drive circuit 110 includes a demodulation circuit 111, a physical layer interface circuit 112, a data processing control circuit 113, a pulse width modulation circuit 114, a drive signal generation circuit 115, a relay signal generation circuit 116, and a power supply circuit 117.

[0045] For example, the demodulation circuit 111 is electrically connected to the second input terminal Pwr and the physical layer interface circuit 112, configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit 112. For example, the second input signal input by the second input terminal Pwr is a power line carrier communication signal, and the power line carrier communication signal includes information corresponding to the communication data. For example, the communication data is data reflecting the light-emitting time length and further represents the required light-emitting luminance. Compared with the normal Serial Peripheral Interface (SPI) protocol, the embodiments of the present disclosure adopt the Power Line Carrier Communication (PLC) protocol to superimpose the communication data on the power signal, thereby effectively reducing the number of signal lines.

[0046] FIG. 6B is a waveform diagram of the second input signal in the drive circuit shown in FIG. 6A. As shown in FIG. 6B, the dashed ellipse box represents an enlarged view of the corresponding waveform. When the second input signal becomes high level, its high-level amplitude value fluctuates near the threshold amplitude value Vth. For example, it changes between the first amplitude value V1 and the second amplitude value V2, where V2 < Vth < V1. By modulating the change rules of the first amplitude value V1 and the second amplitude value V2, communication data can be modulated onto the second input signal. As a result, the second input signal transmits information corresponding to the communication data while transmitting electrical energy. For example, the demodulation circuit 111 can filter the DC power supply component of the second input signal to obtain the communication data. For a detailed description of the second input signal, reference can be made to the conventional power line carrier communication signal, and the description is omitted here. Correspondingly, for a detailed description of the demodulation circuit 111, reference can also be made to the demodulation circuit of the conventional power line carrier communication signal, and the description is omitted here.

[0047] For example, the physical layer interface circuit 112 is further electrically connected to the data processing control circuit 113, configured to process communication data to obtain a data frame (such as frame frequency data), and transmit the data frame to the data processing control circuit 113. The data frame obtained by the physical layer interface circuit 112 needs to include information related to the emission time (such as the specific time duration of the emission time) and other information required to be transmitted to the drive circuit 110. For example, the physical layer interface circuit 112 may be a normal port physical layer (PHY: Physical). For a detailed description, reference can be made to the conventional design, and it will not be described in detail here.

[0048] For example, the data processing control circuit 113 is further electrically connected to a first input terminal Di, a pulse width modulation circuit 114, and a relay signal generation circuit 116. The data processing control circuit 113 is configured to generate a pulse width control signal based on a data frame, transmit the pulse width control signal to the pulse width modulation circuit 114, generate a relay control signal based on a first input signal, and transmit the relay control signal to the relay signal generation circuit 116. For example, since the necessary light emission time length of the light emitting element 120 connected to the drive circuit 110 can be known from the data frame, a corresponding pulse width control signal is generated based on the light emission time length. For example, the relay control signal is a signal generated after the data processing control circuit 113 processes the first input signal. By performing processing (such as analysis, latching, decoding, etc.) on the first input signal, the address signal corresponding to the drive circuit 110 can be known, and a relay control signal corresponding to a subsequent address is generated, and the subsequent address corresponds to another drive circuit 110. For example, the data processing control circuit 113 may be realized as a single-chip microcomputer, a central processing unit (CPU), a digital signal processor, or the like.

[0049] For example, the pulse width modulation circuit 114 is further electrically connected to a drive signal generation circuit 115, and is configured to generate a pulse width modulation signal in response to the pulse width control signal and transmit the pulse width modulation signal to the drive signal generation circuit 115. For example, the pulse width modulation signal generated by the pulse width modulation circuit 114 corresponds to the necessary light emission time length of the light emitting element 120. For example, the effective pulse width time length is equal to the necessary light emission time length of the light emitting element 120. For example, for a detailed description of the pulse width modulation circuit 114, a conventional pulse width modulation circuit can be referred to, and the detailed description is omitted here.

[0050] For example, the drive signal generation circuit 115 is further electrically connected to the output terminal OT, and is configured to generate a drive signal in response to the pulse width modulation signal and output the drive signal from the output terminal OT. Here, outputting the drive signal from the output terminal OT can indicate that the drive signal (for example, drive current) flows from the output terminal OT to the light emitting element 120, and can also indicate that the drive signal (for example, drive current) flows from the light emitting element 120 to the output terminal OT. The specific current direction is not limited.

[0051] For example, in some examples, when the drive signal is a drive current, the drive signal generation circuit 115 can include a current source A and a metal oxide semiconductor (MOS) field effect transistor (FET), and the metal oxide semiconductor field effect transistor is called a MOS tube. The control electrode of the MOS tube receives the pulse width modulation signal transmitted by the pulse width modulation circuit 114, and thereby turns on or off under the control of the pulse width modulation signal. The first electrode of the MOS tube is connected to the output terminal OT, the second electrode of the MOS tube is connected to the first electrode of the current source A, and the second electrode of the current source A is connected to the common voltage terminal GND to receive a common voltage. For example, the current source A may be a constant current source.

[0052] When the pulse-width modulation signal becomes the effective level, the MOS tube turns on, and the current source A supplies a drive current via the output terminal OT. When the pulse-width modulation signal becomes the invalid level, the MOS tube turns off, and at this time, the output terminal OT does not supply a drive current. The time length of the effective level of the pulse-width modulation signal is equal to the on-time length of the MOS tube, and the on-time length of the MOS tube is equal to the time length during which the output terminal OT supplies a drive current. Thereby, the light emission time length of the light-emitting element 120 can be further controlled, and the visual light emission luminance can be further controlled. For example, in some examples, when the MOS tube turns on, the drive current flows from the OT output terminal to the drive circuit 110, sequentially flows through the MOS tube and the current source A, and then flows to the ground terminal (for example, the common voltage terminal GND). It should be noted that in the embodiments of the present disclosure, the drive signal generation circuit 115 can further adopt other circuit structure forms, but the embodiments of the present disclosure are not limited thereto.

[0053] For example, the relay signal generation circuit 116 is further electrically connected to the output terminal OT, and is configured to generate a relay signal based on a relay control signal and output the relay signal from the output terminal OT. For example, the relay control signal corresponds to a subsequent address, and the relay signal generated based on the relay control signal includes the subsequent address, and the subsequent address corresponds to another drive circuit 110. After the relay signal is output from the output terminal OT, it is supplied to the first input terminal Di of the separately provided drive circuit 110, and the relay signal is input to the separately provided drive circuit 110 as the first input signal, whereby the separately provided drive circuit 110 acquires the corresponding address signal. The relay signal generation circuit 116 may be realized by a latch, a decoder, an encoder, etc., and the embodiments of the present disclosure are not limited thereto.

[0054] In addition, in the embodiments of the present disclosure, both the drive signal generation circuit 115 and the relay signal generation circuit 116 are electrically connected to the output terminal OT. However, the drive signal generation circuit 115 and the relay signal generation circuit 116 output a drive signal and a relay signal respectively during different periods, and the drive signal and the relay signal are transmitted in a time-sharing manner via the output terminal OT, so they do not affect each other.

[0055] For example, the power supply circuit 117 is electrically connected to the demodulation circuit 111 and the data processing control circuit 113 respectively, and is configured to receive electrical energy and supply power to the data processing control circuit 113. For example, the second input signal is a power line carrier communication signal. After being demodulated by the demodulation circuit 111, the DC power supply component (i.e., electrical energy) of the second input signal is transmitted to the power supply circuit 117 and supplied to the data processing control circuit 113 by the power supply circuit 117. Naturally, the embodiments of the present disclosure are not limited thereto, and the power supply circuit 117 can also be electrically connected to other circuits in the drive circuit 110 to supply electrical energy. The power supply circuit 117 can be realized by a switching circuit, a voltage conversion circuit, a voltage stabilization circuit, etc., but the embodiments of the present disclosure are not limited thereto.

[0056] Note that in the embodiments of the present disclosure, the drive circuit 110 is not limited to the above-described demodulation circuit 111, physical layer interface circuit 112, data processing control circuit 113, pulse width modulation circuit 114, drive signal generation circuit 115, relay signal generation circuit 116, and power supply circuit 117, and can further include more circuits and components. This may be determined according to the functions required for implementation, and the embodiments of the present disclosure are not limited thereto.

[0057] FIG. 6C is a schematic diagram of the operation process of the drive circuit shown in FIG. 6A. FIG. 6D is a signal time chart of the drive circuit shown in FIG. 6A.

[0058] As shown in FIGS. 6C and 6D, when the drive circuit 110 is operating, first, the power is turned on (i.e., current is passed through) to complete initialization, and then an address writing operation is executed in period S1. That is, in period S1, the first input signal Di_1 is input to the drive circuit 110 via the first input terminal Di, whereby an address is written. For example, the first input signal Di_1 is transmitted via a separately provided transmitter.

[0059] Next, in period S2, a drive configuration is executed, and a relay signal Di_2 is output via the output terminal OT. For example, the relay signal Di_2 is input to the first input terminal Di of the drive circuit 110 provided separately as the first input signal. For example, the first period is period S2.

[0060] Next, in period S3, the drive voltage terminal Vled is energized. For example, after all the plurality of drive circuits 110 have acquired the corresponding addresses, it enters period S3 after an interval of about 10 microseconds. In this case, the drive voltage supplied from the drive voltage terminal Vled becomes high level.

[0061] Next, in period S4, the drive circuit 110 is in the normal operation mode, and the output terminal OT supplies a drive signal (e.g., drive current) according to the required time length so that the light-emitting element 120 connected to the drive circuit 110 emits light according to the required time length. For example, the second period is period S4. For example, in the case of the backlight unit of a display device, the light-emitting substrate 10 using the drive circuit 110 can operate in the local dimming mode and realize a high dynamic range effect.

[0062] Finally, in period S5, the system is turned off, that is, the power of the drive circuit 110 is turned off, the drive voltage supplied by the drive voltage terminal Vled becomes low level, and the light-emitting element 120 stops emitting light.

[0063] Note that the above operation process is merely exemplary and not restrictive. The actual operation process of the drive circuit 110 may be determined according to actual needs, but the embodiments of the present disclosure are not limited thereto. In FIG. 6D, VREG, POR, Vreg_1.8, OSC, and Researt_B are all internal signals of the drive circuit 110 and are not input or output via the first input terminal Di, the second input terminal Pwr, the output terminal OT, and the common voltage terminal GND. Di_1 is the first input signal received by the drive circuit 110, Di_2 is the relay signal output by the drive circuit 110 (i.e., the first input signal received by the next connected drive circuit 110), and Di_n is the first input signal received by the nth drive circuit 110 in a plurality of sequentially connected drive circuits 110.

[0064] For example, the drive circuit 110 may be implemented as a chip. The chip size (e.g., length) is several tens of micrometers, the chip area is about several hundred square micrometers or less, which is the same size as the mini LED, has the feature of miniaturization, facilitates integration (e.g., soldering) to the light-emitting substrate 10, does not need to be installed outside the light-emitting substrate 10 by bonding, saves the installation space of the printed circuit board, simplifies the structure, and is advantageous for realizing thin and light. Since each drive circuit 110 directly drives one light-emitting unit 100, problems such as complex operation and easy blinking in the line scanning control mode can be avoided. Moreover, the drive circuit 110 has few ports, few required signals, a simple control form, a simple wiring form, and low cost.

[0065] For example, as shown in FIG. 1, the light-emitting substrate 10 further includes a plurality of address patch codes 130. The plurality of address patch codes 130 extend in the first direction and are configured to transmit the first input signal.

[0066] For example, a plurality of light-emitting units 100 in the light-emitting substrate 10 are arranged in N rows and M columns, divided into a plurality of groups. Each group of light-emitting units 100 includes a total of X*M light-emitting units 100 in X rows and M columns. A plurality of address patch codes 130 correspond one-to-one to the plurality of groups of light-emitting units 100. At this time, the light-emitting units 100 are divided into N / X groups. For example, in the example shown in FIG. 1, each group of light-emitting units 100 includes a total of 10 light-emitting units 100 in 2 rows and 5 columns. Therefore, the light-emitting units 100 every 2 rows correspond to one address patch code 130, and the number of address patch codes 130 in the light-emitting substrate 10 is N / 2. For example, N is an integer greater than 0, M is an integer greater than 0, 0 < X ≤ N, and X is an integer.

[0067] For example, in the light-emitting units 100 of the same group, the X*M light-emitting units 100 are sequentially numbered according to the distribution positions of rows and columns. For example, in some examples, as shown in FIG. 7A, the X*M light-emitting units are numbered row by row and column by column in a zigzag pattern. Each rectangle in FIG. 7A represents one light-emitting unit 100, and the number of each light-emitting unit 100 is marked in each rectangle. For example, in some other examples, as shown in FIG. 7B, the X*M light-emitting units are numbered row by row and column by column in an S-shaped pattern. Similarly, each rectangle in FIG. 7B represents one light-emitting unit 100, and the number of each light-emitting unit 100 is marked in each rectangle. Note that the form of numbering the light-emitting units 100 according to the distribution positions of rows and columns is not limited to the above form, and numbers can also be assigned according to other forms. Thereby, the connection form of the plurality of light-emitting units 100 may be flexibly adjusted, and the embodiments of the present disclosure are not limited thereto.

[0068] For example, as shown in FIG. 1, in the light-emitting units 100 of the same group, the first input terminal Di of the drive circuit 110 of the light-emitting unit 100 numbered 1 is electrically connected to the address patch code 130 corresponding to the light-emitting units 100 of the group. The output terminal OT of the drive circuit 110 of the light-emitting unit 100 numbered P is electrically connected to the first input terminal Di of the drive circuit 110 of the light-emitting unit 100 numbered P + 1. The first input terminal Di of the drive circuit 110 of the light-emitting unit 100 numbered P + 1 receives, as the first input signal, the relay signal output by the output terminal OT of the drive circuit 110 of the light-emitting unit 100 numbered P. For example, 0 < P < X * M, and P is an integer.

[0069] For example, when the numbering form shown in FIG. 7A is adopted, for the light-emitting units 100 of a group numbered 1 (i.e., the group of light-emitting units 100 at the uppermost side of the light-emitting substrate 10, or the group of light-emitting units 100 called the first group of light-emitting units 100), the first input terminal Di of the drive circuit 110 of the light-emitting units 100 in the first row and the first column is electrically connected to the address patch code 130 corresponding to the light-emitting units 100 of the group. The output terminal OT of the drive circuit 110 of each light-emitting unit 100 is electrically connected to the first input terminal Di of the drive circuit 110 of the next light-emitting unit 100 (the output terminal OT of the drive circuit 110 of the last light-emitting unit 100 is not connected to other drive circuits 110). For the light-emitting units 100 of a group numbered 2 (i.e., the group of light-emitting units 100 adjacent to the first group of light-emitting units 100, or the group of light-emitting units 100 called the second group of light-emitting units 100), the first input terminal Di of the drive circuit 110 of the light-emitting units 100 in the third row and the first column is electrically connected to the address patch code 130 corresponding to the light-emitting units 100 of the group. The output terminal OT of the drive circuit 110 of each light-emitting unit 100 is electrically connected to the first input terminal Di of the drive circuit 110 of the next light-emitting unit 100, and its connection form is similar to that of the first group of light-emitting units 100.

[0070] With the above connection form, in each group of light-emitting units 100, only the first input terminal Di of the drive circuit 110 of the first light-emitting unit 100 is electrically connected to the address patch code 130, while the first input terminals Di of the drive circuits 110 of the other light-emitting units 100 receive the relay signal output by the drive circuit 110 of the previous light-emitting unit 100 as the first input signal. Thus, in the case of one group of light-emitting units 100, by supplying only one first input signal (i.e., address signal) via one address patch code 130, all the light-emitting units 100 in the group of light-emitting units 100 can acquire their respective address signals. As a result, the number of signal lines is significantly reduced, the wiring space is saved, and the control method is simplified.

[0071] For example, as shown in FIG. 1, the light-emitting substrate 10 further includes a plurality of voltage patch codes 140. The plurality of voltage patch codes 140 extend along the first direction and are configured to transmit a second input signal, and the plurality of voltage patch codes 140 correspond one-to-one to the light-emitting units in N rows. For example, each row of light-emitting units 100 corresponds to one voltage patch code 140, and the number of voltage patch codes 140 on the light-emitting substrate 10 is N. For example, as shown in FIG. 1, the light-emitting units 100 in the first row, the light-emitting units 100 in the second row, and the light-emitting units 100 in the third row each correspond to one voltage patch code 140.

[0072] For example, in the case of the light-emitting units 100 in one row, the second input terminal Pwr of the drive circuit 110 in the light-emitting units 100 is electrically connected to the voltage patch code 140 corresponding to the row where the light-emitting units 100 including the drive circuit 110 are located. That is, the second input terminals Pwr of all the drive circuits 110 in the light-emitting units 10 in one row are all electrically connected to the voltage patch code 140 corresponding to that row to receive the second input signal.

[0073] For example, as shown in FIG. 1, the light-emitting substrate 10 further includes a plurality of source address lines 150 and a plurality of source voltage lines 160 extending along the second direction.

[0074] For example, a plurality of source address lines 150 are electrically connected in a one-to-one correspondence with a plurality of address patch codes 130 and are configured to transmit a first input signal. For example, the number of source address lines 150 is equal to the number of address patch codes 130, and both are equal to N / X. That is, when the light emitting units 100 are divided into N / X groups, each group of light emitting units 100 corresponds to one source address line 150 and one address patch code 130, and the source address line 150 and the address patch code 130 transmit the first input signal to the first light emitting unit 100 in the group of light emitting units 100. For example, as shown in FIG. 1, the source address line xAddr1 transmits the first input signal to the first group of light emitting units 100, and the source address line xAddr2 transmits the first input signal to the second group of light emitting units 100.

[0075] For example, a plurality of source voltage lines 160 are in one-to-one correspondence with a plurality of groups of light emitting units 100, and each source voltage line 160 is electrically connected to a plurality of voltage patch codes 140 corresponding to one group of light emitting units 100 and is configured to transmit a second input signal. For example, the number of source voltage lines 160 is N / X. That is, when the light emitting units 100 are divided into N / X groups, each group of light emitting units 100 corresponds to one source voltage line 160, and the source voltage line 160 transmits the second input signal to a plurality of voltage patch codes 140 corresponding to the group of light emitting units 100, thereby supplying the second input signal to all the light emitting units 100 in the group of light emitting units 100. For example, the source address line 150 and the source voltage line 160 of the light emitting units 100 in the same group are provided adjacent to each other.

[0076] For example, as shown in FIG. 1, the source voltage line xPwr1 is electrically connected to two voltage patch codes 140 corresponding to the first group of light-emitting units 100 to supply a second input signal to the light-emitting units 100 in the first row and the second row. The source voltage line xPwr2 is electrically connected to two voltage patch codes 140 corresponding to the second group of light-emitting units 100, thereby supplying a second input signal to the light-emitting units 100 in the third row and the fourth row (the light-emitting unit 100 in the fourth row and the corresponding voltage patch code 140 are not shown in the figure).

[0077] In addition, in the light-emitting units 100 of the same group, the second input terminals Pwr of the drive circuits 110 of all the light-emitting units 100 are electrically connected to the corresponding voltage patch codes 140, and these voltage patch codes 140 are connected to the same source voltage line 160. Thereby, in the case of one group of light-emitting units 100, by supplying only one second input signal via one source voltage line 160, all the light-emitting units 100 in the light-emitting units 100 of the group can obtain the second input signal. As a result, the number of signal lines is significantly reduced, the wiring space is saved, and the control method is simplified.

[0078] For example, in the light-emitting substrate 10, both the number of source address lines 150 and the number of source voltage lines 160 are N / X.

[0079] For example, in some examples, on the base substrate 01, the source address line 150 and the source voltage line 160 are located in the same layer, the voltage patch code 140 and the address patch code 130 are located in the same layer, and the source address line 150 and the address patch code 130 are located in different layers. That is, the source address line 150 and the source voltage line 160 are fabricated by a one-time patterning process (e.g., a photolithography process), the voltage patch code 140 and the address patch code 130 are fabricated by another one-time patterning process, and an insulating layer is provided between the film layer where the source address line 150 and the source voltage line 160 are located and the film layer where the voltage patch code 140 and the address patch code 130 are located, and the corresponding wirings are electrically connected through via holes penetrating the insulating layer. With this configuration, the manufacturing process can be simplified, it is compatible with the normal semiconductor film layer manufacturing process, and the manufacturing efficiency can be improved.

[0080] In the embodiments of the present disclosure, the light-emitting units 100 are divided into a plurality of groups. When the above connection form is adopted, the light-emitting luminance of the light-emitting units 100 in each group may be independently controlled. For example, by setting the first input signal and the second input signal supplied to the light-emitting units 100 in each group, the light-emitting time length of the light-emitting units 100 in each group is controlled, and further the visual light-emitting luminance is controlled. The light-emitting time lengths of the light-emitting units 100 in each group may be the same or different, which may be determined according to the usage form and needs. The first input signals supplied to the light-emitting units 100 in each group are independent of each other, and the second input signals supplied to the light-emitting units 100 in each group are independent of each other. Therefore, the light-emitting luminance of the light-emitting units 100 in each group may be independently controlled. The light-emitting substrate 10 can achieve independent control of the light-emitting luminance by area, and has a wide application range. Furthermore, the driving circuit 110 has a small number of ports and a small number of required control signals. Therefore, the control form is simple, the power consumption is small, and the operation is also easy. Since the light-emitting substrate 10 has a high integration degree, high-contrast display can be realized in combination with a liquid crystal display device.

[0081] FIG. 8A is a schematic diagram of test points of a light-emitting substrate according to some embodiments of the present disclosure. For example, as shown in FIG. 8A, in some embodiments, the light-emitting substrate 10 further includes a plurality of first test points 181, a plurality of second test points 182, a plurality of third test points 183, and a plurality of fourth test points 184. For example, the plurality of light-emitting units 100 are mainly distributed in area Q. Note that all the light-emitting units 100 may be located in area Q, most of the light-emitting units 100 may be located in area Q, and some of the remaining light-emitting units 100 may be located around area Q. That is, area Q represents an approximate distribution area of more than at least 70% of the total number of the plurality of light-emitting units 100.

[0082] For example, the plurality of first test points 181 are located at the ends of the source address line 150 and the source voltage line 160 away from the light-emitting unit 100. The plurality of second test points 182 are located at the connection between the source address line 150 and the address patch code 130, and at the connection between the source voltage line 160 and the voltage patch code 140 that is the farthest from the first test point 181 in the voltage patch code 140 connected to the source voltage line 160. The plurality of third test points 183 are located at both ends of the voltage patch code 140 and at the ends of the address patch code 130 away from the light-emitting unit 100. The plurality of fourth test points 184 are located at the connection between the source voltage line 160 and the voltage patch code 140 other than the position of the second test point 182. For example, in some examples, as shown in FIG. 8A, the first test point 181 is located on the first side F1 of the light-emitting substrate 10, the second test point 182 and the fourth test point 184 are located in the middle area of the light-emitting substrate 10, and the third test point 183 is located on the second side F2 and the third side F3 of the light-emitting substrate 10.

[0083] In the manufacturing process of the mini-LED backlight, the address patch code 130 and the voltage patch code 140 are located in the same layer, the source address line 150 and the source voltage line 160 are located in the same layer, these two film layers are in different layers, and the corresponding wirings are electrically connected via via holes. However, during the manufacturing process, due to process limitations or other factors, etc., there may be disconnection of signal lines and short circuits of each signal line. As a result, the light-emitting substrate cannot operate normally. If detection is not performed and the faulty light-emitting substrate is put into the subsequent process, production resources will be wasted.

[0084] Therefore, by setting the first test point 181, the second test point 182, the third test point 183, and the fourth test point 184, the disconnection and short circuit of signal lines can be detected timely and conveniently during manufacturing and before shipment, and the faulty light-emitting substrate can be found as soon as possible, without executing the subsequent process on the faulty light-emitting substrate. Thereby, waste of production resources is avoided, the corresponding backlight process and the quality of the backlight product are effectively monitored, and the product quality is improved.

[0085] For example, each test point may be metal exposed at a certain process stage so that a probe (e.g., a test pen) is placed for detection. However, when subsequent processes are performed, the test point may be covered by a subsequent film layer (e.g., an insulating layer such as a dielectric layer) and not exposed, or may still be in an exposed state. For example, each test point is electrically connected to a corresponding signal line. The test point may be integrally formed with the corresponding signal line, or a separately provided conductive pattern may be electrically connected to the signal line by welding, adhesion with a conductive adhesive, etc., and the separately provided conductive pattern is used as the test point. The structural form and formation form of the test point are not limited to this in the embodiments of the present disclosure. For example, a voltmeter, ammeter, ohmmeter, or any other suitable test equipment is used, and a probe is used to detect the voltage, current, or resistance of the test point, thereby determining whether there are situations such as an open circuit or a short circuit in the line between two test points. For the detection principle of situations such as an open circuit or a short circuit, reference can be made to the conventional design and will not be described in detail here.

[0086] FIG. 8B and FIG. 8C are plan views of a single test point on a light-emitting substrate according to some embodiments of the present disclosure. As shown in FIG. 8B, the test point Te1 overlaps and is electrically connected to the signal line L1. The test point Te1 may be any one of the first test point 181, the second test point 182, the third test point 183, and the fourth test point, and the signal line L1 may be any one of the address patch code 130, the voltage patch code 140, the source address line 150, and the source voltage line 160. For example, the shape of the test point Te1 is circular. For example, the diameter of the circle is equal to or greater than the line width of the signal line L1, which facilitates the placement of the probe, and as a result, the probe and the signal line L1 are better electrically connected.

[0087] As shown in FIG. 8C, the test point Te2 overlaps with the signal line L2 and is electrically connected thereto. Similarly, the test point Te2 may be any one of the first test point 181, the second test point 182, the third test point 183, and the fourth test point, and the signal line L2 may be any one of the address patch code 130, the voltage patch code 140, the source address line 150, and the source voltage line 160. For example, the shape of the test point Te2 is polygonal, and specifically may be square. For example, the side length of the square is equal to or greater than the line width of the signal line L2, whereby the arrangement of the probe is facilitated, and as a result, the probe and the signal line L2 are better electrically connected.

[0088] Note that in the embodiments of the present disclosure, the shape of each test point is not limited to the above-mentioned circular and square shapes, and may be any regular or irregular shape such as a hexagonal shape, an elliptical shape, a trapezoidal shape, a rectangular shape, a triangular shape, etc., which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto. The relationship between the size of the test point and the size of the signal line may also be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0089] Hereinafter, the test form and use of each test point will be briefly described in conjunction with FIG. 8A. Here, taking as an example that the address patch code 130 and the voltage patch code 140 are located in the same layer, and the source address line 150 and the source voltage line 160 are located in the same layer and these film layers are different layers, the source address line 150 and the source voltage line 160 are manufactured by a previous process, and the address patch code 130 and the voltage patch code 140 are formed on the source address line 150 and the source voltage line 160 by a subsequent process. There is an insulating layer between the two film layers, and the corresponding wirings are electrically connected through via holes.

[0090] For example, after the source address line 150 and the source voltage line 160 are formed, by using the first test point 181 and the second test point 182, it is possible to detect whether there is an open circuit in each of the source address line 150 and the source voltage line 160. For example, a voltage can be applied to both ends of the same source address line 150 or the same source voltage line 160 by using a test pen, that is, a voltage is applied between one first test point 181 and one second test point 182, and at the same time, it is possible to test whether there is a current between these two test points. When a current is detected, there is no open circuit between the first test point 181 and the second test point 182, that is, the corresponding source address line 150 or source voltage line 160 is not open-circuited. When no current is detected, an open circuit occurs between the first test point 181 and the second test point 182, indicating that the corresponding source address line 150 or source voltage line 160 is open-circuited. For example, it is also possible to detect the resistance value between the first test point 181 and the second test point 182. When the resistance value is infinite, it indicates that an open circuit occurs between the two. When the resistance value is within a reasonable range, it indicates that no open circuit occurs between the two. For example, in some examples, a signal can be applied between the first test point Addr1_D and the second test point Addr1_U to detect whether an open circuit occurs.

[0091] For example, after the address patch code 130 and the voltage patch code 140 are formed, when using the first test point 181 and the third test point 183, it is possible to test whether the line formed by the source address line 150 and the address patch code 130 is disconnected, and whether the line formed by the source voltage line 160 and the voltage patch code 140 is disconnected. For example, a test pen can be used to apply a voltage to both ends of the same line, that is, apply a voltage between one first test point 181 and one third test point 183, and at the same time, test whether there is a current between these two test points. For example, in some examples, a signal can be applied between the first test point Addr1_D and the third test point Addr1_L to detect whether a disconnection occurs. For example, in some examples, if a disconnection occurs between the first test point Addr1_D and the third test point Addr1_L, a signal can be applied between the first test point Addr1_D and the second test point Addr1_U, and between the second test point Addr1_U and the third test point Addr1_L to detect whether a disconnection occurs in each part. The disconnection detection form is as described above, and the description is omitted here.

[0092] For example, when using the third test point 183, it is possible to test whether the voltage patch code 140 is disconnected. For example, a test pen can be used to apply a voltage to both ends of the same voltage patch code 140, that is, apply a voltage between one third test point 183 (for example, the third test point on the left side) and another third test point 183 (for example, the third test point 183 on the right side), and at the same time, test whether there is a current between these two test points. For example, in some examples, a signal can be applied between the third test point Pwr1_L and the third test point Pwr1_R to detect whether a disconnection occurs. The disconnection detection form is as described above, and the description is omitted here.

[0093] For example, when using the second test point 182 and the fourth test point 184, if a disconnection occurs after the address patch code 130 and the voltage patch code 140 are formed, the position where the disconnection occurs can be found. For example, a voltage can be applied between the second test point 182 and the fourth test point 174 corresponding to the same group of light-emitting units 100 using a test pen, and at the same time, it can be tested whether there is a current between these two test points, thereby determining which part of the line is disconnected. The disconnection detection form is as described above, and the description is omitted here.

[0094] For example, in the case of a short circuit, after the source address line 150 and the source voltage line 160 are formed, it can be detected using the first test point 181, and after the address patch code 130 and the voltage patch code 140 are formed, it can also be detected using the first test point 181. For example, a voltage can be applied between two first test points 181 using a test pen, and at the same time, it can be tested whether there is a current between these two test points. If a current is detected, a short circuit occurs between these two first test points 181, that is, a short circuit occurs between the corresponding two lines. If no current is detected, it indicates that there is no short circuit between these two first test points 181, that is, there is no short circuit between the corresponding two lines. For example, the resistance value between these two first test points 181 can also be detected. If the resistance value is infinite, it indicates that there is no short circuit between them, and if the resistance value is small within a certain range, it indicates that there is a short circuit between them. For example, in some examples, a signal can be applied between the first test point Addr1_D and the first test point Pwr1_D to detect whether a short circuit occurs. Similarly, the second test point 182 can be used to detect a short circuit, that is, a signal can be applied between two second test points 182 to detect whether a short circuit occurs.

[0095] In various embodiments of the present disclosure, the number and structure of test points are not limited and may be determined according to actual needs. For example, it is not necessary to provide test points on each signal line, but test points can be set only on some signal lines that require attention, which simplifies the manufacturing process and improves production efficiency. For example, in addition to the above test points, other test points can be set on the light-emitting substrate 10 according to the embodiments of the present disclosure to meet various test needs.

[0096] For example, as shown in FIG. 8A, in some embodiments, the light-emitting substrate 10 can further include a flexible printed circuit board (FPC). The flexible printed circuit board 170 overlaps with the source address line 150 and the source voltage line 160 and is electrically connected by bonding. The first test point 181 is located on the side of the flexible printed circuit board 170 away from the light-emitting unit 100. For example, the flexible printed circuit board 170 is also used for bonding with other components such as a light-emitting control circuit. The light-emitting control circuit can supply a plurality of first input signals and a plurality of second input signals, and these first input signals and second output signals are transmitted to each source address line 150 and source voltage line 160 through the flexible printed circuit board 170, and further transmitted to each group of light-emitting units 100 to control the light-emitting substrate 10 to emit light.

[0097] FIG. 9 is a schematic diagram of the wiring of a light-emitting substrate according to some embodiments of the present disclosure. For example, as shown in FIG. 9, in the light-emitting substrate, a plurality of source address lines 150 and a plurality of source voltage lines 160 are provided alternately.

[0098] For example, the leftmost source address line xAddr1 and source voltage line xPwr1 are used to supply a first input signal and a second input signal to the first group of light-emitting units 100. Since the first group of light-emitting units 100 is located at the uppermost side of the light-emitting substrate, the source address line xAddr1 and the source voltage line xPwr1 are long. The source address line xAddr1 and the address patch code Addr1 are electrically connected to transmit the first input signal to the first input terminal Di of the drive circuit 110 of the first light-emitting unit 100 in the group. The source voltage line xPwr1 and the plurality of address patch codes Pwr1 corresponding to the light-emitting units 100 in the group are electrically connected to transmit the second input signal to the second input terminal Pwr of the drive circuit 110 of all the light-emitting units 100 in the group.

[0099] For example, the rightmost source address line xAddrn and source voltage line xPwrn are used to supply a first input signal and a second input signal to the last group of light-emitting units 100. Since the last group of light-emitting units 100 is located at the lowermost side of the light-emitting substrate, the source address line xAddrn and the source voltage line xPwrn are short. The source address line xAddrn and the address patch code Addrn are electrically connected to transmit the first input signal to the first input terminal Di of the drive circuit 110 of the first light-emitting unit 100 in the group. The source voltage line xPwrn and the plurality of address patch codes Pwrn corresponding to the light-emitting units 100 in the group are electrically connected to transmit the second input signal to the second input terminal Pwr of the drive circuit 110 of all the light-emitting units 100 in the group.

[0100] For example, from left to right, the lengths of a plurality of source voltage lines xPwr1, xPwr2, ..., xPwrn are sequentially shortened, and the lengths of a plurality of source address lines xAddr1, xAddr2, ..., xAddrn are also sequentially shortened. Therefore, the leftmost source voltage line xPwr1 overlaps with the address patch codes Addr2, ..., Addrn-1, Addrn excluding the address patch code Addr1 to sequentially generate capacitors Cpa_1_2, ..., Cpa_1_n-1, Cpa_1_n. Similarly, the source voltage line xPwr2 overlaps with the address patch codes Addr3, ..., Addrn-1, Addrn excluding the address patch codes Addr1 and Addr2 to sequentially generate capacitors Cpa_2_3, ..., Cpa_2_n-1, Cpa_2_n. Similarly, the source voltage line xPwrn-1 overlaps with the address patch code Addrn to generate a capacitor Cpa_n-1_n. For example, the above capacitors may be parasitic capacitors generated between lines and are not single capacitors.

[0101] In the design and use process, it is necessary to make the load of the second input signal among the plurality of source voltage lines xPwr1, xPwr2, ..., xPwrn lower than a certain value, and it is necessary to make the capacitor corresponding to the second input signal as small as possible. In the light-emitting substrate shown in FIG. 9, the capacitors generated by the overlap of the source voltage lines xPwr1, xPwr2, ..., xPwrn-1 and the address patch codes Addr2, ..., Addrn-1, Addrn may cause an extra load, and therefore may have an extra impact on the optical performance of the backlight using the light-emitting substrate.

[0102] Furthermore, when applying the light-emitting substrate to a backlight and then applying the backlight to a display device, the backlight including the light-emitting substrate is usually stacked on a separately provided display panel, and the display panel is provided on the backlight. The display panel usually includes a gate driving circuit, and the gate driving circuit is formed, for example, on the left side of the display panel to form a GOA (Gate Driver On Array) circuit and is used to supply a scanning signal to pixels in the display panel. As shown in FIG. 9, since the leftmost source address line xAddr1 and source voltage line xPwr1 have a long length in the second direction, they may affect the GOA circuit in the display panel, generate signal crosstalk between the backlight source and the display panel, and thereby may have an extra impact on the display effect of the display device.

[0103] FIG. 10 is a schematic diagram of the wiring of a light-emitting substrate according to some embodiments of the present disclosure. The light-emitting substrate can effectively avoid the above problems.

[0104] For example, as shown in FIG. 10, in some embodiments, a plurality of source address lines 150 are arranged along the first direction, the lengths of the plurality of source address lines 150 along the second direction are different from each other, and among the two source address lines 150 farthest along the first direction, the length of the source address line 150 closer to the gate driving circuit of the display panel stacked on the light-emitting substrate 10 is shorter than the length of the source address line farther from the gate driving circuit. A plurality of source voltage lines 160 are arranged along the first direction, the lengths of the plurality of source voltage lines 160 along the second direction are different from each other, and among the two source voltage lines 160 farthest along the first direction, the length of the source voltage line 160 closer to the gate driving circuit is shorter than the length of the source voltage line 160 farther from the gate driving circuit.

[0105] For example, in this example, N = 36, X = 4, N / X = 36 / 4 = 9. That is, the light-emitting units 100 for every 4 rows share one second input signal, and one first input signal needs to be supplied to the light-emitting units 100 for every 4 rows. The light-emitting units 100 are divided into 9 groups from top to bottom. For example, the source voltage line xPwr1 supplies the second input signal to the light-emitting units 100 in the first to fourth rows, and the source voltage line xPwr2 supplies the second input signal to the light-emitting units 100 in the fifth to eighth rows, and so on by analogy. Correspondingly, the source address line xAddr1 is connected to the first input terminal Di of the driving circuit 110 of the light-emitting unit 100 in the first row and the first column, and the source address line xAddr2 is connected to the first input terminal Di of the driving circuit 110 of the light-emitting unit 100 in the fifth row and the first column, and so on by analogy.

[0106] For example, the leftmost source address line xAddrn and source voltage line xPwrn are used to supply the first input signal and the second input signal to the light-emitting units 100 in the last group. Since the light-emitting units 100 in the last group are located at the lowermost side of the light-emitting substrate, the source address line xAdrn and source voltage line xPwrn are short. The rightmost source address line xAddr1 and source voltage line xPwr1 are used to supply the first input signal and the second input signal to the light-emitting units 100 in the first group. Since the light-emitting units 100 in the first group are located at the uppermost side of the light-emitting substrate, the source address line xAddr1 and source voltage line xPwrn are long.

[0107] For example, the plurality of source address lines 150 are parallel to each other, and the lengths of the plurality of source address lines 150 sequentially arranged along the first direction monotonically change. For example, they become longer sequentially from left to right. The plurality of source voltage lines 160 are parallel to each other, and the lengths of the plurality of source voltage lines 160 sequentially arranged along the first direction monotonically change. For example, they become longer sequentially from left to right. For example, as shown in FIGS. 1 and 10, corresponding to the source address lines 150 and source voltage lines 160 of the same group of light-emitting units 100 being provided adjacent to each other, the source address lines 150 and source voltage lines 160 are located in the gaps between the multiple rows of light-emitting units 100. By providing the source address lines 150 and source voltage lines 160 not on the leftmost or rightmost side of the multiple rows of light-emitting units 100 but in the gaps between the multiple rows of light-emitting units 100, it is possible to avoid the signals in the source address lines 150 and source voltage lines 160 from affecting the display panel stacked on the light-emitting substrate 10.

[0108] For example, the source voltage line 160 does not overlap with any of the address patch codes 130. Therefore, no capacitor (parasitic capacitor) is generated between the source voltage line 160 and the address patch code 130, so no extra load is caused, thereby improving the optical performance of the backlight using the light-emitting substrate 10.

[0109] Furthermore, the gate driving circuit is usually provided on the leftmost side of the display panel. Since the lengths of the source address line xAddrn and the source voltage line xPwrn on the leftmost side of the light-emitting substrate 10 in the second direction are short, the influence on the gate driving circuit is small, and crosstalk between the backlight light source and the display panel can be reduced or avoided, thereby improving the display effect of the display device.

[0110] In addition, in the embodiments of the present disclosure, the installation positions of the address patch code 130, the voltage patch code 140, the source address line 150, and the source voltage line 160 may be changed according to needs, and are not limited to the forms shown in FIGS. 9 and 10. Thereby, it can better adapt to the application scenario and better meet the application needs.

[0111] FIG. 11 is a schematic diagram of another light-emitting substrate according to some embodiments of the present disclosure. For example, as shown in FIG. 11, in some embodiments, the light-emitting substrate 10 further includes a plurality of first driving voltage lines 191 and a plurality of first common voltage lines 201 extending along the second direction, and a plurality of second driving voltage lines 192 and a plurality of second common voltage lines 202 extending along the first direction.

[0112] For example, the first driving voltage line 191 is electrically connected to the driving voltage terminal Vled of each light-emitting unit 100 and is configured to transmit a driving voltage. The second driving voltage line 192 is electrically connected to the first driving voltage line 191 to form a grid-like wiring, reduce the transmission resistance, and improve the voltage uniformity in the light-emitting substrate 10.

[0113] For example, the first common voltage line 201 is electrically connected to the common voltage terminal GND of the driving circuit 110 of each light-emitting unit 100 and is configured to transmit a common voltage (for example, a ground voltage). The second common voltage line 202 is electrically connected to the first common voltage line 201 to form a grid-like wiring, reduce the transmission resistance, and improve the voltage uniformity in the light-emitting substrate 10.

[0114] For example, the first driving voltage line 191 and the first common voltage line 201 are located in the same layer and are located in the same layer as the source address line 150 and the source voltage line 160. Since the first driving voltage line 191, the first common voltage line 201, the source address line 150, and the source voltage line 160 all extend along the second direction, the four may be provided in the same layer without overlapping each other, thereby simplifying the structure and the manufacturing process.

[0115] For example, the second driving voltage line 192 and the second common voltage line 202 are located in the same layer and are also located in the same layer as the address patch code 130 and the voltage patch code 140. Since the second driving voltage line 192, the second common voltage line 202, the address patch code 130, and the voltage patch code 140 all extend along the first direction, the four may be provided in the same layer without overlapping each other, thereby simplifying the structure and the manufacturing process.

[0116] Note that the film layer where the first driving voltage line 191 in FIG. 11 is located is located under the light-emitting element 120. Therefore, the first driving voltage line 191 may extend under the positive electrode of the light-emitting element 120 and be electrically connected to the positive electrode of the light-emitting element 120 through a via hole. That is, the first driving voltage line 191 can transmit the driving voltage to the positive electrode of the light-emitting element 120 (that is, transmit it to the driving voltage terminal Vled). The negative electrode of the light-emitting element 120 in FIG. 11 overlaps with the first driving voltage line 191, but since the two are located in different film layers, the negative electrode of the light-emitting element 120 is not electrically connected to the first driving voltage line 191. For example, the film layer where the first common voltage line 201 is located is under the driving circuit 110. Therefore, the first common voltage line 201 is located under the driving circuit 110 and is electrically connected to the common voltage terminal GND of the driving circuit 110 through a via hole.

[0117] Note that in the embodiments of the present disclosure, the lengths and widths of the first driving voltage line 191, the second driving voltage line 192, the first common voltage line 201, and the second common voltage line 202 can be set to arbitrary values, and their lengths may be the same or different, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0118] At least one embodiment of the present disclosure further provides a display device including a display panel and a light-emitting substrate described in any one of the embodiments of the present disclosure. The display device can achieve independent control of the light-emitting luminance for each area, has low power consumption, high integration, a simple control form, and can achieve high-contrast display in combination with a liquid crystal display device.

[0119] FIG. 12 is a cross-sectional view of a display device according to some embodiments of the present disclosure. For example, as shown in FIG. 12, in some embodiments, the display device 20 includes a display panel 210 and a light-emitting substrate 220. For example, the light-emitting substrate 220 may be a light-emitting substrate according to any embodiment of the present disclosure, for example, the above-described light-emitting substrate 10.

[0120] For example, the display panel 210 has a display side P1 and a non-display side P2 facing the display side P1, and the light-emitting substrate 220 is provided on the non-display side P2 of the display panel 210 as a backlight unit. For example, the light-emitting substrate 220 can provide a backlight to the display panel 210 as a surface light source. For example, the display panel 210 may be an LCD panel, an electronic paper display panel, etc., and the embodiments of the present disclosure are not limited thereto.

[0121] For example, the display device 20 may be an LCD device, an electronic paper display device, etc., or may be other devices having a display function, etc., and the embodiments of the present disclosure are not limited thereto. For example, the display device 20 may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an e-book, etc., and the embodiments of the present disclosure are not limited thereto.

[0122] Note that the light-emitting substrate 10 according to the embodiments of the present disclosure can be applied to the above-described display device 20 as a backlight unit, and may be used alone as a substrate having a display function or a light-emitting function, and the embodiments of the present disclosure are not limited thereto.

[0123] For a detailed description and technical effects of the display device 20, reference can be made to the description of the above-described light-emitting substrate 10, and the description is omitted here. The display device 20 can further include more members and structures, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0124] At least one embodiment of the present disclosure further provides a method for driving a light-emitting substrate, and by this driving method, the light-emitting substrate according to any embodiment of the present disclosure can be driven. By this driving method, independent control for each area to the light-emitting luminance can be realized, the control form is simple, and high-contrast display can be realized in combination with a liquid crystal display device.

[0125] For example, in some embodiments, the driving method includes the following operations: Supply a first input signal and a second input signal, output a relay signal to the output terminal OT in a first period, and supply a driving signal to a plurality of light-emitting elements 120 connected in series in sequence to the output terminal OT in a second period, whereby the plurality of light-emitting elements 120 are caused to emit light by the action of the driving signal within the second period.

[0126] For a detailed description and technical effects of the driving method, reference can be made to the description of the above light-emitting substrate 10, and the description is omitted here. The driving method can further include more steps and operations, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0127] It is necessary to explain the following points: (1) The drawings of the embodiments of the present disclosure are only related to the structure according to the embodiments of the present disclosure, and for other structures, normal designs can be referred to. (2) If there is no contradiction, the embodiments and features of the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0128] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should conform to the protection scope of the above patent claims.

Claims

1. A light-emitting substrate, comprising a plurality of light-emitting units arranged in an array, each light-emitting unit including a drive circuit, a plurality of light-emitting elements, and a drive voltage terminal, wherein the drive circuit includes a first input terminal, a second input terminal, and an output terminal, the plurality of light-emitting elements are connected in series in sequence and are connected between the drive voltage terminal and the output terminal, the drive circuit is configured to output a relay signal via the output terminal during a first period and supply a drive signal via the output terminal to the plurality of light-emitting elements connected in series in sequence during a second period based on a first input signal received by the first input terminal and a second input signal received by the second input terminal, the drive circuit includes a demodulation circuit, a physical layer interface circuit, a data processing control circuit, a pulse width modulation circuit, a drive signal generation circuit, and a relay signal generation circuit, the demodulation circuit is electrically connected to the second input terminal and the physical layer interface circuit, configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit, the physical layer interface circuit is further electrically connected to the data processing control circuit, configured to process the communication data to obtain a data frame, and transmit the data frame to the data processing control circuit, the data processing control circuit is further electrically connected to the first input terminal, the pulse width modulation circuit, and the relay signal generation circuit, configured to generate a pulse width control signal based on the data frame, transmit the pulse width control signal to the pulse width modulation circuit, generate a relay control signal based on the first input signal, and transmit the relay control signal to the relay signal generation circuit, the pulse width modulation circuit is further electrically connected to the drive signal generation circuit, configured to generate a pulse width modulation signal in response to the pulse width control signal, and transmit the pulse width modulation signal to the drive signal generation circuit, the drive signal generation circuit is further electrically connected to the output terminal, configured to generate the drive signal in response to the pulse width modulation signal, and output the drive signal from the output terminal The relay signal generation circuit is further electrically connected to the output terminal, and is configured to generate the relay signal based on the relay control signal and output the relay signal from the output terminal. Light-emitting substrate. **Claim 2** The second input signal is a power line carrier communication signal. The power line carrier communication signal includes information corresponding to the communication data. The light-emitting substrate according to claim 1. **Claim 3** Further including a plurality of address patch codes, the plurality of address patch codes extend along a first direction, and are configured to transmit the first input signal. The plurality of light-emitting units are arranged in N rows and M columns, and are divided into a plurality of groups. Each of the light-emitting units in a group includes a total of X*M light-emitting units arranged in X rows and M columns. The plurality of address patch codes correspond one-to-one with the light-emitting units of the plurality of groups. In the light-emitting units of the same group, the X*M light-emitting units are sequentially numbered according to the distribution positions of rows and columns. The first input terminal of the driving circuit of the light-emitting unit numbered 1 is electrically connected to the address patch code corresponding to the light-emitting units of the group. The output terminal of the driving circuit of the light-emitting unit numbered P is electrically connected to the first input terminal of the driving circuit of the light-emitting unit numbered P+1. The first input terminal of the driving circuit of the light-emitting unit numbered P+1 receives the relay signal output by the output terminal of the driving circuit of the light-emitting unit numbered P as the first input signal. N is an integer greater than 0. M is an integer greater than 0. 0 < X ≤ N, X is an integer, 0 < P < X*M and P is an integer. The light-emitting substrate according to claim 2. **Claim 4** In the light-emitting units of the same group, the X*M light-emitting units are sequentially numbered row by row and column by column according to a Z-shape, or are sequentially numbered row by row and column by column according to an S-shape. The light-emitting substrate according to claim 3. **Claim 5** Further including a plurality of voltage patch codes. The plurality of voltage patch codes extend along the first direction and are configured to transmit the second input signal. The plurality of voltage patch codes correspond one-to-one with the light-emitting units in N rows. The second input terminal of the driving circuit is electrically connected to the voltage patch code corresponding to the row where the light-emitting unit including the driving circuit is located. The light-emitting substrate according to claim 3 or 4. **Claim 6** Further including a plurality of source address lines and a plurality of source voltage lines extending along a second direction, The plurality of source address lines are electrically connected in a one-to-one correspondence with the plurality of address patch codes and are configured to transmit the first input signal, The plurality of source voltage lines correspond in a one-to-one correspondence to the plurality of groups of light-emitting units, Each source voltage line is electrically connected to a plurality of voltage patch codes corresponding to one corresponding group of light-emitting units and is configured to transmit the second input signal, The first direction intersects the second direction, The light-emitting substrate according to claim 5.

7. The source address lines and the source voltage lines are located in the same layer, The voltage patch codes and the address patch codes are located in the same layer, The source address lines and the address patch codes are located in different layers, The light-emitting substrate according to claim 6.

8. Further including a plurality of first test points, a plurality of second test points, a plurality of third test points, and a plurality of fourth test points, The plurality of first test points are located at ends of the source address lines and the source voltage lines that are away from the light-emitting units, The plurality of second test points are located at connection portions between the source address lines and the address patch codes, and at connection portions between the source voltage lines and the voltage patch code that is farthest from the first test point among the voltage patch codes connected to the source voltage lines, The plurality of third test points are located at both ends of the voltage patch codes and at ends of the address patch codes that are away from the light-emitting units, The plurality of fourth test points are located at connection portions other than the position of the second test point at the connection portion between the source voltage lines and the voltage patch codes, The light-emitting substrate according to claim 6 or 7.

9. The plurality of source address lines are arranged along the first direction, and lengths of the plurality of source address lines along the second direction are different from each other, Among the two source address lines that are farthest along the first direction, the length of the source address line closer to the gate driving circuit of the display panel stacked on the light-emitting substrate is shorter than the length of the source address line farther from the gate driving circuit, The plurality of source voltage lines are arranged along the first direction, and lengths of the plurality of source voltage lines along the second direction are different from each other, Among the two source voltage lines farthest along the first direction, the length of the source voltage line closer to the gate drive circuit is shorter than the length of the source voltage line farther from the gate drive circuit. The light-emitting substrate according to any one of claims 6 to 8.

10. The plurality of source address lines are parallel to each other, and the lengths of the plurality of source address lines arranged sequentially along the first direction change monotonically. The plurality of source voltage lines are parallel to each other, and the lengths of the plurality of source voltage lines arranged sequentially along the first direction change monotonically. The light-emitting substrate according to claim 9.

11. The source address line and the source voltage line corresponding to the same light-emitting unit in the same group are installed adjacent to each other. The light-emitting substrate according to claim 9 or 10.

12. The source voltage line does not overlap with the address patch code. The light-emitting substrate according to any one of claims 9 to 11.

13. The source address line and the source voltage line are located in the gaps between the plurality of rows of light-emitting units. The light-emitting substrate according to any one of claims 6 to 12.

14. Further including a plurality of first drive voltage lines and a plurality of first common voltage lines extending along the second direction. The first drive voltage line is electrically connected to the drive voltage terminal of each light-emitting unit and is configured to transmit a drive voltage. The drive circuit further includes a common voltage terminal. The first common voltage line is electrically connected to the common voltage terminal of the drive circuit of each light-emitting unit and is configured to transmit a common voltage. The light-emitting substrate according to claim 6.

15. The first drive voltage line and the first common voltage line are located in the same layer and are located in the same layer as the source address line and the source voltage line. The light-emitting substrate according to claim 14.

16. Further including a plurality of second drive voltage lines and a plurality of second common voltage lines extending along the first direction. The second drive voltage line is electrically connected to the first drive voltage line and forms a grid-like wiring. The second common voltage line is electrically connected to the first common voltage line and forms a grid-like wiring. The second drive voltage line and the second common voltage line are located in the same layer and are located in the same layer as the address patch code and the voltage patch code. The light-emitting substrate according to claim 14 or 15.

17. In the same light-emitting unit, the plurality of light-emitting elements are arranged in an array, and the drive circuit is arranged within a gap of the array formed by the plurality of light-emitting elements. The light-emitting substrate according to any one of claims 1 to 16.

18. The light-emitting element is a micro light-emitting diode. The light-emitting substrate according to any one of claims 1 to 16.

19. Further including a flexible printed circuit board, The flexible printed circuit board overlaps and is electrically connected to the source address line and the source voltage line, The first test point is located on a side of the flexible printed circuit board away from the light-emitting unit. The light-emitting substrate according to claim 8.

20. The light-emitting element emits light under the action of the drive signal during the second period, The demodulation circuit filters a DC power supply component of the second input signal to obtain the communication data, The data frame obtained by the physical layer interface circuit includes information that needs to be transmitted to the drive circuit, The physical layer interface circuit is a port physical layer, The data processing and control circuit generates a corresponding pulse width control signal based on the required light emission time length of the light-emitting element connected to the drive circuit determined from the data frame, and by performing processing on the first input signal, knows the address signal corresponding to the drive circuit and generates a relay control signal corresponding to a subsequent address, wherein the subsequent address corresponds to another drive circuit. The pulse width modulation circuit generates a pulse width modulation signal corresponding to the required light emission time length of the light-emitting element. The drive signal generation circuit generates a drive signal for driving the light emission of the light-emitting element. The relay signal generation circuit generates the relay signal, and among them, the relay signal generated based on the relay control signal includes a subsequent address. The light-emitting substrate according to claim 16.

21. A display device, Including a display panel and the light-emitting substrate according to any one of claims 1 to 20, The display panel has a display side and a non-display side facing the display side, The light-emitting substrate is provided on the non-display side of the display panel as a backlight unit. Display device.

22. A method for driving the light-emitting substrate according to any one of claims 14 to 16 and 20, Supplying the first input signal and the second input signal, outputting the relay signal at the output terminal during the first period, and supplying the drive signal to the plurality of light-emitting elements connected in series in sequence at the output terminal during the second period, thereby causing the plurality of light-emitting elements to emit light under the action of the drive signal within the second period, including A method for driving a light-emitting substrate.

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