Decryption device and decryption method

Abstract

To operate a decoding device by a quantum error correction code under an ultralow temperature environment.SOLUTION: A decoding device by a quantum error correction code includes a single magnetic flux quantum circuit, wherein the single magnetic flux quantum circuit includes: an observed value acquisition part for acquiring an observed value of an auxiliary quantum bit; a matching part for executing matching processing on the basis of the observed value; and an error correction part for correcting an error of a data quantum bit on the basis of the result of the matching processing.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a decoding device and a decoding method.

Background Art

[0002] A quantum computer is a technology that performs calculations by utilizing the principle of superposition in quantum mechanics. Since it is expected to solve problems such as prime factorization and quantum chemical calculations at high speed, its development is being actively promoted worldwide. A (classical) bit, which is an element constituting a classical computer, takes a value of 0 or 1. On the other hand, a quantum bit, which is an element constituting a quantum computer, can take a continuous superposition state of 0 and 1 in addition to 0 and 1. By using this superposition state, it becomes possible to simultaneously execute calculations when the bit value is 0 and when it is 1. However, when a quantum bit is observed, its value is determined to be 0 or 1, and the superposition state is broken.

[0003] Since errors are likely to occur in quantum bits, it is necessary to correct those errors in order to proceed with the calculations of a quantum computer. However, due to the nature of the quantum bits described above, it is not possible to directly observe the quantum bits to check for errors like ordinary classical bits. Therefore, Non-Patent Document 1 proposes a framework called a quantum error correction code that encodes a plurality of physical quantum bits with different roles to form one logical quantum bit.

[0004] Although several methods for realizing quantum bits are known, among them, superconducting quantum bits have high integration potential and design freedom, and are promising as the first candidate for quantum computer elements. Since superconducting quantum bits have the constraint of operating only in an extremely low temperature environment, they generally operate in a dilution refrigerator that creates an extremely low temperature environment.

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

[0006] Superconducting qubits operate in an extremely low temperature environment, while decoding devices often operate in mind of room temperature or near-room temperature environments. To operate qubits and decoding devices in different temperature environments, a huge amount of wiring is required, which limits the scalability of superconducting quantum computers. Therefore, when operating qubits in an extremely low temperature environment, there is a desire to operate the decoding device in an extremely low temperature environment as well. However, since the power consumption allowed in an extremely low temperature environment is very small, there is a problem that conventional decoding devices using quantum error correction codes are difficult to operate in an extremely low temperature environment.

[0007] The disclosed technology aims to operate a decoding device using a quantum error correction code in an extremely low temperature environment. Means for Solving the Problems

[0008] The disclosed technology is a decoding device using a quantum error correction code, comprising a single-flux quantum circuit, wherein the single-flux quantum circuit includes an observation value acquisition unit that acquires an observation value of an auxiliary qubit, a matching unit that executes a matching process based on the observation value, and an error correction unit that corrects an error of a data qubit based on a result of the matching process. Effects of the Invention

[0009] According to the disclosed technology, a decoding device using a quantum error correction code can be operated in an extremely low temperature environment. Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention (the present embodiments) will be described with reference to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the following embodiments.

[0012] Note that the numbers and titles of reference documents related to the reference technology and the like of the present embodiments are collectively described at the end of the present embodiments. In the following description, the numbers of related reference documents are indicated as "[1]" and the like.

[0013] (Overview of this Embodiment) The decoding device according to this embodiment is a decoding device using a quantum error correction code, and reduces power consumption by solving the graph matching problem using a single flux quantum (SFQ) circuit.

[0014] (Regarding the Surface Code) FIG. 1 is a diagram for explaining the surface code. The surface code is one of the typical quantum error correction codes. The surface code includes, for example, regularly arranged data qubits 201, a first auxiliary qubit 202 for detecting bit flip errors, and a second auxiliary qubit 203 for detecting phase flip errors.

[0015] The data qubits 201 are used to represent the superposition state of logical qubits and are not directly observable. The observed values of the first auxiliary qubit 202 and the second auxiliary qubit 203 give the parity of the errors occurring in the adjacent data qubits 201. Identifying the type and location of the actual errors occurring in the data qubits 201 from this parity is called decoding.

[0016] (Regarding the Surface Code) FIG. 2 is a diagram for explaining decoding. It is known that the decoding process of the surface code can be implemented by solving the graph matching problem [1]. The graph matching problem is a problem of pairing nodes 901 in a two-dimensional lattice as shown in FIG. 2, which is formed by performing a predetermined process on the error detection signal.

[0017] Here, the set of edges 902 between the paired vertices corresponds to the estimated error. The decoding device is realized by a classical computer. By combining such a decoding device that performs such matching processing with qubits, a quantum computer with error tolerance can be configured.

[0018] (Functional Configuration of the Decoding Device) FIG. 3 is a diagram showing an example of the functional configuration of the decoding device. The decoding device 10 includes an observation value acquisition unit 11, a matching unit 12, and an error correction unit 13. Each of these units is realized by a single flux quantum (SFQ) circuit.

[0019] The decoding device 10 and the quantum bit 20 are connected by a wiring 30. The observation value acquisition unit 11 acquires observation values from the first auxiliary quantum bit 202 and the second auxiliary quantum bit 203 via the wiring 30.

[0020] The matching unit 12 solves the graph matching problem based on the observation values. Specifically, the matching unit 12 executes a matching process described later. The matching process may be a process when there is no observation error or a process when there is an observation error. For example, a switch circuit that can be selected by the user may be provided according to the frequency of the observation error, the purpose of the process, etc.

[0021] When an error is detected in the data quantum bit 201, the error correction unit 13 corrects the detected error. Specifically, in the matching process described later, a process for correcting the error is executed.

[0022] The graph of the matching process is composed of units corresponding to vertices and paths corresponding to edges connecting the vertices. Each unit corresponds to one auxiliary quantum bit (the first auxiliary quantum bit 202 or the second auxiliary quantum bit 203).

[0023] The units are classified into hot units, non-hot units, boundary units, etc. The hot unit and the non-hot unit correspond to the cases where the parity represented by the observation value of the auxiliary quantum bit (the first auxiliary quantum bit 202 or the second auxiliary quantum bit 203) is odd and even, respectively. Also, the boundary unit corresponds to one boundary of the logical bit (data quantum bit 201).

[0024] (Operation of the Decryption Device) Next, the operation of the decryption device 10 will be described with reference to the drawings.

[0025] Figure 4 is a flowchart showing an example of the flow of the matching process. Figure 4 shows the flow of the process when matching within the area of one logical bit. The matching unit 12 sequentially passes a token to each unit and determines the sink unit (step S1).

[0026] Subsequently, the matching unit 12 determines the transmission direction of the spike signal from each unit other than the sink unit to point to the sink unit (step S2). Each hot unit transmits a spike signal (step S3).

[0027] Next, the non-hot unit that has received the spike signal relays the spike signal (step S4). The relayed non-hot unit stores the direction from which the spike signal was received (step S5).

[0028] Subsequently, the hot unit transmits an acknowledge signal in the direction of the first-arrived spike signal (step S6). The non-hot unit that has received the acknowledge signal relays the acknowledge signal in the stored direction (step S7).

[0029] When the acknowledge signal returns to the hot unit, the matching process ends (step S8). The data quantum bit 201 on the path through which the acknowledge signal has passed is corrected.

[0030] Next, the details of the above-described matching process will be further described with reference to the drawings.

[0031] FIG. 5 is a first diagram for explaining the matching process. In step S3 of the matching process, the matching unit 12 causes a spike signal to be transmitted from the hot unit 911 toward the hot unit 913.

[0032] Also, in step S4 of the matching process, the matching unit 12 relays the spike signal to the non-hot unit 912. Then, in step S5 of the matching process, the matching unit 12 causes the non-hot unit 912 to store the direction in which the spike signal was received (the direction toward the hot unit 911).

[0033] FIG. 6 is a second diagram for explaining the matching process. In step S6 of the matching process, the error correction unit 13 causes an acknowledge signal 916 to be transmitted to the hot unit 913 in the direction of the first-arrived spike signal 914.

[0034] In step S7 of the matching process, the non-hot unit 912 that has received the acknowledge signal 916 relays the acknowledge signal 916 in the stored direction (the direction toward the hot unit 911). In FIG. 6, the relayed acknowledge signal is transmitted as the acknowledge signal 918 to the hot unit 911.

[0035] Also, when matching the boundary of logical bits, in step S3 of the matching process, the matching unit 12 causes the boundary unit (Boundary Unit) to send a spike signal to each unit (Unit) adjacent to the boundary. The processing after step S4 is the same as the flow of the processing when matching within the area of one logical bit.

[0036] FIG. 7 is a third diagram for explaining the matching process. When matching the boundary of logical bits, in step S3 of the matching process, the matching unit 12 causes the boundary unit (Boundary Unit) 919 to send a spike signal to each unit (Unit) (e.g., non-hot unit (Non-hot Unit) 920) adjacent to the boundary.

[0037] Next, the processing of each unit in the matching process will be described. The observed value of the auxiliary quantum bit (the first auxiliary quantum bit 202 or the second auxiliary quantum bit 203) is held in the variable Reg as 0 when the error parity is even and 1 when it is odd. When there is no observation error, the variable Reg is a 1-bit value. On the other hand, when there is an observation error, the variable Reg becomes an array that holds multiple observed values.

[0038] FIG. 8 is a flowchart showing an example of the processing flow of each unit when there is no observation error. The matching unit 12 determines whether the unit to be processed has a token (step S101).

[0039] Subsequently, when the matching unit 12 determines that the unit to be processed does not have a token (step S101: No), it waits for a spike signal transmission request (step S102).

[0040] When the processing target unit receives a transmission request for a Spike signal, the matching unit 12 determines whether the variable Reg is 1 (step S103). If the matching unit 12 determines that the variable Reg is 1 (step S103: Yes), it determines that the processing target unit is a Hot Unit and causes the processing target unit to transmit a Spike signal (step S104).

[0041] Next, the processing target unit waits for an Acknowledge signal (step S105). When it receives the Acknowledge signal, the matching unit 12 requests a reset signal (step S106).

[0042] Also, in step S103, if the matching unit 12 determines that the variable Reg is not 1 (step S103: No), it determines that the processing target unit is a Non-hot Unit. The processing target unit waits for a Spike signal (step S107). When the processing target unit receives the Spike signal, the matching unit 12 causes the processing target unit to transmit (relay) the Spike signal (step S108).

[0043] Next, the processing target unit waits for an Acknowledge signal (step S109). When it receives the Acknowledge signal, the error correction unit 13 corrects the error of the data quantum bit and causes the processing target unit to transmit (relay) the Acknowledge signal (step S110).

[0044] Also, in step S101, if the matching unit 12 determines that the processing target unit has a Token (step S101: Yes), it determines whether the variable Reg is 1 (step S111).

[0045] If the matching unit 12 determines that the variable Reg is not 1 (step S111: No), it requests a reset signal (step S112).

[0046] When the matching unit 12 determines that the variable Reg is 1 (step S111: Yes), it determines that the processing target unit is a sink unit, and requests the processing target unit to transmit a spike signal (step S113).

[0047] The processing target unit waits for a spike signal (step S114). When the processing target unit receives the spike signal, the error correction unit 13 corrects the error of the data quantum bit and causes the processing target unit to transmit an acknowledge signal (step S115).

[0048] FIG. 9 is a flowchart showing an example of the processing flow of each unit when there is an observation error. Assuming that there is an observation error, the observation value acquisition unit 11 acquires a plurality of observation values. Here, among the plurality of observation values acquired by the observation value acquisition unit 11, the process of designating the observation value b is performed. The matching unit 12 determines whether the processing target unit has a token (step S201).

[0049] Subsequently, when the matching unit 12 determines that the processing target unit does not have a token (step S201: No), it waits for a spike signal transmission request (step S202).

[0050] When the matching unit 12 receives a spike signal transmission request from the processing target unit, it sets b to the variable t (step S203) and determines whether the array Reg[t] is 1 (step S204). When the matching unit 12 determines that the array Reg[t] is 1 (step S204: Yes), it determines that the processing target unit is a hot unit and causes the processing target unit to transmit a spike signal (step S205).

[0051] Next, the processing target unit waits for an Acknowledge signal (step S206). When the Acknowledge signal is received, the matching unit 12 requests a reset signal (step S207).

[0052] Also, in step S204, when the matching unit 12 determines that the array Reg[t] is not 1 (step S204: No), it determines whether the processing target unit has received a Spike signal (step S208). When the matching unit 12 determines that the processing target unit has not received a Spike signal (step S208: No), it adds 1 to the variable t (step S209) and returns to the process of step S204.

[0053] On the other hand, when the matching unit 12 determines that the processing target unit has received a Spike signal (step S208: Yes), it determines that the processing target unit is a Non-hot Unit. The matching unit 12 transmits (relays) a Spike signal to the processing target unit (step S210).

[0054] Next, the processing target unit waits for an Acknowledge signal (step S211). When the Acknowledge signal is received, the error correction unit 13 corrects the error of the data quantum bit and transmits (relays) an Acknowledge signal to the processing target unit (step S212).

[0055] Also, in step S201, when the matching unit 12 determines that the processing target unit has a Token (step S201: Yes), it determines whether the array Reg[b] is 1 (step S213).

[0056] When the matching unit 12 determines that the array Reg[b] is not 1 (step S213: No), it requests a reset (step S214).

[0057] When the matching unit 12 determines that the array Reg[b] is 1 (step S213: Yes), it determines that the processing target unit is a sink unit, and requests the processing target unit to transmit a spike signal (step S215).

[0058] The matching unit 12 sets b to the variable t (step S216), and determines whether the processing target unit has received a spike signal (step S217). When the matching unit 12 determines that the processing target unit has received a spike signal (step S217: Yes), the error correction unit 13 corrects the error of the data quantum bit and causes the processing target unit to transmit an acknowledge signal (step S218).

[0059] On the other hand, when the matching unit 12 determines that the processing target unit has not received a spike signal (step S217: No), it determines whether the variable t is not b and the array Reg[b] is 1 (step S219).

[0060] When the matching unit 12 determines that the variable t is b or the array Reg[b] is not 1 (step S219: No), it adds 1 to the variable t (step S220) and returns to the process of step S217.

[0061] On the other hand, when the matching unit 12 determines that the variable t is not b and the array Reg[b] is 1 (step S219: Yes), the error correction unit 13 corrects the error of the data quantum bit and causes the processing target unit to transmit a reset signal (step S221).

[0062] According to this embodiment, a decoding device 10 composed of SFQ circuits is provided by means of collaborative design at the algorithm-hardware level. Constructing a large-scale random access memory using SFQ circuits is costly in terms of power consumption and circuit area. Even if a decoding device that executes a conventional graph matching algorithm that requires a large-scale memory is designed with SFQ circuits, it does not necessarily achieve low power consumption and small area that enables operation within a dilution refrigerator.

[0063] The graph matching process according to this embodiment is a graph matching algorithm with a distributed processing method that takes into account the locality of the processes necessary for decoding surface codes and the characteristics of SFQ circuits. The decoding device 10 does not require a large-scale memory, and has a structure in which simple processing units corresponding to each auxiliary qubit exchange several-bit signals with each other, enabling operation with low power consumption and excellent scalability.

[0064] FIG. 10 is a diagram for explaining a conventional decoding device. Conventional decoding devices generally operate at room temperature. Therefore, the huge wiring connecting the qubits and the decoding device becomes a bottleneck, limiting the scalability of superconducting quantum computers.

[0065] FIG. 11 is a diagram for explaining the decoding device according to this embodiment. The decoding device according to this embodiment is composed of SFQ circuits that operate at high speed and low power consumption, does not require a large-scale memory, and can operate with low power consumption. Therefore, the decoding device can be operated in an ultra-low temperature environment, eliminating the need for huge amounts of wiring and relaxing the limitations on the scalability of superconducting quantum computers.

[0066] Also, regarding the decoding of surface codes when an observation error occurs in an auxiliary qubit, a "batch processing method" in which decoding processing is performed after observing the auxiliary qubit a sufficient number of times has been common.

[0067] FIG. 12 is a diagram for explaining a decoding method of a batch processing system. In the batch processing system, data regarding errors of quantum bits accumulates while the observation process is repeated, making it difficult to perform decoding processing in a realistic time following the quantum computer.

[0068] On the other hand, the decoding apparatus according to the present embodiment realizes a decoding method of an "online processing system" that simultaneously performs observation and decoding of auxiliary quantum bits and can operate in a realistic environment.

[0069] FIG. 13 is a diagram for explaining a decoding method of an online processing system. In a superconducting quantum computer, the observation process of auxiliary quantum bits is repeated at intervals of about 1 microsecond, but the decoding apparatus 10 can execute the decoding process in 1 microsecond or less and has the high speed required for online processing.

[0070] In addition, in an actual quantum computer, errors may occur in the observation of auxiliary quantum bits. According to the decoding apparatus according to the present embodiment, by performing observation of auxiliary quantum bits a plurality of times and performing decoding processing based on all the obtained observation values, it is possible to cope with observation errors.

[0071] [References] [1] Holmes, Adam, et al. "NISQ+: Boosting quantum computing power by approximating quantum error correction." 2020 ACM / IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2020.

[0072] (Summary of the Embodiment) This specification describes at least the decoding apparatus and the decoding method described in each of the following sections. (Section 1) A decoding apparatus using a quantum error correction code, comprising a single-flux quantum circuit, The single-flux quantum circuit is an observation value acquisition unit that acquires observation values of the auxiliary quantum bits, a matching unit that executes matching processing based on the observation values, and an error correction unit that corrects errors in the data quantum bits based on the result of the matching processing, and includes a decoding device. (Item 2) The observation value acquisition unit acquires a plurality of observation values as the observation values of the auxiliary quantum bits, and the matching unit executes matching processing based on the plurality of observation values assuming that the plurality of observation values include observation errors. The decoding device according to Item 1. (Item 3) The quantum error correction code is a surface code including data quantum bits, a first auxiliary quantum bit for detecting bit flip errors, and a second auxiliary quantum bit for detecting phase flip errors. The decoding device according to Item 1 or Item 2. (Item 4) A decoding method using a quantum error correction code executed by a computer including a single-flux quantum circuit, including the steps of acquiring observation values of auxiliary quantum bits, executing matching processing based on the observation values, and correcting errors in the data quantum bits based on the result of the matching processing. The decoding method.

[0073] According to any of the above configurations, a technology is provided that enables a decoding device using a quantum error correction code to operate in an ultra-low temperature environment. According to Item 2, errors in data quantum bits can be corrected in response to the case where observation errors are included in the observation values. According to Item 3, bit flip errors and phase flip errors can be corrected by the surface code.

[0074] As described above, although the present embodiment has been explained, the present invention is not limited to such a specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

Explanation of Signs

[0075] 10 Decoder 11 Observation Value Acquisition Unit 12 Matching Unit 13 Error Correction Unit 20 Quantum Bit 30 Wiring 201 Data Quantum Bit 202 First Auxiliary Quantum Bit 203 Second Auxiliary Quantum Bit

Claims

1. A decoding device using a quantum error correction code, comprising a single-flux quantum circuit, wherein the single-flux quantum circuit comprises an observation value acquisition unit that repeatedly acquires observation values of an auxiliary qubit every predetermined first time interval, a matching unit that repeatedly executes matching processing based on the observation values every second time interval shorter than the first time interval, and an error correction unit that repeatedly corrects errors in data qubits based on the result of the matching processing every second time interval. Decoding device.

2. The observation value acquisition unit acquires a plurality of observation values as observation values of the auxiliary qubit, and the matching unit executes matching processing based on the plurality of observation values assuming that the plurality of observation values include observation errors. The decoding device according to Claim 1.

3. The quantum error correction code is a surface code including a data qubit, a first auxiliary qubit for detecting a bit flip error, and a second auxiliary qubit for detecting a phase flip error. The decoding device according to Claim 1 or 2.

4. A decoding method using a quantum error correction code, executed by a computer comprising a single-flux quantum circuit, comprising the steps of repeatedly acquiring observation values of an auxiliary qubit every predetermined first time interval, repeatedly executing matching processing based on the observation values every second time interval shorter than the first time interval, and repeatedly correcting errors in data qubits based on the result of the matching processing every second time interval. Decoding method.

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