Ceramic electronic component, circuit board, and method for manufacturing ceramic electronic component

Abstract

To reduce stress applied to an element body through an external electrode.SOLUTION: A ceramic electronic component according to an embodiment includes an element body having a dielectric and internal electrodes, a base layer connected to the internal electrode and formed on the element body such that an end portion thereof is located on the first surface side of the element body, and a pair of external electrodes formed on the base layer and having a plated layer having ends formed at different positions from the ends of the base layer in the normal direction of the first surface.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a ceramic electronic component, a circuit board, and a method for manufacturing a ceramic electronic component.

Background Art

[0002] A multilayer ceramic capacitor includes a ceramic body in which a plurality of internal electrodes are arranged, and external electrodes formed on the surface of the body and connected to the internal electrodes. Then, the external electrodes are joined to a mounting substrate by solder or the like, whereby the multilayer ceramic capacitor is mounted on the mounting substrate.

[0003] Patent Document 1 discloses a technique in which a terminal electrode has a laminated structure of a first electrode layer and a second electrode layer made of a conductive resin, and the tip of the covering portion of the second electrode layer extends 50 μm or more toward the mating terminal electrode from the tip of the covering portion of the first electrode layer.

[0004] Patent Document 2 discloses a technique in which a resin layer is provided between the surfaces of the ceramic body that wraps around the side surface of the ceramic body in order to make it difficult for cracks to occur in a portion corresponding to the wrapping tip of the external electrode of the ceramic body.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the technology disclosed in Patent Document 1, a two-layer third electrode layer of a Ni plating layer and a solder plating layer is formed on the second electrode layer, and the tip of the first electrode layer and the tip of the third electrode layer are located on the same plane. For this reason, the stress applied to the first electrode layer and the stress applied to the third electrode layer are likely to concentrate on the same point of the ceramic element, and there is a risk that cracks are likely to occur in the ceramic element.

[0007] In the technology disclosed in Patent Document 2, in order to have a resin layer between the tip region of the wraparound portion of the external electrode and the surface of the ceramic element, it is necessary to form a gap between the tip region of the wraparound portion of the external electrode and the surface of the ceramic element.

[0008] Also, as in Patent Document 3, a structure in which external electrodes are continuously formed on the first surface and the fifth surface, and the second surface and the fifth surface of the capacitor body is known. Further, as in Patent Document 4, a structure in which an external electrode is formed only on one end surface of the substrate is known.

[0009] Therefore, an object of the present invention is to provide a ceramic electronic component, a circuit board, and a method for manufacturing a ceramic electronic component capable of reducing the stress applied to the element via an external electrode.

Means for Solving the Problems

[0010] In order to solve the above problems, according to a ceramic electronic component according to an aspect of the present invention, an element having a dielectric and an internal electrode, a base layer formed on the element so as to be connected to the internal electrode and having an end portion located on the first surface side of the element, and a pair of external electrodes formed on the base layer and having a plating layer formed at a position different from the position of the end portion of the base layer in the normal direction of the first surface are provided.

[0011] Also, according to a ceramic electronic component according to an aspect of the present invention, on the first surface side of the element, the element includes a step or an inclined surface between the surface on which the end portion of the base layer is located and the surface on which the end portion of the plating layer is located.

[0012] Also, according to the ceramic electronic component according to one aspect of the present invention, the internal electrodes are drawn out to a pair of opposing side surfaces of the element body, and the external electrodes are continuously formed on the pair of side surfaces and on four peripheral surfaces adjacent to the pair of side surfaces, respectively.

[0013] Also, according to the ceramic electronic component according to one aspect of the present invention, the internal electrodes are drawn out to a pair of opposing side surfaces of the element body, and the external electrodes are continuously formed on the pair of side surfaces and on one surface adjacent to the pair of side surfaces, respectively.

[0014] Also, according to the ceramic electronic component according to one aspect of the present invention, the internal electrodes are drawn out to only one surface of the element body, and the pair of external electrodes are formed spaced apart from the one surface.

[0015] Also, according to the ceramic electronic component according to one aspect of the present invention, the thickness in the normal direction of the first surface of the element body at the position covered by the base layer is thicker than the thickness in the normal direction of the first surface of the element body at the position exposed from the base layer.

[0016] Also, according to the ceramic electronic component according to one aspect of the present invention, the height difference between the surface where the end of the base layer is located and the surface where the end of the plating layer is located is 0.5 μm or more and 2.0 μm or less.

[0017] Also, according to the ceramic electronic component according to one aspect of the present invention, the plating layer includes a first plating layer laminated on the base layer and a second plating layer laminated on the first plating layer, and the ends of the first plating layer and the ends of the second plating layer are different in the position in the normal direction of the first surface with respect to the end of the base layer.

[0018] Also, according to the ceramic electronic component according to one aspect of the present invention, the plating layer includes a first plating layer laminated on the base layer and a second plating layer laminated on the first plating layer, and when the tip of the first plating layer contacts the element body, the wrapping angle of the first plating layer from the end of the base layer to the element body is 180° or more and 270° or less.

[0019] Also, according to the ceramic electronic component according to one aspect of the present invention, the plating layer further includes a third plating layer laminated on the second plating layer, and the ends of the first plating layer, the second plating layer, and the third plating layer have different positions in the normal direction of the first surface with respect to the end of the base layer.

[0020] Also, according to the ceramic electronic component according to one aspect of the present invention, the plating layer is a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

[0021] Also, according to the ceramic electronic component according to one aspect of the present invention, the external electrode and the internal electrode are a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

[0022] Also, according to the ceramic electronic component according to one aspect of the present invention, the main component of the dielectric is selected from at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanium zirconate, and titanium oxide.

[0023] Also, according to the ceramic electronic component according to one aspect of the present invention, the base layer contains Ni as a main component.

[0024] Also, according to the ceramic electronic component according to one aspect of the present invention, the base layer includes a co-material containing the dielectric as a main component.

[0025] Also, according to the ceramic electronic component according to one aspect of the present invention, the outer dimension is selected from any one of 0201 to 4532.

[0026] Also, according to the ceramic electronic component according to one aspect of the present invention, the internal electrode includes a first internal electrode layer and a second internal electrode layer laminated on the first internal electrode layer via a dielectric layer including the dielectric, and the external electrode includes a first external electrode connected to the first internal electrode layer and a second external electrode provided separately from the first external electrode and connected to the second internal electrode layer.

[0027] Also, according to the ceramic electronic component according to one aspect of the present invention, the element body includes a cover layer including the dielectric and covering the first internal electrode layer and the second internal electrode layer in the stacking direction, a side margin portion including the dielectric and covering the first internal electrode layer and the second internal electrode layer in the width direction, and a step or inclined surface formed in the cover layer and the side margin portion.

[0028] Also, according to the circuit board according to one aspect of the present invention, it is a circuit board on which any of the above-described ceramic electronic components is mounted, and the ceramic electronic component is connected via a solder layer attached to the conductor.

[0029] Also, according to the method for manufacturing a ceramic electronic component according to one aspect of the present invention, a step of forming an element body provided with a dielectric and an internal electrode, and having the internal electrode drawn out to the side surface; a step of applying a base material for an external electrode to a part of the side surface of the element body and four surfaces perpendicular to the side surface; a step of firing the base material to form a base layer for the external electrode; a step of etching the element body through an exposed surface from the base layer to form a step or inclined surface in the element body; and a step of laminating a plating layer on the base layer so that an end portion contacts an etched surface of the element body in a state where the step or the inclined surface is covered.

Effects of the Invention

[0030] According to one aspect of the present invention, the stress applied to the element body via the external electrode can be reduced.

Brief Description of the Drawings

[0031]

Figure 1

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Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 6F

Figure 6G

Figure 6H

Figure 6I

Figure 6J

Figure 7

Figure 8

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Figure 10

Embodiments for Carrying Out the Invention

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the following embodiments do not limit the present invention, and not all combinations of the features described in the embodiments are essential to the configuration of the present invention. The configuration of the embodiments can be appropriately modified or changed according to the specifications of the device to which the present invention is applied and various conditions (usage conditions, usage environment, etc.). The technical scope of the present invention is determined by the scope of the claims and is not limited by the following individual embodiments. Also, the drawings used in the following description may differ from the actual structure, scale, shape, etc. in order to make each configuration easier to understand.

[0033] (First Embodiment) FIG. 1 is a perspective view showing the configuration of a multilayer ceramic capacitor according to the first embodiment, and FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the length direction. In FIGS. 1 and 2, the multilayer ceramic capacitor 1 includes a body 2 and external electrodes 6A and 6B. The body 2 includes a laminate 2A, a lower cover layer 5A, and an upper cover layer 5B. The laminate 2A includes internal electrode layers 3A, 3B, and a dielectric layer 4.

[0034] The lower cover layer 5A is provided on the lower layer of the laminate 2A, and the upper cover layer 5B is provided on the upper layer of the laminate 2A. The internal electrode layers 3A and 3B are alternately laminated via the dielectric layer 4. In FIGS. 1 and 2, an example in which a total of 11 layers of the internal electrode layers 3A and 3B are laminated is shown, but the number of laminated internal electrode layers 3A and 3B is not particularly limited. At this time, the shapes of the body 2 and the laminate 2A can be substantially rectangular parallelepiped shapes.

[0035] In the following description, the direction in which the side surfaces of the body 2 face each other may be referred to as the length direction DL, the direction in which the front and rear surfaces of the body 2 face each other may be referred to as the width direction DW, and the direction in which the upper and lower surfaces of the body 2 face each other may be referred to as the height direction DH. At this time, the lower surface of the body 2 can be arranged at a position facing the mounting surface of the circuit board on which the multilayer ceramic capacitor 1 is mounted. The body 2 may be chamfered along the ridge lines of the body 2. At this time, the body 2 has a curved surface R with chamfered corners.

[0036] As shown in FIGS. 1 and 2, the external electrodes 6A and 6B are formed on the body 2 so as to face each other in a state of being separated from each other in the length direction DL. Here, each of the external electrodes 6A and 6B is continuously formed from the lower surface side of the body 2 to the upper surface side of the body 2 via the side surface. Further, each of the external electrodes 6A and 6B may also be formed on the front and rear surfaces that face each other and are perpendicular to both the lower surface and the side surface of the body 2.

[0037] In the longitudinal direction DL, the internal electrode layers 3A and 3B are alternately arranged at different positions within the laminate 2A. At this time, the internal electrode layer 3A can be arranged on one side surface side of the longitudinal direction DL of the body 2 with respect to the internal electrode layer 3B, and the internal electrode layer 3B can be arranged on the other side surface side of the longitudinal direction DL of the body 2 with respect to the internal electrode layer 3A. Then, the end portion of the internal electrode layer 3A is drawn out to the end portion of the dielectric layer 4 on one side surface side of the longitudinal direction DL of the body 2 and connected to the external electrode 6A. The end portion of the internal electrode layer 3B is drawn out to the end portion of the dielectric layer 4 on the other side surface side of the longitudinal direction DL of the body 2 and connected to the external electrode 6B. On the other hand, in the width direction DW of the body 2, the end portions of the internal electrode layers 3A and 3B are covered with the dielectric layer 4. In the width direction DW, the positions of the end portions of the internal electrode layers 3A and 3B may be aligned. At this time, the body 2 can include a side margin portion 10 that covers the internal electrode layers 3A and 3B in the width direction DW.

[0038] Note that the thicknesses of the internal electrode layers 3A and 3B and the dielectric layer 4 in the height direction DH can each be in the range of 0.05 μm to 25 μm, for example, 0.3 μm. The materials of the internal electrode layers 3A and 3B can be selected from metals such as Cu (copper), Fe (iron), Zn (zinc), Al (aluminum), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), and may be alloys containing these metals.

[0039] The material of the dielectric layer 4 can be mainly composed of, for example, a ceramic material having a perovskite structure. Note that the main component only needs to be contained at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 can be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanium zirconate, and titanium oxide.

[0040] The materials of the lower cover layer 5A and the upper cover layer 5B can be mainly composed of, for example, a ceramic material. At this time, the main component of the ceramic material of the lower cover layer 5A and the upper cover layer 5B may be the same as the main component of the ceramic material of the dielectric layer 4. The thicknesses of the lower cover layer 5A and the upper cover layer 5B are each preferably 5 μm or more and 30 μm or less.

[0041] Each of the external electrodes 6A and 6B includes an underlayer 7 formed on the body 2 and a plating layer 9 laminated on the underlayer 7. The underlayer 7 is formed on a pair of side surfaces of the body 2 so as to face each other in a state of being separated from each other in the length direction DL, and is connected to the internal electrode layers 3A and 3B, respectively. At this time, the underlayer 7 is continuously formed on the side surface of the body 2 and the four peripheral surfaces adjacent to the side surface. That is, the underlayer 7 may be continuously formed from the lower surface side through the side surface to the upper surface side, and further continuously formed from the side surface side to the front surface side and the rear surface side.

[0042] The metal used as the conductive material of the underlayer 7 can be mainly composed of, for example, a metal or an alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The underlayer 7 may contain a co-material. The co-material can reduce the difference in the coefficient of thermal expansion between the body 2 and the underlayer 7 by being mixed in an island shape in the underlayer 7, and can relieve the stress applied to the underlayer 7. The co-material is, for example, a ceramic component that is the main component of the dielectric layer 4. The underlayer 7 may contain a glass component. The glass component can densify the underlayer 7 by being mixed in the underlayer 7. This glass component is, for example, an oxide such as Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron).

[0043] Here, the underlayer 7 is preferably composed of a metal sintered body. Thereby, while ensuring the adhesion between the body 2 and the underlayer 7, it becomes possible to increase the thickness of the underlayer 7, and while ensuring the strength of each of the external electrodes 6A and 6B, the electrical conductivity with the internal electrode layers 3A and 3B can be ensured.

[0044] The plating layer 9 is continuously formed for each of the external electrodes 6A and 6B so as to cover the base layer 7. The plating layer 9 is electrically connected to the internal electrode layers 3A and 3B through the base layer 7. Further, the plating layer 9 is electrically connected to the terminals of the mounting substrate through solder.

[0045] The material of the plating layer 9 is, for example, a metal or an alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The plating layer 9 may be a plating layer of a single metal component or a plurality of plating layers of different metal components. The plating layer 9 can have, for example, a three-layer structure including a Cu plating layer 9A formed on the base layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A can improve the adhesion of the plating layer 9 to the base layer 7. The Ni plating layer 9B can improve the heat resistance of each of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C can improve the wettability of the solder to the plating layer 9.

[0046] Here, as shown in FIGS. 2 and 3A, when the end portion EU of the base layer 7 and the end portion EM of the plating layer 9 are located on the first surface side of the element body 2, the positions of the end portion EU of the base layer 7 and the end portion EM of the plating layer 9 are different in the normal direction of the first surface of the element body 2. Here, the end portion of the base layer 7 and the end portion of the plating layer 9 refer to the end portions where the respective layers are interrupted on the surface of the element body. The first surface of the element body 2 may be the upper surface of the element body 2, the lower surface of the element body 2, the front surface of the element body 2, the rear surface of the element body 2, or a plurality of these surfaces. For example, when the first surface of the element body 2 is the upper surface or the lower surface of the element body 2, the positions of the end portion EU of the base layer 7 in the height direction DH and the end portion EM of the plating layer 9 in the height direction DH are different. When the first surface of the element body 2 is the front surface or the rear surface of the element body 2, the positions of the end portion EU of the base layer 7 in the width direction DW and the end portion EM of the plating layer 9 in the width direction DW are different. Also, the plating layer 9 may be composed of a plurality of layers. The end portion EA of the Cu plating layer 9A, the end portion EB of the Ni plating layer 9B, and the end portion EC of the Sn plating layer 9C, which are sequentially formed on the base layer 7 as shown in FIG. 3A, have different positions from the end portion EU of the base layer 7 in the normal direction of the first surface of the element body 2. The end portions of each plating layer 9 and the end portion EU of the base layer 7 are on the element body 2, and the end portions of each plating layer 9 are closer to the center of the element body 2 in the normal direction.

[0047] Here, by making the positions of the end portion EU of the base layer 7 and the end portion EM of the plating layer 9 different in the normal direction of the first surface of the element body 2, it is possible to prevent the stress load point from the base layer 7 and the stress load point from the plating layer 9 from being located on the same plane of the element body 2. The stress load point is the position where the stress applied to the element body 2 via the base layer 7 or the plating layer 9 becomes maximum, and is likely to be the starting point of crack generation. Therefore, the stress applied to the element body 2 via the external electrodes 6A and 6B can be dispersed, and the crack generated in the element body 2 can be suppressed.

[0048] As shown in FIG. 3A, in order to make the positions of the end EU of the base layer 7 and the end EM of the plating layer 9 different in the normal direction of the first surface of the element body 2, a step 8 can be provided on the first surface side of the element body 2. At this time, the step 8 is provided between the end EU of the base layer 7 and the end EM of the plating layer 9, and the first surface of the element body 2 can be separated into an upper surface M1 and a lower surface M2. Then, the end EU of the base layer 7 can be arranged on the upper surface M1, and the end EM of the plating layer 9 can be arranged on the lower surface M2. Instead of the step 8, an inclined surface may be provided on the first surface side of the element body 2. The height H of the step 8 is preferably 0.5 μm or more and 2.0 μm or less. Here, by setting the height H of the step 8 to 0.5 μm or more, the stress applied to the element body 2 via the external electrodes 6A and 6B can be effectively dispersed. By setting the height H of the step 8 to 2.0 μm or less, a reduction in the thickness of the element body 2 between the external electrodes 6A and 6B can be suppressed, and a decrease in the flexural strength of the multilayer ceramic capacitor 1 can be suppressed.

[0049] As shown in FIG. 1, the step 8 may be formed so as to go around the element body 2 along the ends of the base layer 7 of each of the external electrodes 6A and 6B. In this case, for each of the external electrodes 6A and 6B, the step 8 can be formed on the four surfaces of the upper surface, lower surface, front surface, and rear surface of the element body 2. That is, the step 8 can be formed in the lower cover layer 5A, the upper cover layer 5B, and the side margin portion 10. At this time, the thickness of the element body 2 at the position covered by the base layer 7 can be made thicker than the thickness of the element body 2 at the position exposed from the base layer 7. The thickness of the element body 2 referred to here is the length in the height direction DH of the element body in FIG. 1, and is measured at a position within 20 μm from the step 8. The width of the element body 2 at the position covered by the base layer 7 can be made wider than the width of the element body 2 at the position exposed from the base layer 7. The width of the element body 2 referred to here is the length in the width direction DW of the element body in FIG. 1, and is measured at a position within 20 μm from the step 8. At this time, the thickness of the lower cover layer 5A, the thickness of the upper cover layer 5B, and the width of the side margin portion 10 can be set so that the internal electrode layers 3A and 3B are not exposed from the element body 2 in which the step 8 is formed.

[0050] The size of the multilayer ceramic capacitor 1 is not particularly limited. For example, as design values, the length is 0.25 mm, the width is 0.125 mm, and the height is 0.125 mm (0201 size), or the length is 0.4 mm, the width is 0.2 mm, and the height is 0.2 mm (0402 size), or the length is 0.6 mm, the width is 0.3 mm, and the height is 0.3 mm (0603 size), or the length is 1.0 mm, the width is 0.5 mm, and the height is 0.5 mm (1005 size), or the length is 3.2 mm, the width is 1.6 mm, and the height is 1.6 mm (3216 size), or the length is 4.5 mm, the width is 3.2 mm, and the height is 2.5 mm (4532 size), or the length is 5.7 mm, the width is 5.0 mm, and the height is 2.3 mm (5750 size). Any one of these sizes can be selected. Preferably, it can be selected from any one within the range of 0201 size to 4532 size.

[0051] FIG. 3A is a cross-sectional view showing the stress loading points when there is a step in the external electrode of FIG. 2, and FIG. 3B is a cross-sectional view showing the stress loading points when there is no step in the external electrode of FIG. 2. In FIG. 3A, the region R1 of FIG. 2 is enlarged and shown.

[0052] In FIG. 3A, when there is a step 8 in the element body 2 at the position of the end of the base layer 7, the end EU of the base layer 7 is located on the upper surface M1, and the end EM of the plating layer 9 is located on the lower surface M2. Therefore, it is possible to prevent the stress loading point P1 from the base layer 7 and the stress loading point P2 from the plating layer 9 from being located on the same plane of the element body 2. As a result, the stress applied to the element body 2 via the base layer 7 and the stress applied to the element body 2 via the plating layer 9 can be dispersed, and cracks generated in the element body 2 can be suppressed.

[0053] On the one hand, in FIG. 3B, it is assumed that an underlayer 7' is formed on the substrate 2' without the step 8, and a plating layer 9' is laminated on the underlayer 7'. The plating layer 9' can have, for example, a three-layer structure of a Cu plating layer 9A', a Ni plating layer 9B', and a Sn plating layer 9C'. In this case, the end EU' of the underlayer 7' and the end EM' of the plating layer 9' are located on the same surface M3 of the substrate 2'. For this reason, the stress application point P3 from the underlayer 7' and the stress application point P3 from the plating layer 9' are located on the same surface M3 of the substrate 2'. As a result, the stress applied to the substrate 2' via the underlayer 7' and the stress applied to the substrate 2' via the plating layer 9' are concentrated, and cracks are likely to occur in the substrate 2'.

[0054] FIG. 4A is a cross-sectional view showing the wrapping angle of the tip of the plating layer when there is a step in the external electrode of FIG. 2, and FIG. 4B is a cross-sectional view showing the wrapping angle of the tip of the plating layer when there is no step in the external electrode of FIG. 2. Note that FIG. 4A shows the same region as FIG. 3A, and FIG. 4B shows the same region as FIG. 3B.

[0055] In FIG. 4A, when there is a step 8 in the substrate 2 at the position of the end of the underlayer 7, the step 8 is covered by the Cu plating layer 9A, and the Cu plating layer 9A wraps around the position of the step 8. Note that the end of the underlayer 7 may be in an acute angle shape. For this reason, the wrapping angle θ1 of the Cu plating layer 9A from the end EU of the underlayer 2 to the substrate 2 when the end of the Cu plating layer 9A contacts the substrate 2 is 180° or more and 270° or less.

[0056] On the other hand, in FIG. 4B, when there is no step 8 in the substrate 2' at the position of the end of the underlayer 7', the tip of the underlayer 7 and the tip of the Cu plating layer 9A are located on the same plane. For this reason, the wrapping angle θ2 of the Cu plating layer 9A' from the end EU' of the underlayer 2' to the substrate 2' when the end of the Cu plating layer 9A' contacts the substrate 2' is 180° or less.

[0057] FIG. 5 is a flowchart showing an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment, and FIGS. 6A to 6J are cross-sectional views showing an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. In FIGS. 6C to 6J, the case where the internal electrode layers 3A and 3B are alternately laminated by three layers via the dielectric layer 4 is taken as an example.

[0058] In S1 of FIG. 5, a dispersant and an organic binder and an organic solvent as a molding aid are added to the dielectric material powder, and pulverized and mixed to generate a paste-like slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may contain an additive. The additive is, for example, an oxide or glass of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si. The organic binder is, for example, a polyvinyl butyral resin or a polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0059] Next, as shown in S2 of FIG. 5 and FIG. 6A, a slurry containing ceramic powder is applied in a sheet shape onto a carrier film to produce a green sheet 24 that is dried. The carrier film is, for example, a PET (polyethylene terephthalate) film. For applying the slurry, a doctor blade method, a die coater method, a gravure coater method, or the like can be used.

[0060] Next, as shown in S3 of FIG. 5 and FIG. 6B, a conductive paste for internal electrodes is applied to the green sheet 24 of the layer that forms the internal electrode layers 3A and 3B among the plurality of green sheets so as to form a predetermined pattern, thereby forming the internal electrode pattern 23. At this time, a plurality of internal electrode patterns 23 separated in the longitudinal direction of the green sheet 24 can be formed on one green sheet 24. The conductive paste for internal electrodes contains a metal powder used as the material of the internal electrode layers 3A and 3B. For example, when the metal used as the material of the internal electrode layers 3A and 3B is Ni, the conductive paste for internal electrodes contains Ni powder. Further, the conductive paste for internal electrodes contains a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for internal electrodes may contain, as a co-material, a ceramic material that is the main component of the dielectric layer 4. For the application of the conductive paste for internal electrodes, a screen printing method, an inkjet printing method, a gravure printing method, or the like can be used.

[0061] Next, as shown in S4 of FIG. 5 and FIG. 6C, a laminated block is produced by stacking a plurality of green sheets 24 with the internal electrode pattern 23 formed thereon and outer-layer green sheets 25A and 25B on which the internal electrode pattern 23 is not formed, in a predetermined order. The thicknesses of the outer-layer green sheets 25A and 25B are larger than the thickness of the green sheet 24 on which the internal electrode pattern 23 is formed. At this time, the internal electrode patterns 23A and 23B of the green sheets 24 adjacent in the stacking direction are stacked so as to be alternately shifted in the longitudinal direction of the green sheet 24. Also, a portion where only the internal electrode pattern 23A is stacked in the stacking direction, a portion where the internal electrode patterns 23A and 23B are alternately stacked in the stacking direction, and a portion where only the internal electrode pattern 23B is stacked in the stacking direction are formed.

[0062] Next, as shown in S5 of FIG. 5 and FIG. 6D, the laminated block obtained in the molding step of S4 of FIG. 5 is pressed to crimp the green sheets 24, 25A, and 25B. As a method for pressing the laminated block, for example, a method of sandwiching the laminated block with a resin film and performing hydrostatic pressing can be used.

[0063] Next, as shown in S6 of FIG. 5 and FIG. 6E, the pressed laminated block is cut and separated into individual rectangular parallelepiped-shaped elements. The cutting of the laminated block is performed at the portion where only the internal electrode pattern 23A is stacked in the stacking direction and the portion where only the internal electrode pattern 23B is stacked in the stacking direction. For cutting the laminated block, methods such as blade dicing can be used, for example.

[0064] At this time, as shown in FIG. 6F, internal electrode layers 3A and 3B alternately laminated via the dielectric layer 4 are formed on the separated element 2´, and cover layers 5A and 5B are formed on the lowermost layer and the uppermost layer. The internal electrode layer 3A is drawn out from the surface of the dielectric layer 4 on one side surface of the element 2´, and the internal electrode layer 3B is drawn out from the surface of the dielectric layer 4 on the other side surface of the element 2´. Note that in FIG. 6F, one separated element in FIG. 6E is shown enlarged in the length direction.

[0065] Next, as shown in S7 of FIG. 5 and FIG. 6G, chamfering of the element 2´ is performed to form an element 2 provided with a curved surface R at the corner portion of the element 2´. For chamfering the element 2´, barrel polishing can be used, for example.

[0066] Next, as shown in S8 of FIG. 5, the binder contained in the element 2 chamfered in S7 of FIG. 5 is removed. For removing the binder, the element 2 is heated in an N2 atmosphere at about 350°C, for example.

[0067] Next, as shown in S9 of FIG. 5, conductive paste for the underlayer is applied to both side surfaces of the green body 2 from which the binder has been removed in S8 of FIG. 5 and to four surfaces (the upper surface, the lower surface, the front surface, and the rear surface) of the peripheral surface of each side surface, and then dried. For example, the dipping method can be used to apply the conductive paste for the underlayer. The conductive paste for the underlayer contains metal powder or filler used as the conductive material of the underlayer 7. For example, when the metal used as the conductive material of the underlayer 7 is Ni, the conductive paste for the underlayer contains Ni powder or filler. Further, the conductive paste for the underlayer contains, as a co-material, for example, a ceramic component which is the main component of the dielectric layer 4. For example, particles of oxide ceramic mainly composed of barium titanate (for example, D50 particle size: 0.8 μm to 4 μm) are mixed into the conductive paste for the underlayer as a co-material. The conductive paste for the underlayer also contains a binder and a solvent.

[0068] Next, as shown in S10 of FIG. 5 and FIG. 6H, the green body 2 coated with the conductive paste for the underlayer in S9 of FIG. 5 is fired to integrate the internal electrode layers 3A and 3B with the dielectric layer 4 and to form the underlayer 7 integrated with the green body 2. The firing of the green body 2 and the conductive paste for the underlayer is performed, for example, in a firing furnace at 1000 to 1400 °C for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A and 3B, in order to prevent oxidation of the internal electrode layers 3A and 3B, firing can be performed in a reducing atmosphere in the firing furnace. In addition, for the formation of the underlayer 7, a re-oxidation treatment may be performed at a temperature of 600 °C to 1000 °C in an N2 gas atmosphere.

[0069] Next, as shown in S11 of FIG. 5 and FIG. 6I, the green body 2 is etched through the exposed surface from the underlayer 7 to form a step 8 in the green body 2 along the edge of the underlayer 7. At this time, an etching surface EM is formed on the lower surface, the upper surface, the front surface, and the rear surface of the green body 2, and the step 8 encircles the green body 2 for each of the external electrodes 6A and 6B.

[0070] The etching of the substrate 2 may be wet etching or dry etching. In the etching of the substrate 2, a hydrofluoric acid-based etching solution or etching gas can be used. By adjusting the etching time, etching temperature, etching rate, the input amount of the substrate 2 on which the underlying layer 7 is formed, or the stirring rate of the etching solution, the etching amount of the substrate 2 can be adjusted.

[0071] Next, as shown in S12 of FIG. 5 and FIG. 6J, a Cu plating layer 9A, a Ni plating layer 9B, and a Sn plating layer 9C are sequentially formed on the underlying layer 7. At this time, the ends of the Cu plating layer 9A, the Ni plating layer 9B, and the Sn plating layer 9C are in contact with the etching surface EM of the substrate 2. Here, the substrate 2 on which the underlying layer 7 is formed is accommodated in a barrel together with the plating solution, and the plating layer 9 can be formed by rotating the barrel and applying electricity.

[0072] Here, in the etching process for forming the step 8 on the substrate 2, the metal oxide film and the co-material on the surface of the underlying layer 7 can be removed. For this reason, it is possible to form the step 8 on the substrate 2 while suppressing an increase in the number of steps, and it is possible to improve the adhesion of the Cu plating layer 9A to the underlying layer 7.

[0073] (Second Embodiment) FIG. 7 is a cross-sectional view showing the configuration of a multilayer ceramic capacitor according to the second embodiment. In FIG. 7, the multilayer ceramic capacitor 1X includes a substrate 2X and external electrodes 6AX, 6BX. The substrate 2X includes a laminate 2A, a lower cover layer 5AX, and an upper cover layer 5BX. The laminate 2A includes internal electrode layers 3A, 3B, and a dielectric layer 4. The lower cover layer 5AX is provided on the lower layer of the laminate 2A, and the upper cover layer 5BX is provided on the upper layer of the laminate 2A. The laminate 2A has the same configuration as that in FIG. 2.

[0074] The external electrodes 6AX and 6BX are formed on the element body 2X so as to face each other in a state of being separated from each other in the length direction DL. Here, each of the external electrodes 6AX and 6BX is continuously formed from the lower surface side to the side surface of the element body 2X. At this time, each of the external electrodes 6AX and 6BX is not formed on the upper surface side of the element body 2X. Also, the upper ends of each of the external electrodes 6AX and 6BX are formed at positions lower than the upper surface of the element body 2X on the side surface side of the element body 2X.

[0075] Also, each of the external electrodes 6AX and 6BX may or may not be formed on the front and rear surfaces facing each other and perpendicular to both the lower surface and the side surface of the element body 2X. When the external electrodes are also formed on the front and rear surfaces of the element body 2X, the upper ends of each of the external electrodes 6AX and 6BX are formed at positions lower than the upper surface of the element body 2X on the front surface side and the rear surface side of the element body 2X.

[0076] Each of the external electrodes 6AX and 6BX includes an underlayer 7X formed on the element body 2X and a plating layer 9X laminated on the underlayer 7X. The underlayer 7X is formed on a pair of side surfaces of the element body 2X so as to face each other in a state of being separated from each other in the length direction DL, and is connected to the internal electrode layers 3A and 3B, respectively. At this time, the underlayer 7X is continuously formed on the side surface of the element body 2X and three or one surface adjacent to the side surface. At this time, the underlayer 7X is not formed on the upper surface side of the element body 2X. That is, the underlayer 7X is continuously formed from the lower surface side to the side surface, or may be further continuously formed from the side surface side to the front surface side and the rear surface side. Also, as shown in FIG. 7, the upper end of the underlayer 7X is formed at a position lower than the upper surface of the element body 2X on the side surface side of the element body 2X. However, the upper end of the underlayer 7X is formed at a position higher than the positions of the internal electrode layers 3A and 3B on the side surface side of the element body 2X.

[0077] The plating layer 9X is continuously formed for each of the external electrodes 6AX and 6BX so as to cover the base layer 7X. The plating layer 9X is electrically connected to the internal electrode layers 3A and 3B through the base layer 7X. The plating layer 9X can have, for example, a three-layer structure including a Cu plating layer 9AX formed on the base layer 7X, a Ni plating layer 9BX formed on the Cu plating layer 9AX, and a Sn plating layer 9CX formed on the Ni plating layer 9BX.

[0078] In the element body 2X and the external electrodes 6AX and 6BX, the structure on the lower cover layer 5AX side is the same as the structure on the lower cover layer 5A side in FIG. 2, and the structure on the upper cover layer 5BX side is different from the structure on the upper cover layer 5B side in FIG. 2. Hereinafter, the differences between the element body 2X and the external electrodes 6AX and 6BX and the structure on the upper cover layer 5B side in FIG. 2 will be described.

[0079] On the upper cover layer 5BX side of the external electrodes 6AX and 6BX, the positions of the end EU of the base layer 7X and the end EM of the plating layer 9X are different in the normal direction (length direction DL) of the side surface of the element body 2. Also, when the external electrodes 6AX and 6BX are formed on the front surface and the rear surface as well, the positions of the end EU of the base layer 7X and the end EM of the plating layer 9X may be different in the normal direction (width direction DW in FIG. 1) of the front surface and the rear surface of the element body 2X. Further, the end EA of the Cu plating layer 9AX, the end EB of the Ni plating layer 9BX, and the end EC of the Sn plating layer 9CX formed in sequence on the base layer 7X are different in the position in the normal direction of the side surface of the element body 2X from the end EU of the base layer 7X. Here, the term "end" refers to the termination end where each layer ends.

[0080] In order to make the positions of the end EU of the base layer 7X and the end EM of the plating layer 9X different in the normal direction of the side surface of the element body 2X, a step 8X can be provided on the side surface side of the element body 2X. At this time, the step 8X is provided between the end EU of the base layer 7X and the end EM of the plating layer 9X, and the side surface of the element body 2X can be separated into an upper surface M3 and a lower surface M4. Then, the end EU of the base layer 7X can be arranged on the upper surface M3, and the end EM of the plating layer 9X can be arranged on the lower surface M4. Instead of the step 8X, an inclined surface may be provided on the side surface side of the element body 2X.

[0081] The step 8X may be formed on the upper cover layer 5BX along the end portions of the underlying layers 7X of the respective external electrodes 6AX, 6BX. In this case, for each of the external electrodes 6AX, 6BX, when the external electrodes 6AX, 6BX are also formed on a pair of side surfaces of the upper cover layer 5BX, or further on the front surface and the rear surface, the step 8X can be formed on the four surfaces of the front surface and the rear surface as well. In both cases, the end portions of the plating layer 9X and the end portions of the underlying layer 7X are on the element body, and the end portions of the plating layer 9X are closer to the center side of the element body in the normal direction.

[0082] Here, by providing the steps 8, 8X on the element body 2X, it becomes possible to reduce the stress from the external electrodes 6AX, 6BX applied to the lower surface and the side surfaces of the element body 2X, and the height of the multilayer ceramic capacitor 1X can be reduced. Further, since the terminal ends of the external electrodes 6AX, 6BX are present on the lead-out surfaces of the internal electrodes 3A, 3B, the stress at a position close to the capacitance generation portion where the internal electrodes 3A, 3B face each other can be reduced, and the occurrence of cracks can be prevented. The end portion EM of the plating layer 9X and the end portion EU of the underlying layer 7X are on the element body 2X, and the end portions of each plating layer 9X are closer to the center side of the element body in the normal direction.

[0083] (Third Embodiment) FIG. 8 is a perspective view showing the configuration of the multilayer ceramic capacitor according to the third embodiment cut along the position in the longitudinal direction. In FIG. 8, the multilayer ceramic capacitor 1Y includes an element body 2Y and external electrodes 6AY, 6BY. The element body 2Y includes a laminate 2AY, a lower cover layer 5AY, and an upper cover layer 5BY. The laminate 2AY includes internal electrode layers 3AY, 3BY and a dielectric layer 4Y. The lower cover layer 5AY is provided on the lower surface side of the laminate 2A, and the upper cover layer 5BY is provided on the upper surface side of the laminate 2A.

[0084] The internal electrode layers 3AY and 3BY are alternately laminated in the length direction DL of the element body 2 via the dielectric layer 4Y. And each of the internal electrode layers 3AY and 3BY is located within the element body 2Y in a state of standing upright in the height direction DH of the element body 2. Lead electrodes LA and LB are connected to the lower end sides of the internal electrode layers 3AY and 3BY respectively. The lead electrodes LA and LB are arranged at different positions in the width direction DW of the element body 2 for each of the internal electrode layers 3AY and 3BY and are drawn out to the lower surface side of the element body 2. At this time, the respective lead electrodes LA of the internal electrode layer 3AY can have the same position in the width direction DW of the element body 2, and the respective lead electrodes LB of the internal electrode layer 3BY can have the same position in the width direction DW of the element body 2. The materials and thicknesses of the internal electrode layers 3AY and 3BY and the dielectric layer 4Y are the same as those of the internal electrode layers 3A and 3B and the dielectric layer 4 in FIG. 2. The materials of the lower cover layer 5AY and the upper cover layer 5BY are the same as those of the lower cover layer 5A and the upper cover layer 5B in FIG. 2.

[0085] The external electrodes 6AY and 6BY are formed in parallel on the lower surface side of the element body 2X in a state of being separated from each other in the width direction DW. Each of the external electrodes 6AY and 6BY includes an underlayer 7Y formed on the lower surface side of the element body 2Y and a plating layer 9Y laminated on the underlayer 7Y. The underlayer 7Y is formed in parallel on the lower surface side of the element body 2Y in a state of being separated from each other in the width direction DW and is connected to the lead electrodes LA and LB respectively.

[0086] The plating layer 9Y is continuously formed for each of the external electrodes 6AY and 6BY so as to cover the underlayer 7Y. The plating layer 9Y is electrically connected to the internal electrode layers 3AY and 3BY via the underlayer 7Y. The plating layer 9Y can have a three-layer structure, for example, a Cu plating layer 9AY formed on the underlayer 7Y, a Ni plating layer 9BY formed on the Cu plating layer 9AY, and a Sn plating layer 9CY formed on the Ni plating layer 9BY.

[0087] The positions of the end EU of the underlying layer 7Y and the end EM of the plating layer 9Y are different in the normal direction (height direction DH) of the lower surface of the base body 2Y. Further, the positions of the end EA of the Cu plating layer 9AY, the end EB of the Ni plating layer 9BY, and the end EC of the Sn plating layer 9CY, which are sequentially formed on the underlying layer 7Y, are different from the position of the end EU of the underlying layer 7Y in the normal direction of the side surface of the base body 2Y. Here, the end mentioned refers to the end portion where each layer ends. Both the end of the plating layer 9Y and the end of the underlying layer 7Y are on the base body 2, and the end of the plating layer 9Y is closer to the center of the base body 2 in the normal direction.

[0088] In order to make the positions of the end EU of the underlying layer 7Y and the end EM of the plating layer 9Y different in the normal direction of the lower surface of the base body 2Y, a step 8Y can be provided on the lower surface side of the base body 2Y. At this time, the step 8Y is provided between the end EU of the underlying layer 7Y and the end EM of the plating layer 9Y. Instead of the step 8Y, an inclined surface may be provided on the lower surface side of the base body 2Y.

[0089] Here, by providing the step 8Y on the base body 2Y, it is possible to reduce the stress from the external electrodes 6AY and 6BY applied only to the lower surface of the base body 2Y, and the height of the multilayer ceramic capacitor 1Y can be reduced. Further, since the end portions of the external electrodes 6AY and 6BY are on the lead-out surfaces of the lead electrodes LA and LB, the stress at a position close to the capacitance generation portion where the internal electrodes 3AY and 3BY face each other can be reduced, and the occurrence of cracks can be prevented.

[0090] (Fourth Embodiment) FIG. 9 is a cross-sectional view showing a configuration example of a circuit board on which a multilayer ceramic capacitor according to the fourth embodiment is mounted. In FIG. 9, land electrodes 12A and 12B are formed on the circuit board 11. The circuit board 11 may be a printed circuit board or a semiconductor substrate such as Si. The multilayer ceramic capacitor 1 is connected to the land electrodes 12A and 12B via solder layers 13A and 13B attached to the Sn plating layers 9C of the external electrodes 6A and 6B.

[0091] Here, by providing a step 8 in the element body 2 at the position of the end of the base layer 7, the stress loading point from the base layer 7 and the stress loading point from the plating layer 9 can be made not to be located on the same plane of the element body 2. Therefore, even when stress is applied to the external electrodes 6A and 6B due to bending, expansion, or contraction of the circuit board 11, the stress applied to the element body 2 via the external electrodes 6A and 6B can be dispersed, and the occurrence of cracks in the element body 2 can be suppressed.

[0092] (Fifth Embodiment) FIG. 10 is a perspective view showing a configuration example of a ceramic electronic component according to the fifth embodiment. In FIG. 10, a chip inductor is taken as an example of the ceramic electronic component. In FIG. 10, the chip inductor 21 includes an element body 22 and external electrodes 26A and 26B. The element body 22 includes a coil pattern 23, internal electrode layers 23A and 23B, and a magnetic material 24. The magnetic material 24 is also used as a dielectric that insulates the internal electrode layers 23A and 23B. The shape of the element body 22 can be a substantially rectangular parallelepiped shape. The external electrodes 26A and 26B are located on opposite side surfaces of the element body 22 in a separated state from each other. Each of the external electrodes 26A and 26B is continuous from each side surface of the element body 22 to the front and rear surfaces and the upper and lower surfaces.

[0093] The coil pattern 23 and the internal electrode layers 23A and 23B are covered with the magnetic material 24. However, the end of the internal electrode layer 23A is exposed from the magnetic material 24 on one side surface side of the element body 22 and is connected to the external electrode 26A. The end of the internal electrode layer 23B is exposed from the magnetic material 24 on the other side surface side of the element body 22 and is connected to the external electrode 26B.

[0094] The materials of the coil pattern 23 and the internal electrode layers 23A and 23B can be selected from metals such as Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, and may be alloys containing these metals. The magnetic material 24 is, for example, ferrite.

[0095] Each of the external electrodes 26A and 26B includes an underlayer 27 formed on the element body 22 and a plating layer 29 laminated on the underlayer 27. The underlayer 27 is formed on the element body 22 so as to face each other in a state of being separated from each other in the length direction DL. At this time, the underlayer 27 is continuously formed from the lower surface side of the element body 22 to the upper surface side via the side surface. Note that the underlayer 27 may be continuously formed from the lower surface side of the element body 22 to the front surface side and the rear surface side. The plating layer 29 is continuously formed for each of the external electrodes 26A and 26B so as to cover the underlayer 27. The plating layer 29 is electrically connected to the internal electrode layers 23A and 23B via the underlayer 27.

[0096] A step 28 is provided in the element body 22. The step 28 can go around the element body 22 along the ends of the underlayer 27 of each of the external electrodes 26A and 26B. Then, the end of the underlayer 27 and the end of the plating layer 29 are separated by the step 28.

[0097] Thereby, the stress loading points from the underlayer 27 and the stress loading points from the plating layer 29 can be prevented from being located on the same plane of the element body 22. For this reason, the stress applied to the element body 22 via the external electrodes 26A and 26B can be dispersed, and cracks generated in the element body 22 can be suppressed.

[0098] In the above-described embodiment, the multilayer ceramic capacitor and the chip inductor are taken as examples of the ceramic electronic component, but a chip resistor or a sensor chip may be used. Further, in the above-described embodiment, the ceramic electronic component having two-terminal external electrodes is taken as an example, but a ceramic electronic component having three or more terminal external electrodes may be used.

Description of Reference Numerals

[0099] 1 Multilayer ceramic capacitor 2 Element body 2A Stacked body 3A, 3B Internal electrode layer 4 Dielectric layer 5A, 5B Cover layer 6A, 6B External electrode 7 Underlayer 8-step difference 9, 9A to 9C plating layers

Claims

1. A base body having a dielectric and internal electrodes, a base layer formed on the base body and connected to the internal electrodes, with an end portion positioned on the first surface side of the base body, and a pair of external electrodes formed on the base layer and having plating layers with end portions formed at positions different from the position of the end portion of the base layer in the normal direction of the first surface, A ceramic electronic component comprising: On the first surface side of the base body, the base body has a step between the surface where the end portion of the base layer is located and the surface where the end portion of the plating layer is located, and the step is a step in the normal direction, A ceramic electronic component characterized in that the thickness of the first surface of the base body in the normal direction at the position covered by the base layer is thicker than the thickness of the first surface of the base body in the normal direction at the position exposed from the base layer.

2. The ceramic electronic component according to claim 1, wherein the internal electrodes are drawn out to a pair of opposing side surfaces of the base body, and the external electrodes are continuously formed on the pair of side surfaces and four peripheral surfaces adjacent to the pair of side surfaces, respectively.

3. The ceramic electronic component according to claim 1, wherein the internal electrodes are drawn out to a pair of opposing side surfaces of the base body, and the external electrodes are continuously formed on the pair of side surfaces and one surface adjacent to the pair of side surfaces, respectively.

4. The ceramic electronic component according to claim 1, wherein the internal electrodes are drawn out to only one surface of the base body, and the pair of external electrodes are formed spaced apart from the one surface.

5. The ceramic electronic component according to any one of claims 1 to 3, wherein the height difference between the surface where the end portion of the base layer is located and the surface where the end portion of the plating layer is located is 0.5 μm or more and 2.0 μm or less.

6. The plating layer includes a first plating layer laminated on the base layer and a second plating layer laminated on the first plating layer, The ceramic electronic component according to any one of claims 1 to 4, wherein the end portions of the first plating layer and the end portions of the second plating layer have different positions in the normal direction of the first surface with respect to the end portion of the base layer.

7. The ceramic electronic component according to claim 6, wherein the wrapping angle of the first plating layer from the end portion of the base layer to the base body when the tip of the first plating layer contacts the base body is 180° or more and 270° or less.

8. The plating layer further includes a third plating layer laminated on the second plating layer. The ceramic electronic component according to claim 6, wherein the end portions of the first plating layer, the end portions of the second plating layer, and the end portions of the third plating layer have different positions in the normal direction of the first surface with respect to the end portion of the base layer.

9. The ceramic electronic component according to any one of claims 1 to 6, wherein the plating layer is a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

10. The ceramic electronic component according to any one of claims 1 to 7, wherein the external electrode and the internal electrode are a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

11. The ceramic electronic component according to any one of claims 1 to 8, wherein the main component of the dielectric is selected from at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanium zirconate, and titanium oxide.

12. The ceramic electronic component according to any one of claims 1 to 9, wherein the base layer has Ni as a main component.

13. The ceramic electronic component according to claim 10, wherein the base layer includes a co-material containing the dielectric as a main component.

14. The ceramic electronic component according to any one of claims 1 to 12, wherein the outer dimension is selected from any one of 0201 to 4532.

15. The internal electrode is a first internal electrode layer, and a second internal electrode layer laminated on the first internal electrode layer via a dielectric layer containing the dielectric, The external electrode is a first external electrode connected to the first internal electrode layer, and a second external electrode provided separately from the first external electrode and connected to the second internal electrode layer. The ceramic electronic component according to any one of claims 1 to 14.

16. The element body is a cover layer containing the dielectric and covering the first internal electrode layer and the second internal electrode layer in the stacking direction. A side margin portion that includes the dielectric and covers the first internal electrode layer and the second internal electrode layer in the width direction; The ceramic electronic component according to claim 15, further comprising a step formed in the cover layer and the side margin portion.

17. A circuit board on which the ceramic electronic component according to any one of claims 1 to 15 is mounted, The circuit board, wherein the ceramic electronic component is connected via a solder layer attached to the conductor.

18. A step of forming a body provided with a dielectric and an internal electrode, the internal electrode being drawn out to a side surface; A step of applying a base material for an external electrode to a side surface of the body and a part of four surfaces perpendicular to the side surface; A step of firing the base material to form a base layer of the external electrode; A step of etching the body through an exposed surface from the base layer to form a step in the body; A step of laminating a plating layer on the base layer so that an end portion contacts an etched surface of the body in a state where the step is covered; and The etching is performed so that the base layer does not remain on the step, and the step is a step in the normal direction of a surface on which the base material is applied other than the side surface. A method for manufacturing a ceramic electronic component.

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