Multilayer Hard Mask for Defect Reduction in EUV Patterning

Abstract

Various embodiments herein relate to methods, apparatus, and systems that utilize a multilayer hard mask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multilayer hard mask includes (1) an upper layer including a metal-containing material, such as a metal oxide, metal nitride, or metal oxynitride, and (2) a lower layer including an inorganic dielectric silicon-containing material. Together, these layers of the multilayer hard mask provide excellent etch selectivity and reduce the formation of defects such as microbridges and open circuits. Certain embodiments relate to the deposition of the multilayer hard mask. Other embodiments relate to the etching of the multilayer hard mask. Some embodiments involve both the deposition and etching of the multilayer hard mask.

Description

Technical Field

[0001] Incorporation by Reference As part of this application, a PCT application form is filed simultaneously with this specification. Each application specified in this simultaneously filed PCT application form and for which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes.

Background Art

[0002] As the dimensions of semiconductor devices continue to shrink, new processing technologies are required. For example, lithography technology has evolved over time, resulting in smaller and higher-quality features. Extreme ultraviolet (EUV) lithography is a new field that uses the extreme ultraviolet wavelength range to pattern a substrate.

[0003] The background description provided herein is for the purpose of generally presenting the content of the present disclosure. Research by the inventors named at the present time, within the scope described in this background art section, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing the application, are not admitted as prior art against the present disclosure, whether explicitly or implicitly.

Summary of the Invention

[0004] Various embodiments herein relate to methods, apparatuses, and systems for processing a semiconductor substrate. In particular, multilayer hard masks are described, especially for use with extreme ultraviolet photoresists for patterning applications.

[0005] In one aspect of the disclosed embodiments, a method of processing a substrate is provided, the method comprising: (a) receiving a substrate, the substrate comprising (i) a base material, (ii) an organic planarization layer disposed on the base material, (iii) a multilayer hard mask disposed on the organic planarization layer, the multilayer hard mask comprising (1) a lower layer comprising an inorganic dielectric silicon-containing material, and (2) an upper layer comprising a metal oxide, a metal nitride, or a metal oxynitride, and (iv) a layer of extreme ultraviolet (EUV) photoresist disposed on the multilayer hard mask, the layer of EUV photoresist being patterned to include concave features, a portion of the upper layer of the multilayer hard mask being exposed within the concave features; (b) etching the exposed portion of the upper layer of the multilayer hard mask, thereby expanding the concave features into the upper layer of the multilayer hard mask and exposing a portion of the lower layer of the multilayer hard mask; (c) etching the exposed portion of the lower layer of the multilayer hard mask, thereby expanding the concave features into the lower layer of the multilayer hard mask and exposing a portion of the organic planarization layer; (d) etching the exposed portion of the organic planarization layer, thereby expanding the concave features into the organic planarization layer and exposing a portion of the base material; and (e) etching the exposed portion of the base material, thereby expanding the concave features into the base material.

[0006] In some embodiments, the lower layer of the multilayer hard mask may comprise a material selected from the group consisting of amorphous silicon, silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, silicon oxynitride, and combinations thereof. In these or other embodiments, the lower layer of the multilayer hard mask may have a thickness of about 10 nm or less. In these or other embodiments, the metal oxide, metal nitride, or metal oxynitride of the upper layer of the multilayer hard mask may comprise a metal selected from the group consisting of titanium, tantalum, hafnium, tin, ruthenium, and combinations thereof. In these or other embodiments, the upper layer of the multilayer hard mask may have a thickness of about 10 nm or less.

[0007] In some cases, the method may further include additional steps. For example, the method may further include exposing the substrate to a first plasma to remove excess EUV photoresist within the concave features prior to (b). In these or other embodiments, etching the exposed portions of the upper layer of the multilayer hard mask may include exposing the substrate to a second reactant, where the second reactant includes a chlorine-containing etchant and / or a bromine-containing reactant. In these or other embodiments, etching the exposed portions of the upper layer of the multilayer hard mask may include exposing the substrate to a second plasma. In these or other embodiments, etching the exposed portions of the lower layer of the multilayer hard mask may include exposing the substrate to a third reactant, where the third reactant includes a fluorine-containing reactant and / or a chlorine-containing reactant. In these or other embodiments, etching the exposed portions of the lower layer of the multilayer hard mask may include exposing the substrate to a third plasma. In these or other embodiments, both the upper and lower layers of the multilayer hard mask may each have a thickness of about 10 nm or less.

[0008] In certain embodiments, the underlying material may include an oxide layer disposed beneath the organic planarization layer, a titanium nitride layer or a titanium oxynitride layer disposed beneath the oxide layer, and a silicon nitride layer disposed beneath the titanium nitride layer or the titanium oxynitride layer. Etching the exposed portions of the underlying material may extend the concave features into the oxide layer and into the titanium nitride layer or the titanium oxynitride layer. At least the etching in (b) and (c) may be driven by an inductively coupled plasma. In these or other embodiments, the method may further include removing the organic planarization layer after the concave features have been extended into the oxide layer and into the titanium nitride layer or the titanium oxynitride layer.

[0009] In some embodiments, the underlying material may include a sacrificial hard mask layer disposed under the organic planarization layer, an ultra-low-k dielectric layer disposed under the sacrificial hard mask layer, and a cap layer disposed under the ultra-low-k dielectric layer. Etching the exposed portion of the underlying material may extend the concave feature into the sacrificial hard mask layer, the ultra-low-k dielectric layer, and the cap layer. The etching in at least (b) and (c) may be driven by capacitively coupled plasma. In these or other cases, the sacrificial hard mask layer may include silicon nitride. In these or other cases, the method may further include removing the organic planarization layer after the concave feature has been extended into the sacrificial hard mask layer, the ultra-low-k dielectric layer, and the cap layer.

[0010] In another aspect of the disclosed embodiments, a method of processing a substrate is provided. The method includes: (a) receiving a substrate having an underlying material thereon; (b) depositing a lower layer of a multilayer hard mask on the underlying material, the lower layer of the multilayer hard mask including an inorganic dielectric silicon-containing material; (c) depositing an upper layer of the multilayer hard mask on the underlying material, the upper layer of the multilayer hard mask including a metal oxide, a metal nitride, or a metal oxynitride; and (d) depositing an extreme ultraviolet photoresist on the upper layer of the multilayer hard mask.

[0011] In some embodiments, each of the lower and upper layers of the multilayer hard mask has a thickness of about 10 nm or less. In these or other cases, each of the lower and upper layers of the multilayer hard mask may be deposited by either atomic layer deposition or plasma-enhanced atomic layer deposition. In other cases, one or more of these layers may be deposited by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, etc.

[0012] In a further aspect of the disclosed embodiments, an apparatus for processing a substrate is provided, the apparatus comprising: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate plasma within the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller having at least one processor and a memory, the at least one processor and the memory being communicatively connected to each other, the memory storing computer-executable instructions for controlling the at least one processor to execute any of the methods described herein.

[0013] In another aspect of the disclosed embodiments, an apparatus for processing a substrate is provided, the apparatus comprising: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate plasma within the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller having at least one processor and a memory, the at least one processor and the memory being communicatively connected to each other, the memory controlling the at least one processor to: (i) receive a substrate within the reaction chamber, the substrate comprising: (1) a base material; (2) an organic planarization layer disposed on the base material; (3) a multilayer hard mask disposed on the organic planarization layer, the multilayer hard mask comprising: (a) a lower layer comprising an inorganic dielectric silicon-containing material, and (b) an upper layer comprising a metal oxide, a metal nitride, or a metal oxynitride; and (4) a layer of extreme ultraviolet (EUV) photoresist disposed on the multilayer hard mask, the layer of EUV photoresist being patterned to include recessed features, portions of the upper layer of the multilayer hard mask being exposed within the recessed features; (ii) etch the exposed portions of the upper layer of the multilayer hard mask, thereby expanding the recessed features into the upper layer of the multilayer hard mask and exposing portions of the lower layer of the multilayer hard mask; (iii) etch the exposed portions of the lower layer of the multilayer hard mask, thereby expanding the recessed features into the lower layer of the multilayer hard mask and exposing portions of the organic planarization layer; (iv) etch the exposed portions of the organic planarization layer, thereby expanding the recessed features into the organic planarization layer and exposing portions of the base material; and (v) etch the exposed portions of the base material, thereby expanding the recessed features into the base material.

[0014] In a further aspect of the disclosed embodiments, a system for processing a substrate is provided, the system comprising: (a) a first reaction chamber configured to perform deposition; (b) a second reaction chamber configured to perform etching; and (c) a controller having at least one processor and a memory, the at least one processor and the memory being communicatively connected to each other, the memory controlling the at least one processor to: (i) receive a substrate into the first reaction chamber; (ii) deposit a lower layer of a multilayer hard mask on the substrate, the lower layer of the multilayer hard mask comprising an inorganic dielectric silicon-containing material; (iii) deposit an upper layer of the multilayer hard mask on the lower layer of the multilayer hard mask, the upper layer of the multilayer hard mask comprising a metal oxide, a metal nitride, or a metal oxynitride; (iv) deposit a layer of extreme ultraviolet photoresist on the upper layer of the multilayer hard mask; (v) pattern the layer of extreme ultraviolet photoresist to define a concave feature, thereby exposing a portion of the upper layer of the multilayer hard mask; (vi) transfer the substrate to the second reaction chamber; (vii) etch the exposed portion of the upper layer of the multilayer hard mask, thereby expanding the concave feature into the upper layer of the multilayer hard mask and exposing a portion of the lower layer of the multilayer hard mask; and (viii) etch the exposed portion of the lower layer of the multilayer hard mask, thereby expanding the concave feature into the lower layer of the multilayer hard mask and exposing a portion of the substrate disposed under the lower layer of the multilayer hard mask, the controller storing computer-executable instructions for causing the above to be performed.

[0015] In some embodiments, the second reaction chamber may include an inductively coupled plasma generator, and the memory may store computer-executable instructions for controlling at least one processor to generate a first inductively coupled plasma and etch an exposed portion of the upper layer of the multilayer hard mask in (vii), and to generate a second inductively coupled plasma and etch an exposed portion of the lower layer of the multilayer hard mask in (viii). In some other embodiments, the second reaction chamber may include a capacitively coupled plasma generator, and the memory may store computer-executable instructions for controlling at least one processor to generate a first capacitively coupled plasma and etch an exposed portion of the upper layer of the multilayer hard mask in (vii), and to generate a second capacitively coupled plasma and etch an exposed portion of the lower layer of the multilayer hard mask in (viii).

[0016] These and other aspects are further described below with reference to the drawings.

Brief Description of the Drawings

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[0026] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. The disclosed embodiments are described in conjunction with specific embodiments, but it will be understood that the disclosed embodiments are not intended to be limiting.

[0027] Extreme ultraviolet (EUV) lithography has gained popularity in the field of semiconductor processing. However, EUV technology still faces many challenges. For example, when practicing conventional EUV technology, the thickness of the EUV resist layer is a major limitation with respect to transferring patterns to the underlying hard mask film in 3-layer and 4-layer patterning stacks. In particular, resist scum and local thinning of resist lines can cause undesirable microbridges and line breaks. One scenario where these problems are likely to occur is when patterning features with a pitch of less than 30 nm. At these dimensions, the resist height is not sufficient to open the hard mask (e.g., transfer the pattern from the EUV resist to the hard mask) without forming microbridges (e.g., opens) or line breaks due to thinning of the resist (e.g., shorts). Thus, conventional EUV processing techniques result in a large number of defects, along with associated yield degradation and high processing costs.

[0028] In various embodiments herein, a novel hard mask is used in conjunction with EUV patterning to transfer a pattern from an EUV resist layer to a hard mask layer, and thereafter the pattern can be transferred to an underlying material. The hard mask includes a plurality of layers that together provide improved selectivity between the EUV resist and the hard mask material, enabling faithful pattern transfer through the various layers.

[0029] This disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, but it should also be understood that it is applicable to other next-generation lithography techniques. In addition to EUV with the standard 13.5 nm EUV wavelength currently in use and under development, the radiation sources most relevant to such lithography generally refer to DUV (deep UV) which involves the use of an excimer laser source of 248 nm or 193 nm, X-rays which formally include EUV in the lower energy range of the X-ray spectrum, and e-beams which can cover a wide energy range.

[0030] The hard mask includes at least an upper layer and a lower layer. The upper layer of the hard mask includes a metal-containing material. Exemplary metal-containing materials include metal oxides, metal nitrides, and metal oxynitrides. The metal in the metal-containing material can include titanium, tantalum, hafnium, tin, zinc, molybdenum, ruthenium, etc., as well as combinations thereof. Thus, the upper layer of the hard mask can include, for example, titanium oxide, titanium nitride, titanium oxynitride, tantalum oxide, tantalum nitride, tantalum oxynitride, hafnium oxide, hafnium nitride, hafnium oxynitride, tin oxide, tin nitride, tin oxynitride, ruthenium oxide, ruthenium nitride, ruthenium oxynitride, etc. The metal-containing material of the upper layer of the hard mask generates secondary electrons during EUV lithography exposure. This generation of secondary electrons is beneficial as it reduces the amount of resist scum formed during exposure and thus improves the degree to which features are properly opened. Further, the generation of secondary electrons during EUV exposure provides a dose-versus-size advantage, meaning that for the same level of EUV resist removal, it can be achieved at a lower exposure dose due to increased electron generation from the metal-containing material of the upper layer of the hard mask. Another advantage associated with the disclosed hard mask is that the metal-containing material in the upper layer of the hard mask enables direct adhesion of the EUV resist to the upper layer of the hard mask without the use of an additional organic adhesion layer.

[0031] The upper layer of the hard mask can be formed by any available deposition method. In certain embodiments, the upper layer of the hard mask is formed by atomic layer deposition that can be driven by plasma energy or thermal energy. In other embodiments, the upper layer of the hard mask can be formed by plasma or thermally enhanced chemical vapor deposition, or physical vapor deposition, or spin coating. In various embodiments, the upper layer of the hard mask has a thickness of about 10 nm or less.

[0032] The lower layer of the hard mask includes an inorganic dielectric silicon-containing material. Exemplary silicon-containing materials include, but are not limited to, amorphous silicon (e.g., a-Si), silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, and silicon oxynitride. The lower layer of the hard mask provides excellent selectivity to the underlying layer during pattern transfer. This high selectivity ensures high-quality pattern transfer, significantly reduces the amount of shorts formed, and improves the yield as compared to what is achieved with conventional hard masks.

[0033] The lower layer of the hard mask can be formed by any available deposition method. In certain embodiments, the lower layer of the hard mask is formed by atomic layer deposition that can be driven by plasma energy or thermal energy. In other embodiments, the lower layer of the hard mask can be formed by plasma or thermally enhanced chemical vapor deposition, or physical vapor deposition, or spin coating. In various embodiments, the lower layer of the hard mask has a thickness of about 10 nm or less.

[0034] FIG. 1 is a flowchart of a method of patterning a substrate according to various embodiments of the present specification. FIGS. 2A-2H illustrate a partially fabricated semiconductor substrate as it undergoes the method shown in FIG. 1. The operations of FIG. 1 are described with reference to the substrate 200 shown in FIGS. 2A-2H.

[0035] The method of FIG. 1 begins with substrate 200 shown in FIG. 2A. Substrate 200 includes a base material 201. The base material 201 can include an organic planarization layer (OPL) on its upper surface. In some cases, the organic planarization layer may include spin-on glass, amorphous carbon, and / or similar materials. The base material 201 can also include a series of layers (e.g., one or more layers such as oxides, nitrides, ultra-low k dielectric materials, etc.) on which features are to be formed. The composition and layout of this series of layers depend on the application. Further details regarding specific embodiments are provided below.

[0036] In operation 101, as shown in FIG. 2B, the lower layer 202b of the multilayer hard mask 202 is deposited on the base material 201. As described above, the lower layer 202b can be formed by atomic layer deposition or plasma-enhanced atomic layer deposition among other methods. The lower layer 202b includes the metal-containing material described above. Next, in operation 103, as shown in FIG. 2C, the upper layer 202a of the multilayer hard mask 202 is deposited on the lower layer 202b of the multilayer hard mask 202. The upper layer 202a can be formed by atomic layer deposition or plasma-enhanced atomic layer deposition among other methods. The upper layer 202a includes the inorganic dielectric silicon-containing material described above. At this point, the multilayer hard mask 202 is completely deposited. Next, in operation 105, as shown in FIG. 2D, a layer of photoresist 203 is deposited and patterned on the upper layer 202a of the multilayer hard mask 202. The photoresist 203 can be an extreme ultraviolet (EUV) photoresist in various embodiments. In certain embodiments, the photoresist 203 can have a thickness of about 10 - 50 nm in the deposited state. The photoresist 203 can be patterned by lithography techniques.

[0037] After the photoresist 203 is patterned, typically, there is some extra photoresist (indicated by arrow 203a) remaining on the substrate 200. This extra photoresist 203a can be disposed between adjacent protruding features in the patterned photoresist 203, as shown in FIG. 2D. This configuration may be referred to as a microbridging defect (or microbridge) because the extra photoresist 203a forms a small bridge between adjacent protruding features in the photoresist 203. The extra photoresist 203a can be a result of the non-uniform thickness of the photoresist 203 deposited across the substrate 200 (e.g., in regions where the photoresist 203 is thinner, the photoresist 203a may be reduced after lithographic patterning, and there may be a risk of open circuits in the line pattern).

[0038] In operation 107, as shown in FIG. 2E, the extra photoresist 203a is removed. In various embodiments, the extra photoresist 203a is removed in a descum operation involving exposing the substrate 200 to plasma. Advantageously, the upper layer 202a of the multilayer hard mask 202 is highly resistant to the chemicals / conditions used to remove the extra photoresist 203a. Thus, the upper layer 202a of the multilayer hard mask 202 is not substantially etched while the extra photoresist 203a is being removed. Thus, the conditions used to remove the extra photoresist 203a can be more aggressive / severe than the conditions tolerated by other hard masks, such as silicon-based hard masks, that may be damaged under similar processing conditions.

[0039] Different types of plasma can be used for various applications. For example, in some cases, inductively coupled plasma can be used for descumming. An example where inductively coupled plasma can be used is in the context of a hard mask opening process. FIGS. 3A - 3E, which will be further described below, provide additional details regarding such embodiments. In other cases, descumming can be performed using capacitively coupled plasma. An example where capacitively coupled plasma can be used is in the context of back - end - of - line dielectric etching, such as a process used to etch vias. FIGS. 4A - 4D, which will be further described below, provide additional details regarding such embodiments.

[0040] The descumming chemistry and plasma conditions are selected such that they are selective to the upper layer 202a of the multilayer hard mask 202 (e.g., such that the upper layer 202a remains substantially intact while excess photoresist 203a is removed from between adjacent photoresist features). In one example where descumming is performed using inductively coupled plasma, the descumming chemistry can include, for example, any combination of Cl2, HBr, CF4, and O2. A low bias (e.g., about 100 V or less) can be applied to the substrate. The power used to generate the inductively coupled plasma can be about 500 W or less. The bias and / or plasma power can be pulsed, for example, to minimize damage to the photoresist and improve roughness. In another example where descumming is performed using capacitively coupled plasma, the descumming chemistry can include any combination of CF4, N2, H2, O2, C x F y etc. A low bias of 60 MHz can be applied to the substrate. The power used to generate the capacitively coupled plasma can be about 100 - 300 W. The bias can be pulsed to minimize damage to the photoresist and improve roughness. Although the bias and / or plasma generation power may be relatively low, it can be made higher than when used with conventional mask materials that are more prone to damage.

[0041] For removing at least the excess photoresist 203a, relatively strong processing conditions are used, and for secondary electron generation from the upper layer 202a during EUV exposure, the multilayer hard mask 202 substantially reduces the formation of microbridges and similar defects on the substrate. This represents a significant improvement over the prior art.

[0042] Returning to FIG. 1, the method continues at operation 109, and as shown in FIG. 2F, the concave feature 204 is anisotropically etched into the upper layer 202a of the multilayer hard mask 202. The etching process may be reactive ion etching. During this etching operation, the photoresist 203 acts as a mask and protects the upper layer 202a of the multilayer hard mask 202 in the regions where the photoresist 203 is present. Thus, the etching is limited to the regions of the concave feature 204 where the photoresist 203 has been previously removed. The etching in operation 109 is highly selective such that the material of the upper layer 202a is removed while the photoresist 203 is substantially preserved. This high selectivity helps to prevent disconnection. During this etching operation, some amount of the photoresist 203 may be consumed.

[0043] In various embodiments, the chemicals used to etch the upper layer 202a may include chlorine-based chemicals and / or bromine-based chemicals. Different types of plasmas can be used for various applications. For example, in some cases, the upper layer 202a can be etched using inductively coupled plasma. An example where inductively coupled plasma can be used is in the context of a hard mask opening process. FIGS. 3A - 3E, described further below, provide additional details regarding such embodiments. In other cases, the upper layer 202a can be etched using capacitively coupled plasma. An example where capacitively coupled plasma can be used is in the context of back-end-of-line dielectric etching, such as a process used to etch vias. FIGS. 4A - 4D, described further below, provide additional details regarding such embodiments.

[0044] When etching the upper layer 202a using inductively coupled plasma, the following gases: HBr, Cl2, H2, C x H y any combination of can be provided to the reaction chamber. Optionally, additional reactants or other gases may be provided. The substrate may be biased at about 300 V or less, and the inductively coupled plasma may be generated with power of about 300 W or less. The plasma can be pulsed with a duty cycle of about 30% or less. The pressure in the reaction chamber can be about 5 - 20 mTorr (e.g., about 0.66 - 2.67 Pa). The substrate support can be maintained at a temperature of about 30 °C or less. When etching the upper layer 202a using capacitively coupled plasma, the chemicals used for etching are C x H y , H2, and C x F y can include any combination of. Optionally, additional reactants or other gases may be provided. For example, at a power level of about 100 - 800 W, lower power may be applied at 60 MHz and 27 MHz. The plasma can be pulsed with a duty cycle of about 20 - 30%. The pressure in the reaction chamber can be about 20 - 80 mTorr (e.g., about 2.66 - 10.7 Pa).

[0045] Next, in operation 111, as shown in FIG. 2G, the concave feature 204 is extended by anisotropic etching into the lower layer 202b of the multilayer hard mask 202. This etching process may be a reactive ion etching process. During this etching operation, the photoresist 203 and the upper layer 202a of the multilayer hard mask act as a mask and protect the lower layer 202b in the regions where these materials are present. Thus, the etching is limited to the unprotected regions of the concave feature 204. The photoresist 203 may be partially consumed while the concave feature 204 is etched into the lower layer 202b of the multilayer hard mask 202. In other embodiments, the photoresist 203 may be completely consumed during this operation (e.g., in this case, there is no photoresist 203 on the substrate shown in FIG. 2G). In such embodiments, the upper layer 202a continues to act as a mask and protects the lower layer 202b in the regions where the upper layer 202a is present. The etching in operation 111 is highly selective such that the material of the lower layer 202b is removed while the material of the upper layer 202a is substantially preserved. This high selectivity reduces the possibility of forming unwanted disconnections.

[0046] In various embodiments, the chemicals used to etch the lower layer 202b may include fluorine-based chemicals and / or chlorine-based chemicals. Generally, the chemicals used to etch the upper layer 202a are different from the chemicals used to etch the lower layer 202b. For example, the upper layer 202a may be etched with a chlorine-based chemical, and the lower layer 202b may be etched with a fluorine-based chemical. 。 In another example, the upper layer 202a may be etched with a bromine-based chemical, and the lower layer 202b may be etched with a chlorine-based chemical. Exemplary chlorine and bromine-based chemicals are shown above. Exemplary fluorine-based chemicals include, for example, C x F y and C x H y F z and the like.

[0047] Different types of plasma can be used for various applications. For example, in some cases, the lower layer 202b can be etched using inductively coupled plasma. An example where inductively coupled plasma can be used is in the context of a hard mask opening process. As described above, FIGS. 3A - 3E provide additional details regarding such embodiments. In other cases, the lower layer 202b can be etched using capacitively coupled plasma. An example where capacitively coupled plasma can be used is in the context of back - end - of - line dielectric etching, such as a process used to etch vias. FIGS. 4A - 4D provide additional details regarding such embodiments.

[0048] The chemical for etching the lower layer 202b is selected to be selective with respect to the photoresist 203 and the upper layer 202a (e.g., such that the chemical targets the removal of the lower layer 202b). This selectivity helps prevent disconnection. In embodiments where the lower layer 202b is etched with inductively coupled plasma, the chemicals used can include any combination of C x F y 、O2, N2, C x H y F z 、Ar, SF6, and NF3. In some cases, additional reactants or other gases may be provided. The substrate may be biased at about 300V or less, and the inductively coupled plasma may be generated with power of about 300W or less. The plasma can be pulsed with a duty cycle of about 10 - 30%. The reaction chamber can be maintained at a pressure of about 5 - 20 mTorr (e.g., about 0.66 - 2.67 Pa). The substrate support can be maintained at a temperature of about 10 - 60°C. In the case where the lower layer 202b is etched with capacitively coupled plasma, the chemicals used for etching can include C x F y 、O2, N2, C x H y F zand any combination of Ar. Optionally, additional reactants may be provided. For example, at a power level of about 100 - 800 W, lower power may be provided at 60 MHz and 27 MHz. The plasma can be pulsed at a duty cycle of about 10 - 30%. The substrate temperature can be maintained at about 0 - 60 °C.

[0049] Returning to FIG. 1, the method continues at operation 113, and as shown in FIG. 2H, the recessed feature 204 is extended by anisotropic etching into the underlying material 201. During this etching operation, the upper layer 202a and the lower layer 202b of the multilayer hard mask 202 (as well as the remaining photoresist 203) act as a mask to protect the underlying material 201 in the regions where the multilayer hard mask 202 (or a portion thereof) is present. Thus, the etching is limited to the unprotected regions of the recessed feature 204. The underlying material 201 may be etched in several different steps depending on the materials and structures present on the substrate 200. For example, different layers within the underlying material 201 may be etched in different steps, with each step targeting the removal of a specific type of layer.

[0050] When the underlying material 201 is etched, the remaining photoresist 203 is consumed. After the photoresist 203 is consumed, the upper layer 202a of the multilayer hard mask 202 is consumed. When the upper layer 202a is consumed, the lower layer 202b of the multilayer hard mask 200 is consumed. The lower layer 202b provides excellent selectivity with respect to the underlying material 201. In other words, the etching process used to etch the recessed feature 204 into the underlying material 201 is highly selective such that most of the lower layer 202b remains preserved while the underlying material 201 is removed. Of course, with sufficient plasma exposure or other processing, the lower layer 202b can be removed by consuming it as a mask material or by a specially designed step to remove the lower layer 202b.

[0051] In some embodiments, the underlying material 201 includes an organic planarization layer over another structure (e.g., a series of layers), and the organic planarization layer is on the top surface of the underlying material 201. In some such embodiments, the organic planarization layer (which may have a thickness of about 40 - 100 nm) is completely etched without completely consuming the upper layer 202a of the multilayer hard mask 202. In such embodiments, the upper layer 202a may continue to act as a mask while the 204 concave feature is etched into a series of layers below the organic planarization layer. In other cases, the upper layer 202a of the multilayer hard mask 202 may be completely consumed while etching the organic planarization layer. In such cases, the lower layer 202b of the multilayer hard mask 202 may act as a mask while completing the etching of the organic planarization layer and / or while etching a series of layers below the organic planarization layer.

[0052] FIG. 1 illustrates many different operations that can be performed, but it is understood that in certain embodiments, many of these operations may be omitted. For example, the method can begin by receiving a substrate, as shown in any of FIGS. 2A - 2E. In such cases, many of the operations shown in FIG. 1 (especially those earlier in the method) may be omitted. In one embodiment, the method begins with operation 103 on the substrate, as shown in FIG. 2B. In another embodiment, the method begins with operation 105 on the substrate, as shown in FIG. 2C. In another embodiment, the method begins with operation 107 on the substrate, as shown in FIG. 2D. In another embodiment, the method begins with operation 109 on the substrate, as shown in FIG. 2E. Generally, all of these embodiments involve etching the substrate while the multilayer hard mask is present on the substrate. Still other embodiments may include deposition steps related to the formation of the multilayer hard mask without involving some or all of the etching steps. For example, in one embodiment, the method involves operations 101 and 103. In another embodiment, the method involves operations 101, 103, and 105. After these operations, other operations shown in FIG. 1 may or may not follow.

[0053] Figures 1 and 2A - 2H both illustrate techniques that can be used in various embodiments. Figures 3A - 3E show specific scenarios in which a particular embodiment can be practiced. More specifically, Figures 3A - 3E illustrate various stages of a hard mask opening process in which a concave feature is formed in an organic planarization layer, then an oxide layer, and then a titanium nitride layer. Although Figures 3A - 3E illustrate specific structures and materials, these represent only one embodiment of the disclosed technology, and it should be understood that such structures and materials are not intended to be limiting. Generally speaking, the etching operations described in connection with Figures 3A - 3E can be performed in a reaction chamber configured to generate inductively coupled plasma. In other words, inductively coupled plasma can be used to drive the etching operations described in Figures 3A - 3E.

[0054] Figure 3A shows a substrate 200 having a multilayer hard mask 202 with an ultra - low k dielectric layer 315, a silicon nitride layer 314, a titanium nitride layer 313, an oxide layer 312, an organic planarization layer 311, and upper layer 202a and lower layer 202b. Examples of ultra - low k dielectric materials include, for example, various versions of SiCOH. In some cases, the titanium nitride layer 313 may further include oxygen so as to be a titanium oxynitride layer. The oxide layer 312 may be a TEOS - based oxide layer (e.g., a silicon oxide layer) in a particular embodiment. The substrate 200 of Figure 3A can be formed by the process flow described in Figure 1 (e.g., operations 101 - 111, or a subset thereof) and Figures 2A - 2G. For the sake of brevity, the description will not be repeated. The substrate 200 of Figure 3A is similar to the substrate 200 of Figure 2G, and the underlying material 201 of Figure 2G corresponds to the layers 311, 312, 313, 314, and 315 of Figure 3A.

[0055] As shown in FIG. 3A, after the concave feature 204 is transferred to both the upper layer 202a and the lower layer 202b of the multilayer hard mask 202, as shown in FIG. 3B, the concave feature 204 is extended into the organic planarization layer 311. This etching process may be a reactive ion etching process. During this anisotropic etching, the remaining photoresist 203 acts as a mask, thereby protecting the material under the photoresist 203. When the photoresist 203 is consumed, the upper layer 202a of the multilayer hard mask can continue to act as a mask. The etching process for forming the concave feature 204 in the organic planarization layer 311 is selected such that the material of the organic planarization layer 311 is targeted for removal at a higher etching rate and the remaining photoresist 203 and / or the upper layer 202a of the multilayer hard mask 202 are etched at a lower rate.

[0056] When the organic planarization layer is etched using inductively coupled plasma, the etching chemistry can use any combination of SO x , CH4, O2, N2, H2, and CO x . When the organic planarization layer is etched using capacitively coupled plasma, the etching chemistry can use any combination of CO x , N2, H2, and O2. In either case, additional reactants or other gases may be provided in some embodiments. Generally speaking, this etching step can be carried out using conventional processing conditions.

[0057] Next, as shown in FIG. 3C, the concave feature 204 is extended into the oxide layer 312. This etching process may be reactive ion etching. During this anisotropic oxide etching, the remaining portion of the upper layer 202a of the multilayer hard mask 202 acts as a mask to ensure that the concave feature 204 is transferred as desired. When the upper layer 202a of the multilayer hard mask 202 is consumed, the lower layer 202b of the multilayer hard mask 202 continues to act as a mask. This etching process is selective such that the material of the oxide layer 312 is removed at a higher etching rate and the material of the upper layer 202a and / or the lower layer 202b of the multilayer hard mask 202 is removed at a lower etching rate. In certain embodiments, the chemicals used to etch the concave feature 204 into the oxide layer 312 are C x F y 、C x H y F z 、N2, O2, H2, C x H y 、SF6, NF3, and He can include any combination. In some cases, other reactants or process gases may be provided. Generally speaking, this step can be achieved using conventional processing conditions.

[0058] Next, as shown in FIG. 3D, the concave feature 204 is extended into the titanium nitride layer 313. This etching process may be reactive ion etching. During this anisotropic titanium nitride etching, the remaining portion of the lower layer 202b of the multilayer hard mask 202 acts as a mask to ensure that the concave feature 204 is transferred as desired. When the lower layer 202b of the multilayer hard mask 202 is consumed, the organic planarization layer 311 continues to act as a mask. This etching process is selective such that the material of the titanium nitride layer 313 is removed at a higher etching rate and the material of the lower layer 202b and / or the organic planarization layer 311 is removed at a lower etching rate. In certain implementations, the chemicals used to etch the recess feature 204 into the titanium nitride layer 313 can include any combination of Cl2, HBr, CH4, Ar, N2, He. In some cases, additional reactants or other process gases may be provided. The plasma may be an inductively coupled plasma as described above.

[0059] As shown in FIG. 3E, after the concave feature 204 is etched into the titanium nitride layer 313, the organic planarization layer 311 is removed. In some embodiments, the organic planarization layer 311 can be removed by exposing the substrate 200 to an ashing plasma such as an oxygen-containing plasma. The removal of the organic planarization layer 311 is selective such that the material of the organic planarization layer 311 is targeted for removal at a relatively high removal rate and the oxide layer 312, the titanium nitride layer 313, and the silicon nitride layer 314 are substantially preserved (and / or etched at a much lower rate compared to the organic planarization layer 311).

[0060] The process flows described in FIGS. 2A-2H and FIGS. 3A-3E show a hard mask opening process that can transfer features from a patterned EUV photoresist layer containing a titanium nitride layer disposed under an oxide layer using the disclosed multilayer hard mask. In certain embodiments, the various etching operations described in connection with FIGS. 3A-3D or FIGS. 3A-3E can be performed within a single reaction chamber having at least an inductively coupled plasma generator.

[0061] FIGS. 4A-4D show another process flow that can be used in combination with the process flow shown in FIGS. 2A-2H. This example is provided in the context of via etching. In certain embodiments, the etching operations described in connection with FIGS. 4A-4D can be performed within a reaction chamber having a capacitively coupled plasma generator. In other words, the etching reactions of FIGS. 4A-4D can be driven by capacitively coupled plasma.

[0062] FIG. 4A illustrates a substrate 200 having a multilayer hard mask 202 including an underlying structure 425, a cap layer 424, an ultra-low-k dielectric layer 423, a sacrificial hard mask layer 422, an organic planarization layer 411, an upper layer 202a and a lower layer 202b, and a photoresist 203. The cap layer 424 can be referred to as a dielectric cap. The cap layer 424 may be silicon nitride, but embodiments are not so limited. Exemplary materials for the ultra-low-k dielectric layer 423 include various types of SiCOH and similar materials. One exemplary material for the sacrificial hard mask layer 422 is silicon nitride, but embodiments are not so limited. The substrate 200 shown in FIG. 4A can be formed by the processes described in FIG. 1 (e.g., operations 101-111) and FIGS. 2A-2G. For the sake of brevity, the description is not repeated. The substrate 200 of FIG. 4A is similar to the substrate 200 of FIG. 2G, and the underlying material 201 of FIG. 2G corresponds to the layers 411, 422, 423, 424, and 425 of FIG. 4A.

[0063] As shown in FIG. 4A, after the concave feature 204 is transferred to both the upper layer 202a and the lower layer 202b of the multilayer hard mask 202, as shown in FIG. 4B, the concave feature 204 is extended into the organic planarization layer 411. The etching process may be reactive ion etching. During this anisotropic etching process, the remaining photoresist 203 acts as a mask, thereby protecting the material under the photoresist 203. If the photoresist 203 is consumed, the upper layer 202a of the multilayer hard mask can continue to act as a mask. The etching process for forming the concave feature 204 in the organic planarization layer 411 is selected such that the material of the organic planarization layer 411 is targeted for removal at a higher etching rate and the remaining photoresist 203 and / or the upper layer 202a of the multilayer hard mask 202 is etched at a lower rate. In some cases, the chemicals for this step can include any combination of O2, N2, H2, and CO x and may include any combination of. In some cases, other reactants or process gases may be provided. Generally speaking, conventional processing conditions can be used for this step.

[0064] Next, as shown in FIG. 4C, the concave feature 204 is extended into the sacrificial hard mask layer 422, the ultra-low-k dielectric layer 423, and the cap layer 424. This can be achieved with one or more anisotropic etching operations, where each operation is targeted at removing one or more of the layers. The etching operation may be a reactive ion etching operation. During this etching process, the upper layer 202a and the lower layer 202b of the multilayer hard mask 202, as well as the organic planarization layer 411, act as masks to transfer the pattern through the various layers. For example, while the upper layer 202a is present, it acts to protect the underlying material from etching. When the upper layer 202a is consumed, the lower layer 202b continues to act as a mask to protect the underlying material from etching. When the lower layer 202b is consumed, the organic planarization layer 411 continues to act as a mask to protect the underlying material from etching. In this way, the pattern of the concave feature 204 can be transferred through the various layers and reach the substrate 200 shown in FIG. 4C. Generally speaking, conventional chemicals (e.g., C x H y F z 、C x F y 、N2、O2、CO x 、Ar, etc.) can be used with conventional processing conditions to achieve these steps.

[0065] As shown in FIG. 4D, after the concave feature 204 is etched into the cap layer 424, the remaining organic planarization layer 411 can be removed. This removal is similar to, for example, the removal of the organic planarization layer 311 described in connection with FIG. 3E, but different plasmas and plasma generation conditions can be used. In certain embodiments, one or more of the layers are, for example, O2, CO xIt can be removed using a stripping chemical containing any combination of N2, and H2. The figure shows the removal of the organic planarization layer 411 after the concave feature 204 has extended into the cap layer 424, although in some cases this may be done in a different order. For example, the organic planarization layer 411 can be removed after the concave feature 204 has extended into the ultra-low k dielectric layer 423. In some embodiments, all of the etching operations described in FIGS. 4A-4D can be performed within a single reaction chamber.

[0066] The process flows described in FIGS. 1, 2A-2H, and 4A-4D can be used, in certain embodiments, for example, in scenarios where vias or similar features are etched. FIGS. 3A-3E and 4A-4D merely provide two examples of applications where the disclosed multilayer hard mask can be used. The disclosed multilayer hard mask can also be used for other applications as desired.

[0067] Device The technology described in this specification can be implemented in various apparatuses. One or more reaction chambers can be configured to perform deposition, for example, depositing an upper layer and / or a lower layer of a multilayer hard mask, and / or any other layer / material described in this specification. Further, one or more reaction chambers can be configured to perform etching, for example, etching an upper layer and / or a lower layer of a multilayer hard mask, and / or any other layer / material described in this specification. Similarly, one or more reaction chambers can be configured to perform other material removal operations such as ashing and / or cleaning. These can be dry (e.g., plasma-based) operations or wet (e.g., liquid-based) operations. In certain embodiments, a single reaction chamber may be configured to perform multiple types of tasks such as both deposition and etching. In some embodiments, multiple reaction chambers can be combined in a single apparatus, and each reaction chamber is configured to perform a specific purpose such as deposition or etching. In some embodiments, multiple apparatuses can be combined in a single system, and each apparatus is configured to perform a specific purpose such as deposition or etching. Many configurations are possible.

[0068] FIG. 5 schematically shows one embodiment of a process station 500 that can be used to deposit materials using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), both of which can be plasma enhanced. The process station 500 can be used to deposit various layers described herein, including upper and / or lower layers of a multilayer hard mask. Similarly, the process station 500 can be used to deposit various other layers described in connection with FIGS. 2A-2H, FIGS. 3A-3E, and FIGS. 4A-4D. Of course, other deposition chambers can be used as desired for a particular operation or application. For simplicity, the process station 500 is shown as a stand-alone process station having a process chamber body 502 for maintaining a low-pressure environment. However, it will be understood that multiple process stations 500 may be included in a common process tool environment. Further, in some embodiments, one or more hardware parameters of the process station 500 (including those described in detail below) can be programmatically adjusted by one or more computer controllers.

[0069] The process station 500 is in fluid communication with a reactant delivery system 501 for delivering process gas to a distribution showerhead 506. The reactant delivery system 501 includes a mixing vessel 504 for blending and / or conditioning the process gas delivered to the showerhead 506. One or more mixing vessel inlet valves 520 can control the introduction of process gas into the mixing vessel 504. Similarly, a showerhead inlet valve 505 can control the introduction of process gas into the showerhead 506.

[0070] Some reactants, such as BTBAS, can be stored in liquid form before vaporization and subsequent delivery to the process station. For example, the embodiment of FIG. 5 includes a vaporization point 503 for vaporizing a solid reactant supplied to the mixing vessel 504. In some embodiments, the vaporization point 503 can be a heated vaporizer. The reactant vapor generated from such a vaporizer may condense in the downstream delivery piping. Exposure of the condensed reactant to an incompatible gas may generate small particles. These small particles can clog the piping, interfere with the operation of the valves, or contaminate the substrate. Some approaches to address these problems involve purging and / or venting the delivery piping to remove residual reactants. However, purging the delivery piping can increase the cycle time of the process station and potentially reduce the throughput of the process station. Accordingly, in some embodiments, the delivery piping downstream of the vaporization point 503 can be heat traced. In some examples, the mixing vessel 504 can also be heat traced. In one non-limiting example, the piping downstream of the vaporization point 503 has a rising temperature profile ranging from about 100° C. to about 150° C. in the mixing vessel 504.

[0071] In some embodiments, the reactant liquid can be vaporized by a liquid injector. For example, the liquid injector can inject pulses of the liquid reactant into a carrier gas stream upstream of the mixing vessel. In one scenario, the liquid injector can vaporize the reactant by flashing the liquid from a high pressure to a low pressure. In another scenario, the liquid injector can atomize the liquid into dispersed micro-droplets that subsequently vaporize in a heated delivery pipe. It will be appreciated that small droplets can vaporize faster than large droplets, reducing the delay between liquid injection and complete vaporization. The faster the vaporization, the shorter the length of the piping downstream from the vaporization point 503 can be. In one scenario, the liquid injector may be directly attached to the mixing vessel 504. In another scenario, the liquid injector may be directly attached to the showerhead 506.

[0072] In some embodiments, a liquid flow controller can be provided upstream of the vaporization point 503 to control the mass flow rate of the liquid that is vaporized and fed to the process station 500. For example, the liquid flow controller (LFC) can include a thermal mass flow meter (MFM) located downstream of the LFC. Next, the plunger valve of the LFC can be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller that is in electrical communication with the MFM. However, it may take more than one second to stabilize the liquid flow using feedback control. This can potentially extend the dosing time of the liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, the LFC can be dynamically switched from the feedback control mode to the direct control mode by disabling the sensing tube and the PID controller of the LFC.

[0073] The showerhead 506 distributes the process gas toward the substrate 512. In the embodiment shown in FIG. 5, the substrate 512 is located below the showerhead 506 and is shown resting on the pedestal 508. It will be appreciated that the showerhead 506 may have any suitable shape and may have any suitable number and arrangement of ports for distributing the process gas to the substrate 512. In many embodiments herein, the showerhead 506 can distribute the process gas in a stepwise manner, enabling, for example, atomic layer deposition that relies on the periodic delivery and adsorption of the process gas on the substrate surface.

[0074] In some embodiments, the microvolume 507 is located below the showerhead 506. Performing ALD and / or CVD processes in the microvolume rather than the full volume of the process station can reduce the exposure and purge times to the reactants, can reduce the time to change process conditions (e.g., pressure, temperature, etc.), and can limit the exposure of the process station robot to the process gas, among other things. Exemplary microvolume sizes include, but are not limited to, volumes from 0.1 liter to 2 liters. This microvolume also affects the productivity throughput. While the deposition rate per cycle decreases, the cycle time is simultaneously shortened. In some cases, the latter effect is sufficiently effective to improve the overall throughput of the module for a given target thickness of the film.

[0075] In some embodiments, the pedestal 508 can be raised or lowered to expose the substrate 512 to the microvolume 507 and / or to change the volume of the microvolume 507. For example, during the substrate transfer stage, the pedestal 508 can be lowered to enable the substrate 512 to be loaded onto the pedestal 508. During the deposition process stage, the pedestal 508 can be raised to position the substrate 512 within the microvolume 507. In some embodiments, the microvolume 507 can completely surround the substrate 512 as well as a portion of the pedestal 508 and can form a region of high flow impedance during the deposition process.

[0076] Optionally, the pedestal 508 may be lowered and / or raised during a portion of the deposition process to adjust the process pressure, reactant concentration, etc. within the microvolume 507. In one scenario where the process chamber body 502 remains at the base pressure during the deposition process, the microvolume 507 can be evacuated by lowering the pedestal 508. Exemplary volume ratios of the microvolume to the process chamber volume include, but are not limited to, volume ratios from 1:500 to 1:10. It will be appreciated that in some embodiments, the height of the pedestal can be programmatically adjusted by a suitable computer controller.

[0077] In another scenario, by adjusting the height of pedestal 508, it may be possible to vary the plasma density during the plasma activation cycle and / or the plasma treatment cycle included in the deposition process. At the end of the deposition process stage, pedestal 508 can be lowered during the transfer stage of another substrate to enable removal of substrate 512 from pedestal 508.

[0078] Although the exemplary microvolume variations described herein refer to a pedestal with adjustable height, it will be understood that in some embodiments, the position of showerhead 506 can be adjusted relative to pedestal 508 to vary the volume of microvolume 507. Further, it will be understood that the vertical position of pedestal 508 and / or showerhead 506 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, pedestal 508 may include a rotational axis for rotating the orientation of substrate 512. It will be understood that in some embodiments, one or more of these exemplary adjustments can be programmatically implemented by one or more suitable computer controllers.

[0079] Returning to the embodiment shown in FIG. 5, the showerhead 506 and pedestal 508 are in electrical communication with an RF power supply 514 and a matching network 516 to supply power to the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 514 and the matching network 516 can operate at any suitable power to form a plasma having a desired composition of radical species. Examples of suitable power are included above. Similarly, the RF power supply 514 can provide RF power at any suitable frequency. In some embodiments, the RF power supply 514 can be configured to control high-frequency and low-frequency RF power independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies from 50 kHz to 500 kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies from 1.8 MHz to 2.45 GHz. It will be appreciated that any suitable parameters can be adjusted discretely or continuously to provide plasma energy for surface reactions. In one non-limiting example, the plasma power can be pulsed intermittently to reduce ion bombardment at the substrate surface compared to a plasma that is continuously powered.

[0080] In some embodiments, the plasma can be monitored in-situ by one or more plasma monitors. In one scenario, the plasma power can be monitored by one or more voltage and current sensors (e.g., VI probes). In another scenario, the plasma density and / or process gas concentration may be measured by one or more optical emission spectrometers (OES). In some embodiments, one or more plasma parameters can be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, an OES sensor can be used in a feedback loop to provide program control of the plasma power. It will be appreciated that in some embodiments, other monitors can be used to monitor the plasma and other process characteristics. Such monitors can include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0081] In some embodiments, the plasma can be controlled via input / output control (IOC) sequence commands. In one example, commands for setting plasma conditions for a plasma process step may be included in a corresponding plasma activation recipe step of a deposition process recipe. Optionally, the process recipe steps may be arranged in sequence such that all commands for a deposition process step are executed simultaneously with that process step. In some embodiments, commands for setting one or more plasma parameters may be included in a recipe step preceding the plasma process step. For example, a first recipe step may include commands for setting the flow rates of an inert gas and / or a reactant gas, commands for setting the plasma generator to a power set point, and a time delay command for the first recipe step. A second subsequent recipe step may include commands for enabling the plasma generator, and a time delay command for the second recipe step. A third recipe step may include commands for disabling the plasma generator, and a time delay command for the third recipe step. It will be appreciated that these recipe steps can be further subdivided and / or repeated in any suitable manner within the scope of the present disclosure.

[0082] In some deposition processes, the plasma strike persists for an order of magnitude of several seconds or more. In certain embodiments, much shorter plasma strikes can be used. These can be on the order of about 10 milliseconds to 1 second, typically on the order of about 20 to 80 milliseconds, with a specific example being 50 milliseconds. Such very short RF plasma strikes are accompanied by a very rapid stabilization of the plasma. To achieve this, the plasma generator can be configured such that while allowing for frequency variations, the impedance matching is preset to a specific voltage. Conventionally, high-frequency plasma is generated at an RF frequency of about 13.56 MHz. In various embodiments disclosed herein, the frequency is allowed to vary to a value different from this standard value. By allowing for frequency variations while fixing the impedance matching to a predetermined voltage, the plasma can stabilize more rapidly, which can be important when using very short plasma strikes associated with some types of deposition cycles.

[0083] In some embodiments, the pedestal 508 can be temperature-controlled via the heater 510. Further, in some embodiments, pressure control for the deposition process station 500 can be provided by the butterfly valve 518. As shown in the embodiment of FIG. 5, the butterfly valve 518 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the process station 500 can also be adjusted by varying the flow rate of one or more gases introduced into the process station 500.

[0084] FIG. 6 shows a schematic diagram of an embodiment of a multi-station processing tool 600 that includes an inbound load lock 602 and an outbound load lock 604, either or both of which may include a remote plasma source. A robot 606 is configured to move wafers from a cassette loaded via a pod 608 at atmospheric pressure to the inbound load lock 602 via an atmospheric port 610. The wafer is placed on a pedestal 612 of the inbound load lock 602 by the robot 606, the atmospheric port 610 is closed, and the load lock is pumped down. If the inbound load lock 602 includes a remote plasma source, the wafer may be subjected to remote plasma processing within the load lock before being introduced into the processing chamber 614. Additionally, the wafer may also be heated in the inbound load lock 602, for example, to remove moisture and adsorbed gases. Next, a chamber transfer port 616 to the processing chamber 614 is opened, and another robot (not shown) moves the wafer into the reactor and places it on a pedestal at the first station shown within the reactor for processing. Although the embodiment illustrated in FIG. 6 includes load locks, it will be understood that in some embodiments, wafers may be directly introduced into the process station.

[0085] The illustrated processing chamber 614 includes four process stations numbered from 1 to 4 in the embodiment shown in FIG. 6. Each station has a heating pedestal (shown as 618 for station 1) and a gas line inlet. It will be appreciated that in some embodiments, each process station may have different purposes or multiple purposes. For example, one process station may be configured to deposit a lower layer of a multilayer hard mask, and another process station may be configured to deposit an upper layer of the multilayer hard mask. Each processing station may be as described above with respect to FIG. 5. Although the illustrated processing chamber 614 includes four stations, it is understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, and in other embodiments, the processing chamber may have three or fewer stations.

[0086] FIG. 6 also illustrates one embodiment of a wafer handling system 690 for transferring wafers within the processing chamber 614. In some embodiments, the wafer handling system 690 can transfer wafers between various process stations and / or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 6 also illustrates one embodiment of a system controller 650 used to control the process conditions and hardware state of the process tool 600. The system controller 650 can include one or more memory devices 656, one or more mass storage devices 654, and one or more processors 652. The processor 652 can include a CPU or computer, analog and / or digital input / output connections, a stepping motor controller board, and the like.

[0087] In some embodiments, system controller 650 controls all of the activities of process tool 600. System controller 650 executes system control software 658 that is stored in mass storage device 654, loaded into memory device 656, and executed by processor 652. System control software 658 may include instructions for controlling timing, gas mixing, chamber pressure and / or station pressure, chamber temperature and / or station temperature, purge conditions and timing, wafer temperature, RF power level, RF frequency, substrate, pedestal, chuck position and / or susceptor position, and other parameters of the particular processes performed by process tool 600. System control software 658 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components that perform various process tool processes according to the disclosed methods. System control software 658 may be coded in any suitable computer-readable programming language.

[0088] In some embodiments, system control software 658 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a PEALD process may include one or more instructions for execution by system controller 650. Instructions for setting process conditions for a PEALD process stage may be included in the corresponding PEALD recipe stage. In some embodiments, the PEALD recipe stages may be arranged in sequence such that all instructions for a PEALD process stage are executed simultaneously with that process stage.

[0089] In some embodiments, other computer software and / or programs stored in the mass storage device 654 and / or the memory device 656 associated with the system controller 650 may be used. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0090] The substrate positioning program can include program code for process tool components used to load a substrate onto the pedestal 618 and control the spacing between the substrate and other parts of the process tool 600.

[0091] The process gas control program can include code for controlling the gas composition and flow rate to stabilize the pressure of the process station, and optionally code for flowing the gas to one or more process stations prior to deposition. The process gas control program may include code for controlling the gas composition and flow rate within any of the disclosed ranges. The pressure control program can include code for controlling the pressure of the process station, for example, by adjusting a throttle valve in the exhaust system of the process station, the gas flow to the process station, etc. The pressure control program may include code for maintaining the pressure within the process station within any of the disclosed pressure ranges.

[0092] The heater control program can include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program can control the delivery of a heat transfer gas (such as helium) to the substrate. The heater control program may include instructions for maintaining the temperature of the substrate within any of the disclosed ranges.

[0093] The plasma control program can include code for setting the RF power level and frequency applied to the process electrodes in one or more process stations using, for example, any of the RF power levels disclosed herein. The plasma control program can also include code for controlling the duration of each plasma exposure.

[0094] In some embodiments, there may be a user interface associated with the system controller 650. The user interface can include a display screen, a graphical software display of the device and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0095] In some embodiments, the parameters adjusted by the system controller 650 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (such as RF power level, frequency, and exposure time, etc.). These parameters may be provided to the user in the form of a recipe and can be input using the user interface.

[0096] Signals for monitoring the process may be provided from various process tool sensors to the analog and / or digital input connections of the system controller 650. Signals for controlling the process can be output at the analog and digital output connections of the process tool 600. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain process conditions.

[0097] To implement the disclosed embodiments, any suitable chamber can be used. Exemplary deposition apparatuses include, but are not limited to, apparatuses from the ALTUS® product family, the VECTOR® product family, and / or the SPEED® product family, each available from Lam Research Corporation of Fremont, California, or any of a variety of other commercially available processing systems. Two or more stations may perform the same function. Similarly, two or more stations may perform different functions. Each station can be designed / configured to perform a particular desired function / method.

[0098] Figures 7A - 7C illustrate one embodiment of a capacitively coupled confinement RF plasma reactor 700 having an adjustable gap that can be used to perform the etching operations described herein. For example, such a reactor can be used to etch any one or more of the layers described herein, including but not limited to the upper and lower layers of a multilayer hard mask, as well as organic planarization layers and other layers described in connection with FIGS. 2A - 2H and FIGS. 4A - 4D. For a particular application, other types of etching reactors having different types or additional types of plasma generators can be used as desired. As shown, the vacuum chamber 702 includes a chamber housing 704 that surrounds an internal space that houses a lower electrode 706. At the upper portion of the chamber 702, an upper electrode 708 is vertically spaced from the lower electrode 706. The planes of the upper and lower electrodes 708, 706 are substantially parallel and orthogonal to the vertical direction between the electrodes. Preferably, the upper and lower electrodes 708, 706 are circular and coaxial with respect to a vertical axis. The lower surface of the upper electrode 708 faces the upper surface of the lower electrode 706. The spaced and facing electrode surfaces define an adjustable gap 710 therebetween. During operation, the lower electrode 706 is supplied with RF power by an RF power (match) 720. The RF power is supplied to the lower electrode 706 through an RF supply conduit 722, an RF strap 724, and an RF power member 726. A ground shield 736 can surround the RF power member 726 to provide a more uniform RF field to the lower electrode 706. The wafer is inserted through a wafer port 782 and supported at the gap 710 on the lower electrode 706 for processing, and a process gas is supplied to the gap 710 and excited to a plasma state by the RF power. The upper electrode 708 may be energized or grounded.

[0099] In the embodiment shown in FIGS. 7A - 7C, the lower electrode 706 is supported on a lower electrode support plate 716. An insulating ring 714 inserted between the lower electrode 706 and the lower electrode support plate 716 insulates the lower electrode 706 from the support plate 716.

[0100] The RF bias housing 730 supports the lower electrode 706 on the RF bias housing bowl 732. The bowl 732 is connected to the conduit support plate 738 through an opening in the chamber wall plate 718 by an arm 734 of the RF bias housing 730. In a preferred embodiment, the RF bias housing bowl 732 and the RF bias housing arm 734 are integrally formed as one component, but the arm 734 and the bowl 732 can also be two separate components bolted or joined to each other.

[0101] The RF bias housing arm 734 includes one or more hollow passages for passing RF power and equipment such as gas coolant, liquid coolant, RF energy, cables for lift pin control, electrical monitoring and actuation signals, etc. from the outside of the vacuum chamber 702 to the inside of the vacuum chamber 702 in the space behind the lower electrode 706. The RF supply conduit 722 is insulated from the RF bias housing arm 734, and the RF bias housing arm 734 provides a feedback path for RF power to the RF power supply 720. The equipment conduit 740 provides a passage for equipment components. Further details of the equipment components are not shown here for the sake of simplicity of description. The gap 710 is preferably surrounded by a confinement ring assembly or a shroud (not shown). The interior of the vacuum chamber 702 is maintained at a low pressure by connecting it to a vacuum pump through a vacuum portal 780.

[0102] The conduit support plate 738 is attached to the actuating mechanism 742. The actuating mechanism 742, such as a servo motor or a stepping motor, is attached to the vertical linear bearing 744 by, for example, a screw gear 746 such as a ball screw and a motor for rotating the ball screw. During operation to adjust the size of the gap 710, the actuating mechanism 742 moves along the vertical linear bearing 744. FIG. 7A shows the arrangement when the actuating mechanism 742 is in a high position on the linear bearing 744, resulting in a small gap 710a. FIG. 7B shows the arrangement when the actuating mechanism 742 is in an intermediate position on the linear bearing 744. As shown, the lower electrode 706, the RF bias housing 730, the conduit support plate 738, and the RF power supply 720 all move downward relative to the chamber housing 704 and the upper electrode 708, resulting in a medium-sized gap 710b.

[0103] FIG. 7C shows a large gap 710c when the actuating mechanism 742 is in a low position on the linear bearing. Preferably, the upper and lower electrodes 708, 706 remain coaxial during gap adjustment, and the opposing surfaces of the upper and lower electrodes across the gap remain parallel.

[0104] This embodiment enables adjustment of the gap 710 between the lower and upper electrodes 706, 708 in the CCP chamber 702 during a multi-step process recipe (such as BARC, HARC, and STRIP) to maintain uniform etching across a large-diameter substrate such as a 300 mm wafer or a flat panel display. In particular, this chamber relates to a mechanical arrangement that enables linear movement to provide an adjustable gap between the lower and upper electrodes 706, 708.

[0105] FIG. 7A shows a laterally deflected bellows 750 sealed at the proximal end to the conduit support plate 738 and at the distal end to the stepped flange 728 of the chamber wall plate 718. The inner diameter of the stepped flange defines an opening 712 in the chamber wall plate 718 through which the RF bias housing arm 734 passes. The distal end of the bellows 750 is clamped by a clamp ring 752.

[0106] The laterally deflected bellows 750 provides a vacuum seal while allowing for vertical movement of the RF bias housing 730, the conduit support plate 738, and the actuating mechanism 742. The RF bias housing 730, the conduit support plate 738, and the actuating mechanism 742 can be referred to as a cantilever assembly. Preferably, the RF power supply 720 moves with the cantilever assembly and can be attached to the conduit support plate 738. FIG. 7B shows the bellows 750 in a neutral position when the cantilever assembly is in an intermediate position. FIG. 7C shows the laterally deflected bellows 750 when the cantilever assembly is in a lower position.

[0107] A labyrinth seal 748 provides a particle barrier between the bellows 750 and the interior of the plasma processing chamber housing 704. A fixed shield 756 is immovably attached to the inner wall of the chamber housing 704 at the chamber wall plate 718 such that the movable shield plate 758 provides a labyrinth groove 760 (slot) for vertical movement corresponding to the vertical movement of the cantilever assembly. The outer portion of the movable shield plate 758 remains within the slot at all vertical positions of the lower electrode 706.

[0108] In the illustrated embodiment, the labyrinth seal 748 includes a fixed shield 756 attached to the inner surface of the chamber wall plate 718 around the opening 712 in the chamber wall plate 718 that defines the labyrinth groove 760. A movable shield plate 758 is attached and extends radially from the RF bias housing arm 734, and the arm 734 passes through the opening 712 in the chamber wall plate 718. The movable shield plate 758 extends into the labyrinth groove 760, is spaced from the fixed shield 756 by a first gap, and is spaced from the inner surface of the chamber wall plate 718 by a second gap, allowing the cantilever assembly to move vertically. The labyrinth seal 748 blocks particles peeled off from the bellows 750 from moving into the interior 705 of the vacuum chamber and blocks radicals from the process gas plasma from moving to the bellows 750. Radicals that enter the bellows 750 form deposits, and then the deposits may be peeled off.

[0109] FIG. 7A shows the movable shield plate 758 at a higher position within the labyrinth groove 760 above the RF bias housing arm 734 when the cantilever assembly is in the high position (small gap 710a). FIG. 7C shows the movable shield plate 758 at a lower position within the labyrinth groove 760 above the RF bias housing arm 734 when the cantilever assembly is in the low position (large gap 710c). FIG. 7B shows the movable shield plate 758 in a neutral or intermediate position within the labyrinth groove 760 when the cantilever assembly is in the intermediate position (medium gap 710b). The labyrinth seal 748 is shown as symmetric with respect to the RF bias housing arm 734, but in other embodiments, the labyrinth seal 748 may be asymmetric with respect to the RF bias arm 734.

[0110] In certain embodiments, different types of etching reactors can be used, such as those having alternative or additional plasma generators for forming different types of plasmas. In some cases, inductively coupled plasmas may be used. The substrate may be directly exposed to the plasma, or the plasma may be generated remote from the substrate. Exemplary etching apparatuses that can be used in some cases include products from the Flex® product family, the Kiyo® product family, and the Versys® product family, each available from Lam Research Corporation of Fremont, California.

[0111] FIG. 8 schematically shows a cross-sectional view of an inductively coupled plasma etching apparatus 800 according to certain embodiments of the present specification. For example, such an apparatus can be used to etch any one or more of the layers described herein, including but not limited to the upper and lower layers of a multilayer hard mask, as well as organic planarization layers and other layers described in connection with FIGS. 2A-2H and FIGS. 3A-3E. As described above, for a particular application, other types of etching reactors having different or additional types of plasma generators can be used as desired. The inductively coupled plasma etching apparatus 800 includes an integrated etching chamber structurally defined by a chamber wall 801 and a window 811. The chamber wall 801 can be fabricated from stainless steel or aluminum. The window 811 can be fabricated from quartz or other dielectric material. An optional internal plasma grid 850 divides the integrated etching chamber into an upper subchamber 802 and a lower subchamber 803. The plasma grid 850 can include a single grid or multiple individual grids. In many embodiments, the plasma grid 850 can be removed, thereby utilizing the chamber space consisting of subchambers 802 and 803.

[0112] The chuck 817 is disposed within the lower subchamber 803 near the inner surface of the bottom. The chuck 817 is configured to receive and hold the semiconductor wafer 819 on which the etching process is performed. The chuck 817 can be an electrostatic chuck for supporting the wafer 819 if present. In some embodiments, an edge ring (not shown) surrounds the chuck 817 and has an upper surface that is substantially planar with the upper surface of the wafer 819 if present on top of the chuck 817. The chuck 817 also includes electrostatic electrodes for chucking and de-chucking the wafer. For this purpose, a filter and a DC clamp power supply (not shown) may be provided. Other control systems for lifting the wafer 819 from the chuck 817 may also be provided. The chuck 817 can be charged using the RF power supply 823. The RF power supply 823 is connected to the matching circuit 821 through the connection portion 827. The matching circuit 821 is connected to the chuck 817 through the connection portion 825. In this way, the RF power supply 823 is connected to the chuck 817.

[0113] The coil 833 is disposed above the window 811. The coil 833 is made of a conductive material and includes at least one complete turn. The exemplary coil 833 shown in FIG. 8 includes three turns. The cross-section of the coil 833 is indicated by symbols, where the coil with an "X" rotates and extends within the page, while the coil with a "●" rotates and extends out of the page. The RF power supply 841 is configured to supply RF power to the coil 833. Generally, the RF power supply 841 is connected to the matching circuit 839 through the connection portion 845. The matching circuit 839 is connected to the coil 833 through the connection portion 843. In this way, the RF power supply 841 is connected to the coil 833. An optional Faraday shield 849 is disposed between the coil 833 and the window 811. The Faraday shield 849 can be maintained at a spaced-apart relationship with respect to the coil 833. The Faraday shield 849 is disposed immediately above the window 811. The coil 833, the Faraday shield 849, and the window 811 are each configured to be substantially parallel to each other. The Faraday shield can prevent metals or other species from depositing on the dielectric window of the process chamber.

[0114] The process gas can be supplied through a main injection port 860 arranged in the upper chamber and / or through a side injection port 870, which may also be referred to as an STG. Using a vacuum pump, for example, a single-stage or two-stage mechanical dry pump and / or a turbo molecular pump 840, Etching the process gas is drawn out of the chamber, and during the plasma treatment operation, by using a closed-loop control flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown) Etching chamber the pressure inside can be maintained.

[0115] During the operation of the device, one or more reactant gases can be supplied through the injection ports 860 and / or 870. In certain embodiments, the gas can be supplied only through the main injection port 860 or only through the side injection port 870. In some cases, the injection port can be replaced with a showerhead. The Faraday shield 849 and / or an optional grid 850 can include internal channels and holes that enable the feeding of the process gas into the chamber. Either or both of the Faraday shield 849 and the optional grid 850 may function as a showerhead for feeding the process gas.

[0116] Radio frequency power is supplied from an RF power source 841 to a coil 833 such that an RF current flows through the coil 833. The RF current flowing through the coil 833 generates an electromagnetic field around the coil 833. The electromagnetic field generates an induced current within the upper sub-chamber 802. Through the physical and chemical interactions of various generated ions and radicals with the wafer 819, the features of the wafer are selectively etched.

[0117] When the plasma grid 850 is used such that both the upper sub-chamber 802 and the lower sub-chamber 803 are present, the induced current acts on the gas present in the upper sub-chamber 802 to generate an electron-ion plasma in the upper sub-chamber 802. The optional internal plasma grid 850, if present, can act to limit the number of hot electrons in the lower sub-chamber 803. In some embodiments, the device is designed and operated such that the plasma present in the lower sub-chamber 803 is an ion-ion plasma. In other embodiments, the device may be designed and operated such that the plasma present in the lower sub-chamber 803 is an electron-ion plasma.

[0118] Volatile etching by-products can be removed from the lower sub-chamber 803 through the port 822. The chuck 817 disclosed herein can operate at a high temperature in the range of about 30 °C to about 250 °C. In some cases, the chuck 817 can also operate at a lower temperature, such as when the chuck 817 is actively cooled. In such cases, the chuck 817 can operate at a substantially lower temperature as desired. The temperature depends on the etching process operation and the specific recipe. In some embodiments, the chamber 801 can operate at a pressure in the range of about 1 mTorr to about 95 mTorr. In certain embodiments, the pressure can be higher.

[0119] Apparatus 800 When installed in a clean room or a fabrication facility, it may be coupled to a facility (not shown). The facility includes piping that provides process gas, vacuum, temperature control, and environmental particle control. These facilities, when installed in the intended fabrication facility, Apparatus 800 are coupled to. In addition, Apparatus 800 can be coupled to a transfer chamber that allows a robot to use typical automated operations to move semiconductor wafers Apparatus 800 in and out.

[0120] In some embodiments, a system controller 830 (which may include one or more physical or logical controllers) controls some or all of the operations of the etching chamber. The system controller 830 can include one or more memory devices and one or more processors. The processor can include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the system controller 830 or provided via a network. In certain embodiments, the system controller 830 executes system control software.

[0121] In some cases, the system controller 830 controls the gas concentration, the movement of the wafer, and / or the power supplied to the coil 833 and / or the electrostatic chuck 817. The system controller 830 can control the gas concentration, for example, by opening and closing associated valves to generate one or more inlet gas flows that provide reactants at appropriate concentrations. The movement of the wafer can be controlled, for example, by instructing the wafer positioning system to move as desired. The power supplied to the coil 833 and / or the chuck 817 can be controlled to provide a specific RF power level. Similarly, when the internal grid 850 is used, the RF power applied to the grid can be adjusted by the system controller 830.

[0122] The system controller 830 can control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, etc. reach specific thresholds), the timing of operations (e.g., opening a valve at a specific time during the process), or instructions received from a user. Exemplary controllers are further described below.

[0123] FIG. 9 illustrates a semiconductor process cluster architecture with various modules interfacing with a vacuum transfer module 938 (VTM). The arrangement of transfer modules for "transferring" wafers between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. The airlock 930, also known as a load lock or transfer module, is shown in the VTM 938 with four processing modules 920a - 920d that can be individually optimized for various fabrication processes. By way of example, the processing modules 920a - 920d can be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processes. One or more of the substrate etching processing modules (any of 920a - 920d) can be implemented as disclosed herein. The airlock 930 and the process modules 920 are sometimes referred to as "stations". Each station has a facet 936 that interfaces the station to the VTM 938. Inside each facet, sensors 1 - 18 are used to detect the passage of the wafer 926 as it moves between the respective stations.

[0124] The robot 922 transfers the wafer 926 between stations. In one embodiment, the robot 922 can have one arm, and in another embodiment, the robot 922 can have two arms, each arm having an end effector 924 for picking up wafers such as the transfer wafer 926. The front - end robot 932 within the atmospheric transfer module (ATM) 940 can be used to transfer the wafer 926 from the front - opening unified pod (FOUP) 934 within the cassette or load - port module (LPM) 942 to the airlock 930. The module center 928 within the process module 920 is a place for placing the wafer 926. The aligner 944 within the ATM 940 can be used to align the wafers.

[0125] In an exemplary processing method, a wafer is placed in one of the FOUPs 934 within the LPM 942. The front-end robot 932 transfers the wafer from the FOUP 934 to the aligner 944, whereby the wafer 926 can be properly centered before being etched or processed. After being aligned, the wafer 926 is moved into the airlock 930 by the front-end robot 932. Since the airlock module has the ability to match the environment between the ATM and the VTM, the wafer 926 can move between the two pressure environments without being damaged. From the airlock module 930, the wafer 926 is moved by the robot 922 through the VTM 938 to one of the process modules 920a - 920d. To accomplish this wafer transfer, the robot 922 uses the end effector 924 on each of its arms. When the wafer 926 is processed, it is moved by the robot 922 from the process modules 920a - 920d to the airlock module 930. From here, the wafer 926 can be moved by the front-end robot 932 to one of the FOUPs 934 or the aligner 944.

[0126] Note that the computer controlling the wafer movement may be local to the cluster architecture, or located outside the cluster architecture within the manufacturing floor or remotely, and connected to the cluster architecture via a network.

[0127] In some embodiments, the controller is part of a system, and such a system may be part of the examples described above. Such a system can include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after processing of a semiconductor wafer or substrate. Such electronics may be referred to as a "controller" and may control various components or sub-components of one or more systems. The controller may be programmed to control any of the processes disclosed herein, depending on the processing requirements and / or the type of system. Such processes include feeding of process gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting in some systems, RF matching circuit setting, frequency setting, flow rate setting, fluid feed setting, position and motion setting, loading and unloading of wafers to and from tools, and loading and unloading of wafers to and from other transfer tools and / or load locks connected or interfaced with a particular system.

[0128] In a broad sense, the controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive commands, issue commands, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, i.e., a microcontroller that executes program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that may define operating parameters for executing a particular process on or for a semiconductor wafer or for a system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0129] In some embodiments, the controller may be part of a computer that is integrated or coupled with the system, or otherwise network-connected to the system, or coupled to such a computer, or a combination thereof. For example, the controller may be within the "cloud", or may be all or part of a fab host computer system. This enables remote access to wafer processing. The computer enables remote access to the system, monitors the current progress of the fabrication operation, considers the history of past fabrication operations, considers trends or performance criteria from multiple fabrication operations, changes the parameters of the current process, sets the process steps following the current process, or may start a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data. Such data specifies parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the controller is configured to interact with or control. Thus, as described above, the controller may be distributed, for example, by comprising one or more individual controllers that are network-connected to each other and cooperate towards a common purpose (such as the processes and controls described herein). Examples of distributed controllers for such purposes include one or more integrated circuits on a chamber that communicate with one or more integrated circuits that are remotely located (e.g., at the platform level or as part of a remote computer) and combined to control the process in the chamber.

[0130] Exemplary systems can include, but are not limited to, a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be related to or used in the fabrication and / or manufacturing of semiconductor wafers.

[0131] As described above, depending on one or more process steps performed by a tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, a main computer, another controller, or a tool used for material transport to load and unload a wafer container to and from a tool location and / or load port within a semiconductor manufacturing factory.

[0132] Conclusion Although the foregoing embodiments have been described in some detail for purposes of clear understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Note that there are many other ways to implement the processes, systems, and apparatuses of this embodiment. Therefore, this embodiment should be regarded as illustrative and not restrictive, and those embodiments should not be limited to the details described herein. The present invention can also be implemented, for example, in the following aspects. Application Example 1: A method for processing a substrate, the method comprising: a. Receiving a substrate, wherein the substrate comprises: i. A base material; ii. An organic planarization layer disposed on the base material; iii. A multilayer hard mask disposed on the organic planarization layer, the multilayer hard mask comprising: 1. A lower layer containing an inorganic dielectric silicon-containing material, and 2. An upper layer containing a metal oxide, a metal nitride, or a metal oxynitride a multilayer hard mask; iv. A layer of extreme ultraviolet (EUV) photoresist disposed on the multilayer hard mask, the layer of EUV photoresist being patterned to include a concave feature, and a portion of the upper layer of the multilayer hard mask being exposed within the concave feature, a layer of EUV photoresist; including receiving the substrate; b. Etching the exposed portion of the upper layer of the multilayer hard mask, thereby expanding the concave feature into the upper layer of the multilayer hard mask and exposing a portion of the lower layer of the multilayer hard mask; c. Etching the exposed portion of the lower layer of the multilayer hard mask, thereby expanding the concave feature into the lower layer of the multilayer hard mask and exposing a portion of the organic planarization layer; d. Etching the exposed portion of the organic planarization layer, thereby expanding the concave feature into the organic planarization layer and exposing a portion of the base material; e. Etching the exposed portion of the base material, thereby expanding the concave feature into the base material including the method. Application Example 2: The method of Application Example 1, wherein the lower layer of the multilayer hard mask comprises a material selected from the group consisting of amorphous silicon, silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, silicon oxynitride, and combinations thereof. Application Example 3: The method of Application Example 1, wherein the lower layer of the multilayer hard mask has a thickness of about 10 nm or less. ​ ​ ​ Application Example 4: The method of Application Example 1, wherein the metal oxide, metal nitride, or metal oxynitride of the upper layer of the multilayer hard mask contains a metal selected from the group consisting of titanium, tantalum, hafnium, tin, ruthenium, and combinations thereof. Application Example 5: The method of Application Example 1, wherein the upper layer of the multilayer hard mask has a thickness of about 10 nm or less. Application Example 6: The method of Application Example 1, wherein prior to (b), the substrate is exposed to a first plasma to remove excess EUV photoresist within the concave feature is further included. Application Example 7: The method of Application Example 1, wherein etching the exposed portion of the upper layer of the multilayer hard mask includes exposing the substrate to a second reactant, and the second reactant includes a chlorine-containing etchant and / or a bromine-containing reactant. Application Example 8: The method of Application Example 1, wherein etching the exposed portion of the upper layer of the multilayer hard mask includes exposing the substrate to a second plasma. Application Example 9: The method of Application Example 1, wherein etching the exposed portion of the lower layer of the multilayer hard mask includes exposing the substrate to a third reactant, and the third reactant includes a fluorine-containing reactant and / or a chlorine-containing reactant. Application Example 10: The method of Application Example 1, wherein etching the exposed portion of the lower layer of the multilayer hard mask includes exposing the substrate to a third plasma. Application Example 11: The method according to any one of Application Examples 1 to 10, wherein both the upper layer and the lower layer of the multilayer hard mask each have a thickness of about 10 nm or less. Application Example 12: The method according to any one of Application Examples 1 to 10, wherein the underlayer material includes an oxide layer disposed under the organic planarization layer, a titanium nitride layer or a titanium oxynitride layer disposed under the oxide layer, and a silicon nitride layer disposed under the titanium nitride layer or the titanium oxynitride layer, and etching the exposed portion of the underlayer material extends the concave feature into the oxide layer and into the titanium nitride layer or the titanium oxynitride layer, and at least the etching in (b) and (c) is driven by an inductively coupled plasma. Application Example 13: The method of Application Example 12, wherein A method further comprising removing the organic planarization layer after the concave feature has extended into the oxide layer and the titanium nitride layer or titanium oxynitride layer. Application Example 14: A method according to any one of Application Examples 1 to 10, wherein the underlying material includes a sacrificial hard mask layer disposed under the organic planarization layer, an ultra-low k dielectric layer disposed under the sacrificial hard mask layer, and a cap layer disposed under the ultra-low k dielectric layer, and etching the exposed portion of the underlying material extends the concave feature into the sacrificial hard mask layer, the ultra-low k dielectric layer, and the cap layer, and at least the etching in (b) and (c) is driven by capacitively coupled plasma. Application Example 15: A method according to Application Example 14, wherein the sacrificial hard mask layer contains silicon nitride. Application Example 16: A method according to Application Example 14, further comprising removing the organic planarization layer after the concave feature has extended into the sacrificial hard mask layer, the ultra-low k dielectric layer, and the cap layer. Application Example 17: A method of processing a substrate, the method comprising: a. receiving a substrate having an underlying material thereon; b. depositing a lower layer of a multilayer hard mask on the underlying material, wherein the lower layer of the multilayer hard mask contains an inorganic dielectric silicon-containing material; c. depositing an upper layer of the multilayer hard mask on the underlying material, wherein the upper layer of the multilayer hard mask contains a metal oxide, a metal nitride, or a metal oxynitride; d. depositing an extreme ultraviolet photoresist on the upper layer of the multilayer hard mask and including. Application Example 18: A method according to Application Example 17, wherein each of the lower layer and the upper layer of the multilayer hard mask has a thickness of about 10 nm or less. Application Example 19: A method according to Application Example 17 or 18, wherein each of the lower layer and the upper layer of the multilayer hard mask is deposited by either atomic layer deposition or plasma-enhanced atomic layer deposition. Application Example 20: An apparatus for processing a substrate, the apparatus comprising: a. a reaction chamber; b. a substrate support disposed within the reaction chamber; c. a plasma generator configured to generate plasma within the reaction chamber; d. one or more inlets to the reaction chamber e. A controller having at least one processor and a memory, wherein the at least one processor and the memory are communicatively connected to each other, and the memory stores computer-executable instructions for controlling the at least one processor to execute any one of the methods of Application Examples 1 to 19 A device comprising the above Application Example 21: A device for processing a substrate, the device comprising a. A reaction chamber b. A substrate support disposed within the reaction chamber c. A plasma generator configured to generate plasma within the reaction chamber d. One or more inlets to the reaction chamber e. A controller having at least one processor and a memory, wherein the at least one processor and the memory are communicatively connected to each other, and the memory controls the at least one processor to i. Receive the substrate within the reaction chamber, the substrate comprising 1. A base material 2. An organic planarization layer disposed on the base material 3. A multilayer hard mask disposed on the organic planarization layer, the multilayer hard mask comprising a. A lower layer containing an inorganic dielectric silicon-containing material, and b. An upper layer containing a metal oxide, a metal nitride, or a metal oxynitride A multilayer hard mask including the above 4. A layer of extreme ultraviolet (EUV) photoresist disposed on the multilayer hard mask, the layer of EUV photoresist being patterned to include concave features, and a portion of the upper layer of the multilayer hard mask being exposed within the concave features, a layer of EUV photoresist Including receiving the substrate as described above ii. Etch the exposed portion of the upper layer of the multilayer hard mask, thereby expanding the concave features into the upper layer of the multilayer hard mask and exposing a portion of the lower layer of the multilayer hard mask iii. Etch the exposed portion of the lower layer of the multilayer hard mask, thereby expanding the concave features into the lower layer of the multilayer hard mask and exposing a portion of the organic planarization layer iv. Etch the exposed portion of the organic planarization layer, thereby expanding the concave features into the organic planarization layer and exposing a portion of the base material v. etching the exposed portion of the underlying material, thereby expanding the concave feature into the underlying material a controller storing computer-executable instructions for causing the execution thereof An apparatus comprising. Application Example 22: A system for processing a substrate, the system comprising: a. a first reaction chamber configured to perform deposition; b. a second reaction chamber configured to perform etching; c. a controller having at least one processor and a memory, the at least one processor and the memory being communicatively connected to each other, the memory controlling the at least one processor to i. receive a substrate into the first reaction chamber; ii. depositing a lower layer of a multilayer hard mask on the substrate, the lower layer of the multilayer hard mask comprising an inorganic dielectric silicon-containing material; iii. depositing an upper layer of the multilayer hard mask on the lower layer of the multilayer hard mask, the upper layer of the multilayer hard mask comprising a metal oxide, a metal nitride, or a metal oxynitride; iv. depositing a layer of extreme ultraviolet photoresist on the upper layer of the multilayer hard mask; v. patterning the layer of extreme ultraviolet photoresist to define a concave feature, thereby exposing a portion of the upper layer of the multilayer hard mask; vi. transferring the substrate to the second reaction chamber; vii. etching the exposed portion of the upper layer of the multilayer hard mask, thereby expanding the concave feature into the upper layer of the multilayer hard mask and exposing a portion of the lower layer of the multilayer hard mask; viii. etching the exposed portion of the lower layer of the multilayer hard mask, thereby expanding the concave feature into the lower layer of the multilayer hard mask and exposing a portion of the substrate disposed under the lower layer of the multilayer hard mask a controller storing computer-executable instructions for causing the execution thereof A system comprising. Application Example 23: The system of Application Example 22, wherein The second reaction chamber includes an inductively coupled plasma generator, and the memory controls the at least one processor to generate a first inductively coupled plasma and etch the exposed portion of the upper layer of the multilayer hard mask in (vii), and to generate a second inductively coupled plasma and etch the exposed portion of the lower layer of the multilayer hard mask in (viii), and stores computer-executable instructions for causing the operations to be performed, a system. Application Example 24: The system of Application Example 22, wherein the second reaction chamber includes a capacitively coupled plasma generator, and the memory controls the at least one processor to generate a first capacitively coupled plasma and etch the exposed portion of the upper layer of the multilayer hard mask in (vii), and to generate a second capacitively coupled plasma and etch the exposed portion of the lower layer of the multilayer hard mask in (viii), and stores computer-executable instructions for causing the operations to be performed, a system.

Claims

1. A method of processing a substrate, the method comprising: a. Receiving a substrate, wherein the substrate comprises: i. A base material; ii. An organic planarization layer disposed on the base material; iii. A multilayer hard mask disposed on the organic planarization layer, the multilayer hard mask comprising:

1. A lower layer comprising an inorganic dielectric silicon-containing material; and 2. An upper layer comprising a metal oxide, a metal nitride, or a metal oxynitride; iv. A layer of extreme ultraviolet (EUV) photoresist disposed on the multilayer hard mask, the layer of EUV photoresist being patterned to include concave features, and portions of the upper layer of the multilayer hard mask being exposed within the concave features; Receiving the substrate; b. Etching the exposed portions of the upper layer of the multilayer hard mask, thereby expanding the concave features into the upper layer of the multilayer hard mask and exposing portions of the lower layer of the multilayer hard mask; c. Etching the exposed portions of the lower layer of the multilayer hard mask, thereby expanding the concave features into the lower layer of the multilayer hard mask and exposing portions of the organic planarization layer; d. Etching the exposed portions of the organic planarization layer, thereby expanding the concave features into the organic planarization layer and exposing portions of the base material; e. Etching the exposed portions of the base material, thereby expanding the concave features into the base material; Further comprising exposing the substrate to a first plasma prior to (b) to remove excess EUV photoresist within the concave features. A method.

2. The method of claim 1, wherein the lower layer of the multilayer hard mask comprises a material selected from the group consisting of amorphous silicon, silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, silicon oxynitride, and combinations thereof.

3. The method of claim 1, wherein the lower layer of the multilayer hard mask has a thickness of 10 nm or less.

4. The method of claim 1, ​ ​ ​ ​ ​ The method wherein the metal oxide, metal nitride, or metal oxynitride of the upper layer of the multilayer hard mask contains a metal selected from the group consisting of titanium, tantalum, hafnium, tin, ruthenium, and combinations thereof.

5. The method according to claim 1, wherein the upper layer of the multilayer hard mask has a thickness of 10 nm or less.

6. The method according to claim 1, wherein etching the exposed portion of the upper layer of the multilayer hard mask includes exposing the substrate to a second reactant, and the second reactant includes a chlorine-containing etchant and / or a bromine-containing reactant.

7. The method according to claim 1, wherein etching the exposed portion of the upper layer of the multilayer hard mask includes exposing the substrate to a second plasma.

8. The method according to claim 1, wherein etching the exposed portion of the lower layer of the multilayer hard mask includes exposing the substrate to a third reactant, and the third reactant includes a fluorine-containing reactant and / or a chlorine-containing reactant.

9. The method according to claim 1, wherein etching the exposed portion of the lower layer of the multilayer hard mask includes exposing the substrate to a third plasma.

10. The method according to any one of claims 1 to 9, wherein both the upper layer and the lower layer of the multilayer hard mask each have a thickness of 10 nm or less.

11. The method according to any one of claims 1 to 9, wherein the underlying material includes an oxide layer disposed under the organic planarization layer, a titanium nitride layer or a titanium oxynitride layer disposed under the oxide layer, and a silicon nitride layer disposed under the titanium nitride layer or the titanium oxynitride layer, and etching the exposed portion of the underlying material expands the concave feature into the oxide layer and into the titanium nitride layer or the titanium oxynitride layer, and at least the etching in (b) and (c) is driven by inductively coupled plasma.

12. The method according to claim 11, further comprising removing the organic planarization layer after the concave feature has been expanded into the oxide layer and the titanium nitride layer or the titanium oxynitride layer.

13. The method according to any one of claims 1 to 9, The underlying material includes a sacrificial hard mask layer disposed under the organic planarization layer, an ultra-low-k dielectric layer disposed under the sacrificial hard mask layer, and a cap layer disposed under the ultra-low-k dielectric layer. Etching the exposed portion of the underlying material extends the concave feature into the sacrificial hard mask layer, the ultra-low-k dielectric layer, and the cap layer. At least the etching in (b) and (c) is driven by capacitively coupled plasma. Method.

14. The method according to claim 13, wherein the sacrificial hard mask layer contains silicon nitride. Method.

15. The method according to claim 13, further comprising removing the organic planarization layer after the concave feature has been extended into the sacrificial hard mask layer, the ultra-low-k dielectric layer, and the cap layer. Method.

16. A method of processing a substrate, the method comprising: a. Receiving a substrate having an underlying material thereon; b. Depositing a lower layer of a multilayer hard mask on the underlying material, wherein the lower layer of the multilayer hard mask contains an inorganic dielectric silicon-containing material; c. Depositing an upper layer of the multilayer hard mask on the underlying material, wherein the upper layer of the multilayer hard mask contains a metal oxide, a metal nitride, or a metal oxynitride; d. Depositing an extreme ultraviolet (EUV) photoresist on the upper layer of the multilayer hard mask, wherein the layer of EUV photoresist is patterned to include concave features, and portions of the upper layer of the multilayer hard mask are exposed within the concave features; and exposing the substrate to a first plasma to remove excess EUV photoresist within the concave features. Method.

17. The method according to claim 16, wherein each of the lower layer and the upper layer of the multilayer hard mask has a thickness of 10 nm or less. Method.

18. The method according to claim 16 or 17, wherein each of the lower layer and the upper layer of the multilayer hard mask is deposited by either atomic layer deposition or plasma-enhanced atomic layer deposition. Method.

19. An apparatus for processing a substrate, the apparatus comprising: a. A reaction chamber; b. A substrate support disposed within the reaction chamber; c. A plasma generator configured to generate plasma within the reaction chamber; d. one or more inlets to the reaction chamber, e. a controller having at least one processor and a memory, the at least one processor and the memory being communicatively connected to each other, the memory storing computer-executable instructions for controlling the at least one processor to execute any of the methods of claims 1 to 18 A device comprising. **Claim 20** A device for processing a substrate, the device comprising a. a reaction chamber, b. a substrate support disposed within the reaction chamber, c. a plasma generator configured to generate plasma within the reaction chamber, d. one or more inlets to the reaction chamber, e. a controller having at least one processor and a memory, the at least one processor and the memory being communicatively connected to each other, the memory controlling the at least one processor to i. receive the substrate within the reaction chamber, the substrate comprising 1. a base material, 2. an organic planarization layer disposed on the base material, 3. a multilayer hard mask disposed on the organic planarization layer, the multilayer hard mask comprising a. a lower layer comprising an inorganic dielectric silicon-containing material, and b. an upper layer comprising a metal oxide, a metal nitride, or a metal oxynitride a multilayer hard mask including, 4. a layer of extreme ultraviolet (EUV) photoresist disposed on the multilayer hard mask, the layer of EUV photoresist being patterned to include concave features, portions of the upper layer of the multilayer hard mask being exposed within the concave features, a layer of EUV photoresist receiving the substrate including, ii. etching the exposed portion of the upper layer of the multilayer hard mask, thereby expanding the concave features into the upper layer of the multilayer hard mask and exposing a portion of the lower layer of the multilayer hard mask, iii. etching the exposed portion of the lower layer of the multilayer hard mask, thereby expanding the concave features into the lower layer of the multilayer hard mask and exposing a portion of the organic planarization layer, iv. etching the exposed portion of the organic planarization layer, thereby expanding the concave features into the organic planarization layer and exposing a portion of the base material v. etching the exposed portion of the underlying material, thereby expanding the concave feature into the underlying material a controller storing computer-executable instructions for causing execution thereof comprising the memory controls the at least one processor to prior to (ii) above, expose the substrate to a first plasma to remove excess EUV photoresist within the concave feature a device further storing computer-executable instructions for causing execution thereof **Claim 21** A system for processing a substrate, the system comprising: a. a first reaction chamber configured to perform deposition; b. a second reaction chamber configured to perform etching; c. a controller having at least one processor and a memory, the at least one processor and the memory being communicatively connected to each other, the memory controlling the at least one processor to i. receive a substrate into the first reaction chamber; ii. deposit a lower layer of a multilayer hard mask on the substrate, the lower layer of the multilayer hard mask comprising an inorganic dielectric silicon-containing material; iii. deposit an upper layer of the multilayer hard mask on the lower layer of the multilayer hard mask, the upper layer of the multilayer hard mask comprising a metal oxide, a metal nitride, or a metal oxynitride; iv. deposit a layer of extreme ultraviolet photoresist on the upper layer of the multilayer hard mask; v. pattern the layer of extreme ultraviolet photoresist to define a concave feature, thereby exposing a portion of the upper layer of the multilayer hard mask; vi. transfer the substrate to the second reaction chamber; vii. etch the exposed portion of the upper layer of the multilayer hard mask, thereby expanding the concave feature into the upper layer of the multilayer hard mask and exposing a portion of the lower layer of the multilayer hard mask; viii. etch the exposed portion of the lower layer of the multilayer hard mask, thereby expanding the concave feature into the lower layer of the multilayer hard mask and exposing a portion of the substrate disposed under the lower layer of the multilayer hard mask a controller storing computer-executable instructions for causing execution thereof comprising The memory controls the at least one processor to prior to (vii), expose the substrate to a first plasma to remove excess EUV photoresist within the concave feature and stores computer-executable instructions for causing the same to be executed, a system. **Claim 22** The system according to claim 21, wherein the second reaction chamber includes an inductively coupled plasma generator, and the memory controls the at least one processor to generate a first inductively coupled plasma and etch the exposed portion of the upper layer of the multilayer hard mask in (vii), and to generate a second inductively coupled plasma and etch the exposed portion of the lower layer of the multilayer hard mask in (viii), and stores computer-executable instructions for causing the same to be executed, a system. **Claim 23** The system according to claim 21, wherein the second reaction chamber includes a capacitively coupled plasma generator, and the memory controls the at least one processor to generate a first capacitively coupled plasma and etch the exposed portion of the upper layer of the multilayer hard mask in (vii), and to generate a second capacitively coupled plasma and etch the exposed portion of the lower layer of the multilayer hard mask in (viii), and stores computer-executable instructions for causing the same to be executed, a system.

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