Multi-zone radio frequency transistor amplifier

Abstract

The RF transistor amplifier includes a III-nitride based semiconductor layer structure and an RF transistor amplifier die having a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal, each on a top surface of the semiconductor layer structure; an interconnect structure on the top surface of the RF transistor amplifier die; and coupling elements between the RF transistor amplifier die and the interconnect structure that electrically connect the gate terminals, the drain terminals, and the source terminals to the interconnect structure.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 16 / 911,757, filed Jun. 25, 2020, the entire content of which is hereby incorporated by reference as if fully set forth herein.

[0002] The present invention relates to microelectronic devices, and more particularly, to radio frequency (“RF”) transistor amplifiers.

Background Art

[0003] Electrical circuits that operate at high frequencies such as the R-band (0.5 - 1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12 - 18 GHz), K-band (18 - 27 GHz), Ka-band (27 - 40 GHz), and V-band (40 - 75 GHz) and require high power handling capabilities are becoming more widespread. In particular, there is currently a high demand for RF transistor amplifiers used to amplify RF signals at frequencies of 500 MHz or higher (including microwave frequencies). These RF transistor amplifiers often need to exhibit high reliability, good linearity, and handle high output levels.

[0004] Most RF transistor amplifiers are implemented in silicon or wide bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. As used herein, the term “group III nitride” refers to those semiconductor compounds formed between nitrogen and elements in group III of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). This term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have an empirical formula in which 1 mole of nitrogen is combined with a total of 1 mole of group III elements.

[0005] Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal oxide semiconductor ("LDMOS") transistors. Silicon LDMOS RF transistor amplifiers can exhibit a high level of linearity and can be manufactured relatively inexpensively. Group III nitride-based RF transistor amplifiers are typically implemented as high electron mobility transistors ("HEMTs") and are used mainly in applications that require high power and / or high frequency operation where LDMOS RF transistor amplifiers may have inherent performance limitations.

[0006] An RF transistor amplifier may include one or more amplification stages, and each stage is typically implemented as a transistor amplifier. To increase the output power and current handling capabilities, RF transistor amplifiers are typically implemented in a "unit cell" configuration where a number of individual "unit cell" transistors are electrically arranged in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die", or may include multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0007] RF transistor amplifiers often include matching circuits such as (1) an impedance matching circuit designed to improve the impedance match (for RF signals at the fundamental operating frequency of the amplifier) between the RF transistor amplifier die and the transmission lines connected thereto, and (2) a harmonic termination circuit designed to at least partially terminate harmonics such as second and third harmonics that may be generated during device operation. The RF transistor amplifier die as well as the impedance matching and harmonic termination circuits may be encapsulated within a package. Conductive leads may extend from the package and are used to electrically connect the RF transistor amplifier to external circuit elements such as input and output RF transmission lines and bias voltage sources.

[0008] As described above, group-III nitride-based RF transistor amplifiers are often used in high-power and / or high-frequency applications. Typically, during operation, a high level of heat is generated within a group-III nitride-based RF transistor amplifier die. If the RF transistor amplifier die becomes too hot, its performance (such as output power, efficiency, linearity, gain, etc.) may degrade and / or the RF transistor amplifier die may be damaged. Therefore, group-III nitride-based RF transistor amplifiers are typically mounted in a package that can be optimized for heat removal.

[0009] Figures 1A through 1D are various views schematically showing a conventional group-III nitride-based RF transistor amplifier die 10. In particular, FIG. 1A is a schematic plan view of the group-III nitride-based RF transistor amplifier die 10, and FIG. 1B is a cross-sectional view of the RF transistor amplifier die 10 taken along line 1B-1B of FIG. 1A. FIG. 1C is a schematic cross-sectional view taken along line 1C-1C of FIG. 1B showing the metallization on the upper surface of the semiconductor layer structure of the RF transistor amplifier die 10, and FIG. 1D is a cross-sectional view of the RF transistor amplifier die 10 taken along line 1D-1D of FIG. 1C. FIGS. 1E and 1F are schematic cross-sectional views showing two exemplary forms in which the RF transistor amplifier die 10 of FIGS. 1A through 1D is packaged to provide packaged RF transistor amplifiers 1A and 1B, respectively. It will be appreciated that FIGS. 1A through 1F (and many of the other drawings of the present application) are highly simplified views, and an actual RF transistor amplifier may include many additional unit cells as well as various circuits and elements not shown in the simplified views herein.

[0010] As shown in FIG. 1A, the RF transistor amplifier die 10 includes a gate terminal 22 and a drain terminal 24 that are exposed on the upper side of the RF transistor amplifier die 10. A first circuit element (not shown) may be connected to the gate terminal 22, for example, by a bond wire (not shown), and a second circuit element (not shown) may be connected to the drain terminal 24, for example, by a bond wire (not shown). The first circuit element may transmit, for example, an input RF signal to be amplified to the RF transistor amplifier die 10, and the second circuit element may receive the amplified RF signal output by the RF transistor amplifier die 10. A protective insulating layer or pattern 28 may cover the remainder of the upper surface of the RF transistor amplifier die 10.

[0011] Referring to FIGS. 1B - 1D, the RF transistor amplifier die 10 includes a semiconductor layer structure 30, an upper metallization structure 20, and a backside metallization structure that acts as a source terminal 26 for the RF transistor amplifier die 10.

[0012] The semiconductor layer structure 30 includes a plurality of semiconductor layers. The RF transistor amplifier die 10 may be a HEMT - based RF transistor amplifier die, and thus the semiconductor layer structure 30 may include at least a channel layer and a barrier layer. Referring to FIG. 1D, in the example shown, the semiconductor layer structure 30 includes a total of three layers, namely a growth substrate 32, a semiconductor channel layer 34 formed on the growth substrate 32, and a semiconductor barrier layer 36 formed on the channel layer 34 on the side opposite to the growth substrate 32. The growth substrate 32 may be a semiconductor or an insulating substrate (such as a SiC or sapphire substrate). Even if the growth substrate 32 is formed from a non - semiconductor material, it is considered to be part of the semiconductor layer structure 30.

[0013] Referring back to FIG. 1B, the semiconductor layer structure 30 has an upper side 12 and a lower side 14. The upper metallization structure 20 is formed on the upper side 12 of the semiconductor layer structure 30, and the source terminal 26 is formed on the lower side 14 of the semiconductor layer structure 30. The upper metallization structure 20 includes, among other things, a conductive (typically metal) gate manifold 42 and a conductive (typically metal) drain manifold 44, conductive gate and drain vias 43, 45, conductive gate and drain terminals 22, 24, and gate, drain, and source fingers 52, 54, 56 (described below). The gate manifold 42 is electrically connected to the gate terminal 22 via the gate via 43, and the drain manifold 44 is electrically connected to the drain terminal 24 via the conductive drain via 45. The gate and drain vias 43, 45 may include, for example, metal pillars formed through a dielectric material such as silicon oxide or silicon nitride.

[0014] As shown in FIG. 1C, the RF transistor amplifier die 10 includes a plurality of unit cell transistors 16, one of which is indicated by the dashed box in FIG. 1C. Each unit cell transistor 16 includes a gate finger 52, a drain finger 54, and a source finger 56. The gate, drain, and source fingers 52, 54, 56 are formed on the upper surface of the semiconductor layer structure 30 and include a part of the upper metallization structure 20. The upper metallization structure 20 further includes a gate manifold 42 and a drain manifold 44. The gate finger 52 is electrically connected to the gate manifold 42, and the drain finger 54 is electrically connected to the drain manifold 44. The source finger 56 is electrically connected to the source terminal 26 (FIG. 1B) via a plurality of conductive source vias 66 that extend through the semiconductor layer structure 30. The conductive source vias 66 may include metal-plated vias that extend completely through the semiconductor layer structure 30.

[0015] FIG. 1E is a schematic side view of a packaged group-III nitride-based RF transistor amplifier 1A including the RF transistor amplifier die 10 of FIGS. 1A-1D. As shown in FIG. 1E, the packaged RF transistor amplifier 1A includes an RF transistor amplifier die 10 and an open cavity package 70. The package 70 includes a metal gate lead 72, a metal drain lead 74, a metal submount 76, a ceramic sidewall 78, and a ceramic lid 80.

[0016] The RF transistor amplifier die 10 is mounted on the upper surface of the metal submount 76 (which may be a metal flange) in a cavity defined by the metal submount 76, the ceramic sidewall 78, and the ceramic lid 80. The source terminal 26 of the RF transistor amplifier die 10 may be in direct contact with the metal submount 76. The metal submount 76 may provide an electrical connection to the source terminal 26 and may function as a heat dissipation structure for dissipating heat generated in the RF transistor amplifier die 10. Heat is generated mainly in the upper portion of the RF transistor amplifier die 10 where a relatively high current density occurs, for example, in the channel region of the unit cell transistor 16. This heat may be transferred through the source via 66 and the semiconductor layer structure 30 to the source terminal 26 and then to the metal submount 76.

[0017] The input matching circuit 90 and / or the output matching circuit 92 may also be mounted within the package 70. These matching circuits 90, 92 match the impedance of the fundamental component of the RF signal input to or output from the RF transistor amplifier 1A to the impedance at the input or output of the harmonic termination circuit configured to ground the harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die 10, and / or the RF transistor amplifier die 10, and may be impedance matching circuits. Two or more input matching circuits 90 and / or output matching circuits 92 may be provided. As schematically shown in FIG. 1E, the input and output matching circuits 90, 92 may be mounted on the metal submount 76. The gate lead 72 may be connected to the input matching circuit 90 by one or more first bond wires 82, and the input matching circuit 90 may be connected to the gate terminal 22 of the RF transistor amplifier die 10 by one or more second bond wires 84. Similarly, the drain lead 74 may be connected to the output matching circuit 92 by one or more fourth bond wires 88, and the output matching circuit 92 may be connected to the drain terminal 24 of the RF transistor amplifier die 10 by one or more third bond wires 86. The bond wires 82, 84, 86, 88, which are inductive elements, may form part of the input and / or output matching circuits. The gate lead 72 and the drain lead 74 may extend through the ceramic sidewall 78. The interior of the package 70 may include an air-filled cavity.

[0018] Figure 1F is a schematic side view of another conventional packaged group-III nitride-based RF transistor amplifier 1B. The RF transistor amplifier 1B is different from the RF transistor amplifier 1A in that it includes a different package 70'. The package 70' includes a metal submount 76 (which acts as a metal heat sink and can be mounted as a metal slug), as well as gate and drain leads 72', 74'. The RF transistor amplifier 1B also includes a plastic overmold 78' that at least partially surrounds the RF transistor amplifier die 10, leads 72', 74', and the metal submount 76. Other components of the RF transistor amplifier 1B may be the same as the components of the same number of the RF transistor amplifier 1A, and thus, further description thereof is omitted.

SUMMARY OF THE INVENTION

MEANS FOR SOLVING THE PROBLEM

[0019] According to an embodiment of the present invention, there is provided a radio frequency transistor amplifier including: an RF transistor amplifier die having a group-III nitride-based semiconductor layer structure, a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal, each of which is on an upper surface of the semiconductor layer structure; an interconnection structure on the upper surface of the RF transistor amplifier die; and coupling elements between the RF transistor amplifier die and the interconnection structure that electrically connect the gate terminals, the drain terminals, and the source terminals to the interconnection structure.

[0020] In some embodiments, the RF transistor amplifier die may be divided into a plurality of zones, each of the zones including a plurality of unit cell transistors, and at least one of the zones can be operated independently of the others of the zones. In such embodiments, a first one of the zones may be configured to amplify an RF signal in a first frequency range, and a second one of the zones may be configured to amplify an RF signal in a second frequency range different from the first frequency range. In some embodiments, each of the zones includes its plurality of unit cell transistors, and gate fingers in a first one of the zones may have a first length, and gate fingers in a second one of the zones may have a second length different from the first length. In some embodiments, the RF amplifier is configured to transfer an RF signal to a first subset of the zones for operation in a first range of output power levels and to transfer the RF signal to a second subset of zones different from the first subset for operation in a second range of output power levels different from the first range of output power levels.

[0021] In some embodiments, the RF transistor amplifier may further include an input switching network and an output switching network configured to switch a zone among the zones to an RF transmission path between an input portion to the RF transistor amplifier and an output portion of the RF transistor amplifier. In some embodiments, at least one of the input switching network and the output switching network is provided on and / or within an interconnection structure.

[0022] In some embodiments, one of the zones includes a redundant zone, and the RF transistor amplifier further includes a switching network that can be set to switch the transmission path from a first one of the zones to the redundant zone.

[0023] In some embodiments, the unit cell transistors of the first zone among the zones may be electrically coupled in series with the unit cell transistors of the second zone among the zones.

[0024] In some embodiments, the unit cell transistors of the first zone among the zones may be configured as a preamplifier, and the unit cell transistors of the second zone among the zones may be configured as a main amplifier.

[0025] In some embodiments, the unit cell transistors of the first zone among the zones may have a configuration different from that of the unit cell transistors of the second zone among the zones, and the unit cell transistors of the first zone among the zones and the unit cell transistors of the second zone among the zones may be electrically connected in parallel.

[0026] In some embodiments, the unit cell transistors of the first zone among the zones are configured as the main amplifier of a Doherty amplifier, and the unit cell transistors of the second zone among the zones are configured as the peak amplifier of the Doherty amplifier.

[0027] In some embodiments, the gate terminals of the first zone among the zones are coupled to a ground connection, and the source terminals of the second zone among the zones are coupled to a ground connection.

[0028] In some embodiments, the first zone and the second zone may form a common gate - common source amplifier.

[0029] In some embodiments, the RF transistor amplifier may further include an impedance matching network coupled between the output of the first zone and the input of the second zone. In some embodiments, the impedance matching network may be on and / or within the interconnection structure.

[0030] In some embodiments, the interconnect structure may include a connection network that electrically connects a subset of zones in parallel.

[0031] In some embodiments, each gate terminal may be coupled to the input of the RF transistor amplifier by a respective RF transmission path, and the electrical lengths of the RF transmission paths may be substantially equal.

[0032] In some embodiments, a first drain terminal of the drain terminals may be electrically coupled in series to a second gate terminal of the gate terminals.

[0033] In some embodiments, the interconnect structure may include a redistribution layer laminate structure or a printed circuit board. In some embodiments, a plurality of circuit elements are mounted on the interconnect structure. The circuit elements may include, for example, at least one of a surface mount capacitor and a surface mount inductor.

[0034] In some embodiments, the side of the RF transistor amplifier die that is not connected to the interconnect structure may be encapsulated.

[0035] In some embodiments, each zone may include one of each of the gate terminals and one of each of the drain terminals.

[0036] In some embodiments, the number of gate terminals may be different from the number of drain terminals.

[0037] According to an embodiment of the present invention, there is provided an RF transistor amplifier including an RF transistor amplifier die having a group III nitride-based semiconductor layer structure, a plurality of gate terminals, a plurality of drain terminals, and a source terminal, each of which is on the upper surface of the semiconductor layer structure. The RF transistor amplifier die is divided into a plurality of zones, each of the zones includes a plurality of unit cell transistors, and a first zone among the zones is electrically coupled in series with a second zone among the zones.

[0038] In some embodiments, the first zone among the zones may be electrically coupled in parallel with a third zone among the zones. In some embodiments, the second zone among the zones may be electrically coupled in parallel with a fourth zone among the zones.

[0039] In some embodiments, the RF transistor amplifier may further include an interconnection structure on the upper surface of the RF transistor amplifier die and a coupling element between the RF transistor amplifier die and the interconnection structure that electrically connects the gate terminal, the drain terminal, and the source terminal to the interconnection structure.

[0040] In some embodiments, the unit cell transistors in the first zone among the zones may be configured as a preamplifier, and the unit cell transistors in the second zone among the zones may be configured as a main amplifier.

[0041] In some embodiments, the gate terminal electrically connected to the unit cell transistor of the first zone of the zones may be coupled to a ground connection, and the source terminal electrically connected to the unit cell transistor of the second zone of the zones may be coupled to a ground connection. In some embodiments, the first zone and the second zone may form a common gate - common source amplifier. The RF transistor amplifier may further include an impedance matching network coupled between the output of the first zone and the input of the second zone. The impedance matching network may be on and / or within an interconnect structure on the top surface of the RF transistor amplifier die.

[0042] In some embodiments, the first drain terminal of the drain terminals may be electrically coupled in series to the second gate terminal of the gate terminals.

[0043] In some embodiments, the interconnect structure may be a redistribution layer laminate structure and / or a printed circuit board.

[0044] In some embodiments, each zone may include one gate terminal of the gate terminals and one drain terminal of the drain terminals.

[0045] According to a further embodiment of the present invention, there is provided an RF transistor amplifier die having a group - III nitride - based semiconductor layer structure and a plurality of unit cell transistors, each unit cell transistor including a gate finger, the RF transistor amplifier die including a first gate finger of the gate fingers having a first length and a second gate finger of the gate fingers having a second length different from the first length.

[0046] In some embodiments, the RF transistor amplifier die may be divided into a plurality of zones configured for operation in different frequency bands, a first gate finger of the gate fingers may be in a first zone of the zones, and a second gate finger of the gate fingers may be in a second zone of the zones. In some embodiments, the first zone of the zones may be configured to amplify an RF signal in a first frequency range, and the second zone of the zones may be configured to amplify an RF signal in a second frequency range different from the first frequency range. In some embodiments, the RF transistor amplifier may further include an interconnection structure on the surface of the RF transistor amplifier die and a coupling element between the RF transistor amplifier die and the interconnection structure that electrically connects the RF transistor amplifier die to the interconnection structure.

[0047] In some embodiments, the interconnection structure may include a first RF input portion corresponding to the first zone and a second RF input portion corresponding to the second zone.

[0048] In some embodiments, a plurality of circuit elements are attached to the interconnection structure. The circuit elements may include, for example, at least one of a surface mount capacitor and a surface mount inductor.

[0049] In some embodiments, the RF transistor amplifier die may further include a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal, and each of the gate terminals may be coupled to one of the plurality of zones.

[0050] According to a further additional embodiment of the present invention, there is provided an RF transistor amplifier including an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and a plurality of gate manifolds, an interconnection structure on the upper surface of the RF transistor amplifier die, the interconnection structure including an RF input portion, the interconnection structure, a coupling element between the RF transistor amplifier die and the interconnection structure for electrically connecting the RF transistor amplifier die to the interconnection structure, and a plurality of RF transmission lines extending from the RF input portion to respective gate manifolds, each of the transmission lines having substantially the same electrical length.

[0051] In some embodiments, each of the RF transmission lines may have substantially the same physical length.

[0052] In some embodiments, the RF transistor amplifier die may be divided into a plurality of zones, each of the zones may include a plurality of unit cell transistors, and each gate manifold may be connected to the unit cell transistors of each respective zone of the zones.

[0053] According to a further additional embodiment of the present invention, there is provided an RF transistor amplifier including an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and an interconnection structure on the upper surface of the RF transistor amplifier die, the interconnection structure including an RF input portion, the interconnection structure. The RF transistor amplifier die is divided into a plurality of zones, each of the zones includes a plurality of unit cell transistors, and the interconnection structure includes a switch network configured to selectively connect the RF input portion to one or more of the plurality of zones.

[0054] In some embodiments, the first zone of the zones may be a redundant zone, and the switch network may be set to transfer an RF signal received at the RF input portion to the redundant zone instead of another zone that has failed.

[0055] In some embodiments, at least one of the zones may be configured to operate independently of the other zones of the zones.

[0056] In some embodiments, an RF amplifier may be configured to transfer an RF signal to a first subset of zones for operation in a first range of output power levels and to transfer the RF signal to a second subset of zones different from the first subset for operation in a second range of output power levels different from the first range of output power levels.

[0057] In some embodiments, one of the zones may include a redundant zone, and a switching network may be configured to switch a transmission path from a first zone of the zones to the redundant zone.

[0058] According to a further embodiment of the present invention, there is provided an RF transistor amplifier including an RF transistor amplifier die, the RF transistor amplifier die being a group III nitride-based semiconductor layer structure divided into a plurality of zones, each of the zones including a plurality of unit cell transistors, a plurality of gate terminals, each unit cell transistor of each zone being electrically connected to one of the gate terminals, a plurality of drain terminals, each unit cell transistor of each zone being electrically connected to one of the drain terminals, and at least one source terminal.

[0059] In some embodiments, all of the gate terminal, the drain terminal, and the at least one source terminal may be on the upper surface of the semiconductor layer structure.

[0060] In some embodiments, at least one of the zones can be operated independently of the other zones of the zones. BRIEF DESCRIPTION OF THE DRAWINGS

[0061]

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[0062] According to an embodiment of the present invention, a group III nitride-based RF transistor amplifier is provided that includes an RF transistor amplifier die divided into a number of different zones. Each zone may include a plurality of unit cell transistors and may operate as an individual amplifier unit. The RF transistor amplifier die may be divided into a number of zones by forming a number of gate terminals and a number of drain terminals on the RF transistor amplifier die. The number of gate terminals, the number of drain terminals, and one or more source terminals may all be disposed on the upper side of the RF transistor amplifier die. The RF transistor amplifier die may be connected to the interconnection structure, for example, via coupling elements. By dividing the RF transistor amplifier die into a plurality of potentially independent zones, various different capabilities may be supported.

[0063] For example, in some embodiments, the RF transistor amplifier may include a switching network that may be used to select different combinations of zones. This may enable the RF transistor amplifier to be customized for a particular application. For example, in the case of a low-power application, the switching network may connect only a few zones along the RF transmission path between the input and output of the RF transistor amplifier, whereas in the case of a high-power application, most or all of the zones may be switched into the RF transmission path. This may enable the RF transistor amplifier to be configured to provide high-efficiency operation. The switching network may be provided on the interconnection structure in some embodiments. Further, in other embodiments, the switching network may be omitted, and instead, different interconnection structures each having a wiring RF transmission line connecting different combinations of zones of the RF transistor amplifier die along the RF transmission path between the input and output of the RF transistor amplifier may be provided. In these embodiments, a common RF transistor amplifier die may be used, and different interconnection structures may be attached to the RF transistor amplifier die to arrange a desired number of zones along the RF transmission path.

[0064] In other embodiments, an RF transistor amplifier may be provided that includes one or more built-in redundant amplifier units that may be used if the main amplifier unit fails during operation.

[0065] In yet other embodiments, a multi-zone group III nitride-based RF transistor amplifier having different zones configured for operation in different frequency bands is provided. The gate fingers in each zone may have different lengths. These RF transistor amplifiers may enable one RF transistor amplifier to be used in a variety of different applications, for example, by selecting which zone is connected to an external circuit. These RF transistor amplifiers may enable one part to be used in a number of different applications, reducing the number of parts and providing flexibility for integrators.

[0066] In yet other embodiments, a multi-zone RF transistor amplifier die according to an embodiment of the present invention may be used to implement an RF amplifier that includes a number of RF transistor amplifiers using one RF transistor amplifier die. For example, one common RF amplifier configuration includes a preamplifier and a main amplifier electrically connected in series. Such an amplifier configuration may also include one or more of an input matching circuit, an inter-stage matching circuit, and an output matching circuit. According to an embodiment of the present invention, a first subset of zones of the RF transistor amplifier die may be used to implement the preamplifier, and a second subset of zones of the RF transistor amplifier die may be used to implement the main amplifier. An interconnect structure may be used to electrically connect the preamplifier and the main amplifier in series, and the matching circuits may also be implemented at least partially within and / or on the interconnect structure. The same techniques may be used to implement a number of amplifiers in parallel (e.g., Doherty amplifier configuration) or to implement an RF transistor amplifier having other unique configurations such as a common gate - common source configuration using one RF transistor amplifier die. Further, as described above, different interposers (or switching networks on the interconnect structure) may be used to vary the number of zones included in each amplifier in these multi - amplifier circuits. This may advantageously reduce the number of RF transistor amplifier designs required.

[0067] One problem with conventional RF transistor amplifiers is that the input RF signal reaches different gate fingers of the RF transistor amplifier die at different times, such that sub-components of the RF signal amplified in different parts of the die are somewhat out of phase with each other. This results in a performance degradation. The RF transistor amplifier according to an embodiment of the present invention reduces or even eliminates this problem. This is because the electrical lengths of the RF transmission paths to each zone may be equalized (e.g., in the interconnect structure), whereby the phases of the sub-components of the RF signal provided to different zones are matched.

[0068] According to some embodiments, an RF transistor amplifier is provided that includes a group-III nitride-based semiconductor layer structure and an RF transistor amplifier die having a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal, each on the upper surface of the semiconductor layer structure. An interconnect structure is attached to the upper surface of the RF transistor amplifier die, and coupling elements that electrically connect the gate terminals, drain terminals, and source terminals to the interconnect structure are provided between the RF transistor amplifier die and the interconnect structure. The RF transistor amplifier die may be divided into a plurality of zones, each zone including a plurality of unit cell transistors. In some embodiments, at least one of the zones can be operated independently of the other zones of the zones.

[0069] In one particular embodiment, a first zone of the zones may be configured to amplify an RF signal in a first frequency range, and a second zone of the zones may be configured to amplify an RF signal in a second frequency range different from the first frequency range. In such an embodiment, the gate fingers in the first zone of the zones may have a first length, and the gate fingers in the second zone of the zones may have a second length different from the first length.

[0070] In other embodiments, the unit cell transistors of the first zone among the zones may be electrically coupled in series with the unit cell transistors of the second zone among the zones. For example, the unit cell transistors in the first zone among the zones may be configured as a preamplifier and may be coupled in series with the unit cell transistors of the second zone among the zones that may be configured as a main amplifier.

[0071] In yet other embodiments, the unit cell transistors of the first zone among the zones may be electrically coupled in parallel with the unit cell transistors of the second zone among the zones, and the unit cell transistors of the first zone among the zones may have a different configuration from the unit cell transistors of the second zone among the zones. For example, the unit cell transistors of the first zone among the zones may be configured as the main amplifier of a Doherty amplifier, and the unit cell transistors of the second zone among the zones may be configured as the peak amplifier of a Doherty amplifier. As another example, the gate terminal for the first zone among the zones may be coupled to a ground connection, and the source terminal for the second zone among the zones may be coupled to a ground connection, whereby the first zone and the second zone form a common gate - common source amplifier.

[0072] In some embodiments, the coupling element may be directly connected to the gate, drain, and / or source terminals of the RF transistor amplifier die. In some embodiments, the coupling element may physically and electrically connect the gate, drain, and / or source terminals of the RF transistor amplifier die to an interconnect structure. In other embodiments, the interconnect structure may be omitted, and the coupling element may physically and electrically connect the gate, drain, and / or source terminals of the RF transistor amplifier die to separately mounted components and / or leads of the RF transistor amplifier.

[0073] Here, embodiments of the present invention will be described in more detail with reference to FIGS. 2 to 12D.

[0074] Figure 2 is a schematic cross-sectional view of an RF transistor amplifier 100 according to an embodiment of the present invention. As shown in Figure 2, the RF transistor amplifier 100 includes an RF transistor amplifier die 110, a coupling element 120, and an interconnect structure 130. The RF transistor amplifier die 110 may include a Group III nitride-based RF transistor amplifier die including a plurality of unit cell transistors (not shown). Each unit cell transistor may include a field effect transistor (e.g., a HEMT transistor) having a gate, a drain, and a source. At least some of the unit cell transistors may be electrically connected in parallel. The RF transistor amplifier die 110 may include a plurality of gate terminals 122, a plurality of drain terminals 124, and at least one source terminal 126. The gate terminals 122, the drain terminals 124, and the source terminal 126 may all be disposed on the upper side of the RF transistor amplifier die 110.

[0075] As further shown in FIG. 2, a coupling element 120 is provided on the upper surface of the RF transistor amplifier die 110, and an interconnect structure 130 is provided on the upper surface of the coupling element 120. Thus, the coupling element 120 may be disposed between the RF transistor amplifier die 110 and the interconnect structure 130. In some embodiments, the coupling element 120 may include conductive structures (e.g., metal pillars and pads) formed during wafer-level processing using conventional semiconductor processing techniques and / or other methods (i.e., before a semiconductor wafer including a plurality of RF transistor amplifier dies 110 is diced into individual RF transistor amplifier dies 110). In such embodiments, an underfill material such as a capillary underfill material may be injected to fill the space between the conductive structures of the coupling element 120. It should be noted that even if the coupling element is formed as part of wafer-level processing, it is described herein as a separate element from the RF transistor amplifier die 110 for convenience of explanation. In other embodiments, the coupling element 120 may be a separate structure such as a redistribution layer ("RDL") laminate structure and / or an interposer formed separately from the RF transistor amplifier die 110, which may be attached to or applied to the RF transistor amplifier die 110 during wafer-level processing steps (i.e., before the wafer is diced into individual RF transistor amplifier dies 110). It should also be noted that the interconnect structure 130 may be omitted in some embodiments of the present invention, as will be described in more detail below.

[0076] Positioning all three of the gate terminal 122, drain terminal 124, and source terminal 126 on the same side of the RF transistor amplifier die may have several advantages.

[0077] First, this arrangement may reduce manufacturing costs. This is because it may no longer be necessary to form vias through the semiconductor layer structure of the RF transistor amplifier die, and in some cases, the backside metallization process may also be omitted. Further, the source terminal may be formed in the same steps used to form the conventional upper gate and drain terminals, such that the manufacture of the source terminal may not require additional processing steps.

[0078] Second, prior to the formation of the source via 66 to reduce the thickness of the growth substrate, polishing operations are commonly performed in conventional RF transistor amplifier dies such as the RF transistor amplifier die 10 of FIGS. 1A - 1F. When all three of the gate, drain, and source terminals are formed on the upper side of the semiconductor layer structure, such polishing operations may be omitted or less polishing may be performed, which also reduces manufacturing costs. Further, a thicker die may provide an improvement in manufacturing yield (by having fewer cracked dies), and may facilitate easier handling and improved thermal management capabilities.

[0079] Thirdly, all three of the gate, drain, and source terminals are on the upper side of the RF transistor amplifier die, and the RF transistor amplifier according to an embodiment of the present invention may be attached in a flip-chip arrangement, in which the RF transistor amplifier die may be attached to another substrate, such as an interconnect structure, in a stacked arrangement as shown in FIG. 2. Thereby, the RF transistor amplifier according to an embodiment of the present invention may not include bond wires for gate and / or drain connections. Bond wires typically have a specific inductance used to supply part of the impedance matching and / or harmonic termination circuit inductance of a conventional RF transistor amplifier. The amount of inductance provided by the bond wire may be varied by changing the length and / or cross-sectional area (e.g., diameter) of the bond wire so that the bond wire provides the desired amount of inductance. Unfortunately, as the application migrates to higher frequencies, even the inductance of a very short bond wire may exceed the desired amount of inductance for impedance matching and / or the harmonic termination circuit. When this occurs, the matching network may not be able to achieve good impedance matching and / or may not be able to sufficiently terminate secondary or third harmonics. Furthermore, wire bonding equipment, typically used for high-volume production, may have a tolerance of ±0.0254 mm (±1 mil), i.e., the length of any particular bond wire may vary by 0.1016 mm (4 mil) (i.e., ±0.0254 mm (±1 mil) at each end of the bond wire). For high-frequency applications, the inductance change associated with 0.1016 mm (4 mil) of the bond wire may be significant, whereby if the bond wire is too short or too long by 0.0254 mm to 0.0508 mm (1 to 2 mil) from the desired nominal length, the performance of the matching circuit may be degraded. Therefore, by reducing or eliminating the need for bond wires, improved matching and more consistent performance may be obtained.

[0080] Fourth, elimination of the gate and drain terminal bond wires may reduce an undesirable inherent gate-to-drain capacitance that can have an adverse effect on the operation of the device.

[0081] Fifth, providing all three of the gate, drain, and source terminals on the same side and potentially in the same plane of the RF transistor amplifier die may facilitate attaching the RF transistor die to an interconnect structure that may include other circuit elements such as capacitors or inductors for impedance matching, combinational circuits, switches, etc.

[0082] One additional advantage of arranging all three of the gate, drain, and source terminals on the same side of the RF transistor amplifier die is that the RF transistor amplifier die may be divided into a plurality of zones. This may be achieved, for example, by dividing at least one of the gate and / or drain terminals into a number of gate and / or drain terminals. Each zone may include a plurality of unit cell transistors electrically connected in parallel to form respective amplifier units. Different zones / amplifier units may be connected in any suitable form including in parallel, in series, selectively connected to each other, etc. As described above, dividing the RF transistor amplifier die into a plurality of zones may facilitate providing an RF transistor amplifier that (1) has optimized performance at different power levels, (2) can operate in a number of different frequency bands, (3) can implement a multi-amplifier circuit using one RF transistor amplifier die, (4) can exhibit improved phase performance, and / or (5) can provide redundancy. Here, examples of RF transistor amplifiers that provide each of the above advantages will be described in more detail. Before describing these examples, an example of a Group III nitride-based RF transistor amplifier 200 according to an embodiment of the present invention including a number of zones will be described with reference to FIGS. 3A - 3F.

[0083] In particular, FIG. 3A is a schematic plan view of a group-III nitride-based RF transistor amplifier 200. FIG. 3B is a schematic cross-sectional view of the RF transistor amplifier 200 taken along line 3B-3B of FIG. 3A. FIG. 3C is a schematic plan view of the upper metallization portion in direct contact with the semiconductor layer structure of the RF transistor amplifier die 210 included in the RF transistor amplifier 200, taken along line 3C-3C of FIG. 3B. FIGS. 3D and 3E are schematic cross-sectional views of the RF transistor amplifier 200 taken along lines 3D-3D and 3E-3E of FIG. 3C, respectively. FIG. 3E is a cross-sectional view of the RF transistor amplifier 200 showing how the RF transistor amplifier 200 may include and be attached to an optional interconnect structure 300 such as a rewiring laminate structure or a printed circuit board.

[0084] Referring to FIGS. 3A and 3B, the group-III nitride-based RF transistor amplifier 200 may include an RF transistor amplifier die 210 and a coupling element 270 attached to the upper surface of the RF transistor amplifier die 210. As will be further described with reference to FIG. 3F, the RF transistor amplifier 200 may further include an interconnect structure 300. The coupling element 270 may be between the RF transistor amplifier die 210 and the interconnect structure 300 and may electrically connect the RF transistor amplifier die 210 to the interconnect structure 300. The RF transistor amplifier die 210, the coupling element 270, and the interconnect structure 300 may be in a stacked relationship or arrangement.

[0085] The RF transistor amplifier die 210 includes a semiconductor layer structure 230 having an upper side 212 and a back side 214. The upper metallization structure 220 is formed on the upper side 212 of the semiconductor layer structure 230, and a lower temperature layer 240 may be formed on the lower side 214 of the semiconductor layer structure 230. The upper metallization structure 220 includes a plurality of gate terminals 222, a plurality of drain terminals 224, a plurality of source terminals 226, and other metallizations that will be described in more detail below. The RF transistor amplifier die 210 may be a HEMT-based RF transistor amplifier die, in which case the semiconductor layer structure 230 may include at least a channel layer and a barrier layer, as will be described in more detail below.

[0086] Each gate terminal 222 may receive an RF signal from a first external circuit input to the RF transistor amplifier die 210 and couple these input RF signals to each one of the zones of the multi-zone RF transistor amplifier die 210. Each drain terminal 224 may output an RF signal amplified by each one of the zones of the multi-zone RF transistor amplifier die 210.

[0087] The coupling element 270 is formed on the RF transistor amplifier die 210 in the upper metallization structure 220. The coupling element 270 may be used to connect the RF transistor amplifier die 210 to another structure such as an interconnect structure. FIG. 3F shows how the coupling element 270 may be used to connect the RF transistor amplifier die 210 to an interconnect structure 300 in the form of a printed circuit board. In some embodiments, the coupling element 270 may be formed during wafer-level processing using semiconductor and / or non-semiconductor processing techniques. In other embodiments, the coupling element 270 may include a separate structure such as, for example, an RDL laminate structure or an interposer. The RDL laminate structure means a substrate having a conductive layer pattern and / or conductive vias.

[0088] As shown in FIGS. 3A - 3B, the coupling element 270 includes a plurality of gate connection pads 272, a plurality of drain connection pads 274, and a plurality of source connection pads 276. In the figures, bipartite reference numerals may be used to describe like elements (e.g., drain terminal 274 - 2), and while complete reference numerals may be used to refer to a particular example of an element, the first part of the reference numeral may be used to refer to the elements collectively. Each of these connection pads 272, 274, 276 may include, for example, an exposed copper pad, but the invention is not limited thereto. Each gate connection pad 272 may be electrically coupled to each one of the gate terminals 222 by one or more conductive gate pillars 273. Similarly, each drain connection pad 274 may be electrically coupled to each one of the drain terminals 224 by one or more conductive drain pillars 275, and each source connection pad 276 may be electrically coupled to each one of the source terminals 226 by one or more conductive source pillars 277. Although not shown, the coupling element 270 may alternatively have a fan - in configuration or a fan - out configuration.

[0089] In some embodiments, the coupling element 270 may be formed as part of a wafer-level processing operation. For example, the coupling element 270 can be formed by forming a conductive gate pillar 273 on the gate terminal 222, a conductive drain pillar 275 on the drain terminal 224, and a conductive source pillar 277 on the source terminal 226. In some embodiments, the conductive pillars 273, 275, 277 may include copper pillars. For example, the conductive pillars may be formed by electroplating a copper seed layer on the gate, drain, and source terminals 222, 224, 226 and using one or more masks to form the conductive pillars 273, 275, 277 thereon. Then, the gate connection pad 272, the drain connection pad 274, and the source connection pad 276 may be formed on their respective gate, drain, and source pillars 273, 275, 277. The conductive pillars 273, 275, 277 and the connection pads 272, 274, 276 may be at least partially disposed within an encapsulation structure (not shown) that includes a dielectric material. For example, a wide variety of dielectric materials including silicon oxide, silicon nitride, polymers, molding materials, and / or combinations thereof may be used. The dielectric material may be processed (e.g., planarized) to expose the gate connection pad 272, the drain connection pad 274, and / or the source connection pad 276. If the coupling element 270 is formed using a wafer-level process, multiple coupling elements 270 may be formed (one on each RF transistor amplifier die 210 included in the wafer), and then the RF transistor amplifier die 210 may be singulated with the individual coupling elements 270 formed thereon.

[0090] In some embodiments, the coupling element 270 may be formed in a chip - first or chip - last process. In a chip - first process, the coupling element 270 may be formed directly on a wafer (or, alternatively, on a singulated RF transistor amplifier die 210) that includes the RF transistor amplifier die 210 in the form described above. In a chip - last process, the coupling element 270 may be formed on a temporary carrier layer (not shown). The conductive pillars 273, 275, 277 and the connection pads 272, 274, 276 may be formed in a similar manner as the chip - first process on the temporary carrier layer. Once completed, the coupling element 270 may be separated from the temporary carrier layer and then coupled to the RF transistor amplifier die 210 (either as a wafer - level process or a chip - level process).

[0091] For example, other coupling elements 270 such as a printed circuit board (e.g., a multi - layer printed circuit board), an RDL laminate structure, a ceramic substrate including conductive vias and / or pads, or any coupling that can form a suitable electrical connection to the RF transistor amplifier die 210 may be alternatively used. In some configurations, as further described herein, the coupling element 270 may be omitted.

[0092] The arrangement of the conductive pillars 273, 275, 277 and the connection pads 272, 274, 276 shown in FIGS. 3A - 3B is merely an example, and other arrangements are possible without departing from the present invention.

[0093] In an embodiment where the semiconductor layer structure 230 of the RF transistor amplifier die 210 has a high thermal conductivity, the back side of the RF transistor amplifier die 210 can be attached to a thermally conductive carrier substrate or submount, such as a metal slug, lead frame, or flange, to provide improved heat dissipation of the heat generated by the RF transistor amplifier die from the amplifier package. As described above, the optional temperature layer 240 may be formed on the back side 214 of the semiconductor layer structure 230. The temperature layer 240 may be configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate or submount. In some embodiments, the temperature layer 240 may be a die attach layer, such as a eutectic layer. The temperature layer 240 can be a metal layer for forming a eutectic bond or other metal bond. In some embodiments, the temperature layer 240 can be a thermal adhesive.

[0094] FIG. 3C is a schematic plan view of the RF transistor amplifier die 210 taken along line 3C-3C of FIG. 3B, showing a portion of the upper metallization structure 220 in contact with the semiconductor layer structure 230. The RF transistor amplifier die 210 may include a group-III nitride-based HEMT RF transistor amplifier including a plurality of unit cell transistors 216 electrically connected to each other in parallel. The dashed box in FIG. 3C highlights one of the unit cell transistors 216. The unit cell transistor 216 includes gate fingers 252, drain fingers 254, and source fingers 246, together with a lower portion of the semiconductor layer structure 230.

[0095] As shown in FIG. 3C, the RF transistor amplifier die 210 includes a plurality of gate manifolds 242 and a plurality of drain manifolds 244. The plurality of gate fingers 252 extend in the X direction from each gate manifold 242, the plurality of drain fingers 254 extend in the X direction from each drain manifold 244, and the source finger 246 extends parallel to the gate fingers 242. All of these elements may be formed on the upper surface of the semiconductor layer structure 230. The region between the gate manifold 242 and the drain manifold 244 that includes the unit cell transistor 216 is referred to as the active region 218 of the RF transistor amplifier die 210.

[0096] The gate fingers 252 may be formed of a material capable of forming a Schottky contact to a group III nitride-based semiconductor material such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The drain fingers 254 and the source finger 246 may include a metal such as TiAlN that is capable of forming a resistive contact to a group III nitride-based material. A dielectric layer (or series of dielectric layers) that helps isolate the gate manifold / fingers 242, 252, the drain manifold / fingers 244, 254, and the source finger 246 from each other is not shown in FIG. 3C for the sake of better showing the elements of the RF transistor amplifier die 210.

[0097] The RF transistor amplifier die 210 is divided into a plurality of zones 260. Each zone 260 includes a subset of unit cell transistors 216. In the embodiments of FIGS. 3A-3F, the RF transistor amplifier die 210 is divided into a total of four zones 260-1 to 260-4, but the embodiments of the invention are not limited thereto. In other embodiments, the RF transistor amplifier die 210 may be divided into two, three, five, six, seven, eight, nine, or ten or more zones 260. In fact, in some embodiments, a number of different zones 260 (e.g., 20 or 40 zones) may be provided. As will be described in more detail herein, dividing the RF transistor amplifier die 210 into a plurality of zones 260 may have a number of advantages and may enable the RF transistor amplifier to be configured to operate in a variety of new and different forms.

[0098] As seen in FIGS. 3A-3C, in some embodiments, each zone 260 may include a gate manifold 242, a drain manifold 244, a plurality of unit cell transistors 216, a gate connection pad 272, a drain connection pad 244, and a source connection pad 276. All gate fingers 252 within the zone 260 may be electrically connected to a common gate manifold 242, all drain fingers 254 within the zone 260 may be electrically connected to a common drain manifold 244, and all source fingers 246 may be electrically connected to each other via a common source terminal 226 (described below). Thus, the unit cell transistors 216 within each zone 260 may be electrically connected to each other in parallel.

[0099] The unit cell transistor 216 may be a HEMT device. Suitable structures for III-nitride based HEMT devices that may utilize embodiments of the present invention are described, for example, in U.S. Patent Application Publication No. 2002 / 0066908 (A1) to the same applicant, published Jun. 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same"; U.S. Patent Application Publication No. 2002 / 0167023 (A1), published Nov. 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; U.S. Patent Application Publication No. 2004 / 0061129, published Apr. 1, 2004, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses"; U.S. Patent No. 7,906,799, issued Mar. 15, 2011, entitled "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess"; and U.S. Patent No. 6,316,793, issued Nov. 13, 2001, entitled "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates", the disclosures of which are hereby incorporated by reference in their entirety.

[0100] Referring to FIGS. 3D and 3E, the semiconductor layer structure 230 includes a growth substrate 232 and a plurality of semiconductor layers formed on the growth substrate 232. In the illustrated embodiment, a total of two semiconductor layers, namely a channel layer 234 and a barrier layer 236 above the channel layer 234, are shown on the growth substrate 232. The semiconductor layer structure 230 may include additional semiconductor and / or non-semiconductor layers such as an optional buffer layer, a nucleation layer, and / or a transition layer (not shown) provided on the growth substrate 232 below the channel 234. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the SiC growth substrate 232 and the rest of the semiconductor layer structure 230. Additionally, a strain balancing transition layer as described in U.S. Patent Application Publication No. 2003 / 0102482 (A1) to the same applicant, published on Jun. 5, 2003, entitled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors", the disclosure of which is hereby incorporated by reference as if fully set forth herein, may also be provided. The growth substrate 232 may include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the growth substrate may be or include a different semiconductor material (e.g., group III nitride-based materials, Si, GaAs, AnO, InP) or a non-semiconductor material (e.g., sapphire).

[0101] SiC has a much closer lattice match to group-III nitrides than sapphire (Al2O3) or silicon, which are very common substrate materials for group-III nitride devices. The closer lattice match of SiC may result in higher-quality group-III nitride films than those generally available in sapphire or silicon. SiC also has a very high thermal conductivity, whereby the total output power of group-III nitride devices on silicon carbide is typically not limited by substrate heat dissipation as much as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating SiC substrates may provide device isolation and reduced parasitic capacitance.

[0102] In some embodiments, if the energy of the conduction band edge of the channel layer 234 is lower than the energy of the conduction band edge of the barrier layers 234, 236 at the interface between the channel and the barrier layers 234, 236, the channel layer 234 is Al x Ga 1-x a group-III nitride material such as N, where 0 ≦ x < 1. In one embodiment of the present invention, x = 0, which indicates that the channel layer 234 is gallium nitride (“GaN”). The channel layer 234 may be other group-III nitrides such as InGaN, AlInGaN, etc. The channel layer 234 may be undoped or unintentionally doped and may be grown to a thickness greater than, for example, about 2 nm. The channel layer 234 may be a multilayer structure such as a superlattice or a combination of GaN, AlGaN, etc.

[0103] The channel layer 234 may have a bandgap smaller than at least a part of the bandgap of the barrier layer 236, and the channel layer 234 may also have a larger electron affinity than the barrier layer 236. In certain embodiments, the barrier layer 236 is AlN, AlInN, AlGaN, or AlInGaN or a combination of layers thereof having a thickness of from about 0.1 nm to about 30 nm or more. In a particular embodiment, the barrier layer 236 has a sufficient thickness and a sufficiently high Al composition and doping to produce a significant carrier concentration at the interface between the channel layer 234 and the barrier layer 236.

[0104] The barrier layer 236 may be a group III nitride and may have a larger bandgap than that of the channel layer 234 and a smaller electron affinity than the channel layer 234. In certain embodiments, the barrier layer 236 is undoped or doped with an n-type dopant at a concentration less than about 10 19 cm -3 . In some embodiments of the present invention, the barrier layer 236 is Al x Ga 1-x N with 0 < x < 1. In a particular embodiment, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 236 includes AlGaN having an aluminum concentration of from about 5% to about 100%. In a particular embodiment of the present invention, the aluminum concentration is greater than about 10%. The barrier layer 236 may be implemented as a graded layer and / or multiple layers in some embodiments.

[0105] Due to the difference in bandgap between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is generated in the channel layer 234 at the junction between the channel layer 234 and the barrier layer 236. The 2DEG acts as a highly conductive layer that allows conduction between the source region of each unit cell transistor 216 and its associated drain region, where the source region is the portion of the semiconductor layer structure 230 immediately below the source finger 246, and the drain region is the portion of the semiconductor layer structure 230 immediately below the corresponding drain finger 254.

[0106] An insulating layer (not shown) may be formed over the gate finger 252, drain finger 254, and source finger 246. The insulating layer may include a dielectric material such as SiN, SiO2, etc.

[0107] As shown in FIGS. 3B and 3D, each source terminal 226 may be physically and electrically connected to the source finger 246 in a predetermined zone 260 by a conductive via 247. Similarly, as shown in FIG. 3E, each gate terminal 222 may be physically and electrically connected to its respective gate manifold 242 by a conductive via 243. The drain manifold 244 and drain terminal 224 may have the same design as the gate manifold 242 and gate terminal 222, and thus each drain terminal 224 may be physically and electrically connected to its respective drain manifold 244 by a conductive via 245.

[0108] Since all the terminals 222, 224, 226 are positioned on the upper side of the RF transistor amplifier die 210, conductive vias that penetrate through the semiconductor layer structure 230 to the back side of the RF transistor amplifier die 210 are not required. The absence of vias on the back side of the RF transistor amplifier die 210 that connect the source to a grounded conductive submount allows for the omission of all submounts or the use of non-conductive submounts. Further, the back side of the RF transistor amplifier die 210 may be coupled to a thermally conductive submount or layer 240 (see FIG. 3B), such as a heat sink, to provide improved heat dissipation. In some embodiments, the temperature layer 240 may facilitate this thermal coupling. When SiC is used as the substrate material (for the substrate 232), the thermal characteristics of the package can be further improved by the improved thermal conductivity of SiC.

[0109] Furthermore, arranging all the terminals 222, 224, 226 on the upper side of the RF transistor amplifier die 210 enables the use of a coupling element 270, which can effect all transistor connections to their respective connection pads 272, 274, 276. This may enable the RF transistor amplifier die 210 to be further coupled to other elements of the circuit (e.g., other routing elements, ground elements, harmonic and / or input / output impedance matching elements) by using a connection method that avoids bonding wires.

[0110] FIG. 3F is a schematic cross-sectional view of an RF transistor amplifier 200 that additionally includes an interconnect structure 300 attached to a coupling element 270. The coupling element 270 may be used to connect the RF transistor amplifier die 210 to the interconnect structure 300. Since the RF transistor amplifier die 210 and the coupling element 270 have been described in detail above with reference to FIGS. 3A - 3E, the following description will focus on the interconnect structure 300.

[0111] The interconnect structure 300 may be used to connect the RF transistor amplifier die 210 to other circuit elements. For example, the interconnect structure 300 may include one or more RF input portions 301 that receive respective RF signals coupled to respective zones 260 (groups of zones) of the RF transistor amplifier die 210, and one or more RF output portions 308 that receive respective RF signals output from the RF transistor amplifier die 210. The interconnect structure 300 may further include one or more ground input portions 309 that each receive a grounded reference voltage. The interconnect structure 300 may include a plurality of gate interconnect pads 372 configured to couple to respective gate connection pads 272, a plurality of drain interconnect pads 374 configured to couple to respective drain connection pads 274, and a plurality of source interconnect pads 376 configured to couple to respective source connection pads 276 of the coupling element 270. Bonding elements 360 (e.g., solder balls and / or bumps, conductive die attach materials, etc.) may be used to couple the gate, drain, and source interconnect pads 372, 374, 376 to the respective gate, drain, and source connection pads 272, 274, 276.

[0112] Each gate, drain, and source interconnect pads 372, 374, 376 may be coupled to one or more conductive patterns 320 within the interconnect structure 300. The conductive patterns 320 may provide various routings and / or circuits within the interconnect structure 300. For example, the conductive patterns 320 may connect at least some of the gate interconnect pads 372 to one or more first surface connection pads 312 and / or respective RF input portions 301. Similarly, the conductive patterns 320 may connect at least some of the drain interconnect pads 374 to one or more second surface connection pads 322 and / or respective RF output portions 308. The conductive patterns 320 may also connect the source interconnect pads 376 to one or more third surface connection pads 332 and one or more ground pads 309. Accordingly, the interconnect structure 300 may have a surface (e.g., top surface) having a plurality of first surface connection pads 312, a plurality of second surface connection pads 322, and a plurality of third surface connection pads 332.

[0113] The conductive patterns 320 may be encapsulated within an isolation material 315. In some embodiments, the isolation material 315 may include, for example, silicon oxide, silicon nitride, a polymer, a molding material, a dielectric substrate, or a combination thereof. In some embodiments, the interconnect structure 300 may be formed as a printed circuit board (PCB). In a PCB embodiment, the isolation material 315 may be the substrate of the PCB, and the conductive patterns 320 may be traces and plated or metal-filled vias formed within the substrate.

[0114] Circuit element 350 may also be formed on and / or within interconnect structure 300. For example, circuit element 350 may be coupled between two or more of the first, second, and third surface connection pads 312, 322, 332 (e.g., via solder or other bonding). Circuit element 350 may provide various electronic capabilities to RF transistor amplifier 200. For example, circuit element 350 may include impedances (e.g., resistive, inductive, and capacitive elements) that may be used for impedance matching and / or harmonic termination. Conductive pattern 320 enables circuit element 350 to be coupled along input or output paths in various different configurations.

[0115] Although shown on the surface of interconnect structure 300, it will be understood that additional circuit elements 350 may be provided within interconnect structure 300. For example, capacitors formed between flat panel capacitors, interdigitated capacitors, and / or conductive vias may be implemented within interconnect structure 300. Similarly, spiral inductors or other inductive elements may be implemented within interconnect structure 300. For example, resistive elements may be formed on or within interconnect structure 300 by using a more highly resistive conductive material to form trace segments or conductive vias. In some embodiments, circuit element 350 and / or conductive pattern 320 may be configured to provide at least a portion of a harmonic termination circuit, matching circuit, split circuit, combinational circuit, and / or bias circuit. Without departing from the scope of the present invention, other configurations of conductive pattern 320 and / or other types of circuit elements 250 may be used. It will also be recognized that the configurations of conductive pattern 320 and circuit element 350 shown in FIG. 3F are merely examples and are not intended to limit embodiments of the present invention.

[0116] In some embodiments, interconnect structure 300 and circuit element 350 may optionally be encapsulated within an encapsulation material (not shown). The encapsulation material may include, for example, silicon oxide, silicon nitride, polymers, molding materials, or combinations thereof.

[0117] As shown in FIG. 3F, the provision of the interconnect structure 300 associated with the upper contacts of the RF transistor amplifier die 210 enables additional functions such as impedance matching and / or harmonic termination to be easily added to the RF transistor amplifier 200 without the use of a wide range of wire bonding. Thus, by using different interconnect structures 300, the functionality of the RF transistor amplifier 200 may be easily modified. By reducing or eliminating the wire bond requirement, the die size in some applications (where the size of the wire bond pads drives the die size) may also be reduced, whereby the RF transistor amplifier die according to embodiments of the present invention may also exhibit increased integration density. Thus, the RF transistor amplifier die according to embodiments of the present invention may exhibit improved product assembly consistency, higher yield, increased product integration, reduced cost, and improved RF performance, particularly for products operating at high frequencies such as millimeter wave frequencies.

[0118] FIG. 3G is a schematic cross-sectional view of an RF transistor amplifier 200A similar to the RF transistor amplifier 200 of FIG. 3F. The difference between the RF transistor amplifiers 200 and 200A is that the RF transistor amplifier 200A includes an interconnect structure 300A to which a circuit element 350 is attached on the same side of the interconnect structure 300 as the RF transistor amplifier die 210. In other embodiments, it will be appreciated that the circuit element 350 may be provided on both major surfaces of the interconnect structures 300, 300A. It will also be appreciated that the RF input portion 301, the RF output portion 308, and one or more ground input portions 309 may be provided on either major surface of the interconnect structure (not all of the input portions 301, 308, and 309 need to be on the same major surface). These different arrangements may facilitate different packaging schemes.

[0119] The techniques disclosed herein may be particularly beneficial in higher frequency applications. This is because the inductance required in integrated circuits may be significantly lower in such applications, such that the use of conventional bond wires may introduce an inductance that is too large. Additionally, tolerances in bond wire lengths may have a greater impact at higher frequencies, and in high frequency applications (especially at lower powers), the size of the bond pads may drive the size of the die. In some embodiments, any of the RF transistor amplifier dies disclosed herein may be configured to operate at frequencies higher than 1 GHz. In other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies higher than 2.5 GHz. In yet other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies higher than 3.1 GHz. In still further additional embodiments, these RF transistor amplifier dies may be configured to operate at frequencies higher than 5 GHz. In some embodiments, these RF transistor amplifier dies may be configured to operate in at least one of the frequency bands or portions thereof of 2.5 - 2.7 GHz, 3.4 - 4.2 GHz, 5.1 - 5.8 GHz, 12 - 18 GHz, 18 - 27 GHz, 27 - 40 GHz, or 40 - 75 GHz.

[0120] In the above embodiments, the gate manifold 242 and the gate terminal 222 are separate elements, and the drain manifold 244 and the drain terminal 224 are separate elements (e.g., connected by vias 243, 245 respectively). The present invention is not limited thereto. For example, each gate manifold 242 and its corresponding gate terminal 222 may be formed as one monolithic structure and / or each drain manifold 244 and its corresponding drain terminal 224 may be formed as one monolithic structure.

[0121] Figures 3A-3F show a semiconductor layer structure 230 including a HEMT, but it will be understood that other types of semiconductor devices may be formed in the semiconductor layer structure 230 without departing from the present invention. For example, the semiconductor layer structure 230 may include a MOSFET, a DMOS transistor, a MESFET, and / or an LDMOS transistor. Those skilled in the art will recognize that all arrangements of source / drain / gate contacts on one side of the semiconductor layer structure 230, including the use of the coupling element 270, may enable improved connectivity and better thermal performance.

[0122] It will also be recognized that the RF transistor amplifier die may have various different configurations. For example, the RF transistor amplifier die has upper gate, drain, and source terminals 222, 224, 226, but in some embodiments, it may have one or more of the backside gate, drain, and source terminals 222’, 224’, 226’. Such a calibration is schematically shown in FIG. 3H, which is a schematic cross-sectional view of an RF transistor amplifier 200B corresponding to the cross-sectional view of FIG. 3B. As shown in FIG. 3H, the gate via 211, the drain via 213, and / or the source via 215 may be formed through the semiconductor layer structure 230 connected to their respective gate, drain, and source terminals 222’, 224’, 226’. For example, as described in U.S. Provisional Patent Application No. 63 / 004,985, filed on April 3, 2020 (the “’985 application”), including gate and drain terminals on the backside of the RF transistor amplifier die may have various advantages such as enabling a more flexible impedance matching circuit implementation. The entire content of the ’985 application is incorporated herein by reference. It will be recognized that the backside gate, drain, and source terminals 222’, 224’, 226’ and / or the corresponding gate, drain, and source vias 211, 213, 215 may be included in any of the RF transistor amplifier dies disclosed herein.

[0123] As described above, by dividing an RF transistor amplifier into a plurality of zones 260, a number of new applications can be supported. One such application is to provide an RF transistor amplifier that operates in a plurality of different frequency bands. Group III nitride-based RF transistor amplifiers are widely used in cellular communication applications, particularly as amplifiers in cellular base stations. However, cellular networks may operate in a wide range of different bands and sub-bands, and typically, separate RF transistor amplifiers are manufactured for each sub-band. According to an embodiment of the present invention, one RF transistor amplifier may be provided that can operate in two or more of the sub-bands by designing different zones 260 of an RF transistor amplifier die to operate in a particular sub-band. Thus, a cellular wireless manufacturer may use one RF transistor amplifier in a wireless operating in different frequency bands, resulting in a reduction in parts inventory and enabling the efficiency achievable through mass production of certain parts. The wireless manufacturer may connect a wireless circuit to appropriate gate and drain connection pads connected to zones 260 designed to operate in the operating frequency band of the wireless.

[0124] Figures 4 and 4B are schematic diagrams showing a Group III nitride-based RF transistor amplifier 200C according to an embodiment of the present invention that supports such operation in a number of different frequency bands. In particular, Figure 4A is a bottom view of the RF transistor amplifier 200C, while Figure 4B is a cross-sectional view of the RF transistor amplifier die 210C included in the RF transistor amplifier 200C. The cross-sectional view of Figure 4B corresponds to the cross-sectional view of Figure 3C above (i.e., shows the metallization in contact with the upper surface of the semiconductor layer structure 230 of the RF transistor amplifier die 210C) and shows how the RF transistor amplifier 200 of Figures 3A - 3E may be modified to support operation in a number of different frequency bands.

[0125] First, referring to FIG. 4A, the RF transistor amplifier die 200C includes an RF transistor amplifier die 210C attached to the interconnect structure 300C. A coupling element (not shown) may be used to attach the RF transistor amplifier die 210C to the interconnect structure 300C. The coupling element may include pillars and pads as shown above with reference to FIGS. 3A - 3F, or may simply include conductive bumps (such as solder balls, solder pads, die attach materials, etc.) or a combination of conductive bumps, pillars, pads, etc.

[0126] The interconnect structure 300C includes a plurality of RF input pads 301 - 1 to 301 - 4 and a plurality of RF output pads 308 - 1 to 308 - 4. A total of four RF input pads 301 and RF output pads 308 are shown in FIG. 4A, but it will be appreciated that any suitable number of RF input pads 301 and RF output pads 308 (for example, from 2 to 10 or more in the exemplary embodiments) may be provided. It will also be appreciated that the RF input portion 301 and the RF output portion 308 need not be implemented as pads and may take other forms.

[0127] Referring to FIG. 4B, the RF transistor amplifier die 210C is very similar to the RF transistor amplifier die 210, but it can be seen that the lengths of the gate fingers 252 included in the RF transistor amplifier die 210 are different in different zones 260-1 to 260-4. The length of the gate finger 252 is typically a function of frequency, and lower frequencies have longer gate fingers 252. As shown in FIG. 4B, each of the zones 260-1 to 260-4 has different gate fingers 252 with different lengths such that each zone 260 is configured to support operation in a different frequency band. Manufacturers who install RF transistor amplifier dies in other products such as radios may purchase a number of RF transistor amplifiers 200C and then use these RF transistor amplifiers 200C in radios operating in various different frequency bands. For example, many cellular radios use an RF transistor amplifier as a preamplifier that is used to increase the level of the RF signal input to each main amplifier implemented in other RF transistor amplifier dies. The RF transistor amplifier 200C may function as a multi-frequency band preamplifier that can be used in a wide variety of different radios.

[0128] Referring again to FIG. 4A, each of the RF input pads 301-1 to 301-4 may be electrically connected to one of the gate manifolds 242-1 to 242-4 shown in FIG. 4B. Similarly, each of the RF output pads 308-1 to 308-4 may be electrically connected to one of the drain manifolds 244-1 to 244-4. As described above, each gate manifold 242 and the corresponding drain manifold 244 form one of the different zones 260, and each zone 260 (or alternatively a group of zones) is configured to operate in a different frequency band. The RF transistor amplifier 200C may be attached, for example, to a radio operating in a specific frequency band, and the radio circuit may be connected to the RF input and output pads 301, 308 of the RF transistor amplifier 200C that are electrically connected to the zone 260 in the RF transistor amplifier die 210C configured to operate in the same frequency band as the radio. Other zones 260 may not be used.

[0129] In the embodiments of FIGS. 4A and 4B, the first zone 260-1 of the RF transistor amplifier die 210C is configured to operate in the lowest frequency band (since it has the longest gate fingers 252), the second zone 260-2 is configured to operate in the second frequency band from the lowest frequency band, the third zone 260-3 is configured to operate in the third frequency band from the lowest frequency band, and the fourth zone 260-4 is configured to operate in the highest frequency band. However, it will be appreciated that the zones 260 may be arranged in any suitable form within the RF transistor amplifier die 210C. For example, FIGS. 4C and 4D show a pair of RF transistor amplifier dies 210D, 210E that may be used in place of the RF transistor amplifier die 210C of FIG. 4B. The RF transistor die 210D is configured to operate in two different frequency bands and has two zones 260 dedicated to each frequency band (i.e., zones 260-2 and 260-3 are configured to operate at lower frequencies, and zones 260-1 and 260-4 are configured to operate in a higher frequency band). The RF transistor amplifier die 210D may be part of an RF transistor amplifier including an interconnect structure similar to the interconnect structure 300C of FIG. 4A, except that the interconnect structure used with the RF transistor amplifier die 210D may have only two RF input pads 301 and two RF output pads 308. The RF transistor amplifier die 210E of FIG. 4D shows another variation, where the second zone 260-2 is configured to operate in the lowest frequency band, the fourth zone 260-4 is configured to operate in the second frequency band from the lowest frequency band, the third zone 260-3 is configured to operate in the third frequency band from the lowest frequency band, and the first zone 260-1 is configured to operate in the highest frequency band. Many other variations are possible.

[0130] Figures 4A to 4D show an embodiment in which the lengths of the gate fingers 252 included in the RF transistor amplifier die 210 are varied so that the respective zones 260-1 to 260-4 operate in different frequency bands, but embodiments of the present invention are not limited thereto. As shown in Figure 4E, in other embodiments, the lengths of the drain fingers 254 may be varied. In such embodiments, a gate jumper 251 may be used to center-feed the gate fingers 252. In such embodiments, it is possible to shorten both the gate fingers 252 and the drain fingers 254 for zones operating in higher frequency bands. The extra space in the die provided in these regions may be used for other purposes, such as the on-chip input impedance matching circuit 253 schematically shown in Figure 4E.

[0131] According to a further embodiment of the present invention, there is provided a group III nitride-based RF transistor amplifier that utilizes a multi-zone layout of an RF transistor amplifier die according to an embodiment of the present invention to implement an RF transistor amplifier including two or more RF transistor amplifier circuits using one RF transistor amplifier die. Figures 5A to 8B show four example RF transistor amplifiers according to embodiments of the present invention that include a number of different RF transistor amplifiers on one RF transistor amplifier die.

[0132] First, referring to Figures 5A to 5C, there is shown an RF transistor amplifier 200F according to an embodiment of the present invention that includes a preamplifier and a main amplifier electrically connected in series. Figure 5A is a block diagram of the RF transistor amplifier 200F, while Figure 5B is a schematic plan view of the RF transistor amplifier die 210F and the coupling element 270F of the RF transistor amplifier 200F of Figure 5A. Figure 5C is a schematic block diagram showing how the zones of the RF transistor amplifier die 210F can be interconnected to implement the RF transistor amplifier 200F of Figure 5A (e.g., using the interconnection structure 300F).

[0133] As shown in FIG. 5A, the RF transistor amplifier 200F includes an RF input section 201, a preamplifier 202, an inter-stage impedance matching network 204, a main amplifier 206, and an RF output section 209. Although not shown in FIGS. 5A to 5C, the RF transistor amplifier 200F may further include an input matching network disposed between the RF input section 201 and the preamplifier 202, and / or an output matching network disposed between the main amplifier 206 and the RF output section 209. When included, the input matching network and / or the output matching network may be implemented, for example, on or inside the interconnection structure 300F of the RF transistor amplifier 200F.

[0134] As shown in FIG. 5B, the RF transistor amplifier die 210F included in the RF transistor amplifier 200F is divided into a plurality of zones 260-1 to 260-4. As described above, each zone 260 includes a plurality of unit cell transistors 216. The unit cell transistors of a specific zone 260 may be connected to the corresponding gate manifold 242 and the corresponding drain manifold 244. The gate manifold 242 may be connected to the respective gate terminals 222, and the gate terminals 222 themselves may be coupled to the respective gate interconnect pads 372 on the interconnection structure 300F via the respective gate connection pads 272. Similarly, the drain manifold 244 may be connected to the respective drain terminals 224, and the drain terminals 224 themselves may be coupled to the respective drain interconnect pads 374 on the interconnection structure 300F via the respective drain connection pads 274. Therefore, an RF signal input to a specific gate interconnect pad 372 is amplified by the corresponding zone 260 of the RF transistor amplifier die 210F, and the amplified signal is output to a specific drain interconnect pad 374.

[0135] FIG. 5C shows how different zones 260-1 to 260-4 of an RF transistor amplifier die 210F may be configured to provide the RF transistor amplifier 200F of FIG. 5A including a preamplifier 202, an inter-stage impedance matching network 204, and a main amplifier 206 using one RF transistor amplifier die 210F. In particular, as shown in FIG. 5C, the RF transistor amplifier die 210F is mounted on an interconnect structure 300F. The RF input section 201 may be implemented on the interconnect structure 300F. The interconnect structure 300F may include a conductive structure 320-1 that electrically connects the RF input section 201 to a gate interconnect pad 372-1. As described above, the gate interconnect pad 372-1 may be electrically connected to a first zone 260-1 of the RF transistor amplifier die 210F. The first zone 260-1 of the RF transistor amplifier die 210F may implement the preamplifier 202 and may amplify the RF signal input to the RF input section 201. The first zone 260-1 may output the amplified RF signal to a drain interconnect pad 374-1. The conductive structure 320-2 on the interconnect structure 300F may electrically connect the drain interconnect pad 374-1 to the inter-stage impedance matching network 204.

[0136] The inter-stage impedance matching network 204 may include inductors and / or capacitors arranged in any suitable configuration to form a circuit that improves impedance matching, for example, between the output of the preamplifier 202 and the input of the main amplifier 206. The capacitors may be implemented, for example, as surface-mounted components on the interconnect structure 300F or as plates or interdigitated finger capacitors implemented within the interconnect structure 300F. The inductors may be implemented, for example, as surface-mounted components on the interconnect structure 300F, as bond wires, or as elongated and / or narrowed conductive trace segments (which may have a spiral configuration) on or within the interconnect structure 300F.

[0137] The conductive structures 320-3 on and / or within the interconnect structure 300F may be electrically connected to the gate interconnect pads 372-2 to 372-4 that electrically connect the output of the inter-stage impedance matching network 204 to the zones 260-2 to 260-4 of the RF transistor amplifier die 210F. The zones 260-2 to 260-4 form the main amplifier 206 of FIG. 5A. The zones 260-2 to 260-4 may be electrically connected to each other in parallel and may be electrically connected to the zone 260-1 in series. The RF signal amplified by the preamplifier 202 may be input to the zones 260-2 to 260-4, where the RF signal is further amplified. The amplified RF signal output by the main amplifier 206 is sent to the drain interconnect pads 374-2 to 374-4, and the conductive structure 320-4 carries the amplified RF signal to the RF output section 209 that may include pads on the interconnect structure 300F.

[0138] FIGS. 5A to 5C show one example of how a multi-zone RF transistor amplifier die according to an embodiment of the present invention may be used to implement an amplifier circuit including a number of individual amplifiers. FIGS. 6A to 6C are similar diagrams showing the implementation of another example of an amplifier circuit including a number of individual amplifiers.

[0139] First, referring to FIG. 6A, an RF transistor amplifier 200G including an RF input section 201, a pair of preamplifiers 202-1 and 202-2, a pair of inter-stage impedance matching networks 204-1 and 204-2, a pair of main amplifiers 206-1 and 206-2, and an RF output section 209 is shown. The preamplifier 202-1 and the main amplifier 206-1 (which are electrically connected in series) are electrically arranged in parallel with the preamplifier 202-2 and the main amplifier 206-2 (which are electrically connected in series). Similar to the RF transistor amplifier 200F of FIGS. 5A to 5C, the RF transistor amplifier 200G may further include an input matching network arranged between the RF input section 201 and the preamplifiers 202-1 and 202-2, and / or an output matching network arranged between the main amplifiers 206-1 and 206-2 and the RF output section 209.

[0140] As shown in FIG. 6B, the RF transistor amplifier die included in the RF transistor amplifier 200G is divided into a total of eight zones 260-1 to 260-8 together with each zone 260. The unit cell transistors of each zone 260 are connected to the corresponding gate manifold 242 and the corresponding drain manifold 244. Each gate manifold 242 is connected to the respective gate terminal 222, and the gate terminal 222 itself is coupled to the respective gate interconnect pad 372 on the interconnect structure 300G via the respective gate connection pad 272. Similarly, each drain manifold 244 is connected to the respective drain terminal 224, and the drain terminal 244 itself is coupled to the respective drain interconnect pad 374 on the interconnect structure 300G via the respective drain connection pad 274. Therefore, an RF signal input to a specific gate interconnect pad 372 is amplified by the corresponding zone 260 of the RF transistor amplifier die 210G, and the amplified signal is output to a specific drain interconnect pad 374.

[0141] FIG. 6C shows how different zones 260 of the RF transistor amplifier die 210G may be interconnected to implement the RF transistor amplifier 200G of FIG. 6A. As shown in FIG. 6C, the RF transistor amplifier die 210G is attached to an interconnection structure 300G that includes an RF input section 201 and an RF output section 209. The conductive structure 320-1 on the interconnection structure 300G electrically connects the RF input section 201 to the gate interconnection pads 372-1 and 372-8 to send the RF signal input to the RF transistor amplifier 200G to the preamplifiers 202-1, 202-2. The drain interconnection pad 374-1 is electrically connected to the first inter-stage impedance matching network 204-1 by the conductive structure 320-2 on the interconnection structure 300G, and the drain interconnection pad 374-8 is electrically connected to the second inter-stage impedance matching network 204-2 by the conductive structure 320-3 on the interconnection structure 300G. The inter-stage impedance matching networks 204-1, 204-2 may be similar or identical to the inter-stage impedance matching network 204, and thus further description thereof is omitted.

[0142] The conductive structure 320-4 on the 300G interconnection structure may electrically connect the output of the inter-stage impedance matching network 204-1 to the gate interconnection pads 372-2 to 372-4, and the conductive structure 320-5 on the 300G interconnection structure may electrically connect the output of the inter-stage impedance matching network 204-2 to the gate interconnection pads 372-5 to 372-7. Zones 260-2 to 260-4 of the RF transistor amplifier die 210G form the first main amplifier 206-1 in FIG. 5A, and zones 260-5 to 260-7 of the RF transistor amplifier die 210G form the second main amplifier 206-2 in FIG. 5A. The RF signal amplified by the main amplifier 206-1 is output to the drain interconnection pads 374-2 to 374-4, and the RF signal amplified by the main amplifier 206-2 is output to the drain interconnection pads 374-5 to 374-7. The drain interconnection pads 374-2 to 374-7 may be electrically connected to each other and may be connected to the RF output section 209 by the conductive structure 320-6 on the 300G interconnection structure.

[0143] According to a further embodiment of the present invention, a Doherty amplifier may be implemented using one RF transistor amplifier die. As is known in the art, a Doherty amplifier circuit includes first and second (or more) power-coupled amplifiers. The first amplifier is referred to as the "main" or "carrier" amplifier, and the second amplifier is referred to as the "peak" amplifier. The two amplifiers may be biased differently. For example, in one common Doherty amplifier implementation, the main amplifier may include a class AB or class B amplifier, while the peak amplifier may be a class C amplifier. When operating at a power level backed off from saturation, the Doherty amplifier may operate more efficiently than a balanced amplifier. The RF signal input to the Doherty amplifier is split (using a quadrature coupler), and the outputs of the two amplifiers are combined. The main amplifier is configured to be turned on first (i.e., at a lower input power level), and thus, at lower power levels, only the main amplifier operates. As the input power level is increased towards saturation, the peak amplifier is turned on, and the input RF signal is split between the main amplifier and the peak amplifier.

[0144] Figures 7A - 7C schematically illustrate a Doherty RF transistor amplifier 200H according to an embodiment of the present invention. As shown in Figure 7A, the Doherty RF transistor amplifier 200H includes an RF input section 201, an input splitter 203, a main amplifier 206, a peak amplifier 208, an output combiner 207, and an RF output section 209. The Doherty RF transistor amplifier 200H may optionally include an input matching network and / or an output matching network (not shown).

[0145] As shown in FIG. 7B, the RF transistor amplifier die 210H included in the RF transistor amplifier 200H is divided into a total of four zones 260-1 to 260-4, and each zone 260 is interconnected with respective gate interconnect pads 372 and respective drain interconnect pads 374. FIG. 7C shows how the input splitter 203 and the output combiner 207 may be implemented on the interconnect structure 300H of the RF transistor amplifier 200H, and how different zones 260 of the RF transistor amplifier die 210H may be interconnected to implement a Doherty amplifier. In the specific example shown in FIG. 7C, two zones 260 are used to implement the main amplifier 206, and two zones 260 are used to implement the peak amplifier 208.

[0146] In some embodiments, the RF transistor amplifier die 210H may include a significantly larger number of zones 260 (e.g., 20 zones). In such embodiments, different interconnection structures 300 may be provided that each electrically connect a different number of zones 260 to the main amplifier and the peak amplifiers 206, 208. For example, as schematically shown in FIG. 7D, a first interconnection structure 300I may electrically connect the first output of the input splitter 203 and the first input of the output combiner 207 to zones 260-1 to 260-10, and may electrically connect the second output of the input splitter 203 and the second input of the output combiner 207 to zones 260-11 to 260-20. As shown in FIG. 7E, a second interconnection structure 300J may electrically connect the first output of the input splitter 203 and the first input of the output combiner 207 to zones 260-1 to 260-12, and may electrically connect the second output of the input splitter 203 and the second input of the output combiner 207 to zones 260-13 to 260-20, whereby the main amplifier 206 may have a higher power handling capacity compared to the peak amplifier 208. Additional interconnection structures implementing other splits may be provided. Thereby, in order to provide a series of Doherty amplifiers, one RF transistor amplifier die 210H may be used in association with a set of interconnection structures. This is advantageous because it may be significantly easier to design and manufacture different interconnection structures compared to designing and manufacturing RF transistor amplifier dies that implement different power splits between the main amplifier and the peak amplifiers 206, 208.

[0147] The above-described technique may also be used to implement RF transistor amplifiers having other configurations.

[0148] For example, FIG. 8A is a circuit diagram of an RF transistor amplifier 200K having a common gate - common source or "CGCS" configuration. As shown in FIG. 8A, the RF transistor amplifier 200K includes a first "common gate" transistor amplifier 217 (i.e., the gate of the first transistor amplifier 217 is coupled to ground), a selective inter - stage impedance matching network 204, and a second "common source" transistor amplifier 219 (i.e., the source of the second transistor amplifier 219 is coupled to ground). The first stage of the RF transistor amplifier 200K functions as a trans - impedance amplifier and serves as a current buffer and a voltage amplifier for an RF input signal input at the source of the first common - gate transistor amplifier 217. The drain of the first common - gate transistor amplifier 217 may be DC - or AC - coupled to the gate of the second common - source transistor amplifier 219. As described above, in order to improve the performance in the target frequency band, the selective inter - stage impedance matching network 204 may be coupled between the drain of the first common - gate transistor amplifier 217 and the gate of the second common - source transistor amplifier 219. The RF transistor amplifier 200K may exhibit an improved impedance matching bandwidth and is also a potential method for implementing an enhancement - mode amplifier in a group - III nitride - on - SiC based material system.

[0149] FIG. 8B is a schematic diagram showing how the CGCS RF transistor amplifier 200K of FIG. 8A may be implemented according to an embodiment of the present invention. As shown in FIG. 8B, the CGCS RF transistor amplifier 200K includes an RF input section 201, a common - gate transistor amplifier 217, an inter - stage impedance matching network 204, a common - source transistor amplifier 219, and an RF output section 209. The CGCS RF transistor amplifier 200K may selectively include an input matching network and / or an output matching network (not shown).

[0150] As shown in FIG. 8B, the RF transistor amplifier die included in the RF transistor amplifier 200K is divided into a total of four zones 260-1 to 260-4. The first zone 260-1 may be used to implement the first common-gate transistor amplifier 217. To form the common-gate transistor amplifier 217, the RF input section 201 is coupled to the source interconnect pad 376-1, and the gate connection pad 372-1 is coupled to electrical ground. The drain interconnect pad 374-1 may be coupled to the input of the inter-stage impedance matching network 204. The output of the inter-stage impedance matching network 204 is coupled to a power splitter that supplies an output signal to the gate interconnect pads 372-2 to 372-4 for the three remaining zones 260-2 to 260-4. These zones are used to implement the second common-source transistor amplifier 219. The inter-stage impedance matching network 204 and the power splitter may be implemented, for example, on the interconnect structure 300K of the RF transistor amplifier 200K. The drain interconnect pads 374-2 to 374-4 of the second common-source transistor amplifier 219 are coupled to the RTF output section 209.

[0151] According to a further embodiment of the present invention, an RF transistor amplifier having one or more redundant amplifier circuits may be provided. These RF transistor amplifiers may include a multi-zone RF transistor amplifier die, and at least one of the zones may be designed as a redundant zone that is not initially used. These RF transistor amplifiers may further include an input and output switching network that may be used to bypass a zone that is not operating properly and switch to a circuit in place of the bypassed zone from the redundant zone. These RF transistor amplifiers may further include a detection circuit (not shown) that detects when a zone of the RF transistor amplifier die has failed or is otherwise not operating properly. Upon detection of such a failure, the input and output switching network may be configured to switch the operation from the failed zone of the circuit to the redundant zone. FIG. 9 is a schematic diagram of an RF transistor amplifier 200L according to an embodiment of the present invention that includes such a redundant amplifier circuit.

[0152] As shown in FIG. 9, the RF transistor amplifier 200L includes an RF transistor amplifier die 210L mounted on an interconnection structure 300L. The RF transistor amplifier die 210L is divided into four zones 260-1 to 260-4. Zones 260-1 to 260-3 are "main" zones that are used in the normal operation of the RF transistor amplifier die 210L. Zone 260-4 is a redundant zone that may be switched in place of zones 260-1 to 260-3 if a failure occurs in one or more of these zones 260-1 to 260-3.

[0153] The mutual connection structure 300L includes an input splitter 333, three switches 334-1 to 334-3, and an input combiner 336. The input splitter 333 may be connected to an RF input section 301 provided on the mutual connection structure 300L, and may split the RF signal received at the RF input section 201 into three sub-components output on the three output lines of the input splitter 333. Each output line of the input splitter 333 is connected to the respective RF switches 334-1 to 334-3 (e.g., by a conductive pattern 320 on the mutual connection structure 300L). Each RF switch 334 has a pair of output sections, and depending on the setting of the RF switch 334, outputs the RF signal received at the input section of the RF switch 334 to one of the two output sections. The first output section of the RF switch 334-1 is coupled to the zone 260-1, the first output section of the RF switch 334-2 is coupled to the zone 260-2, and the first output section of the RF switch 334-3 is coupled to the zone 260-3. The second output section of each RF switch 334 is coupled to the input combiner 336.

[0154] The RF signals sent to the zones 260-1 to 260-3 are amplified RF transistor amplifier dies 210L. In the illustrated embodiment, the amplified RF signals output by the zones 260-1 to 260-3 are supplied to the combiner 340. The output of the zone 260-4 is also sent to the combiner 340. The output section of the combiner 340 is coupled to an RF output section 308 on the mutual connection structure 300L.

[0155] During operation, initially each RF switch 334 is set to connect its input to the first output. As a result, the RF transistor amplifier die 210L operates with the first to third zones 260-1 to 260-3 electrically arranged in parallel between the RF input 301 and the RF output 308. The fourth zone 260-4 is isolated from the RF input 301 by the RF switch 334. When the above-described detection circuit detects that a fault has occurred in one of the zones 260-1 to 260-3 of the RF transistor amplifier die 210L (for example, the second zone 260-2), a control signal may be sent to the control input (not shown) of the RF switch 334-2 so that an RF signal is not sent to the faulty zone 260-2. The reset switch 334-2 also functions to arrange the fourth zone 260-4 in parallel with the first and third zones 260-1, 260-3 so that the fourth zone 260-4 effectively replaces the second zone 260-2. In this form, an RF transistor amplifier having an on-die redundant circuit may be provided.

[0156] In the illustrated embodiment, all four zones 260-1 to 260-4 are directly connected to the combiner 340, but in practice, it may be beneficial to add a switch between the zone output and the combiner 340. Three switches are set to send the amplified RF signal to the combiner 340, and the fourth switch is set to terminate the inactive zone 260 to ground.

[0157] Another problem that may occur as the RF transistor amplifier becomes larger is that it may be difficult to ensure that the RF input signal passes through each of the parallel amplification paths of the RF transistor amplifier having a relatively constant wavefront. In a conventional RF transistor amplifier, the RF signal may be input to the gate terminal of the RF transistor amplifier. The RF signal passes from the gate terminal to one or more gate manifolds that connect the gate terminal to the gate fingers of the amplifier. The RF signal may be input, for example, at the center of the gate terminal and then move along the gate terminal to a pillar or other conductive structure that connects the gate terminal to the gate manifold. Unfortunately, in this arrangement, the electrical length of the RF transmission path to each gate finger may vary, and the difference in electrical path length between the gate finger at the center of the RF transistor amplifier die and the gate finger located near the edge of the RF transistor amplifier die may become significant. As a result, the phase of the sub-component of the RF signal sent to each gate finger changes. As a result of this change, the combination of the amplified RF signals becomes incomplete. The same problem occurs conversely on the output side of the device when the amplified RF signals are combined and sent to the drain terminal.

[0158] According to an embodiment of the present invention, an RF transistor amplifier is provided that maintains substantially more stringent phase coherence between the gate fingers of an amplifier. FIG. 10 is a schematic diagram showing an RF transistor amplifier 200M according to an embodiment of the present invention having equal length RF transmission paths to each of a plurality of different zones of an RF transistor amplifier die to maintain better phase coherence. The following description relates to both the "physical" and "electrical" lengths of the RF transmission line. The physical length refers to the measured length of the RF transmission line. The electrical length refers to the length of the RF transmission line that an electrical signal traversing the RF transmission line experiences. As is known to those skilled in the art, the electrical length of an RF transmission line may vary, for example, based on the dielectric constant of the dielectric material adjacent to the conductive structure of the RF transmission line. Thus, for example, if different dielectric materials are used when forming an RF transmission line, two RF transmission lines having the same physical length may have different electrical lengths. To maintain phase coherence, the electrical lengths of the two RF transmission lines should be substantially the same. Here, "substantially" means ±5%.

[0159] As shown in FIG. 10, the RF transistor amplifier 200M includes an RF transistor amplifier die 210M mounted on an interconnect structure 300M. The RF transistor amplifier die 210M is mounted below the interconnect structure 300M in the schematic of FIG. 10 and is thus shown using a dashed line. The interconnect structure 300M has an RF input 301, a plurality of gate interconnect pads 372, a plurality of drain interconnect pads 374, and an RF output 308. A plurality of first transmission lines 361 connect the RF input to the respective gate interconnect pads 372, and a plurality of second transmission lines 363 connect the respective drain interconnect pads 374 to the RF output 308. Each gate interconnect pad 372 and the corresponding drain interconnect pad 374 are connected to a respective zone 260 of the RF transistor amplifier die 210M as described above.

[0160] As shown in FIG. 10, all the first transmission lines 361 may have substantially the same length, and all the second transmission lines 363 may have substantially the same length. As a result, sub-components of the RF signal input at the RF input section 301 may reach their respective gate interconnect pads 372 simultaneously (i.e., in phase). Similarly, the amplified RF signal output to the drain interconnect pads 374 may pass to the RF output section 308 in phase. Thus, each zone 260 of the multi-zone RF transistor amplifier die 210M may be individually supplied, and since the first and second transmission lines 361, 363 may be easily formed to have the same length, it may be easy to maintain good phase uniformity with respect to the RF signal passing through the RF transistor amplifier 200M. Further, this phase uniformity may be maintained even when the size of the RF transistor amplifier die 210M is increased.

[0161] The multi-zone RF transistor amplifier die may also make it easy to provide an RF transistor amplifier that may operate at an increased efficiency level. The higher efficiency level may be achieved by using only a subset of the zones 260 during lower power operation. FIGS. 11A and 11B schematically show an RF transistor amplifier 200N according to an embodiment of the present invention designed to adjust the number of zones 260 used based on, for example, the input or output power level of the RF transistor amplifier 200N.

[0162] FIG. 11A is a schematic diagram of an RF transistor amplifier 200N. As shown in FIG. 11A, the RF transistor amplifier 200N includes an RF transistor amplifier die 210N and an interconnection structure 300N. The RF transistor amplifier die 210N is divided into four zones 260-1 to 260-4 (corresponding to gate and drain interconnection pads 372-1, 374-1; 372-2, 374-2; 372-3, 374-3; 372-4, 374-4). The interconnection structure 300N includes an RF input section 301, an input switching network 342, gate interconnection pads 372-1 to 372-4, drain interconnection pads 374-1 to 374-4, an output switching network 344, and an RF output section 308. The input switching network 342 may include a matrix switch that can connect the RF input section 301 to any combination of one or more of the gate interconnection pads 372. The output switching network 344 may include a matrix switch that can connect the RF output section 308 to any combination of one or more of the drain interconnection pads 374. A power sensor or other circuit for determining the power of the RF signal (e.g., input power, output power, etc.) may be used to determine how the input switch 342 and the output switch 344 are set.

[0163] Instead of using the switching networks 342, 344, it may be possible to use instead a selected one of a plurality of different interconnection structures each having one RF transistor amplifier die to optimize the operation of the die. This is shown with reference to FIG. 11B.

[0164] In particular, referring to the upper diagram of FIG. 11B, when an RF transistor amplifier operating at a low power level is required, a first interconnect structure 300N-A may be used that is only wired to connect the RF input section 301 and the RF output section 308 to one zone (zone 260-2) of the RF transistor amplifier die 210N. Referring to the middle diagram of FIG. 11B, when an RF transistor amplifier die operating at an intermediate power level is required, a second interconnect structure 300N-B may be used that is sometimes wired to connect the RF input section 301 and the RF output section 308 to two of the zones (zones 260-2 and 260-3) of the RF transistor amplifier die 210N. Referring to the lower diagram of FIG. 11B, when an RF transistor amplifier die operating at a high power level is required, a third interconnect structure 300N-C may be used that is sometimes wired to connect the RF input section 301 and the RF output section 308 to all four zones 260-1 to 260-4 of the RF transistor amplifier die 210N. In this format, one RF transistor amplifier die 210N may be designed to operate efficiently in applications using a wide variety of different power levels.

[0165] The multi-zone RF transistor amplifier die according to the above-described embodiments of the present invention is shown for convenience as having the same number of gate terminals, drain terminals, and source terminals. However, it will be appreciated that the embodiments of the present invention are not limited thereto. For example, since the source terminals are typically connected to a common ground reference, any number of source terminals may be provided for many applications. Further, the number of gate terminals and drain terminals need not be the same. For example, depending on how the zones are interconnected via the interconnect structure, the number of gate terminals can be twice the number of drain terminals. Alternatively, the number of drain terminals may be more than the number of gate terminals.

[0166] The RF transistor amplifier according to an embodiment of the present invention may be partially or completely encapsulated in a packaging material together with leads or other contact structures that extend through the packaging to provide a packaged RF transistor amplifier. Any suitable packaging technique may be used. FIGS. 12A - 12D show a plurality of examples of different ways in which an RF transistor amplifier according to an embodiment of the present invention may be packaged.

[0167] In particular, FIG. 12A is a schematic cross - sectional view of a packaged RF transistor amplifier 400 that includes one of the RF transistor amplifiers according to an embodiment of the present invention (shown generally as 420 in FIG. 12A). As shown in FIG. 12A, the packaged RF transistor amplifier 400 includes a package 410, within which the RF transistor amplifier 420 is encapsulated.

[0168] The package 410 includes a ceramic package including a carrier substrate 430, sidewalls 440, and a lid 450, which together define an open cavity 460. The RF transistor amplifier 410 (including the interconnect structure 422) is disposed on the carrier substrate 430 within the open cavity 460.

[0169] The carrier substrate 430 may include materials configured to assist in the thermal management of the package 410. For example, the carrier substrate 430 may include copper and / or molybdenum. In some embodiments, the carrier substrate 430 may consist of multiple layers and / or may include vias / interconnections. In an exemplary embodiment, the carrier substrate 430 may be a multi-layer copper / molybdenum / copper metal flange including a core molybdenum layer with a copper coating layer on either of its main surfaces. The sidewalls 440 and / or the lid 450 may be formed of or may include an insulating material in some embodiments. For example, the sidewalls 440 and / or the lid 450 may be formed of or may include a ceramic material. In some embodiments, the sidewalls 440 and / or the lid 450 may be formed of, for example, Al2O3. The lid 450 may be adhered to the sidewalls 440 using an epoxy adhesive. The sidewalls 440 may be attached to the carrier substrate 430, for example, via brazing. The leads 470-1, 470-2 may be configured to extend through the sidewalls 440, but the embodiments of the present invention are not limited thereto. The leads 470 may be coupled to the interconnect structure 422 using, for example, a conductive die attach material. In the illustrated embodiment, the leads 470 are connected to the interconnect structure 422 without using any wire bonds.

[0170] FIG. 12B is a schematic cross-sectional view of a packaged RF transistor amplifier 500 including one of the RF transistor amplifiers (shown generally at 520 in FIG. 12B) according to an embodiment of the present invention in an overmolded plastic package. The packaged RF transistor amplifier 500 includes a package 510 in which the RF transistor amplifier 520 is encapsulated.

[0171] Package 500 includes a carrier substrate 530, leads 540-1, 540-2, and an overmold plastic material 550. An RF transistor amplifier 520 (including an interconnection structure 522) is disposed on the carrier substrate 530. The leads 540-1, 540-2 are connected to the interconnection structure 522 (in the same form as described above with reference to FIG. 12A, for example). The overmold material 550 may be a plastic or plastic polymer compound. The overmold material 550 is injection molded around the RF transistor amplifier 520 (including the interconnection structure 522), thereby providing protection from the external environment.

[0172] The carrier substrate 530 of the package 500 may include a material configured to assist in thermal management. For example, the carrier substrate 530 may include copper and / or molybdenum. In some embodiments, the carrier substrate 530 may consist of multiple layers and / or include vias / interconnections. In some embodiments, the carrier substrate 530 may include a metal heat sink that is part of a lead frame or metal slug that is at least partially surrounded by the plastic overmold plastic 550.

[0173] As shown in FIG. 12C, in other embodiments, only the RF transistor amplifier die and the coupling elements may be encapsulated within the overmold plastic material, and pads or other structures on the interconnection structure 522 may function as leads for the RF transistor amplifier. As shown in FIG. 12D, in still other embodiments, all three of the RF transistor amplifier die 520, the coupling element 524, and the interconnection structure 522 may be encapsulated. Openings may be formed in the encapsulating material to provide access to various terminals of the device (e.g., RF input terminals, RF output terminals, ground terminals, via voltage terminals, etc.).

[0174] It will be appreciated that any of the RF transistor amplifiers according to the embodiments of the invention described herein may be attached to a package such as the packages shown in FIGS. 12A-12D.

[0175] Examples of the concepts of the present invention have been described above with reference to the accompanying drawings in which examples of the invention are shown. However, the concepts of this invention may be embodied in many different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the concepts of the invention to those skilled in the art. The same numbers refer to the same elements throughout.

[0176] Terms such as first, second, etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0177] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the terms "comprises," "comprising," "includes," and / or "including" indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0178] When an element such as a layer, region, or substrate is described as being "on" or extending "onto" another element, it will be understood that it can be directly on or extend directly onto the other element, or intervening elements may be present. In contrast, when an element is described as being "directly on" or extending "directly onto" another element, no intervening elements are present. When an element is described as being "connected" or "coupled" to another element, it will be understood that it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0179] Relative terms such as "under", "on", "upper", "lower", "horizontal", "lateral", or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the drawings.

[0180] In the drawings and the specification, typical embodiments of the invention are disclosed and specific terms are used, but these terms are used only in a general and descriptive sense and not for purposes of limitation, and the scope of the invention is set forth in the following claims.

Claims

Claim 1 A radio frequency (RF) transistor amplifier comprising a group III nitride-based semiconductor layer structure, and an RF transistor amplifier die having a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal, each on an upper surface of the semiconductor layer structure an interconnection structure on an upper surface of the RF transistor amplifier die coupling elements between the RF transistor amplifier die and the interconnection structure for electrically connecting the plurality of gate terminals, the plurality of drain terminals, and the at least one source terminal to the interconnection structure wherein the RF transistor amplifier die is divided into a plurality of zones, each of the plurality of zones including a plurality of unit cell transistors the interconnection structure includes an inter-stage impedance matching network a radio frequency (RF) transistor amplifier, wherein the unit cell transistors of a first zone of the plurality of zones are electrically coupled in series via the inter-stage impedance matching network to the unit cell transistors of a second zone of the plurality of zones

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