Apparatus and method for vapor deposition and etching during gap filling

Abstract

To provide an apparatus and a method for executing deposition processing and etching processing in an integrated tool.SOLUTION: An apparatus 400a comprises: a capacitively-coupled plasma (CCP) reactor 424 that is a plasma processing chamber, and the CCP reactor includes a showerhead 414 that functions as a top electrode and a pedestal 418 that functions as a bottom electrode. In the apparatus, an RF power supply 402 that is an RF generator supplies power to the top electrode in a deposition mode and supplies power to the bottom electrode in an etching mode. The apparatus may include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in the deposition mode, and the HFRF generator and an LFRF generator are electrically connected to the pedestal and the showerhead is grounded in the etching mode.SELECTED DRAWING: Figure 4A

Description

Background Art

[0001] The manufacture of integrated circuits involves many different processing steps. One of the frequently used operations is the deposition of a dielectric film into the gaps between features patterned on or in a semiconductor wafer. One of the goals when depositing such a material is to form a void - and seam - free fill within the gaps.

[0002] Deposition methods such as high - density plasma (HDP), sub - atmospheric chemical vapor deposition (SACVD), and low - pressure chemical vapor deposition (LPCVD) have been used for gap filling, but these methods do not achieve the desired filling ability and conformality. Flowable chemical vapor deposition and spin - on dielectric (SOD) methods can achieve the desired fill, but tend to deposit very porous films. Furthermore, these methods require many extra processing steps and are thus particularly complex and costly in terms of integration. Atomic layer deposition (ALD) processes have also been used for gap filling to improve conformality, but these processes have the problem of long processing times and low throughput, especially for relatively large gaps. Furthermore, the conformal nature of ALD processes means that the aspect ratio of the gap increases with successive cycles. Thus, the top of the gap is filled more rapidly than the bottom, preventing further diffusion of the precursor material into the gap. Regions can expand such that voids can be formed in the center of high - aspect - ratio gaps.

[0003] In some examples, multi - step deposition processes are used, such as deposition - etching - deposition processes that require different etching operations between successive deposition operations. Etching can be performed to repair or prevent void formation in the gaps. Specifically, the etching step can be anisotropic etching that forms a tapered positive - slope profile so that gap filling can occur by depositing the next layer on a tapered rather than a vertical - slope. This can minimize the occurrence of void formation in the gaps. Voids can lead to high resistance, contamination, loss of filled material, and other performance degradations of the integrated circuit.

Summary of the Invention

[0004] The present disclosure relates to an integrated apparatus for performing vapor deposition processing and etching processing. The integrated apparatus includes a processing chamber, and the processing chamber includes a showerhead and a pedestal. The integrated apparatus further includes a low-frequency radio frequency (LFRF) generator, a high-frequency radio frequency (HFRF) generator, and one or more switches operably connected to one or both of the LFRF generator and the HFRF generator. The one or more switches are configured to switch between (1) a vapor deposition mode for performing vapor deposition processing (at this time, one or more switches in the vapor deposition mode connect at least the HFRF generator to the showerhead) and (2) an etching mode for performing etching processing (at this time, one or more switches in the etching mode connect the HFRF generator and the LFRF generator to the pedestal and ground the showerhead).

[0005] In some embodiments, the processing chamber is a capacitively coupled plasma (CCP) reactor, the showerhead comprises an upper electrode, and the pedestal comprises a lower electrode. In some embodiments, one or more switches in the deposition mode connect the HF RF generator and the LF RF generator to the showerhead and ground the pedestal. In some embodiments, the one or more switches include a first station relay switch configured to electrically connect the LF RF generator and the HF RF generator to the showerhead in the deposition mode, and a second station relay switch configured to electrically connect the LF RF generator and the HF RF generator to the pedestal in the etching mode. In some embodiments, the first station relay switch is configured to switch to a first position for electrically connecting the LF RF generator and the HF RF generator to the showerhead and to a second position for grounding the showerhead, and the second station relay switch is configured to switch to a first position for electrically connecting the LF RF generator and the HF RF generator to the pedestal and to a second position for grounding the pedestal, the first position of the first station relay switch being synchronized with the second position of the second station relay switch, and the first position of the second station relay switch being synchronized with the second position of the first station relay switch. In some embodiments, the LF RF generator is part of a first integrated circuit board and the HF RF generator is part of a second integrated circuit board. In some embodiments, the one or more switches include a switch operably connected to the HF RF generator and configured to switch between supplying power from the HF RF generator to the showerhead in the deposition mode and supplying power from the HF RF generator to the pedestal in the etching mode.

[0006] Furthermore, the present disclosure relates to an integrated apparatus for performing vapor deposition processing and etching processing. The integrated apparatus includes a processing chamber, and the processing chamber includes a shower head and a pedestal. The integrated apparatus further includes an integrated circuit board, and the integrated circuit board includes one or more HF / LFRF generators. The integrated apparatus further includes one or more switches operably connected to the one or more HF / LFRF generators, and the one or more switches are configured to switch between (1) a vapor deposition mode for performing vapor deposition processing (at this time, at least one of the one or more switches in the vapor deposition mode connects at least one of the HF / LFRF generators to the shower head) and (2) an etching mode for performing etching processing (at this time, at least one of the one or more switches in the etching mode connects at least one of the HF / LFRF generators to the pedestal).

[0007] In some embodiments, the processing chamber is a CCP reactor, the showerhead comprises an upper electrode, and the pedestal comprises a lower electrode. In some embodiments, the integrated circuit board comprises one HF / LFRF generator. In some embodiments, the one or more switches include a first station relay switch configured to electrically connect one of the HF / LFRF generators to the showerhead in a deposition mode and a second station relay switch configured to electrically connect one of the HF / LFRF generators to the pedestal in an etching mode. In some embodiments, the first station relay switch is configured to switch to a first position for electrically connecting one of the HF / LFRF generators to the showerhead in a deposition mode and to a second position for grounding the showerhead, and the second station relay switch is configured to switch to a first position for electrically connecting one of the HF / LFRF generators to the pedestal in an etching mode and to a second position for grounding the pedestal. The first position of the first station relay switch is synchronized with the second position of the second station relay switch, and the first position of the second station relay switch is synchronized with the second position of the first station relay switch. In some embodiments, the one or more switches further include a pedestal ground relay switch for grounding the pedestal in a deposition mode when one of the HF / LFRF generators is operably connected to the showerhead and a showerhead ground relay switch for grounding the showerhead in an etching mode when one of the HF / LFRF generators is operably connected to the pedestal.

[0008] Also, the present disclosure relates to a method for filling one or more gaps in a wafer. The method includes: preparing a wafer having one or more gaps each having a depth-to-width aspect ratio greater than about 5:1 on a pedestal in a plasma processing chamber; depositing a first dielectric layer into the one or more gaps using ALD in the plasma processing chamber; slope controlling and anisotropically etching the first dielectric layer in the plasma processing chamber; and depositing a second dielectric layer into the one or more gaps above the first dielectric layer using ALD in the plasma processing chamber.

[0009] In some embodiments, the wafer temperature during deposition of the first dielectric layer, during slope control and anisotropic etching of the first dielectric layer, and during deposition of the second dielectric layer is between about 80°C and about 400°C. In some embodiments, the pressure during deposition of the first dielectric layer, during slope control and anisotropic etching of the first dielectric layer, and during deposition of the second dielectric layer is between about 0.3 and about 1.0 Torr. In some embodiments, the method further includes switching to apply low-frequency power and high-frequency power to the pedestal in the plasma processing chamber and ground the showerhead in the plasma processing chamber before slope controlling and anisotropically etching the first dielectric layer, and switching to apply high-frequency power to the showerhead in the plasma processing chamber and ground the pedestal in the plasma processing chamber before depositing the second dielectric layer.

[0010] These embodiments and other embodiments will be further described below with reference to the drawings.

Brief Description of the Drawings

[0011]

FIG. 1A

FIG. 1B

FIG. 1C

[0012]

FIG. 2

[0013]

FIG. 3

[0014]

FIG. 4A

[0015]

FIG. 4B

[0016]

FIG. 5

[0017]

FIG. 6

[0018]

FIG. 7

[0019]

FIG. 8

[0020]

FIG. 9A

[0021]

FIG. 9B

[0022]

FIG. 10

DETAILED DESCRIPTION OF THE INVENTION

[0023] Introduction: In the following description, numerous specific details are set forth in order to facilitate a thorough understanding of the presented concepts. The presented concepts may be practiced without some or all of these specific details. Also, in order to avoid unnecessarily obscuring the described concepts, detailed descriptions of well-known processing operations are omitted. It should be understood that some concepts are described in the context of specific embodiments, but these embodiments are not intended to be limiting.

[0024] In this application, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "integrated circuit in process" are used interchangeably. One skilled in the art will understand that the term "integrated circuit in process" can refer to a silicon wafer in the middle of any of many stages of integrated circuit processing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. In the following detailed description, it is assumed that the present invention is implemented on a wafer. However, the present invention is not limited thereto. The workpiece may have various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present invention include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, and microelectromechanical elements.

[0025] As circuit density increases in the semiconductor industry, the width of gaps or trenches in the wafer decreases, resulting in a higher aspect ratio, and it is becoming increasingly difficult to fill the gaps or trenches without leaving voids. The formation of voids when the gap is not completely filled can affect the operation of the completed device.

[0026] A deposition-etching-deposition sequence is used to repair or eliminate the presence of voids in gap filling. Common deposition techniques used in the deposition-etching-deposition sequence are ALD, CVD, plasma CVD, and HDP-CVD. After the deposition process, an etching process may follow, such as sputter etching in an HDP application example or reactive ion etching (RIE) in an ALD application example. The etching process may be an anisotropic etching process that forms a tapered positive slope profile. As a result, more material can be removed near the gap opening than inside the gap.

[0027] Figures 1A - 1C are cross - sectional views showing examples of wafers with gaps at various stages of a deposition - etching - deposition gap filling process. Figure 1A shows a cross - sectional view of a non - planar wafer 100 including a gap 102. The gap width can vary according to various embodiments and can be in the range of about 5 Å to about 50 μm. The depth - to - width aspect ratio can be greater than about 2:1, greater than about 5:1, greater than about 10:1, or greater than about 30:1. The gap 102 can be coated with a thin film 104 using any suitable deposition technique such as ALD, CVD, plasma CVD, and HDP - CVD. In some embodiments, the thin film 104 can be conformal or substantially conformal with the gap 102. As shown in Figure 1A, the thin film 104 has a re - entrant portion 106 near the top of the gap 102.

[0028] In Figure 1B, anisotropic etching is performed on the thin film 104. The re - entrant portion 106 of the thin film 104 can be selectively removed by anisotropic etching such that the upper region 104a of the thin film 104 is thinner than the lower region 104b. For example, anisotropic etching can be achieved by imposing mass - transfer limitations and / or lifetime limitations on the active etching species. In some examples, the selective etching at the top of the gap 102 can also adjust the side - wall angle of the gap 102, such that the gap 102 is wider at the top than at the bottom. This can further reduce the bread - loafing effect in subsequent deposition steps.

[0029] In Figure 1C, the next deposition step is performed to fill or substantially fill the gap 102. In some examples, the gap 102 can be filled after multiple deposition - etching - deposition sequences. The gap 102 can be void - free. The gap 102 can be filled using any suitable deposition technique such as ALD, CVD, plasma CVD, HDP - CVD, etc.

[0030] A general gap filling process may utilize an HDP-CVD system. The HDP-CVD system can form a plasma having a density at least about two orders of magnitude greater than that of a standard CCP-CVD system. The HDP-CVD system is typically an inductively coupled plasma (ICP) system. An example of an HDP-CVD system equipped with an ICP reactor for achieving deposition and etching is the Speed™ system manufactured by Lam Research Corporation of Fremont, California. Some HDP-CVD techniques promote sputtering by a high density plasma that can occur simultaneously with film deposition. As a result, the sputtering component of the HDP deposition process slows the deposition of certain features (such as corners or raised surfaces), so that deposition and etching occur simultaneously, thereby contributing to improved gap filling. However, sputtering in such HDP-CVD techniques can lead to undesirable redeposition of material on the sidewalls of the gap. Some HDP-CVD techniques may utilize separate deposition and etching steps. During the etching step, material can be removed non-conformally by anisotropic sputter etching. Corner material can be removed over a short distance along the sidewalls of the gap. However, such anisotropic sputter etching can create a redeposition cusp that can impede gap filling. The HDP-CVD technique can perform a gap filling process within a single chamber or apparatus, but the film deposited by the HDP-CVD technique is not conformal and can actually limit the application of a deposition-etching-deposition sequence performed within a single chamber or apparatus.

[0031] Considering the limitations of HDP-CVD techniques in performing gap filling, an ALD process may be used to improve conformality. In contrast to CVD processing, ALD processing deposits a film layer by layer using a surface-mediated deposition reaction. In some embodiments, the ALD process may be performed within a CCP system (such as the CCP system shown in FIG. 2). The CCP system may be capable of supplying high frequency RF power for generating a plasma. An example of such a CCP system is the Vector™ system manufactured by Lam Research Corporation of Fremont, California.

[0032] FIG. 2 is a schematic diagram showing an example of an apparatus for performing a deposition process in a conventional deposition-etching-deposition gap filling process. As shown in FIG. 2, apparatus 200 includes a processing chamber 224 that houses other components of apparatus 200 and functions to contain plasma. Processing chamber 224 includes a showerhead 214 for supplying a processing gas to processing chamber 224. A high frequency radio frequency (HFRF) generator 204 may be connected to an impedance matching circuit network 206 connected to showerhead 214. In some embodiments, a low frequency radio frequency (LFRF) generator 202 may be connected to an impedance matching circuit network 206 that connects to showerhead 214. The power and frequency supplied by impedance matching circuit network 306 are sufficient to generate plasma from the processing gas. In a typical process, the frequency generated by HFRF generator 204 is between about 2 and 60 MHz, such as 13.56 MHz or 27 MHz. The frequency generated by LFRF generator 202 is between about 250 and 400 kHz, such as 350 kHz or 400 kHz.

[0033] Processing chamber 224 further includes a wafer support, i.e., a pedestal 218. Pedestal 218 can support wafer 216. Pedestal 218 may include a chuck, forks, and / or lift pins for holding wafer 216 during and between processing. In some embodiments, the chuck may be an electrostatic chuck.

[0034] The processing gas is introduced through inlet 212. One or more source gas lines 210 may be connected to manifold 208. The processing gas may or may not be premixed. Appropriate valve operation and mass flow control mechanisms are utilized to ensure that the correct gas is supplied during deposition, etching, and other plasma processing operations. The processing gas may exit processing chamber 224 through outlet 222. Typically, a vacuum pump 226 can draw out the processing gas and maintain an appropriate low pressure within processing chamber 224.

[0035] As shown in FIG. 2, apparatus 200 is a capacitor type system where showerhead 214 is an electrode that cooperates with ground block 220. In other words, apparatus 200 is a CCP system and may be capable of supplying high frequency RF power to the top of process chamber 224, i.e., showerhead 214. The bottom of process chamber 224, i.e., pedestal 218 and block 220, are grounded.

[0036] One or more apparatuses (such as apparatus 200) for performing an evaporation-etching-evaporation sequence may be implemented within a multi-station processing tool. FIG. 3 is a schematic diagram showing an example of a multi-station processing tool. Multi-station processing tool 300 may include an inlet load lock 302 and an outlet load lock 304, and one or both of the load locks may include a plasma source. A robot 306 under atmospheric pressure is configured to move wafers from a cassette loaded through pod 308 into inlet load lock 302 through atmospheric port 310. The wafer is placed on pedestal 312 within inlet load lock 302 by robot 306, atmospheric port 310 is closed, and load lock 302 is pumped down. If inlet load lock 302 includes a plasma source, the wafer may be plasma processed within load lock 312 before being introduced into process chamber 314. Further, the wafer may be heated within inlet load lock 302, for example, to remove moisture and adsorbed gases. Next, chamber transfer port 316 to process chamber 314 is opened, and another robot (not shown) places the wafer into the reactor for processing and positions it on the pedestal of the first station shown within the reactor. The embodiment shown in FIG. 3 includes load locks, but it can be seen that in some embodiments, wafers may be placed directly into the processing station.

[0037] The processing chamber 314 of the figure includes four processing stations numbered from 1 to 4 in the embodiment shown in FIG. 3. Each station may have a heated pedestal (shown as 318 for station 1) and a gas line inlet. It can be seen that in some embodiments, each processing station may have different purposes, i.e., multiple purposes. For example, in some embodiments, one processing station may be switchable between an ALD mode and a PECVD mode. As will be described later according to the present disclosure, in some embodiments, the processing station may include a CCP reactor switchable between a deposition mode and an etching mode. Although the processing chamber 314 of the figure includes four stations, it can be seen that the processing chamber 314 according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber 314 may have 5 or more stations, and in other embodiments, the processing chamber 314 may have 3 or fewer stations.

[0038] FIG. 3 further shows a wafer handling system 390 for moving wafers within the processing chamber 314. In some embodiments, the wafer handling system 390 can move wafers between various processing stations and / or between a processing station and a load lock. It can be seen that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handler robot. FIG. 3 further shows a system controller 350 used to control the processing conditions and hardware state of the multi-station processing tool 300. The system controller 350 may include one or more memory devices 356, one or more mass storage devices 354, and one or more processors 352. The processor 352 may include a CPU or a computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0039] In some embodiments, system controller 350 controls all operations of multi-station processing tool 300. System controller 350 executes system control software 358 that is stored in mass storage device 354, loaded into memory device 356, and executed by processor 352. System control software 358 may include instructions for controlling timing; gas mixing; chamber and / or station pressure; chamber and / or station temperature; purge conditions and timing; wafer temperature; RF power level; RF (radio frequency) frequency; wafer and / or pedestal position; switching between deposition mode and etching mode; and other parameters of specific processes performed by multi-station processing tool 300. System control software 358 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components necessary to perform the processes of various process tools according to the disclosed methods. System control software 358 may be coded in any suitable computer-readable program language.

[0040] In some embodiments, system control software 358 may include input / output control (IOC) sequence instructions for controlling various parameters. For example, each stage of an ALD process may include one or more instructions for execution by system controller 350. Further, switching from a deposition mode to an etching mode may include one or more instructions for execution by system controller 350. Instructions for setting the process conditions of an ALD process may be included in the corresponding ALD stage, and instructions for setting the process conditions of an anisotropic etching process may be included in the corresponding etching recipe stage. In some examples, the ALD and etching recipe stages may be arranged sequentially.

[0041] In some embodiments, other computer software and / or programs stored in the mass storage device 354 and / or the memory device 356 associated with the system controller 350 may be used. Examples of programs or program sections for this purpose include a wafer positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0042] The wafer positioning program may include program code for a processing tool component used to load a wafer onto the pedestal 318 and control the spacing between the wafer and other components of the processing tool 300.

[0043] The process gas control program may include code for flowing gas into one or more processing stations prior to deposition to control the gas composition and flow rate and, optionally, to stabilize the pressure within the processing station. The pressure control program may include code for controlling the pressure within the processing station, for example, by adjusting the throttle valve of the exhaust system of the processing station, the gas flow rate to the processing station, and the like.

[0044] The heater control program may include code for controlling the current to a heating unit used to heat the wafer. Alternatively, the heater control program may control the supply of a heat transfer gas (such as helium) to the wafer.

[0045] The plasma control program may include code for setting the RF power level applied to the processing electrodes within one or more processing stations.

[0046] In some embodiments, there may be a user interface associated with the system controller 350. The user interface may include a display screen (graphical software display of the apparatus and / or processing conditions) and a user input device such as a pointing device, keyboard, touch screen, microphone, etc.

[0047] In some embodiments, the parameters adjusted by the system controller 350 may relate to processing conditions. Non-limiting examples include the composition and flow rate of the processing gas, deposition and etching modes, wafer temperature, pressure, plasma conditions (such as RF power level), etc. These parameters may be provided to the user in the form of a recipe and may be input using the user interface.

[0048] Signals for monitoring the process may be provided from various process tool sensors to the analog and / or digital input connections of the system controller 350. Signals for controlling the process may be output at the analog and digital output connections of the multi-station process tool 300. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback algorithms and control algorithms may be used with the data from these sensors to maintain the processing conditions.

[0049] The system controller 350 may provide program instructions for performing the disclosed processes, such as deposition-etching-deposition gap filling processes. The program instructions may control various processing parameters such as DC power level, RF power level, RF bias power level, pressure, wafer temperature, etc. The instructions may control the parameters to operate the deposition-etching-deposition sequence according to the various embodiments described herein.

[0050] Deposition mode and etching mode: Typically, deposition in a CCP reactor may be performed with a certain hardware configuration, and etching in a CCP reactor may be performed with a different hardware configuration. Specifically, ALD in a CCP reactor may be optimized according to a certain RF hardware configuration, and etching in a CCP reactor may be optimized according to a different RF hardware configuration. FIGS. 4A and 4B show different RF hardware configurations for performing deposition and etching in a CCP reactor. In FIG. 4A, the wafer is supported on the grounded electrode for deposition and powered to the upper electrode. In FIG. 4B, the wafer is supported on the powered electrode for etching and the upper electrode is grounded.

[0051] FIG. 4A is a schematic diagram showing an example of an apparatus including a CCP reactor for performing a deposition process. Apparatus 400a includes a CCP reactor 424 capable of performing PECVD or ALD. CCP reactor 424 includes a showerhead 414 functioning as an upper electrode and a pedestal 418 functioning as a lower electrode. Pedestal 418 is opposed below the showerhead and can support the wafer 416 to be processed. In some embodiments, wafer 416 may have one or more features, and as a result, wafer 416 is non-planar. For example, wafer 416 may have one or more gaps or a plurality of gaps. In some embodiments, pedestal 418 may be raised and lowered. The process gas is introduced into showerhead 414 through gas inlet 412, and showerhead 414 distributes the process gas toward wafer 416 within CCP reactor 424. RF power source 402 may be electrically connected to showerhead 414 to generate plasma 430a in the space between showerhead 414 and wafer 416. Plasma 430a in the hardware configuration of FIG. 4A may be optimized for deposition. In some embodiments, the plasma energy can be controlled by controlling one or more of the chamber pressure, gas concentration, gas mixture, RF source power, RF source frequency, duty cycle, pulse frequency, etc.

[0052] FIG. 4A shows an example of an RF hardware configuration for vapor deposition, where the RF power supply 402 may be an HF RF generator electrically connected to the shower head 414, and the pedestal 418 is grounded. The RF hardware configuration of FIG. 4A generally produces an insufficient voltage drop across the wafer 416 and thus cannot provide a sufficient etching rate. However, the RF hardware configuration of FIG. 4A enables fast frequency tuning, which may be important for ALD applications.

[0053] High-speed frequency adjustment enables impedance matching to be performed quickly in the RF hardware configuration of FIG. 4A. Impedance matching is an operation of designing the input impedance of an electrical load or the output impedance of a corresponding signal source in order to maximize power transfer and minimize reflections from the load. In the context of plasma processing, impedance matching is used to minimize the reflected power returning from the plasma discharge to the transmission line (e.g., RF cable) and to maximize the power transmitted from the RF power source 402 to the plasma discharge. Further, if the RF power source 402 is not matched, there is reflected power that generates a standing wave in the transmission line between the power source (RF power source 402) and the load (plasma 430a), leading to further power waste and potentially causing frequency-dependent losses. In some embodiments, an impedance matching network (not shown) may be connected to the RF power source 402. The impedance matching network can convert the load impedance indicated by the plasma 430a to match the source impedance of the RF power source 402. Typically, the impedance matching network may include one or more capacitors or inductors to adjust the impedance of the RF power source 402 to match the plasma impedance. However, adjusting the impedance using capacitors or inductors can be a long process and may not be desirable for applications that require a short plasma time as expected. For example, for operation within an ALD window, the process can be on the order of 0.5 seconds or less. Therefore, impedance matching can be performed by simply switching the frequency of the RF power source 402 rather than using impedance matching with capacitors or inductors. To explain, if the impedance of the RF power source 402 needs to match the plasma impedance at 50 ohms, the RF power source 402 can quickly switch from operating at 13.56 MHz to 13.8 MHz. This type of high-speed frequency adjustment may not be possible in other RF hardware configurations (such as those shown in FIG. 4B).

[0054] Figure 4B is a schematic diagram showing an example of an apparatus including a CCP reactor for performing an etching process. Apparatus 400b includes a CCP reactor 424 capable of performing plasma etching. Similar to apparatus 400a of Figure 4A, apparatus 400b of Figure 4B includes a showerhead 414, a pedestal 418, a wafer 416, and a gas inlet 412. RF power supplies 404, 406 may be electrically connected to pedestal 418 to apply a voltage drop to wafer 416. RF power supplies 404, 406 may include both an LFRF generator 404 and an HFRF generator 406. Plasma 430b may be generated in the space between showerhead 414 and wafer 416. Plasma 430b in the hardware configuration of Figure 4B may be optimized for etching.

[0055] Figure 4B shows an example of an RF hardware configuration for etching, where the LFRF generator 404 and the HFRF generator 406 may be electrically connected to the pedestal 418 and the showerhead 414 is grounded. In some embodiments, the LFRF generator 404 may be a low-frequency radio frequency (RF) signal between about 2 Hz and about 1000 kHz, for example, a signal of 400 kHz. In some embodiments, the HFRF generator 406 may be a high-frequency RF signal between about 1 MHz and about 100 MHz, for example, a signal of 13.56 MHz. A blocking capacitor 432 may be disposed between the pedestal 418 and both the LFRF generator 404 and the HFRF generator 406. In a state where both the high-frequency signal and the low-frequency signal are mixed, the blocking capacitor 432 may function as a filter connected to the pedestal 418. The RF configuration of Figure 4B cannot perform fast frequency adjustment. This is due in part to the number of components in the RF path that prevent the fast response required for frequency adjustment. Therefore, the ALD process generally cannot operate under such conditions when the pedestal 418 is biased in Figure 4B. However, unlike the RF configuration of Figure 4A, the RF configuration of Figure 4B can provide a high voltage drop across the wafer 416.

[0056] Deposition-etching-deposition integrated apparatus: Rather than performing deposition and etching with an RF hardware configuration that is optimal for one process but not for others, and rather than constantly moving wafers from one device to another device to perform a deposition-etching-deposition sequence, the present disclosure provides an integrated device that is optimal for both deposition and etching and integrates a deposition-etching-deposition sequence in a single device. The integrated device can provide an RF hardware configuration that is optimal for both deposition mode and etching mode using a combination of different hardware components such as a release switch, a DO bit switch, an integrated circuit board (e.g., a splitter board), an RF generator, a coaxial cable, a switch box, an RF filter, a matching unit, etc.

[0057] FIG. 5 is a schematic diagram showing an example of an integrated apparatus including a plasma processing chamber configured to switch between a deposition mode and an etching mode. The integrated apparatus 500 includes a plasma processing chamber 524, where the plasma processing chamber 524 includes a showerhead 514 for supplying a processing gas and a pedestal 518 for supporting a wafer. The plasma processing chamber 524 may be a CCP reactor, where the showerhead 514 includes an upper electrode and the pedestal 518 includes a lower electrode. The integrated apparatus 500 may include a plurality of power supplies for supplying RF power to the showerhead 514 and the pedestal 518. In some embodiments, the integrated apparatus 500 may include an LFRF generator 504 and an HFRF generator 502. The LFRF generator 504 and the HFRF generator 502 may be operably connected to the showerhead 514 or the pedestal 518 via one or more switches 564, 568. As used herein, components that are “operably connected” to each other are components that are electrically connected or otherwise connected to each other in response to the operation of a control device (e.g., a switch, a system controller, etc.). The integrated apparatus 500 may include one or more switches 564, 568 operably connected to one or both of the LFRF generator 504 and the HFRF generator 502. The switches 564, 568 are configured to switch between (1) a deposition mode for performing a deposition process, at which time the switches 564, 568 connect at least the HFRF generator 502 to the showerhead 514, and (2) an etching mode for performing an etching process, at which time the switches 564, 568 connect at least the LFRF generator 504 and the HFRF generator 502 to the pedestal 518 and ground the showerhead 514. When the HFRF generator 502 is coupled to the showerhead 514 in the deposition mode, the HFRF generator 502 can supply RF power to the showerhead 514. When the HFRF generator 502 and the LFRF generator 504 are connected to the pedestal 518 in the etching mode, the HFRF generator 502 and the LFRF generator 504 can supply RF power to the pedestal 518.

[0058] In FIG. 5, switches 564 and 568 may be replaced with filters, where the filters can switch between (1) a deposition mode for performing a deposition process (at this time, the filters selectively pass high-frequency signals to the showerhead 514) and (2) an etching mode for performing an etching process (at this time, the filters selectively pass one or both of high-frequency and low-frequency signals to the pedestal 518 while grounding the showerhead 514).

[0059] As shown in FIG. 5, one or more switches 564 and 568 include a first station relay switch 564 configured to connect the LFRF generator 504 and the HFRF generator 502 to the showerhead 514 in the deposition mode. In the first position, the first station relay switch 564 electrically connects the LFRF generator 504 and the HFRF generator 502 to the showerhead. Thus, the showerhead 514 is powered in the deposition mode. In the second position, the first station relay switch 564 is electrically grounded, and as a result, the showerhead 514 is electrically grounded. As shown in FIG. 5, one or more switches 564 and 568 include a second station relay switch 568 configured to connect the HFRF generator 502 and the LFRF generator 504 to the pedestal 518 in the etching mode. In the first position, the second station relay switch 568 electrically connects the HFRF generator 502 and the LFRF generator 504 to the pedestal 518. Thus, the pedestal 518 is biased in the etching mode. In the second position, the second station relay switch 568 is electrically grounded, and as a result, the pedestal 518 is electrically grounded.

[0060] In some embodiments, the integrated device 500 may include a low-frequency matching unit 505 (or low-frequency impedance matching network 505) connected to the LFRF generator 504. In some embodiments, the integrated device 500 may include a high-frequency matching unit 503 (or high-frequency impedance matching network 503) connected to the HFRF generator 502. In some embodiments, the integrated device may further include one or more filters for selectively passing high or low-frequency signals. The integrated device 500 may include a low-pass filter 554 connected to the low-frequency matching unit 505 and a high-pass filter 552 connected to the high-frequency matching unit 503. In some embodiments, each of the low-pass filter 554 and the high-pass filter 552 includes one or more capacitors and inductors. The low-pass filter 554 can prevent high-frequency signals from returning to the LFRF generator 504, and the high-pass filter 552 can prevent low-frequency signals from returning to the HFRF generator 502. In some embodiments, each of the low-pass filter 554 and the high-pass filter 552 can function as an RF filter not only for the plasma processing chamber 524 but also for a plurality of plasma processing chambers. In some embodiments, a blocking filter 532 may be inserted between the LFRF generator 504 and both the pedestal 518 and the showerhead 514 to selectively block high-frequency or low-frequency signals. The blocking filter 532 can function similarly to the blocking capacitor 432 in the RF hardware configuration of FIG. 4B.

[0061] In FIG. 5, the integration device 500 can be selectively switched between a deposition mode and an etching mode. In the deposition mode according to a particular embodiment, the first station release switch 564 is switched to the first position such that the LFRF generator 504 and the HFRF generator 502 are electrically connected to the showerhead 514, and at the same time, the second station release switch 568 is switched to the second position such that the pedestal 518 is grounded. Such a configuration can be utilized for ALD. In the deposition mode according to another embodiment, the first station release switch 564 is switched to the first position such that the LFRF generator 504 and the HFRF generator 502 are electrically connected to the showerhead 514, and at the same time, the second station release switch 568 is switched to the first position such that the LFRF generator 504 and the HFRF generator 502 are electrically connected to the pedestal 518. In some embodiments, the blocking filter 532 can prevent low-frequency signals from reaching the showerhead 514. In the etching mode according to a particular embodiment, the second station release switch 568 is switched to the first position such that the LFRF generator 504 and the HFRF generator 502 are electrically connected to the pedestal 518, and at the same time, the first station release switch 564 is switched to the second position such that the showerhead 514 is grounded. In some embodiments, the blocking filter 532 can prevent low-frequency or high-frequency signals from reaching the pedestal 518. In some embodiments, both low-frequency and high-frequency signals may be used to bias the pedestal 518 in the etching mode.

[0062] The RF hardware configuration of FIG. 5 can optimize the deposition mode and the etching mode using switches 564 and 568 so that a deposition-etching-deposition sequence can be executed within a single integrated apparatus 500. Further, the RF hardware configuration of FIG. 5 can accommodate both the HFRF generator 502 and the LFRF generator 504 using a plurality of integrated circuit boards (e.g., splitter boards). The splitter board enables signals to be distributed not only to one plasma processing chamber (such as plasma processing chamber 524) but also to a plurality of plasma processing chambers. Each splitter board can include a plurality of stations with a plurality of channels. One splitter board may include the LFRF generator 504, the low-frequency matching unit 505, and the low-pass filter 554, and another splitter board may include the HFRF generator 502, the high-frequency matching unit 503, and the high-pass filter 552. In some embodiments, the switches 564 and 568 may be relay switches capable of at least 4 million, at least 20 million, or at least 25 million cycles.

[0063] FIG. 6 is a block diagram showing an example of a scheme for executing switching between a deposition mode and an etching mode according to some embodiments. Similar to the RF hardware configuration shown in FIG. 5, the integrated device 600 may include a shower head 614, a pedestal 618, an HF RF generator 602, an LF RF generator 604, and a plurality of integrated circuit boards 623, 633 (e.g., splitter boards). The HF RF generator 602 and the LF RF generator 604 may be operably connected to the shower head 614 and the pedestal 618. The integrated device 600 includes a switch 625 operably connected to the HF RF generator 602. The switch 625 is configured to switch between (1) a deposition mode for performing a deposition process (at this time, the switch 625 connects the HF RF generator 602 to the shower head 614) and (2) an etching mode for performing an etching process (at this time, the switch 625 connects at least the LF RF generator 604 and the HF RF generator 602 to the pedestal 618 and grounds the shower head 614).

[0064] In FIG. 6, the integrated device 600 may include a first integrated circuit board 623 and a first high-frequency matching unit 603 related to the deposition mode. In the deposition mode, the HF RF generator 602 is electrically connected to the shower head 614 via the switch 625. As a result, the HF RF generator 602, the first high-frequency matching unit 603, and the first integrated circuit board 623 are electrically connected to the shower head 614. The HF RF generator 602 and the first high-frequency matching unit 603 can supply power to the shower head 614 in the deposition mode. In some embodiments, the pedestal 618 is grounded in the deposition mode.

[0065] In FIG. 6, the integration device 600 may include a second integrated circuit board 633 related to the etching mode, a low-frequency matching unit 605, and a second high-frequency matching unit 613. In the etching mode, the LFRF generator 604 is electrically connected to the pedestal 618, and the HFRF generator 602 is electrically connected to the pedestal 618 via the switch 625. Thus, the HFRF generator 602, the second high-frequency matching unit 613, the LFRF generator 604, the low-frequency matching unit 605, and the second integrated circuit board 633 are electrically connected to the pedestal 618. The HFRF generator 602 and the second high-frequency matching unit 613, and the LFRF generator 604 and the low-frequency matching unit 605 supply power to the pedestal 618 in the etching mode. In some embodiments, the shower head 614 is grounded in the etching mode.

[0066] In some embodiments, switch 625 is an HFRF switch box configured to switch between supplying power from HFRF generator 602 to showerhead 614 in deposition mode and supplying power from HFRF generator 602 to pedestal 618 in etching mode. In deposition mode, only HFRF generator 602 is connected to showerhead 614 through first integrated circuit board 623. In etching mode, both HFRF generator 602 and LFRF generator 604 are connected to pedestal 618 through second integrated circuit board 633. In some embodiments, first integrated circuit board 623 and second integrated circuit board 633 are communicatively connected via synchronous relay control 635, and synchronous relay control 635 is communicatively connected to switch 625. Synchronous relay control 635 is configured to synchronize the switching between deposition mode and etching mode. For example, when first integrated circuit board 623 is supplying power from HFRF generator 602 to showerhead 614 in deposition mode, synchronous relay control 635 can communicate with second integrated circuit board 633 simultaneously so as not to supply power to pedestal 618. Alternatively, when second integrated circuit board 633 is supplying power from HFRF generator 602 and LFRF generator 604 to pedestal 618 in etching mode, synchronous relay control 635 can communicate with first integrated circuit board 623 simultaneously so as not to supply power to showerhead 614.

[0067] The RF hardware configurations in FIGS. 5 and 6 utilize a separate integrated circuit board for powering the HFRF generator, the LFRF generator, and the showerhead and / or pedestal. However, some RF hardware configurations may integrate the HFRF generator and the LFRF generator as a single power source and utilize a single integrated circuit board for powering the showerhead and / or pedestal. In some embodiments, the HFRF generator and the LFRF generator may be part of a single integrated circuit board. The single integrated circuit board can supply high-frequency and / or low-frequency signals to the showerhead in one mode and to the pedestal in another mode. The single integrated circuit board may include multiple stations with multiple channels.

[0068] FIG. 7 is a block diagram showing another example of a scheme for performing switching between a deposition mode and an etching mode according to some embodiments. The integrated device 700 may include an integrated circuit board 710, a showerhead 714, and a pedestal 718. The showerhead 714 and the pedestal 718 may be part of a plasma processing chamber (not shown) for performing a deposition-etching-deposition sequence on a wafer. The plasma processing chamber may be a CCP reactor, where the showerhead 714 includes an upper electrode and the pedestal 718 includes a lower electrode. The integrated circuit board 710 may include one or more HF / LFRF generators 704, 708 and one or more switches 764, 768, where the one or more switches 764, 768 are configured to switch between (1) a deposition mode for performing a deposition process (at this time, one or more switches 764, 768 in the deposition mode connect the HF / LF generator 704 to the showerhead 714) and (2) an etching mode for performing an etching process (at this time, one or more switches 764, 768 in the etching mode connect the HF / LF generator 708 to the pedestal 718). In some embodiments, the HF / LFRF generators 704, 708 shown in FIG. 7 may be a single HF / LFRF generator. The single HF / LFRF generator can supply both high-frequency signals and low-frequency signals. The same HF / LFRF generator may be used to power the showerhead 714 or the pedestal 718.

[0069] In some embodiments, the integrated circuit board 710 may comprise a plurality of channels for powering a plurality of stations. One of the stations may have a first station relay switch 764, and one of the other stations may have a second station relay switch 768. The first station relay switch 764 is configured to connect the first HF / LFRF generator 704 to the showerhead 714 in the deposition mode. When the first station relay switch 764 is in the first position, the integration device 700 is in the deposition mode, and the first HF / LFRF generator 704 is electrically connected to the showerhead 714 to power the showerhead 714. The signal from the HF / LFRF generator 704 reaches the showerhead 714 through the first inductor 774. When the first station relay switch 764 is in the second position, the showerhead 714 is grounded. In some examples, a first capacitor 734 is provided to compensate for the inductance in the feedback path when the showerhead 714 is grounded. The second station relay switch 768 is configured to connect the second HF / LFRF generator 708 to the pedestal 718 in the etching mode. When the second station relay switch 768 is in the first position, the integration device 700 is in the etching mode, and the second HF / LFRF generator 708 is electrically connected to the pedestal 718 to bias the pedestal 718. The signal from the second station relay switch 768 reaches the pedestal 718 through the second inductor 778. When the second station relay switch 768 is in the second position, the pedestal 718 is grounded. In some examples, a second capacitor 738 is provided to compensate for the inductance in the feedback path when the pedestal 718 is grounded.

[0070] In some embodiments, such as those shown in FIG. 7, the integrated circuit board 710 includes a switch 735 configured to synchronize the switching between modes, including a digital output (DO) bit switch. The switch 735 can be connected to a first relay 744 and a second relay 748. In some examples, each of the first relay 744 and the second relay 748 can be a high voltage vacuum relay. When the switch 735 is in the deposition mode, the first relay 744 can be in the open position and the second relay 748 can be in the closed position. When the switch is in the etching mode, the first relay 744 can be in the closed position and the second relay 748 can be in the open position. When the first relay 744 opens and the second relay 748 closes, the first station relay switch 764 moves to the first position and the second station relay switch 768 moves to the second position such that the showerhead 714 is powered and the pedestal 718 is grounded. When the first relay 744 closes and the second relay 748 opens, the first station relay switch 764 moves to the second position and the second station relay switch 768 moves to the first position such that the pedestal 718 is powered and the showerhead 714 is grounded. Such a configuration in FIG. 7 allows the HF / LFRF generators 704, 708 to power the showerhead 714 and ground the pedestal 718 in the deposition mode, or allows the F / LFRF generators 704, 708 to power the pedestal 718 and ground the showerhead 714 in the etching mode.

[0071] The showerhead 714 of FIG. 7 may be grounded through a coaxial cable (not shown) disposed between the showerhead 714 and the first inductor 774. The pedestal 718 of FIG. 7 may also be grounded through a coaxial cable disposed between the pedestal 718 and the second inductor 778. However, grounding through the inductor and the coaxial cable forms a longer feedback path to the electrical ground. As a result, a larger voltage is generated at either the showerhead 714 or the pedestal 718, which can effectively reduce the voltage between the electrodes. Thereby, the etching mode becomes less effective, for example, when the pedestal 718 is biased, but still the voltage between the electrodes can vary.

[0072] Rather than grounding through an inductor and coaxial cable, some RF hardware configurations may ground the showerhead and pedestal locally to the plasma processing chamber. FIG. 8 is a schematic diagram showing an example of an integrated device comprising a plasma processing chamber configured to switch between a deposition mode and an etching mode in accordance with some embodiments. The integrated device 800 includes an integrated circuit board 810 and a plasma processing chamber 824, where the plasma processing chamber 824 includes a showerhead 814 and a pedestal 818. The plasma processing chamber 824 may be a CCP reactor, where the showerhead 814 includes an upper electrode and the pedestal 818 includes a lower electrode. The CCP reactor may be configured to perform a deposition-etching-deposition sequence on a wafer. The integrated circuit board 810 may include one or more HF / LFRF generators 804, 808 and one or more switches 864, 868. The integrated device 800 may further include additional switches 884, 888. The switches 864, 868, 884, 888 are configured to switch between (1) a deposition mode for performing a deposition process and (2) an etching mode for performing an etching process. In the deposition mode, the switches 864, 868, 884, 888 connect the HF / LFRF generator 804 to the showerhead 814 and ground the pedestal 818, and in the etching mode, the switches 864, 868, 884, 888 connect the HF / LFRF generator 808 to the pedestal 818 and ground the showerhead 814. In some embodiments, the HF / LFRF generators 804, 808 shown in FIG. 8 may be a single HF / LFRF generator. A single HF / LFRF generator may be capable of supplying both high frequency and low frequency signals. The same HF / LFRF generator may be used to power the showerhead 814 or the pedestal 818.

[0073] In some embodiments, the integrated circuit board 810 may comprise a plurality of channels for powering a plurality of stations. One of the stations may have a first station relay switch 864, and one of the other stations may have a second station relay switch 868. The first station relay switch 864 is configured to connect the first HF / LFRF generator 804 to the showerhead 814 in the deposition mode. When the first station relay switch 864 is in the first position, the integration device 800 is in the deposition mode, and the first HF / LFRF generator 804 is electrically connected to the showerhead 814 to power the showerhead 814. The signal from the HF / LFRF generator 804 reaches the showerhead 814 through the first inductor 874. When the first station relay switch 864 is in the second position, the showerhead 814 is grounded. However, instead of grounding through the first inductor 874 and the first coaxial cable 854, the showerhead 814 is locally grounded to the plasma processing chamber 824. A showerhead ground relay switch 884 is provided locally to the showerhead 814 and connected to the first station associated with the first station relay switch 864. This can reduce the inductance in the feedback path and eliminate the need for a compensating capacitor. The second station relay switch 868 is configured to connect the second HF / LFRF generator 808 to the pedestal 818 in the etching mode. When the second station relay switch 868 is in the first position, the integration device 800 is in the etching mode, and the second HF / LFRF generator 808 is electrically connected to the pedestal 818 to bias the pedestal 818. The signal from the second station relay switch 868 reaches the pedestal 818 through the second inductor 878. When the second station relay switch 868 is in the second position, the pedestal 818 is grounded. However, instead of grounding through the second inductor 878 and the second coaxial cable 858, the pedestal 818 is locally grounded to the plasma processing chamber 824.The pedestal ground relay switch 888 is locally provided to the pedestal 818 and connected to the second station associated with the second station relay switch 868. This can reduce the inductance in the feedback path and eliminate the need for a compensating capacitor. In some embodiments, locally grounding the electrodes can improve the etching process in the etching mode. However, each station in FIG. 8 includes two relay switches rather than one, such as having relay switches 864, 884 in the first station and relay switches 868, 888 in the second station.

[0074] The integrated circuit board 810 (e.g., splitter board) may comprise a plurality of stations, where each station can switch the power on / off. The integrated circuit board 810 may include a DO bit switch (not shown) at one of the stations, where the DO bit switch is configured to synchronize the switching between modes. Thus, all four relay switches 864, 868, 884, 888 can be synchronized. For example, when the DO bit switch is provided at the first station related to the first station relay switch 864 and the first station relay switch 864 is switched to the first position (e.g., turned on), the shower head 814 is powered and the pedestal 818 is grounded. Specifically, the second station relay switch 868 is switched to the second position (e.g., turned off), and the pedestal ground relay switch 888 locally grounds the pedestal 818. When the first station relay switch 864 is switched to the second position (e.g., turned off), the pedestal 818 is powered and the shower head 814 is grounded. Specifically, the second station relay switch 868 is switched to the first position (e.g., turned on), and the shower head ground relay switch 884 locally grounds the shower head 814. Such a configuration in FIG. 8 enables the HF / LFRF generators 804, 808 to power the shower head 814 and ground the pedestal 818 in the deposition mode, or enables the F / LFRF generators 804, 808 to power the pedestal 818 and ground the shower head 814 in the etching mode.

[0075] The above-described RF hardware configuration in the integrated device described in FIGS. 5-8 can provide a simpler and more flexible tool solution for performing an evaporation-etching-evaporation sequence than conventional tools. FIG. 9A is a schematic diagram showing an example of a conventional multi-station processing tool for performing an evaporation-etching-evaporation gap filling process. The multi-station processing tool 900a includes a robot 906 configured to move a wafer from a cassette loaded through pod 908 to a load lock and ultimately to one of four processing chambers 911, 912, 913, 914, although it is understood that there may be fewer or more processing chambers. The multi-station processing tool 900a may have features similar to the multi-station processing tool 300 of FIG. 3. In the multi-station processing tool 900a, three of the processing chambers 911, 912, 913 may be configured to perform an evaporation process such as ALD, and one of the processing chambers 914 may be configured to perform an etching process.

[0076] FIG. 9B is a schematic diagram showing an example of a multi-station processing tool including the disclosed integrated apparatus for performing a vapor deposition-etching-vapor deposition gap filling process. The multi-station processing tool 900b includes a robot 906 configured to move wafers from a cassette loaded through pod 908 to a load lock and ultimately to one of three processing chambers 921a, 921b, 921c, although it is understood that there may be fewer or more processing chambers. The multi-station processing tool 900b may have features similar to those of the multi-station processing tool 300 of FIG. 3. In the multi-station processing tool 900b, each of the processing chambers 921a, 921b, 921c may be configured to perform both a vapor deposition process and an etching process. For example, each of the processing chambers 921a, 921b, 921c may incorporate an integrated apparatus having the specific RF hardware configuration shown in FIGS. 5-8. The multi-station processing tool 900b can provide high-frequency tuning for vapor deposition processing, high etching rates for etching processing, a tapered etching profile for etching processing, and improved flexibility by performing multiple vapor deposition-etching-vapor deposition sequences for gap filling within the same chamber.

[0077] The multi-station processing tool 900b may include a system controller (not shown), such as the system controller 350 of FIG. 3. The system controller may be configured to provide instructions for performing operations including switching between a deposition mode and an etching mode. The system controller may be part of a system, and the system may be part of an integrated device. The system controller may provide program instructions for operating in the deposition mode and the etching mode using any of the RF hardware configurations described above with reference to FIGS. 5-8. The system controller may include instructions for controlling RF power level, RF frequency, duty cycle, wafer temperature, chamber and / or station temperature, chamber and / or station pressure, wafer and / or pedestal position, timing, gas mixture, gas flow rate, purge conditions and timing, deposition and etching mode switching, etc.

[0078] Generally, the system controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be communicated to the system controller in the form of various individual settings (or program files) and may be operation parameters for performing a specific process on or for a semiconductor wafer, or instructions that define operation parameters for the system. The operation parameters may, in some embodiments, be part of a recipe defined by a process engineer to achieve one or more processing steps during the processing of one or more layers, materials, metals, surfaces, circuits, and / or dies of a wafer.

[0079] In some embodiments, the system controller may be integrated with the system, connected to the system, networked with the system in some other way, or be part of a computer coupled to the system in combinations thereof, and may also be connected to such a computer. For example, the system controller may be within the "cloud" or may be all or part of a fab host computer system that enables remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of the manufacturing operation, examine the history of past manufacturing operations, or examine trends or performance metrics from multiple manufacturing operations, to change the parameters of the current process, set the processing steps according to the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide a processing recipe to the system via a network such as a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings, and the parameters and / or settings are communicated from the remote computer to the system. In some examples, the system controller receives instructions in the form of data, and the instructions specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool configured to interface with or be controlled by the system controller. Thus, as described above, the system controller may be distributed, such as by comprising one or more separate controllers networked to operate towards a common purpose (such as the processes and controls described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more remotely located (such as at the platform level or as part of a remote computer) integrated circuits that cooperate to control the processing in the chamber.

[0080] Depending on one or more processing steps executed by a tool, the system controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, the main computer, another controller, or a tool used for transporting a wafer container to or from a tool location and / or load port within a semiconductor manufacturing factory. The system controller may be configured to include instructions for performing one or more of the operations described below.

[0081] Processing conditions: FIG. 10 is a flowchart showing an example of a processing flow for performing an atomic layer deposition-etching-atomic layer deposition gap fill process on a wafer. The operations within process 1000 may be executed in a different order and / or may be executed to include different, fewer, or additional operations. The system controller described above may be configured to include instructions for performing one or more of the following operations.

[0082] Using the integrated tool solution provided in FIGS. 5 to 9B for atomic layer deposition and etching processes, an atomic layer deposition-etching-atomic layer deposition gap fill process can be executed within the same plasma processing chamber throughout. Further, the processing conditions for performing the etching process may be adapted to the processing conditions for performing the atomic layer deposition process. In some embodiments, processing conditions such as wafer temperature, chamber pressure, frequency, and RF power are adapted to the atomic layer deposition process but may be adjusted to provide effective anisotropic etching in an atomic layer deposition-etching-atomic layer deposition sequence.

[0083] Process 1000 may begin with block 1005 where a wafer is provided in a plasma processing chamber, and the wafer has one or more gaps each having a depth-to-width aspect ratio greater than about 5:1. The wafer may be a semiconductor wafer used in the manufacture of integrated circuits. The wafer may have one or more features, and as a result, the wafer is non-flat. In some embodiments, the one or more features may include one or more gaps, trenches, or recesses. A gap filling process may be performed on a wafer having one or more gaps. The gap width in the wafer can vary according to various embodiments and may be in the range of about 5 Å to about 50 μm or about 100 Å to about 1 μm. Examples of the depth-to-width aspect ratio may be greater than about 2:1, greater than about 5:1, greater than about 10:1, greater than about 30:1, greater than about 50:1, or greater than about 100:1. Further, the plasma processing chamber may be a CCP reactor having a showerhead for supplying a process gas and a pedestal for supporting the wafer, where the showerhead includes an upper electrode and the pedestal includes a lower electrode.

[0084] In block 1010 of process 1000, a first dielectric layer may be deposited within one or more gaps using ALD in a plasma processing chamber. In some embodiments, the first dielectric layer may be a dielectric oxide such as silicon dioxide (SiO2). Using ALD, a conformal film of the first dielectric layer may be deposited on the non-flat wafer. During the deposition of the first dielectric layer by ALD, the plasma processing chamber may be in a deposition mode where at least the showerhead is powered by an RF generator. In some embodiments, the pedestal may be grounded during the deposition of the first dielectric layer. In some embodiments, the RF generator can perform high-frequency tuning.

[0085] In block 1015 of process 1000, the first dielectric layer is slope-controlled and anisotropically etched in a plasma processing chamber. The anisotropic etching forms a tapered positive slope on the film in the state immediately after the deposition of the first dielectric layer. The anisotropic etching can selectively remove more dielectric material near the upper part of the gap than near the middle and bottom of the gap. For the purposes of this description, "near the upper part of the gap" or "near the opening" is defined as an approximate position or region within the gap (i.e., along the sidewalls of the gap) corresponding to about 0 to 10% of the depth of the gap measured from the field region. In a particular embodiment, the region near the opening or the upper part of the gap corresponds to the region of the opening or the upper part of the gap. Further, "near the middle and bottom of the gap" or "in the middle of the gap" is defined as an approximate position or region within the gap corresponding to about 20 to 60% of the depth of the gap from the field region at the upper part of the gap. As a general rule, when the values of certain parameters (e.g., thickness) are specified as those "near the opening" or "in the middle of the gap", these values represent the measured values obtained within these positions / regions or the average of a plurality of measured values. The anisotropic etching is slope-controlled and performed so as to generate a sloped profile near the upper part of the gap rather than near the middle and bottom of the gap. In some examples, the etchant for the anisotropic etching may include a fluorine-based etchant such as nitrogen trifluoride (NF3).

[0086] The anisotropic etching process executed in block 1015 can be executed in the same plasma processing chamber as the deposition process executed in block 1010. In some embodiments, the plasma processing chamber may be in an etching mode in block 1015, at which time the pedestal is powered by an RF generator and the showerhead is grounded. In some examples, one or more switches may be used to switch the RF generator from powering the showerhead in deposition mode to powering the pedestal in etching mode. For example, process 1000 may further comprise a step of applying low-frequency power and high-frequency power to the pedestal in the plasma processing chamber and switching to ground the showerhead in the plasma processing chamber prior to anisotropic etching of the first dielectric layer.

[0087] The processing conditions for the deposition mode in block 1010 may be compatible with the processing conditions for the etching mode in block 1015. In some embodiments, the wafer temperature between both the etching process and the deposition process may be between 50°C and 650°C, above 100°C, above 200°C, above 300°C, or above 400°C. Such wafer temperature may be applied in blocks 1010, 1015, and 1020. In some embodiments, the chamber pressure for both the etching process and the deposition process may be between 0.1 Torr and 10 Torr, or between 0.3 Torr and 1 Torr. Such chamber pressure may be applied in blocks 1010, 1015, and 1020. In some embodiments, the LFRF generator can provide an RF frequency of about 400 kHz, and the HFRF generator can provide an RF frequency of about 13.56 MHz. Such frequencies may be applied in blocks 1010, 1015, and 1020. The generated low-frequency power may be between about 1500 W and about 6000 W, and the generated high-frequency power may be between about 0 W and about 5000 W. Such RF power may be applied in blocks 1010, 1015, and 1020. A typical etching process does not act at such a high wafer temperature and does not act at such a low frequency for generating such a large low-frequency power. In some embodiments, the concentration of NF3 may be between about 1.0 and 2.5% for etching. Also, a typical etching process may not need to use such a small amount of NF3 for etching. Table I provides examples of wafer temperature ranges, gas mixtures, gas concentrations in terms of flow rate, pressure, high-frequency power, low-frequency power, and NF3 concentration.

[0088]

Table 1

[0089] In block 1020 of process 1000, a second dielectric layer can be deposited within one or more gaps over the first dielectric layer using ALD within a plasma processing chamber. In some embodiments, the second dielectric layer can be a dielectric oxide such as SiO2. Using ALD, a conformal film of the second dielectric layer can be deposited over a non-planar wafer. In some embodiments, the second dielectric layer can fill and close one or more gaps. During deposition of the second dielectric layer, the plasma processing chamber can be in a deposition mode in which at least the showerhead is powered by an RF generator. In some embodiments, the pedestal can be grounded during deposition of the second dielectric layer. The second dielectric layer can be deposited within the same plasma processing chamber as the slope-controlled anisotropic etching. In some embodiments, process 1000 can further comprise a step of applying high-frequency power to the showerhead within the plasma processing chamber and switching to ground the pedestal within the plasma processing chamber prior to deposition of the second dielectric layer.

[0090] Lithographic patterning: The above-described apparatus / process may be used with a lithography patterning tool or process, for example, for the processing or manufacturing of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, but not necessarily, such tools / processes are utilized or executed together in a common manufacturing facility. Lithography patterning of thin films typically includes some or all of the following steps, each of which is implemented with a plurality of possible tools: (1) applying a photoresist onto a workpiece (i.e., a substrate) using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate, furnace, or UV curing tool; (3) exposing the photoresist to visible light, UV, or X-rays using a tool such as a wafer stepper; (4) developing the resist to pattern it by selectively removing the resist using a tool such as a wet bench; (5) transferring the resist pattern to the underlying film or workpiece using a dry etching tool or a plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF plasma or microwave plasma resist stripper.

[0091] Another embodiment : Embodiments and application examples of the present invention are illustrated and described herein, but many variations and modifications within the concept, scope, and spirit of the present invention are possible, and these variations will be apparent to those skilled in the art upon a thorough reading of this application. Accordingly, these embodiments are considered to be illustrative and not limiting, and the present invention is not limited to the details shown herein and may be modified within the scope of the appended claims and their equivalents. For example, it can be implemented as the following application examples. [Application Example 1] An integrated apparatus for performing a deposition process and an etching process, comprising a processing chamber equipped with a shower head and a pedestal, a low-frequency radio frequency (LFRF) generator, a high-frequency radio frequency (HFRF) generator, and one or more switches operably connected to one or both of the LFRF generator and the HFRF generator wherein the one or more switches are configured to switch between (1) a deposition mode for performing a deposition process, in which the one or more switches connect at least the HFRF generator to the shower head, and (2) an etching mode for performing an etching process, in which the one or more switches connect the HFRF generator and the LFRF generator to the pedestal and ground the shower head. [Application Example 2] The apparatus according to Application Example 1, wherein the processing chamber is a capacitively coupled plasma (CCP) reactor, the shower head comprises an upper electrode, and the pedestal comprises a lower electrode. [Application Example 3] The apparatus according to Application Example 1, wherein the one or more switches in the deposition mode connect the HFRF generator and the LFRF generator to the shower head and ground the pedestal. [Application Example 4] The apparatus according to Application Example 1, wherein the one or more switches comprise a first station relay switch configured to electrically connect the LFRF generator and the HFRF generator to the shower head in the deposition mode, and a second station relay switch configured to electrically connect the LFRF generator and the HFRF generator to the pedestal in the etching mode. ​ ​ [Application Example 5] The apparatus according to Application Example 4, wherein the first station release switch is configured to switch to a first position for electrically connecting the LFRF generator and the HFRF generator to the shower head, and to switch to a second position for grounding the shower head, and the second station release switch is configured to switch to a first position for electrically connecting the LFRF generator and the HFRF generator to the pedestal, and to switch to a second position for grounding the pedestal, the first position of the first station release switch is synchronized with the second position of the second station release switch, and the first position of the second station release switch is synchronized with the second position of the first station release switch. [Application Example 6] The apparatus according to Application Example 4, further comprising one or more filters selectively filtering so that a low-frequency signal from the LFRF generator does not reach the shower head in the deposition mode. [Application Example 7] The apparatus according to any one of Application Examples 1 to 6, wherein the LFRF generator is part of a first integrated circuit board, and the HFRF generator is part of a second integrated circuit board. [Application Example 8] The apparatus according to any one of Application Examples 1 to 6, wherein the one or more switches are operably connected to the HFRF generator, and include a switch configured to switch between supplying power from the HFRF generator to the shower head in the deposition mode and supplying power from the HFRF generator to the pedestal in the etching mode. [Application Example 9] The apparatus according to Application Example 8, wherein the HFRF generator is connected to the shower head through a first integrated circuit board in the deposition mode, and the HFRF generator and the LFRF generator are connected to the pedestal through a second integrated circuit board in the etching mode. [Application Example 10] The apparatus according to Application Example 9, wherein the first integrated circuit board and the second integrated circuit board are communicably connected via synchronous relay control, and the synchronous relay control is communicably connected to the switch. [Application Example 11] The apparatus according to any one of Application Examples 1 to 6, further comprising A controller configured to include instructions for performing operations, the operations being (a) preparing a wafer having one or more gaps each having a depth-to-width aspect ratio greater than about 5:1 on the pedestal; (b) depositing a first dielectric layer into the one or more gaps using atomic layer deposition (ALD) in the processing chamber in the deposition mode; (c) anisotropically etching the first dielectric layer with slope control in the processing chamber in the etching mode; (d) depositing a second dielectric oxide layer into the one or more gaps on the first dielectric layer using ALD in the processing chamber in the deposition mode An apparatus including the above. [Application Example 12] An integrated apparatus for performing a deposition process and an etching process, A processing chamber including a showerhead and a pedestal; An integrated circuit board including one or more HF / LFRF generators; One or more switches operably connected to the one or more HF / LFRF generators An apparatus comprising: The one or more switches are configured to switch between (1) a deposition mode for performing a deposition process (the one or more switches in the deposition mode connect at least one of the HF / LFRF generators to the showerhead), and (2) an etching mode for performing an etching process (the one or more switches in the etching mode connect at least one of the HF / LFRF generators to the pedestal). [Application Example 13] The apparatus according to Application Example 12, wherein the processing chamber is a CCP reactor, the showerhead includes an upper electrode, and the pedestal includes a lower electrode. [Application Example 14] The apparatus according to Application Example 12, wherein the integrated circuit board includes one HF / LFRF generator. [Application Example 15] The apparatus according to Application Example 12, wherein the one or more switches are A first station relay switch configured to electrically connect one of the HF / LFRF generators to the showerhead in the deposition mode; A second station relay switch configured to electrically connect one of the HF / LFRF generators to the pedestal in the etching mode An apparatus including the above. [Application Example 16] The apparatus according to Application Example 15, wherein the first station release switch is configured to switch to a first position for electrically connecting one of the HF / LFRF generators to the shower head in the deposition mode and to switch to a second position for grounding the shower head, the second station release switch is configured to switch to a first position for electrically connecting one of the HF / LFRF generators to the pedestal in the etching mode and to switch to a second position for grounding the pedestal, the first position of the first station release switch is synchronized with the second position of the second station release switch, and the first position of the second station release switch is synchronized with the second position of the first station release switch. [Application Example 17] The apparatus according to Application Example 16, wherein the one or more switches further include a pedestal ground release switch for grounding the pedestal in the deposition mode when one of the HF / LFRF generators is operably connected to the shower head, and a shower head ground release switch for grounding the shower head in the etching mode when one of the HF / LFRF generators is operably connected to the pedestal. [Application Example 18] The apparatus according to Application Example 17, wherein the first station release switch, the second station release switch, the shower head ground release switch, and the pedestal ground release switch are synchronized such that in the deposition mode, one of the HF / LFRF generators is electrically connected to the shower head and the pedestal is grounded, and in the etching mode, one of the HF / LFRF generators is electrically connected to the pedestal and the shower head is grounded. [Application Example 19] The apparatus according to any one of Application Examples 12 to 18, further comprising a controller configured to include instructions for performing operations, the operations including (a) preparing a wafer having one or more gaps each having an aspect ratio of depth to width greater than about 5:1 on the pedestal, (b) In the processing chamber in the deposition mode, the operation of depositing a first dielectric layer in the one or more gaps using atomic layer deposition (ALD); (c) In the processing chamber in the etching mode, the operation of slope controlling the first dielectric layer to perform anisotropic etching; (d) In the processing chamber in the deposition mode, the operation of depositing a second dielectric oxide layer in the one or more gaps on the first dielectric layer using ALD An apparatus comprising. [Application Example 20] A method for filling one or more gaps in a wafer, comprising: Preparing a wafer having one or more gaps each having an aspect ratio of depth to width greater than about 5:1 on a pedestal in a plasma processing chamber; In the plasma processing chamber, depositing a first dielectric layer in the one or more gaps using ALD; In the plasma processing chamber, slope controlling the first dielectric layer to perform anisotropic etching; In the plasma processing chamber, depositing a second dielectric layer in the one or more gaps on the first dielectric layer using ALD A method comprising. [Application Example 21] The method according to Application Example 20, wherein the wafer temperature during depositing the first dielectric layer, during slope controlling the first dielectric layer to perform anisotropic etching, and during depositing the second dielectric layer is between about 80 °C and about 400 °C. [Application Example 22] The method according to Application Example 20, wherein the pressure during depositing the first dielectric layer, during slope controlling the first dielectric layer to perform anisotropic etching, and during depositing the second dielectric layer is between about 0.3 and about 1.0 Torr. [Application Example 23] The method according to any one of Application Examples 20 to 22, wherein the low-frequency power applied to the plasma processing chamber during depositing the first dielectric layer, during slope controlling the first dielectric layer to perform anisotropic etching, and during depositing the second dielectric layer is between about 1500 W and about 6000 W, and the high-frequency power applied to the plasma processing chamber during depositing the first dielectric layer, during slope controlling the first dielectric layer to perform anisotropic etching, and during depositing the second dielectric layer is between about 0 W and about 5000 W. [Application Example 24] The method described in Application Example 23, wherein the first dielectric layer is deposited, the slope of the first dielectric layer is controlled for anisotropic etching, and the low-frequency of the low-frequency power for depositing the second dielectric layer is about 400 kHz, and the high-frequency of the high-frequency power for depositing the first dielectric layer, controlling the slope of the first dielectric layer for anisotropic etching, and depositing the second dielectric layer is about 13.56 MHz. [Application Example 25] The method according to any one of Application Examples 20 to 22, further comprising before controlling the slope of the first dielectric layer for anisotropic etching, a step of applying low-frequency power and high-frequency power to the pedestal in the plasma processing chamber and switching to ground the shower head in the plasma processing chamber; before depositing the second dielectric layer, a step of applying the high-frequency power to the shower head in the plasma processing chamber and switching to ground the pedestal in the plasma processing chamber and a method comprising the steps.

Claims

1. An integrated apparatus for performing vapor deposition processing and etching processing, comprising: a processing chamber having a shower head and a pedestal; one or more RF generators; one or more filters operably connected to the one or more RF generators; The integrated apparatus is configured to switch between (1) a vapor deposition mode for performing vapor deposition processing, in which the one or more filters in the vapor deposition mode selectively block a low-frequency signal from reaching the shower head and selectively pass a high-frequency signal to the shower head, and (2) an etching mode for performing etching processing, in which the one or more filters in the etching mode selectively pass a high-frequency signal and a low-frequency signal to the pedestal.

2. The apparatus according to claim 1, wherein the processing chamber is a capacitively coupled plasma (CCP) reactor, the shower head comprises an upper electrode, and the pedestal comprises a lower electrode.

3. The apparatus according to claim 1, further comprising: one or more switches operably connected to the one or more RF generators.

4. The apparatus according to claim 3, wherein the one or more switches in the vapor deposition mode connect the one or more RF generators to the shower head.

5. The apparatus according to claim 3, wherein the one or more switches in the etching mode connect the one or more RF generators to the pedestal and ground the shower head.

6. The apparatus according to claim 1, wherein the one or more RF generators include a high-frequency radio frequency (HFRF) generator and a low-frequency radio frequency (LFRF) generator.

7. The apparatus according to claim 6, wherein the one or more switches include: a first station relay switch configured to electrically connect the LFRF generator and the HFRF generator to the shower head in the vapor deposition mode; a second station relay switch configured to electrically connect the LFRF generator and the HFRF generator to the pedestal in the etching mode.

8. An integrated apparatus for performing vapor deposition processing and etching processing, comprising: ​ ​ A processing chamber equipped with a shower head and a pedestal, One or more RF generators, A system controller operably connected to the one or more RF generators, An operation of connecting the one or more RF generators to at least the shower head in a deposition mode, An operation of connecting the one or more RF generators to at least the pedestal in an etching mode, A system controller configured to include instructions for performing, An integrated device comprising.

9. The integrated device according to claim 8, wherein the system controller further An operation of preparing a wafer including a first dielectric layer on the pedestal in the processing chamber, An operation of anisotropically etching the first dielectric layer in the processing chamber when the one or more RF generators are connected to at least the pedestal in the etching mode, An operation of anisotropically etching a second dielectric layer on the first dielectric layer in the processing chamber by ALD when the one or more RF generators are connected to at least the shower head in the deposition mode, An integrated device configured to include instructions for performing.

10. The integrated device according to claim 8, wherein the processing chamber is a capacitively coupled plasma (CCP) reactor, the shower head includes an upper electrode, and the pedestal includes a lower electrode.

11. The integrated device according to claim 8, further One or more filters operably connected to the one or more RF generators, The integrated device switches between (1) the deposition mode for performing a deposition process, wherein the one or more filters in the deposition mode selectively prevent a low-frequency signal from reaching the shower head and selectively pass a high-frequency signal to the shower head, and (2) the etching mode for performing an etching process, wherein the one or more filters in the etching mode selectively pass a high-frequency signal and a low-frequency signal to the pedestal.

12. The integrated device according to claim 8, wherein the one or more RF generators include a high-frequency radio frequency (HFRF) generator and a low-frequency radio frequency (LFRF) generator.

13. The integrated device according to claim 12, wherein the system controller configured to comprise instructions for connecting at least the one or more RF generators to the showerhead in a deposition mode is configured to comprise instructions for connecting at least the HFRF generator to the showerhead for integration, and the system controller configured to comprise instructions for connecting at least the one or more RF generators to the pedestal in an etching mode is configured to connect the HFRF generator and the LFRF generator to the pedestal and to comprise instructions for grounding the showerhead. Integrated device.

14. The integrated device according to claim 9, wherein the wafer has one or more gaps each having a depth-to-width aspect ratio greater than 5:1, and the first dielectric layer is included within the one or more gaps. Integrated device.

15. The integrated device according to claim 8, further comprising one or more switches operably connected to the one or more RF generators. Integrated device.

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