Array substrate, method for detecting an array substrate, and splicing display panel

Abstract

The present invention discloses an array substrate, a method for detecting the array substrate, and a splicing display panel. A pixel 1 of the array substrate includes at least three color sub-pixels 01 and a pixel driving chip 02 for driving the emission of each sub-pixel 01, each sub-pixel 01 including at least one inorganic light emitting diode (ILED). A display area A1 includes a positive signal line Hm connected to the positive electrode of the inorganic light emitting diode, a data signal line Dm connected to the pixel driving chip 02, a scan line Sn, and a reference signal line Vm, and the pixel driving chip 02 is configured to write a signal of the data signal line Dm to the sub-pixels 01 of different colors in a time division manner under the control of the scan line Sn.

Description

Technical Field

[0001] The present invention relates to the technical field of displays, and in particular to an array substrate, a method for detecting an array substrate, and a splicing display panel.

[0002] [Cross-reference to Related Applications] This application claims priority based on a Chinese patent application filed with the Chinese Patent Office on May 13, 2020, with an application number of 202010404359.0 and an invention title of "Array Substrate, Method for Detecting an Array Substrate, and Splicing Display Panel", and incorporates the entire disclosure thereof herein.

Background Art

[0003] Compared with organic light-emitting diodes (OLEDs), submillimeter-level or micron-level light-emitting diodes based on the principle of inorganic light-emitting diodes belong to self-luminous devices such as OLEDs, and like OLEDs, have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. Inorganic light-emitting diodes emit light based on more stable characteristics and lower-resistance metal semiconductors (not organic substances), so they have the advantages of lower power consumption, higher resistance to high and low temperatures, and longer service life compared with OLEDs.

Summary of the Invention

[0004] Embodiments of the present invention provide an array substrate, a method for detecting an array substrate, and a splicing display panel. The specific solutions are as follows.

[0005] In a first aspect, the array substrate provided by an embodiment of the present invention is The array substrate includes a display area and a bezel area, and has a plurality of pixels arranged in an array mode in the display area, a plurality of scanning lines, a plurality of data signal lines, a plurality of positive signal lines, and a plurality of reference signal lines. Any one of the plurality of pixels includes at least three-color sub-pixels and a pixel driving chip that drives the light emission of each of the sub-pixels. Each of the sub-pixels includes at least one inorganic light-emitting diode. The pixel driving chip is connected to the anode of the inorganic light-emitting diode in each of the sub-pixels it drives, one of the plurality of data signal lines, one of the plurality of scanning lines, and one of the plurality of reference signal lines. The pixel driving chip is configured to write the signals of the data signal lines to sub-pixels of different colors in a time-division manner under the control of the scanning line. The reference signal line is configured to provide a negative signal to the pixel driving chip so as to form a current path between the inorganic light-emitting diode and the pixel driving chip.

[0006] Optionally, in the array substrate provided by the embodiment of the present invention, The plurality of pixels include N pixel rows arranged in a first direction and M pixel columns arranged in a second direction, where both N and M are integers greater than 1. The plurality of scanning lines extend in the first direction and are arranged in the second direction. The plurality of data signal lines extend in the second direction and are arranged in the first direction. The plurality of positive signal lines extend in the second direction and are arranged in the first direction. The plurality of reference signal lines extend in the second direction and are arranged in the first direction. The first direction is different from the second direction.

[0007] Optionally, in the array substrate provided by the embodiment of the present invention, Each of the pixel rows corresponds to one of the plurality of scanning lines, and each of the pixel columns corresponds to one of the plurality of data signal lines, one of the plurality of reference signal lines, and one of the plurality of positive signal lines.

[0008] Optionally, in the array substrate provided by the embodiment of the present invention, The pixel includes a sub-pixel of a first color, a sub-pixel of a second color, and a sub-pixel of a third color, Each of the pixel rows corresponds to one of the plurality of scanning lines, and each of the pixel columns corresponds to one of the plurality of data signal lines, one of the plurality of reference signal lines, and two of the plurality of positive signal lines, One of the two positive signal lines is connected to the anode of the inorganic light-emitting diode in the sub-pixel of the first color, and the other positive signal line is connected to the anodes of the inorganic light-emitting diodes in the sub-pixel of the third color and the sub-pixel of the second color.

[0009] Optionally, in the array substrate provided by the embodiment of the present invention, The display area further includes a scanning signal routing wire connected to each of the plurality of scanning lines in a one-to-one correspondence, and the scanning signal routing wire extends in the second direction.

[0010] Optionally, in the array substrate provided by the embodiment of the present invention, N = M. Corresponding to one side of each of the pixel columns, one of the scanning signal routing wires is arranged, and only one of the scanning signal routing wires is arranged between two adjacent pixel columns.

[0011] Optionally, in the array substrate provided by the embodiment of the present invention, N > M. At least one scanning signal routing wire is arranged on each of the two sides of at least one pixel column, At least one scanning signal routing wire is arranged between at least a part of two adjacent pixel columns, and the number of the scanning signal routing wires between two adjacent pixel columns does not exceed two.

[0012] Optionally, in the array substrate provided by the embodiment of the present invention, The scanning lines are disposed on the first metal layer, and the scanning signal routing wires, the data signal lines, the reference signal lines, and the positive signal lines are disposed on the second metal layer.

[0013] Optionally, in the array substrate provided by an embodiment of the present invention, The bezel region disposed at one end of the data signal line includes a bending region, a wiring region, and a bonding region that are sequentially farther away from the display region. At least one first chip and at least one second chip are disposed in the bonding region. The scanning signal routing wire and the data signal line are sequentially connected to the first chip via routing wires disposed in the bending region and the wiring region. The reference signal line and the positive signal line are sequentially connected to the second chip via routing wires disposed in the bending region and the wiring region.

[0014] Optionally, in the array substrate provided by an embodiment of the present invention, A plurality of the first chips and a plurality of the second chips are disposed in the bonding region. The first chip and the second chip are disposed at intervals in the bonding region.

[0015] Optionally, in the array substrate provided by an embodiment of the present invention, All the routing wires in the bending region are disposed on the second metal layer.

[0016] Optionally, in the array substrate provided by an embodiment of the present invention, In the wiring region, the routing wires connected to the scanning signal routing wire and the routing wires connected to the data signal line are all disposed on the first metal layer. In the wiring area, all routing wires connected to the reference signal line and routing wires connected to the positive signal line are arranged in the second metal layer.

[0017] Optionally, in the array substrate provided by the embodiment of the present invention, In the wiring area, all routing wires connected to the scanning signal routing wire and routing wires connected to the data signal line are arranged in the second metal layer, In the wiring area, all routing wires connected to the reference signal and routing wires connected to the positive signal line are arranged in the first metal layer.

[0018] Optionally, in the array substrate provided by the embodiment of the present invention, The scanning signal routing wire, the data signal line, the reference signal line, and the positive signal line are all vertical signal lines, The bezel area further includes a first signal input area arranged on the side of the bonding area far from the wiring area and a second signal input area arranged on the side of the data signal line far from the bending area, First input electrodes corresponding one-to-one to each of the vertical signal lines are arranged in the first signal input area, and each of the vertical signal lines in the display area is sequentially connected to the corresponding first input electrode through routing wires arranged in the bending area and the wiring area, It is arranged on the side of the second input electrode corresponding one-to-one to each of the vertical signal lines in the second signal input area.

[0019] Optionally, in the array substrate provided by the embodiment of the present invention, One end of the scanning line in the bezel area includes a third signal input area, The other end of the scanning line in the bezel area includes a fourth signal input area, The third signal input region is provided with third input electrodes respectively and correspondingly connected to each of the scanning lines one-to-one. It is arranged on the side of the fourth input electrode correspondingly and connected to each of the scanning lines one-to-one in the fourth signal input region.

[0020] In a second aspect, an embodiment of the present invention further provides a splicing display panel including a plurality of arbitrary array substrates provided by the embodiments of the present invention.

[0021] In a third aspect, an embodiment of the present invention further provides a method for detecting any of the above array substrates. The vertical signal lines and scanning lines in the display region are all lines to be detected. The detection method includes: For each of the detected lines, inputting a test signal to one input electrode connected to the detected line; Detecting whether another input electrode connected to the detected line outputs a signal, and if the detection result is that another input electrode connected to the detected line does not output a signal, determining that the detected line is disconnected; Detecting whether an input electrode of another detected line other than the detected line to which the test signal is input outputs a signal, and if the detection result is that an input electrode of another detected line outputs a signal, determining that a short circuit has occurred between the detected line to which the test signal is input and another detected line whose input electrode outputs a signal.

Brief Description of the Drawings

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0023] The inventors have discovered that mini light-emitting diodes and micro light-emitting diodes have the problem of poor luminance uniformity under low current density, so mini light-emitting diodes and micro light-emitting diodes emit light using a large current density. Since the current density of micro inorganic light-emitting diodes is at least two orders of magnitude larger than that of organic light-emitting diodes, micro inorganic light-emitting diodes are not driven by a pixel circuit formed by a thin-film transistor like an organic light-emitting diode. When driven by a pixel circuit formed by a thin-film transistor, it is necessary to increase the size of the thin-film transistor to generate a large current density. When the size of the thin-film transistor increases, the uniformity decreases and the power consumption increases, and the pixel circuit of the existing organic light-emitting diode cannot be directly applied to the micro inorganic light-emitting diode.

[0024] In view of this, embodiments of the present invention provide an array substrate, a method for detecting the array substrate, and a splicing display panel.

[0025] In order to make the above objects, features, and advantages of the present invention clearer and easier to understand, the present invention will be further described below with reference to the accompanying drawings and embodiments. It should not be construed as being limited to the implementations described herein. Rather, these implementations are provided to make the present invention more comprehensive and complete, and the concept of exemplary implementations is comprehensively conveyed to those skilled in the art. Since the reference numerals in the drawings represent the same or similar structures, repeated descriptions are omitted. The words indicating the positions and directions described in the present invention are, for example, descriptions created using the drawings and can be changed as necessary. Such changes are included in the protection scope of the present invention. The drawings of the present invention are only for the purpose of explaining the relative positional relationship and do not represent the true scale.

[0026] Note that specific details are set forth in the following description in order to provide a thorough understanding of the present invention. However, the present invention may be practiced in many other modes different from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out the present application and is a general principle of the present application, but is not intended to limit the scope of the present application. The protection scope of the present application is determined by what is defined in the appended claims.

[0027] The array substrate, method for detecting the array substrate, and splicing display panel provided by an embodiment of the present invention will be described in detail below with reference to the drawings.

[0028] As shown in FIGS. 1 and 2, the array substrate provided by an embodiment of the present invention includes a display area A1 and a bezel area A2. The display area A1 includes a plurality of pixels 1 arranged in an array mode, a plurality of scanning lines Sn, a plurality of data signal lines Dm, a plurality of positive signal lines Hm, and a plurality of reference signal lines Vm.

[0029] As shown in FIG. 3, each of the plurality of pixels 1 includes at least three-color sub-pixels 01 and a pixel driving chip 02 that drives each of the sub-pixels 01 to emit light.

[0030] Each of the sub-pixels O1 includes at least one inorganic light-emitting diode.

[0031] The pixel driving chip 2 is connected to the positive electrode of the inorganic light-emitting diode in each of the sub-pixels 01 it drives, at least one of the plurality of data signal lines Dm, at least one of the plurality of data signal lines Sn, at least one of the scanning line Sn, and at least one of the plurality of reference signal lines Vm.

[0032] Each pixel driving chip 2 is configured to write the signals of the data signal lines Dm to different color sub-pixels 01 in a time-division manner under the control of the scanning line Sn. The reference signal line Vm is configured to provide a negative signal to the pixel driving chip 2 so as to form a current path between the pixel driving chip 2 and the inorganic light-emitting diode.

[0033] In the array substrate provided by the embodiment of the present invention, each pixel includes at least three-color sub-pixels and a pixel driving chip that drives each sub-pixel to emit light. Each sub-pixel includes at least one inorganic light-emitting diode. The display area includes a positive signal line connected to the anode of the inorganic light-emitting diode, a data signal line connected to the pixel driving chip, a scanning line, and a reference signal line. The pixel driving chip is configured to write the signals of the data signal lines to different color sub-pixels in a time-division manner under the control of the scanning line. That is, in the embodiment of the present invention, the display is realized by directly driving all pixels with the pixel driving chip, and since all pixels can be directly driven by the pixel driving chip, a large current density can be provided to the micro inorganic light-emitting diode.

[0034] In a specific implementation, in the array substrate provided by the embodiment of the present invention, the inorganic light-emitting diode may be a mini light-emitting diode (Mini LED) or a micro light-emitting diode (Micro LED), which is not limited herein.

[0035] In a specific implementation, in the array substrate provided by the embodiment of the present invention, each of the sub-pixels includes at least one inorganic light-emitting diode. For example, each of the sub-pixels includes one inorganic light-emitting diode, two inorganic light-emitting diodes, three inorganic light-emitting diodes, or a plurality of inorganic light-emitting diodes, which is not limited in this specification. The drawings of the present invention show an example in which each of the sub-pixels includes two inorganic light-emitting diodes.

[0036] Optionally, in the array substrate provided by the embodiment of the present invention, as shown in FIGS. 1 and 3, the display area A1 includes N pixel rows arranged in the first direction X and M pixel columns arranged in the second direction Y. Here, both N and M are integers greater than 1.

[0037] The plurality of scanning lines Sn extend in the first direction X and are arranged in the second direction Y, and the plurality of data signal lines Dm extend in the second direction Y and are arranged in the first direction X. The plurality of positive signal lines Hm extend in the second direction Y and are arranged in the first direction X, and the plurality of reference signal lines Vm extend in the second direction Y and are arranged in the first direction X.

[0038] The first direction X and the second direction Y are different. Optionally, as shown in FIGS. 1 and 3, in the array substrate provided by the embodiment of the present invention, in order to reduce the amount of wires in the display area, each pixel row is connected corresponding to one of the plurality of scanning lines Sn. Each pixel column is connected corresponding to one of the plurality of data signal lines Dm, one of the plurality of reference signal lines Vm, and one of the plurality of positive signal lines Hm.

[0039] During a specific implementation, the current conversion efficiencies of the first-color inorganic light-emitting diode and the second-color inorganic light-emitting diode are slightly different, and the current conversion efficiencies of both the first-color inorganic light-emitting diode and the second-color inorganic light-emitting diode are significantly different from the current conversion efficiency of the third-color inorganic light-emitting diode. Therefore, the intensity of the electrical signal that the anode of the first-color inorganic light-emitting diode needs to receive is significantly different from the intensity of the electrical signals that the anodes of the second-color inorganic light-emitting diode and the third-color inorganic light-emitting diode need to receive. When sub-pixels of different colors within the same pixel correspond to the same positive signal line, the signal provided by the positive signal line is required, and the first-color inorganic light-emitting diode, the second-color inorganic light-emitting diode, and the third-color inorganic light-emitting diode can emit light at maximum brightness, increasing power consumption. Optionally, in the array substrate provided by the embodiments of the present invention, as shown in FIGS. 2 and 4, pixel 1 includes a sub-pixel 01(R) of the first color, a sub-pixel 01(B) of the second color, and a sub-pixel 01(G) of the third color.

[0040] Each of the pixel rows is connected corresponding to one of the plurality of scanning lines Sn, and each of the pixel columns is connected corresponding to one of the plurality of data signal lines Dm, one of the plurality of reference signal lines Vm, and two of the plurality of positive signal lines (Hm1 and Hm2).

[0041] One of the two positive signal lines Hm1 and Hm2, the positive signal line Hm1, is connected to the positive electrode of the inorganic light-emitting diode of the first-color sub-pixel 01(R), and the other positive signal line Hm2 is connected to the positive electrodes of the inorganic light-emitting diodes of the third-color sub-pixel 01(G) and the second-color sub-pixel 01(B). Therefore, the signals received by the anodes of the inorganic light-emitting diodes within the third-color sub-pixel 01(G) and the second-color sub-pixel 01(B) can be the same. The signal received by the anode of the inorganic light-emitting diode of the first-color sub-pixel 01(R) has a larger amplitude than the signals received by the other two-color sub-pixels. Therefore, it is possible to prevent all the anodes of the three-color sub-pixels from receiving the signal of the pixel that requires the largest signal amplitude among the three-color pixels, and power consumption can be reduced.

[0042] During a specific implementation, the first color, the second color, or the third color can be any of red, blue, and green. For example, the first color is red, the second color is blue, and the third color is green. Optionally, in the array substrate provided by an embodiment of the present invention, as shown in FIG. 5, the display area A1 further includes scanning signal routing wires Cn that are connected to a plurality of scanning lines Sn in a one-to-one correspondence. The scanning signal routing wires Cn extend in the second direction Y. In this way, a scanning signal can be provided to the corresponding scanning line Sn via the scanning signal wiring Cn so that signal sources for providing scanning signals can be arranged at both ends of the scanning signal wiring Cn. Thereby, it is prevented that chips for providing scanning signals are arranged at both ends of the scanning line Sn.

[0043] Optionally, in the array substrate provided by an embodiment of the present invention, as shown in FIG. 5, when the amount N of pixel rows in the display area A1 is the same as the amount M of pixel columns in the display area A1. That is, N = M.

[0044] Each side of each pixel column correspondingly includes one of the scanning signal routing wires Cn, and only one of the scanning signal routing wires Cn is arranged for every two adjacent pixel columns.

[0045] Optionally, in the array substrate provided by an embodiment of the present invention, as shown in FIG. 6, when the amount N of pixel rows in the display area A1 is greater than the amount M of pixel columns in the display area A1, that is, N > M.

[0046] At least one scanning signal routing wire Cn is arranged on each of the two sides of at least one pixel column (for example, in FIG. 6, one scanning signal routing wire C1 is arranged on the left side of the second pixel column, and two scanning signal routing wires C2 and C3 are arranged on the right side of the second pixel column). And at least one of the scanning signal routing wires Cn is arranged between at least a part of every two adjacent pixel columns.

[0047] During a specific implementation, K adjacent pixel columns are all groups of repeat elements. In each group of repeat elements, at least one scanning signal routing wire is arranged on each of the two sides of one pixel column. Two scanning signal routing wires are arranged on one side of the pixel column, and at most one scanning signal routing wire is arranged on the other side of the pixel column. On each of the two sides of the remaining (K - 1) pixel columns, at most one scanning signal routing wire is arranged. For example, one scanning signal routing wire is arranged on each side of each of the (K - 1) pixel columns, and no scanning signal routing wire is arranged on the other side of each of the (K - 1) pixel columns (for example, the pixel column is arranged on the outermost side of the display panel), or only one scanning signal wiring (for example, the pixel column is on the side that is not the outermost side of the display panel) is arranged. Here, K = (min[N, M]) / |N - M|.

[0048] Taking N = 135 and M = 120 as an example, two scanning signal routing wires are arranged corresponding to both sides of each of the 15 pixel columns. In order to evenly distribute the 15 pixel columns among the 120 pixel columns, at least one scanning signal routing wire needs to be arranged on both sides of one pixel column every 8 pixel columns. Adjacent 8 - pixel - column groups are regarded as groups of repeat elements, and there are a total of 15 groups of repeat elements. One pixel column is selected from each group of repeat elements, at least one scanning signal routing wire is arranged on each of the two sides of the selected pixel column, and at most one scanning signal routing wire is arranged on each of the two sides of each of the other 7 pixel columns.

[0049] Optionally, in the array substrate provided by the embodiments of the present invention, as shown in FIGS. 7 and 8, the scanning lines Sn are arranged in the same first metal layer, and the scanning signal routing wires Cn, data signal lines Dm, reference signal lines Vm, and positive signal lines Hm1 and Hm2 are arranged in the same second metal layer.

[0050] In the embodiments of the present invention, for two structures to be "co-layered" or "arranged in the same layer" may mean that both are formed by the same film formation process or the same patterning process. Or they may be arranged in the same layer in a cascade relationship, or may represent an equal distance between both and the substrate.

[0051] Specifically, in the array substrate provided by the embodiments of the present invention, the first metal layer may be arranged on one side of the second metal layer far from the base substrate 100, or the second metal layer may be arranged on the side of the first metal layer far from the base substrate 100, which is not limited in this specification.

[0052] During a specific implementation, as shown in FIGS. 7 and 8, each pixel driving chip (not shown in FIGS. 7 and 8) has a first signal terminal O1, a second signal terminal O2, a third signal terminal O3, a fourth signal terminal O4, a fifth signal terminal O5, and a sixth signal terminal O6. The first signal terminal O1 is connected to the negative electrode R- of the first-color inorganic light-emitting diode, the second signal terminal O2 of the pixel driving chip is connected to the negative electrode G- of the third-color inorganic light-emitting diode, the third signal terminal O3 of the pixel driving chip is connected to the negative electrode B- of the second-color inorganic light-emitting diode, the fourth signal terminal O4 of the pixel driving chip is connected to the scanning line Sn, the fifth signal terminal O5 of the pixel driving chip is connected to the data signal line Dn through the via hole P1, and the sixth signal terminal O6 of the pixel driving chip is connected to the reference signal line Vm through the via hole P2. The positive electrode R+ of the first-color inorganic light-emitting diode is connected to the positive signal line Hm1 through the via hole P5, and the positive electrode G+ of the third-color inorganic light-emitting diode is connected to the positive signal line Hm2 through the via hole P4. The positive electrode B+ of the second-color inorganic light-emitting diode is connected to the positive signal line Hm2 through the via hole 4.

[0053] FIG. 7 is a schematic structural diagram in which only one scanning signal routing wire Cn is arranged in the row direction on both sides of the pixel column. In FIG. 7, the scanning signal routing wire Cn is connected to the scanning line Sn via the via hole P3.

[0054] FIG. 8 is a schematic structural diagram in which scanning signal routing wires (Cn and Cn + 1) are arranged in the row direction on both sides of the pixel column respectively. In FIG. 8, the scanning signal routing Cn is connected to the scanning line Sn via the via hole P3, and the scanning signal routing wire C n+1 is connected to other scanning lines (not shown in FIG. 8).

[0055] Optionally, in the array substrate provided by the embodiment of the present invention, as shown in FIG. 9, the bezel region A2 located at one end of the data signal line Dm includes a bending region A21, a wiring region A22, and a bonding region A23 that are sequentially farther away from the display region.

[0056] The bonding region A23 is provided with at least one first chip IC1 and at least one second chip IC2.

[0057] The scanning signal routing wire Cn and the data signal line Dm are sequentially connected to the first chip IC1 via routing wires arranged in the bending region A21 and the wiring region A22.

[0058] The reference signal line Vm and the positive signal line Hm are sequentially connected to the second chip IC2 via routing wires arranged in the bending region A21 and the wiring region A22.

[0059] During a specific implementation, in the array substrate provided by the embodiment of the present invention, only one first chip and one second chip can be arranged in the bonding region. In this way, the amount of chips can be reduced.

[0060] During a specific implementation, for example, as shown in FIG. 13, when only one first chip IC1 and one second chip IC2 are arranged in the bonding region A23, the first chip IC1 is arranged on the left side and the second chip IC2 is arranged on the right side. Therefore, the routing wires on the left side of the wiring region A22 are close to the first chip IC1 and far from the second chip IC2. The wiring on the right side of the wiring region A22 is far from the first chip IC1 and close to the second chip IC2. That is, the routing wires on the left side of the wiring region A22 and the routing wires on the right side of the wiring region A22 are at different distances from the same chip. This leads to a large difference in the length of the routing wires in the wiring region, that is, an inconsistent load of the wiring, and as a result, the display becomes uneven.

[0061] During a specific implementation, the scan signal routing wires provide a digital voltage signal that functions to control when to write the signal on the data signal line to the pixel driving chip. Therefore, the breakdown current on the scan signal routing wires and the data signal line is small and is not affected by the IR drop generated by the routing wires in the wiring region. Thus, in the wiring region, the width of the corresponding routing wires can be arranged relatively narrow and / or the length can be arranged relatively long. Although the reference signal line and the positive signal line are all fixed voltage signals, they are connected in series to the current path of the inorganic light-emitting diode, and a current of mA magnitude flows through the current path. Therefore, the IR drop generated by the routing wires in the wiring region may affect the signals in the current path. In this case, it is necessary to widen the line width and / or shorten the line length as much as possible for the routing wires in the wiring region.

[0062] Therefore, in the array substrate provided by the embodiment of the present invention, as shown in FIG. 9, a plurality of first chips IC1 and a plurality of second chips IC2 are arranged in the bonding region A23, and the first chip IC1 and the second chip IC2 are arranged at intervals within the bonding region A23. Therefore, the difference in the length of the routing wires in the wiring region can be reduced.

[0063] Furthermore, the first driving chip can be arranged at a position closer to the center of the bonding region, and the second chip can be arranged at positions closer to both sides of the bonding region. Thereby, the routing wire connected to the first chip can be arranged relatively long, and the routing wire connected to the second chip can be arranged relatively short.

[0064] Furthermore, in the array substrate provided by the embodiment of the present invention, since the functions of the signal lines are different, it is necessary to use different chips to provide signals, but signals can also be provided by a single chip. In this case, the pin arrangement of the chip can also be arranged with reference to the above rules. For example, the pins for providing signals to the scanning signal routing wire and the pins for providing signals to the data signal line are arranged in the central region of the chip, and the pins for providing signals to the reference signal line and the positive signal line are arranged at both ends of the chip. Optionally, in the array substrate provided by the embodiment of the present invention, as shown in FIG. 9, all the routing wires 03 in the bending region A21 are arranged in the second metal layer.

[0065] Optionally, in the array substrate provided by the embodiment of the present invention, as shown in FIGS. 9 and 10, in the wiring region A22, all the routing wires 041 connected to the scanning signal routing wire Cn and the routing wires 042 connected to the data signal line Dm are arranged in the first metal layer.

[0066] In the wiring area A22, all of the routing wire 051 connected to the reference signal line Vm and the routing wire 052 connected to the positive signal line Hm are arranged on the second metal layer. For example, FIG. 10 shows an example in which the second metal layer is arranged between the first metal layer and the base substrate 100. Specifically, a planarization layer 101 is further arranged between the first metal layer and the second metal layer, and a protective layer 102 is further arranged on the first metal layer.

[0067] During a specific implementation, the material of the planarization layer can be silicon oxide or silicon nitride or other inorganic materials, or can be an organic material such as a resin not limited herein.

[0068] During a specific implementation, the material of the protective layer can be silicon oxide or silicon nitride or other inorganic materials, or can be an organic material such as a resin not limited herein.

[0069] Alternatively, optionally, in the array substrate provided by the embodiment of the present invention, in the wiring area, all of the routing wires connected to the scanning signal routing wire and the routing wires connected to the data signal lines are arranged on the second metal layer.

[0070] In the wiring area, all of the routing wires connected to the reference signal and the routing wires connected to the positive signal line are arranged on the first metal layer.

[0071] During a specific implementation, in the array substrate provided by the embodiment of the present invention, in the wiring area, in order to solve the problem of limited space in the wiring area, the routing wires are arranged on two metal layers.

[0072] During a specific implementation, in the array substrate provided by the embodiment of the present invention, after the manufacturing procedure of the array substrate is completed, the wiring area and the bonding area are bent to the back of the display panel through the bending area, and the bezel of the display panel can be reduced.

[0073] During a specific implementation, in the array substrate provided by an embodiment of the present invention, as shown in FIG. 9, the scanning signal routing wire Cn, the data signal line Dm, the reference signal line Vm, and the positive signal line Hm are all adjusted to be vertical signal lines.

[0074] The bezel area A2 further includes a first signal input area A24 located on one side of the bonding area A23 far from the wiring area A22, and a second signal input area A25 located on one side of the data signal line Dm far from the bending area A21.

[0075] The first input electrode Tp1 corresponding one-to-one to all the vertical signal lines is arranged in the first signal area A24, and all the vertical signal lines in the display area A1 pass through the routing wires in the bending area A21 and the wiring area A22 in sequence and are connected to the corresponding first input electrode Tp1.

[0076] The second input electrode Tp2 corresponding one-to-one to all the vertical direction signal lines is arranged in the second signal input area A25.

[0077] For example, in the wiring area A22, the routing wire 041 connected to the scanning signal routing wire Cn and the routing wire 042 connected to the data signal line Dm are all arranged in the first metal layer. In the wiring area A22, the routing wire 051 connected to the reference signal line Vm and the routing wire 052 connected to the positive signal line Hm are all arranged in the second metal layer.

[0078] Specifically, as shown in FIG. 11, the scanning signal routing wire Cn disposed in the second metal layer is coupled to the first chip IC1 in the bonding region A23 and connected to the first input electrode Tp1 in the first signal input region A24 in the transparent conductive layer 103 through the bending region A21 and the routing wire 03 located in the second metal layer, and the wiring region A22 and the routing wire 041 located in the first metal layer in sequence. Here, the relationship of the film layer of the data signal line is the same as that of the scanning signal routing wire, and will not be repeated in detail in this specification.

[0079] Specifically, as shown in FIG. 12, the reference signal line Vm located in the second metal layer is coupled to the second chip IC2 in the bonding region A23 and connected to the first input electrode Tp1 in the first signal input region A24 through the bending region A21 and the routing wire 03 located in the second metal layer, and the wiring region A22 and the routing wire 051 located in the second metal layer in sequence, through the first metal layer and the transparent conductive layer 103. Here, the relationship of the film layer of the positive signal line is the same as that of the reference signal line, and will not be repeated in detail in this specification.

[0080] Optionally, in the array substrate provided by the embodiment of the present invention, as shown in FIG. 9, the bezel region A2 located at one end of the scanning line Sn includes a third signal input region A26. The bezel region located at the other end of the scanning line Sn includes a fourth signal input region A27. A third input electrode Tp3 corresponding to each scanning line Sn in a one-to-one manner is disposed in the third signal input region A26. A fourth input electrode Tp4 corresponding to each scanning line Sn in a one-to-one manner is disposed in the fourth signal input region A27.

[0081] During a specific implementation, whether all the vertical signal lines on the array substrate are normal can be detected in a mode of inputting a signal to one input electrode and detecting the signals of other input electrodes. After the detection and confirmation that the product is free of defects, the signal input region can be blocked, which will not affect the use in the subsequent stage of the panel.

[0082] Based on the same inventive concept, embodiments of the present invention further provide a method for detecting any array substrate provided by the embodiments of the present invention. Here, the vertical signal lines and scanning lines in the display area are the lines to be detected. As shown in FIG. 14, this method includes the following steps.

[0083] S101. For each of the lines to be detected, input a test signal to one input electrode connected to the line to be detected.

[0084] S102. Detect whether another input electrode connected to the line to be detected outputs a signal. If the detection result is that another input electrode connected to the line to be detected does not output a signal, it is determined that the line to be detected is disconnected.

[0085] S103. Detect whether the input electrodes of the lines to be detected other than the line to be detected where the test signal is input output a signal. If the detection result is that the input electrode of another line to be detected outputs a signal, it is determined that there is a short circuit between the line to be detected where the test signal is input and another line to be detected whose input electrode outputs a signal.

[0086] By the detection method provided by the embodiments of the present invention, by inputting a signal to the input electrode and detecting whether the input electrode of another line to be detected outputs a signal, it is possible to confirm whether the line to be detected is short-circuited or disconnected. The detection method is simple and is applied to the manufacturing process of array substrate electrodes to reduce costs.

[0087] In a specific implementation, in the method provided by the embodiments of the present invention, the order of steps S102 and S103 is not limited. Step S102 can be executed before step S103, and vice versa, which is not limited in this specification.

[0088] The application of the method for detecting an array substrate provided by the embodiments of the present invention will be described below through an embodiment.

[0089] During a specific implementation, for example, during manufacturing, the second metal layer located under the first metal layer is lifted, the second metal layer is manufactured first, and the scanning signal routing wire, data signal line, reference signal line, and positive signal line are formed on the second metal layer. For the reference signal line and the positive signal line, at present, the first input electrode of the first signal input region and the second input electrode of the second signal input region are used in cooperation with each other to detect whether the reference signal line and the positive signal line are normal. For example, a test signal is input to the first input electrode of the reference signal line, and it is detected whether the second input electrode connected to the reference signal line outputs a signal. If the detection result is that a signal is output, it is determined that the reference signal line is normal; if the detection result is that no signal is output, it is determined that the reference signal line is disconnected and repaired. It is detected whether the first input electrode or the second input electrode connected to another signal line other than the reference signal line outputs a signal. If the detection result is that a signal is output, it is determined that no short circuit has occurred between the reference signal line and the other signal line; if the detection result is that no signal is output, it is determined that a short circuit has occurred between the reference signal line and the other signal line, and the short-circuited signal line is repaired. If there is no abnormality in all the reference signal lines and positive signal lines, the planarization layer continues to be deposited, and via holes are formed in the planarization layer. At present, the detection of the reference signal line and the positive signal line is repeated. After the detection result becomes normal, the second metal layer continues to be deposited, the scanning line is formed on the second metal layer, and the connection between the data signal line and the scanning signal routing wire and the signal of the first output electrode is completed. At present, in order to detect whether all the signal lines on the array substrate are normal, the first input electrode of the first signal input region, the second input electrode of the second signal input region, the third input electrode of the third signal input region, and the fourth input electrode of the fourth signal input region are used in cooperation with each other. If a short circuit or disconnection occurs, repairs are made until all the signal lines are normal. This avoids the situation where the array substrate is scraped due to abnormal signal lines and reduces the manufacturing cost.

[0090] Based on the concept of the same invention, embodiments of the present invention further provide a splicing display panel including a plurality of array substrates provided by the embodiments of the present invention. Since the principle of solving the problems of the display panel is similar to that of the above array substrate, the implementation of the splicing display panel can refer to the implementation of the above array substrate, and the repetition is omitted.

[0091] During a specific implementation, in the splicing display panel provided by the embodiments of the present invention, the second signal input region, the third signal input region, and the fourth signal input region of the array substrate can be cut after the manufacturing of the array substrate is completed, without affecting the subsequent splicing manufacturing procedure. The wiring region and the bonding region are bent to the back of the display panel through the bending region so that the width of the bezel of the display panel can be formed.

[0092] During a specific implementation, in the splicing display panel provided by the embodiments of the present invention, the wiring regions and the bonding regions of the plurality of array substrates are bent to the back of the display panel through the bending regions, and its technical value is very high because of the advantages such as fewer patterning processes, no need for a back process, low process complexity, and a small bezel.

[0093] An array substrate provided by an embodiment of the present invention, a method for detecting the array substrate, and in a splicing display panel, pixels in the array substrate include at least three-color sub-pixels and pixel driving chips that drive each sub-pixel to emit light. Each sub-pixel includes at least one inorganic light-emitting diode. The display area further includes a positive signal line connected to the anode of the inorganic light-emitting diode, a data signal line connected to the pixel driving chip, a scanning line, and a reference signal line. The pixel driving chip is configured to write the signals of the data signal line into different-color sub-pixels in a time-division manner under the control of the scanning line. That is, in the embodiment of the present invention, in order to realize display, all pixels are directly driven through the pixel driving chip. Further, since all pixels are directly driven through the pixel driving chip, a large current density can be provided to the micro inorganic light-emitting diodes.

[0094] Those skilled in the art can make various changes and conversions to the present invention without departing from the spirit and scope of the present invention. In this case, if these changes and conversions of the present invention are within the scope, the present invention also intends to include these changes and conversions among the claims of the present invention and those equivalent thereto.

Claims

Claim 1 An array substrate, wherein the array substrate includes a display area and a bezel area, and the display area includes a plurality of scanning lines, a plurality of data signal lines, a plurality of positive signal lines, a plurality of reference signal lines, and a plurality of pixels arranged in an array, at least one of the plurality of pixels includes at least three-color sub-pixels and a pixel driving chip for driving the light emission of each of the sub-pixels, each of the sub-pixels includes at least one inorganic light-emitting diode, the pixel driving chip is connected to the positive electrode of the inorganic light-emitting diode in each of the sub-pixels it drives, one of the plurality of data signal lines, one of the plurality of scanning lines, and one of the plurality of reference signal lines, the pixel driving chip is configured to write the signal of the data signal line to different-color sub-pixels in a time-division manner under the control of the scanning line, and the reference signal line is configured to provide a negative electrode signal to the pixel driving chip so that a current circuit is formed between the inorganic light-emitting diode and the pixel driving chip, the plurality of pixels include N pixel rows arranged in a first direction and M pixel columns arranged in a second direction, and both N and M are integers greater than 1, the plurality of scanning lines extend in the first direction and are arranged in the second direction, the plurality of data signal lines extend in the second direction and are arranged in the first direction, the plurality of positive signal lines extend in the second direction and are arranged in the first direction, and the plurality of reference signal lines extend in the second direction and are arranged in the first direction, wherein the first direction is different from the second direction. An array substrate characterized by this. Claim 2 Each of the pixel rows corresponds to one of the plurality of scanning lines, and each of the pixel columns corresponds to one of the plurality of data signal lines, one of the plurality of reference signal lines, and one of the plurality of positive signal lines. The array substrate according to Claim 1, characterized by this. Claim 3 The pixel includes a sub-pixel of a first color, a sub-pixel of a second color, and a sub-pixel of a third color, each of the pixel rows corresponds to one of the plurality of scanning lines, and each of the pixel columns corresponds to one of the plurality of data signal lines, one of the plurality of reference signal lines, and two of the plurality of positive signal lines. One of the two positive signal lines is connected to the anode of the inorganic light-emitting diode in the sub-pixel of the first color, and the other positive signal line is connected to the anodes of the inorganic light-emitting diodes in the sub-pixels of the third color and the second color. The array substrate according to claim 1, characterized in that.

4. The display area further includes scanning signal routing wires connected to each of the plurality of scanning lines in a one-to-one correspondence, and the scanning signal routing wires extend in the second direction. The array substrate according to claim 2 or claim 3, characterized in that.

5. N = M. Corresponding to one side of each pixel column, one of the scanning signal routing wires is arranged, and only one of the scanning signal routing wires is arranged between two adjacent pixel columns. The array substrate according to claim 4, characterized in that.

6. N > M. At least one scanning signal routing wire is arranged on each of the two sides of at least one pixel column, At least one scanning signal routing wire is arranged between at least a part of two adjacent pixel columns, and the number of the scanning signal routing wires between two adjacent pixel columns does not exceed two. The array substrate according to claim 4, characterized in that.

7. The scanning line is arranged in the first metal layer, and the scanning signal routing wire, the data signal line, the reference signal line and the positive signal line are arranged in the second metal layer. The array substrate according to claim 4, characterized in that.

8. The bezel area arranged at one end of the data signal line includes a bending area, a wiring area and a bonding area that are sequentially farther away from the display area, At least one first chip and at least one second chip are arranged in the bonding area, The scanning signal routing wire and the data signal line are sequentially connected to the first chip through routing wires arranged in the bending area and the wiring area, The reference signal line and the positive signal line are sequentially connected to the second chip through routing wires arranged in the bending area and the wiring area. The array substrate according to claim 7, characterized in that.

9. A plurality of the first chips and a plurality of the second chips are arranged in the bonding area, The array substrate according to claim 8, wherein the first chip and the second chip are arranged at intervals in the bonding region.

10. The array substrate according to claim 8, wherein all the routing wires in the bending region are arranged in the second metal layer.

11. In the wiring region, all the routing wires connected to the scanning signal routing wires and the routing wires connected to the data signal lines are arranged in the first metal layer. The array substrate according to claim 8, wherein all the routing wires connected to the reference signal line and the routing wires connected to the positive signal line in the wiring region are arranged in the second metal layer.

12. In the wiring region, all the routing wires connected to the scanning signal routing wires and the routing wires connected to the data signal lines are arranged in the second metal layer. The array substrate according to claim 8, wherein all the routing wires connected to the reference signal line and the routing wires connected to the positive signal line in the wiring region are arranged in the first metal layer.

13. The scanning signal routing wire, the data signal line, the reference signal line, and the positive signal line are all vertical signal lines. The bezel region further includes a first signal input region arranged on the side of the bonding region far from the wiring region, and a second signal input region arranged on the side of the data signal line far from the bending region. A first input electrode corresponding one-to-one to each of the vertical signal lines is arranged in the first signal input region, and each of the vertical signal lines in the display region is sequentially connected to the corresponding first input electrode via routing wires arranged in the bending region and the wiring region. The array substrate according to claim 8, wherein the array substrate is arranged on the side of the second input electrode corresponding to each of the vertical signal lines one-to-one in the second signal input region.

14. One end of the bezel region of the scanning line includes a third signal input region. The other end of the bezel region of the scanning line includes a fourth signal input region. The third signal input region is provided with a third input electrode corresponding one-to-one to each of the scanning lines. The array substrate according to claim 13, wherein the array substrate is disposed on a fourth input electrode side that is connected to each of the scanning lines in a one-to-one correspondence in the fourth signal input region.

15. A splicing display panel comprising the array substrate according to any one of claims 1 to 14.

16. A method for detecting the array substrate according to claim 13 or claim 14, wherein the vertical signal lines and the scanning lines in the display region are used as lines to be detected, and the method for detection is as follows: for each of the lines to be detected, inputting a test signal to one input electrode connected to the line to be detected; detecting whether another input electrode connected to the line to be detected outputs a signal, and if the detection result is that another input electrode connected to the line to be detected does not output a signal, determining that the line to be detected is disconnected; detecting whether an input electrode of another line to be detected other than the line to be detected to which the test signal is input outputs a signal, and if the detection result is that the input electrode of another line to be detected outputs a signal, determining that a short circuit has occurred between the line to be detected to which the test signal is input and another line to be detected whose input electrode outputs a signal characterized by comprising the steps.

Images