Differential power amplifier

Abstract

The embodiment of the present invention discloses a differential power amplifier, comprising an input matching network, a first stage amplifier circuit, a first inter-stage matching network, a second stage amplifier circuit, a second inter-stage matching network, a third stage amplifier circuit and an output matching network, which are connected in series in order, the first stage amplifier circuit and the second stage amplifier circuit are single-input single-output circuits, the third stage amplifier circuit is a dual-input dual-output circuit, the second inter-stage matching network comprises a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1 and a second inductor L2, and the output matching network comprises a second transformer T2, so that the inter-stage matching network and the output matching network are realized by the transformer, which can effectively reduce the difficulty of inter-stage matching, effectively optimize the input return loss and gain, and improve the output power.

Description

Technical Field

[0001] The present invention relates to the technical field of power amplifiers, and particularly to differential power amplifiers.

Background Art

[0002] In a 5G wireless communication system, the key module is the RF Power Amplifier located at the final stage of the transmitter. Its function is to amplify the output signal and transmit the amplified signal through the antenna. The RF power amplifier directly affects and determines various performance indicators of the transmitter system, such as output power, efficiency, gain, linearity, operating bandwidth, reflection coefficient, etc., and thereby affects and determines each performance indicator of the entire 5G wireless communication system. The conventional matching structure is a combination of one or more capacitors and inductors in series and parallel. The purpose of the matching structure of capacitors and inductors is to realize impedance changes when connecting the input and output ports of the power amplifier to a 50-ohm port, and achieve effects such as maximum gain transmission or maximum power transmission according to the needs of different amplifiers. Conventional impedance matching is often a "Π-type", "T-type", or "L-type" matching network, and an optimal matching structure and matching device can be selected based on different impedance points.

[0003] In 5G mobile communication, the requirement for the output power of the RF power amplifier is greater. Therefore, more transistors are required to design and realize high power, which improves the difficulty of matching. In addition, capacitors, inductors, and resistors at high frequencies generate large parasitic effects. As a result, there is a certain difference between the actual value and the ideal value of the device, which shows that impedance matching at high frequencies becomes more difficult. In actual design, when only using the conventional matching structure of capacitors and inductors, the input return loss and gain cannot be matched in a good state.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a differential power amplifier that can reduce the difficulty of matching, has high gain and output power, and can optimize input return loss.

Means for Solving the Problem

[0005] To solve the above technical problems, the present invention includes an input matching network, a first-stage amplification circuit, a first-stage inter-stage matching network, a second-stage amplification circuit, a second-stage inter-stage matching network, a third-stage amplification circuit, and an output matching network. The first-stage amplification circuit and the second-stage amplification circuit are single-input single-output circuits, the third-stage amplification circuit is a dual-input dual-output circuit, the second-stage inter-stage matching network includes a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2, and the output matching network includes a second transformer T2. The input terminal and the output terminal of the input matching network are respectively connected to a single-ended RF input signal RFin and the input terminal of the first-stage amplification circuit. The output terminal of the first-stage amplification circuit is connected to the input terminal of the first-stage inter-stage matching network. The output terminal of the first-stage inter-stage matching network is connected to the input terminal of the second-stage amplification circuit. Two input terminals of the first transformer T1 are respectively connected to the output terminal of the second-stage amplification circuit and the supply voltage Vcc2. The single-ended signal from the second-stage amplification circuit is converted into a pair of differential signals and input to two input terminals of the third-stage amplification circuit respectively. Two output terminals of the third-stage amplification circuit are respectively connected to two input terminals of the second transformer T2. One output terminal of the second transformer T2 is grounded, and the other output terminal is used to output a single-ended RF output signal RFout. One terminal of each of the first capacitor C1 and the second capacitor C2 is connected to two input terminals of the first transformer T1, the other terminals of the first capacitor C1 and the second capacitor C2 are grounded respectively, one terminal of each of the first inductor L1 and the second inductor L2 is connected to two output terminals of the first transformer T1 respectively, and the other terminals of the first inductor L1 and the second inductor L2 are grounded respectively, to provide a differential power amplifier.

[0006] Furthermore, the first-stage amplification circuit includes one first transistor Q1, the second-stage amplification circuit includes one second transistor Q2, and the third-stage amplification circuit includes two third transistors Q3. The base, collector, and emitter of the first transistor Q1 are connected to the output terminal of the input matching network, the input terminal of the first inter-stage matching network, and the ground terminal respectively. The base, collector, and emitter of the second transistor Q2 are connected to the output terminal of the first inter-stage matching network, one input terminal of the first transformer T1, and the ground terminal respectively. The bases of the two third transistors Q3 are connected to the two output terminals of the first transformer T1 respectively. The collectors of the two third transistors Q3 are connected to the two input terminals of the second transformer T2 respectively, and the emitters of the two third transistors Q3 are grounded respectively.

[0007] Furthermore, the differential power amplifier further includes a negative feedback network connected between the collector and the base of the first transistor Q1. The negative feedback network includes a first resistor R1 and a third capacitor C3 connected in series. The first-stage amplification circuit further includes a second resistor R2 connected in series between the input matching network and the base of the first transistor Q1 and in parallel with the negative feedback network.

[0008] Furthermore, the second inter-stage matching network further includes a fourth capacitor C4, a fifth capacitor C5, and a third inductor L3. The fourth capacitor C4 is connected in series between one output terminal of the first transformer T1 and the base of one third transistor Q3, the fifth capacitor C5 is connected in series between another output terminal of the first transformer T1 and the base of another third transistor Q3, and the third inductor L3 is connected in series between the input terminal of the first transformer T1 and the power supply voltage Vcc2.

[0009] Furthermore, the output matching network further includes a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, and a fourth inductor L4. One terminal of the sixth capacitor C6 and the seventh capacitor C7 is connected to two input terminals of the second transformer T2 respectively, the other terminal of the sixth capacitor C6 and the seventh capacitor C7 is grounded respectively, one terminal of the eighth capacitor C8 is connected to the grounded output terminal of the second transformer T2, the other terminal of the eighth capacitor C8 is grounded, and the fourth inductor L4 is connected in series between the grounded output terminal of the second transformer T2 and the ground terminal.

[0010] Furthermore, the input matching network includes a ninth capacitor C9, a tenth capacitor C10, a fifth inductor L5, and a sixth inductor L6. One terminal of the ninth capacitor C9 is connected to one terminal of the fifth inductor L5, and the connection node is used to input the single-ended RF input signal RFin. The other terminal of the fifth inductor L5 is grounded. The other terminal of the ninth capacitor C9 is connected to one terminal of the tenth capacitor C10. The other terminal of the tenth capacitor C10 is connected to the input terminal of the first-stage amplification circuit. One terminal of the sixth inductor L6 is connected between the ninth capacitor C9 and the tenth capacitor C10, and the other terminal of the sixth inductor L6 is grounded.

[0011] Furthermore, the second-stage amplification circuit further includes a third resistor R3, and the third resistor R3 is connected in series between the output terminal of the first-stage inter-stage matching network and the input terminal of the second-stage amplification circuit.

[0012] Furthermore, it further includes a base bias circuit connected one-to-one to the base of each of the transistors, The base bias circuit includes a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an eleventh capacitor C11, The base and collector of the fourth transistor Q4, the base of the fifth transistor Q5, one terminal of the fourth resistor R4, and one terminal of the eleventh capacitor C11 are connected. The other terminal of the fourth resistor R4 is connected to the power supply voltage Vreg. The emitter of the fourth transistor Q4, the collector and base of the sixth transistor Q6 are connected. The emitter of the sixth transistor Q6 is connected to one terminal of the fifth resistor R5. The other terminal of the fifth resistor R5 is grounded. The other terminal of the eleventh capacitor C11 is grounded. The collector of the fifth transistor Q5 is connected to the power supply voltage Vbat. The emitter of the fifth transistor Q5 is connected to one terminal of the sixth resistor R6. The other terminal of the sixth resistor R6 is connected to the base of the corresponding transistor.

[0013] Furthermore, the first-stage matching network includes a seventh inductor L7, an eighth inductor L8, a fourteenth capacitor C14, and a fifteenth capacitor C15, One terminal of the seventh inductor L7 and one terminal of the fourteenth capacitor C14 are both connected to the output terminal of the first-stage amplifier circuit. The other terminal of the seventh inductor L7 is connected to the power supply voltage Vcc1. The other terminal of the fourteenth capacitor C14, one terminal of the eighth inductor L8, and one terminal of the fifteenth capacitor C15 are connected. The other terminal of the fifteenth capacitor C15 is connected to the input terminal of the second-stage amplifier circuit. The other terminal of the eighth inductor L8 is grounded.

[0014] Furthermore, both the first transformer T1 and the second transformer T2 are symmetrical mutual-wound transformers.

Advantages of the Invention

[0015] The differential power amplifier of the present invention includes an input matching network, a first-stage amplification circuit, a first-stage inter-stage matching network, a second-stage amplification circuit, a second-stage inter-stage matching network, a third-stage amplification circuit, and an output matching network. The second-stage inter-stage matching network includes a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2. The output matching network includes a second transformer T2. One terminal of the first capacitor C1 and the second capacitor C2 is respectively connected to two input terminals of the first transformer, and the other terminal of the first capacitor C1 and the second capacitor C2 is respectively grounded. One terminal of the first inductor L1 and the second inductor L2 is respectively connected to two output terminals of the first transformer, and the other terminal of the first inductor L1 and the second inductor L2 is respectively grounded. Thereby, by realizing the inter-stage matching network and the output matching network with transformers, the difficulty of inter-stage matching can be effectively reduced, the input return loss and the gain can be effectively optimized, and the output power can be improved. With the functions of capacitors C1, C2, inductors L1, and L2, the matching bandwidth of the transformer can be increased, and the insertion loss of the transformer matching can be reduced.

[0016] Hereinafter, with reference to the drawings, the specific embodiments of the present invention will be described in detail to clarify the technical solution and its beneficial effects of the present invention.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0018] Referring to the drawings, the same reference numerals for the same components represent the same components, and the principle of the present invention will be described by taking its implementation in a suitable computing environment as an example. The following description is based on specific exemplary embodiments of the present invention shown, and should not be considered as limiting other specific embodiments not detailed in the present invention.

[0019] Referring to FIG. 1, the differential power amplifier 100 according to an embodiment of the present invention includes an input matching network 11, a first-stage amplification circuit 12, a first-stage inter-stage matching network 13, a second-stage amplification circuit 14, a second-stage inter-stage matching network 15, a third-stage amplification circuit 16, and an output matching network 17 connected in series in sequence.

[0020] The first-stage amplification circuit 12 and the second-stage amplification circuit 14 are single-input single-output circuits, that is, both the first-stage amplification circuit 12 and the second-stage amplification circuit 14 are circuits having one input terminal and one output terminal, and the third-stage amplification circuit 16 is a dual-input dual-output circuit. The second-stage inter-stage matching network 15 includes a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2, and the output matching network 17 includes a second transformer T2.

[0021] Here, the input terminal and the output terminal of the input matching network 11 are respectively connected to the single-ended RF input signal RFin and the input terminal of the first-stage amplifier circuit 12. The output terminal of the first-stage amplifier circuit 12 is connected to the input terminal of the first-stage inter-stage matching network 13. The output terminal of the first-stage inter-stage matching network 13 is connected to the input terminal of the second-stage amplifier circuit 14. The two input terminals of the first transformer T1 are respectively connected to the output terminal of the second-stage amplifier circuit 14 and the power supply voltage Vcc2. The single-ended signal from the second-stage amplifier circuit 14 is converted into a pair of differential signals and input to the two input terminals of the third-stage amplifier circuit 16 respectively. The two output terminals of the third-stage amplifier circuit 16 are respectively connected to the two input terminals of the second transformer T2. One output terminal of the second transformer T2 is grounded, and the other output terminal is used to output the single-ended RF output signal RFout.

[0022] Here, one terminal of the first capacitor C1 and the second capacitor C2 is respectively connected to the two input terminals of the first transformer T1, and the other terminal of the first capacitor C1 and the second capacitor C2 is respectively grounded. One terminal of the first inductor L1 and the second inductor L2 is respectively connected to the two output terminals of the first transformer T1, and the other terminal of the first inductor L1 and the second inductor L2 is respectively grounded. Here, the first inductor L1 and the second inductor L2 can be realized by using the same inductor element, and their sizes are the same.

[0023] Therefore, in the embodiment of the present invention, the differential power amplifier 100 is realized by using a three-stage amplifier circuit, so that a high gain can be obtained. By realizing the inter-stage matching network and the output matching network with transformers, the difficulty of inter-stage matching can be effectively reduced, the input return loss and the gain can be effectively optimized, which is beneficial to the improvement of the output power. With the action of the capacitors C1, C2, inductors L1, and L2, the matching bandwidth of the transformer can be increased, and the insertion loss of the transformer matching can be reduced.

[0024] In some implementation manners of the present invention, the first-stage amplifier circuit 12, the second-stage amplifier circuit 14, and the third-stage amplifier circuit 16 can be realized by using HBT transistors. Naturally, in some other implementation manners, they may also be realized by using other processes. For example, each stage amplifier circuit may be realized by using a COMS transistor, a HEMT transistor, or a PHEMT transistor.

[0025] Taking the HBT transistor as an example, the first-stage amplifier circuit 12 includes one first transistor Q1, the second-stage amplifier circuit 14 includes one second transistor Q2, and the third-stage amplifier circuit 16 includes two third transistors Q3.

[0026] Here, the base, collector, and emitter of the first transistor Q1 are respectively connected to the output terminal of the input matching network 11, the input terminal of the first inter-stage matching network 13, and the ground terminal. The base, collector, and emitter of the second transistor Q2 are respectively connected to the output terminal of the first inter-stage matching network 13, one input terminal of the first transformer T1, and the ground terminal. The bases of the two third transistors Q3 are respectively connected to the two output terminals of the first transformer T1. The collectors of the two third transistors Q3 are respectively connected to the two input terminals of the second transformer T2. The emitters of the two third transistors Q3 are respectively grounded.

[0027] Furthermore, the differential power amplifier 100 further includes a negative feedback network 18 connected between the collector and the base of the first transistor Q1. The negative feedback network 18 includes a first resistor R1 and a third capacitor C3 connected in series. The first-stage amplification circuit 12 further includes a second resistor R2. The second resistor R2 is connected in series between the input matching network 11 and the base of the first transistor Q1 and is connected in parallel to the negative feedback network 18. In this way, by connecting the second resistor R2 with a small resistance value in series to the base of the first transistor Q1 and adding the negative feedback network 18 between the collector and the base of the first transistor Q1, the stability can be enhanced and the gain and output power of the first-stage amplification circuit 12 can be reduced. Here, the depth of feedback can be adjusted by the action of the first resistor R1.

[0028] As can be seen from FIG. 1, in the embodiment of the present invention, the first-stage amplifier circuit 12 is realized by using a first transistor Q1. In other embodiments, the number of the first transistors Q1 is not limited to one, and the first-stage amplifier circuit 12 can be realized by using a plurality of first transistors Q1 connected in parallel. The method for realizing the parallel connection of the plurality of first transistors Q1 is that the bases of the plurality of first transistors Q1 are respectively connected in series to one second resistor R2 and then connected in parallel, the collectors of the first transistors Q1 are connected in parallel to form the output terminal of the first-stage amplifier circuit 12, and the emitters of the first transistors Q1 are all grounded. Similarly, in the embodiment shown in FIG. 1, the second-stage amplifier circuit 14 is also realized by using a second transistor Q2 to form an amplifier circuit. In other embodiments, the second-stage amplifier circuit 14 can also be realized by using a plurality of second transistors Q2 connected in parallel. The plurality of second transistors Q2 connected in parallel have their bases connected in parallel, their collectors connected in parallel, and their emitters all grounded. Further, the third-stage amplifier circuit 16 is realized by using two third transistors Q3 to form two amplifier circuits respectively. In other embodiments, each amplifier circuit of the third-stage amplifier circuit 16 can be realized by using a plurality of third transistors Q3 connected in parallel. In each circuit, the plurality of third transistors Q3 connected in parallel have their bases connected in parallel, their collectors connected in parallel, and their emitters grounded.

[0029] Furthermore, the second-stage matching network 15 further includes a fourth capacitor C4, a fifth capacitor C5, and a third inductor L3. The fourth capacitor C4 is serially connected between one output terminal of the first transformer T1 and the base of one third transistor Q3. The fifth capacitor C5 is serially connected between another output terminal of the first transformer T1 and the base of another third transistor Q3. The third inductor L3 is serially connected between the input terminal of the first transformer T1 and the power supply voltage Vcc2. The fourth capacitor C4 and the fifth capacitor C5 are DC-blocking capacitors, which can be realized by using the same capacitor element, and their sizes are the same. They can play a role in adjusting the gain of the third-stage amplifier circuit 16.

[0030] Here, the output matching network 17 further includes a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, and a fourth inductor L4.

[0031] One terminal of the sixth capacitor C6 and the seventh capacitor C7 is respectively connected to two input terminals of the second transformer T2, the other terminals of the sixth capacitor C6 and the seventh capacitor C7 are respectively grounded, one terminal of the eighth capacitor C8 is connected to the grounded output terminal of the second transformer T2, the other terminal of the eighth capacitor C8 is grounded, and the fourth inductor L4 is serially connected between the grounded output terminal and the ground terminal of the second transformer T2.

[0032] Here, in order to optimize the insertion return loss of the entire circuit, the input matching network 11 is realized by using a two-stage LC matching, that is, a high-pass matching structure formed by inductors connected in parallel and grounded and connected in series with capacitors, which is advantageous for increasing stability and reducing the gain and output power of the first-stage amplifier circuit 12. Specifically, the input matching network 11 includes a ninth capacitor C9, a tenth capacitor C10, a fifth inductor L5, and a sixth inductor L6. One terminal of the ninth capacitor C9 is connected to one terminal of the fifth inductor L5, and the connection node is used to input the single-ended RF input signal RFin. The other terminal of the fifth inductor L5 is grounded, the other terminal of the ninth capacitor C9 is connected to one terminal of the tenth capacitor C10, the other terminal of the tenth capacitor C10 is connected to one terminal of the second resistor R2, that is, the second resistor R2 is serially connected between the tenth capacitor C10 and the base of the first transistor Q1. One terminal of the sixth inductor L6 is connected between the ninth capacitor C9 and the tenth capacitor C10, and the other terminal of the sixth inductor L6 is grounded.

[0033] Furthermore, the second-stage amplifier circuit 14 further includes a third resistor R3. The first-stage matching network 13 is also realized using two-stage LC matching, and the LC matching structure is also a high-pass matching structure. Specifically, the first-stage matching network 13 includes a seventh inductor L7, an eighth inductor L8, a fourteenth capacitor C14, and a fifteenth capacitor C15. One terminal of the seventh inductor L7 and one terminal of the fourteenth capacitor C14 are both connected to the collector of the first transistor Q1. The other terminal of the seventh inductor L7 is connected to the power supply voltage Vcc1, and the seventh inductor L7 is a choke inductor. The other terminal of the fourteenth capacitor C14, one terminal of the eighth inductor L8, and one terminal of the fifteenth capacitor C15 are connected. The other terminal of the fifteenth capacitor C15 is connected to one terminal of the third resistor R3, the other terminal of the third resistor R3 is connected to the base of the second transistor Q2, and the other terminal of the eighth inductor L8 is grounded. By the action of the first-stage matching network 13 and the third resistor R3, the stability of the second-stage amplifier circuit 14 can be further improved, and the insertion return loss can be optimized. And in order to ensure that the error vector magnitude (EVM) value of the entire circuit is low, a large margin is provided for the output power of the second-stage amplifier circuit 14, and the power at the 1 dB power compression point of this stage circuit is made about 4 dBm larger than the input power required by the third-stage amplifier circuit 16.

[0034] Here, the power supply voltages Vcc1 and Vcc2 are used to supply power to the corresponding devices, and their magnitudes may be the same or different, and can be selected according to actual needs.

[0035] Here, the differential power amplifier 100 further includes base bias circuits connected one-to-one to the bases of the respective transistors. That is, a base bias circuit 191 is connected to the base of the first transistor Q1, a base bias circuit 192 is connected to the base of the second transistor Q2, and a base bias circuit 193 is connected to the base of the third transistor Q3. Each base bias circuit is used to supply a bias voltage to the base of the corresponding transistor. The configurations of the base bias circuit 191, the base bias circuit 192, and the base bias circuit 193 may be the same or different. In the present embodiment, the three bias circuits are realized with the same circuit configuration.

[0036] Specifically, as shown in FIG. 2, the base bias circuit includes a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an eleventh capacitor C11.

[0037] The base and collector of the fourth transistor Q4, the base of the fifth transistor Q5, one terminal of the fourth resistor R4, and one terminal of the eleventh capacitor C11 are connected. The other terminal of the fourth resistor R4 is connected to the voltage signal Vreg. The emitter of the fourth transistor Q4, the collector and base of the sixth transistor Q6 are connected. The emitter of the sixth transistor Q6 is connected to one terminal of the fifth resistor R5. The other terminal of the fifth resistor R5 is grounded. The other terminal of the eleventh capacitor C11 is grounded. The collector of the fifth transistor Q5 is connected to the voltage signal Vbat. The emitter of the fifth transistor Q5 is connected to one terminal of the sixth resistor R6. The other terminal of the sixth resistor R6 is connected to the base of the corresponding transistor. For example, one terminal of the sixth resistor R6 in the base bias circuit 191 is connected to the emitter of the fifth transistor Q5, and the other terminal is connected to the base of the first transistor Q1, and the same applies hereinafter.

[0038] Here, the fourth resistor R4 and the fifth resistor R5 are voltage-dividing resistors, the sixth resistor R6 is a resistor for suppressing thermal effects, I1 and I2 are currents, and the eleventh capacitor C11 is a filter capacitor. The fourth transistor Q4 and the sixth transistor Q6 constitute a clamping voltage, making the current I2 a constant current, and the magnitude of the current I2 can be adjusted by adjusting the magnitudes of the fourth resistor R4 and the fifth resistor R5. The fourth transistor Q4 and the fifth transistor Q5 constitute a current mirror. Due to the amplification function of the fifth transistor Q5, the emitter current of the fifth transistor Q5 is mirror-amplified. Since I2 is a constant current, I1 = βI2. Taking the base bias circuit 191 connected to the first transistor Q1 as an example, when the input power increases and the power amplifier is in a high-power operating state, the DC current of the first transistor Q1 increases. Due to the self-heating effect of the transistor and the rectifying characteristics of the diode, the base potential of the first transistor Q1 decreases, and the signal in the RF circuit leaks to the bias circuit. Because the capacitor C11 exists, the signal reaches the ground through the emitter of the fifth transistor Q5, the base of the fifth transistor Q5, and the capacitor C11 in sequence. As a result, since the base potential of the fifth transistor Q5 does not change, the linearity of the power amplifier is effectively improved. Due to the rectifying action between the base and the emitter of the fifth transistor Q5, the voltage between the base and the emitter decreases, and since the base potential of the fifth transistor Q5 does not change, the decrease in the base voltage of the first transistor Q1 is effectively compensated, enabling the first transistor Q1 to maintain the quiescent point in a state of high input and high output power, and effectively suppressing gain compression.

[0039] Referring to FIGS. 3 and 4, in an embodiment of the present invention, both the first transformer T1 and the second transformer T2 are symmetrical interwound transformers, and the grounding point is on the axis of symmetry. Thereby, the accuracy of the phase can be fully ensured during the phase conversion of the output signal, which has great advantages in transmitting differential signals. In addition, since the symmetrical interwound transformer has a large transformer, the value of its coupling coefficient K is as large as 0.7 to 0.9. The larger the value of K, the closer the transformer approaches the ideal state, its bandwidth is wider, and the insertion loss is smaller. Since the ports of the primary coil and the secondary coil of the transformer are at both ends of the transformer, it is very suitable for cascading the front and rear stage circuits. For example, taking the first transformer T1 as an example, the E and F terminals of the transformer are respectively connected to the output terminal and the isolation terminal (i.e., the DC power supply terminal Vcc2) of the second transistor Q2. The E, F terminals and their connecting coils are the primary coil. The M and N terminals are connected to the input terminals of the two differential signals of the third-stage amplifier circuit. The M, N terminals and their connecting coils are the secondary coil. The ratio of the number of turns of the primary coil to the secondary coil is 2:1 to 1:1.

[0040] Here, the transformer in the embodiment of the present invention is realized by using a metal layer with three layers laminated. The primary coil of the transformer is realized by using the second layer of the metal layer, and the secondary coil is realized by using the first and third layers of the metal layer.

[0041] As shown in Fig. 5, Fig. 5 is a small-signal simulation and test waveform diagram of the differential power amplifier of the present invention. Here, the small signal includes the input return loss S11, the gain S21, and the output return loss S22, that is, Fig. 5 is a simulation and test waveform diagram of the input return loss S11, the gain S21, and the output return loss S22. Here, as the simulation and test conditions, the voltage signals of each Vcc (including Vcc in the bias circuit and Vcc1 to Vcc3) are all 5V, the Vbat of the three bias circuits are all 4.2V, the Vreg1 of the bias circuit 191 is 2.8V, the Vreg2 of the bias circuit 192 and the Vreg3 of the bias circuit 193 are both 3V. As for the quiescent current of each stage, ICC1 is 20.5mA, ICC2 is 82.7mA, and ICC3 is 268mA. At the operating frequency of 3.3 to 4.2 GHz, the simulation result of the gain S21 is 36.5 to 38.5 dB, the test result of the gain S21 is 36 to 38 dB, the gain reaches the desired index, the whole circuit realizes a high gain, the simulation result of the insertion return loss S11 is -15 to -11 dB, the test result of the insertion return loss S11 is -13 to -10.2 dB, the insertion return loss S11 in the entire N77 operating frequency range is less than -10 dB, and the circuit matching result is good. The test results and the simulation results are all close. The output return loss S22 is relatively poor, -7.5 to -11 dB in the simulation stage, and -7 to -10.5 dB in the test stage, and better insertion return loss and gain can be obtained.

[0042] Referring to FIG. 6, FIG. 6 is a simulation waveform diagram of the large signal of the differential power amplifier of the present invention. Here, the large signal includes output power, power added efficiency (efficiency), etc. In the waveform diagram shown in FIG. 6, "Gain" on the left vertical coordinate indicates the gain, "[PAE]" on the right vertical coordinate indicates the power added efficiency, and "[Pout]" on the horizontal coordinate indicates the output power. As can be seen from the waveform diagram, at any of the four frequency points of 3.3 GHz, 3.6 GHz, 3.9 GHz, and 4.2 GHz, P1dB is greater than 37 dBm, and the power added efficiency at any of these four frequency points is greater than 45% at P1dB. The gain compression curve in FIG. 6 increases by about 1 dBm from the P1dB point to the saturation power point. The gain rapidly decreases within 1 dB after the output power reaches P1dB. The output power performance is high, and the output linear power is large. The power amplifier of the present application adopts the quiescent point of the AB type and can obtain high efficiency.

[0043] Also, as can be seen from the experimental data, when the output power is 29 dBm, the ACLR (adjacent channel leakage ratio) test results of the left and right sidebands are -42.5 dBc and -42.3 dBc respectively, meeting the design requirements.

[0044] The differential power amplifier of the present invention improves the insertion return loss of inter-stage matching and overall matching, has high gain, output power and efficiency, has good ACLR of the power amplifier. When the output power is 29 dBm, the ACLR (adjacent channel power leakage ratio) is less than -42 dBc. By using a transformer for inter-stage matching, the chip area can be reduced, and the area of the power amplifier can be made smaller than 1 mm 2 smaller.

[0045] The above has described in detail the differential power amplifier according to the embodiment of the present invention. In this specification, the principle and embodiments of the present invention are described by specific examples. However, the description of the above embodiments is for the purpose of helping to understand the method and the core idea of the present invention. Also, those skilled in the art can change any of the specific embodiments and application scopes based on the idea of the present invention. Therefore, the content of this specification should not be construed as limiting the present invention.

Claims

1. A differential power amplifier comprising an input matching network, a first-stage amplification circuit, a first-stage inter-stage matching network, a second-stage amplification circuit, a second-stage inter-stage matching network, a third-stage amplification circuit, and an output matching network, wherein the first-stage amplification circuit and the second-stage amplification circuit are single-input single-output circuits, the third-stage amplification circuit is a dual-input dual-output circuit, the second-stage inter-stage matching network includes one first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2, a fourth capacitor C4, a fifth capacitor C5, and a third inductor L3, the third-stage amplification circuit includes two third transistors Q3, the output matching network includes one second transformer T2, an input terminal and an output terminal of the input matching network are respectively connected to a single-ended RF input signal RFin and an input terminal of the first-stage amplification circuit, an output terminal of the first-stage amplification circuit is connected to an input terminal of the first-stage inter-stage matching network, and an output terminal of the first-stage inter-stage matching network is connected to an input terminal of the second-stage amplification circuit, the second-stage inter-stage matching network has two input terminals of the first transformer T1 respectively connected to an output terminal of the second-stage amplification circuit and a supply voltage Vcc2, one terminal of the first capacitor C1 and the second capacitor C2 are respectively connected to the two input terminals of the first transformer T1, the other terminals of the first capacitor C1 and the second capacitor C2 are respectively grounded, one terminal of the first inductor L1 and the second inductor L2 are respectively connected to the two output terminals of the first transformer T1, the other terminals of the first inductor L1 and the second inductor L2 are respectively grounded, the fourth capacitor C4 is serially connected between one output terminal of the first transformer T1 and the base of one of the third transistors Q3, and the fifth capacitor C5 is serially connected between the other output terminal of the first transformer T1 and the base of the other third transistor Q3, the third inductor L3 is serially connected between an input terminal of the first transformer T1 and the supply voltage Vcc2, which converts a single-ended signal from the second-stage amplification circuit into a pair of differential signals and inputs them to the two input terminals of the third-stage amplification circuit respectively, the output matching network Two input terminals of the second transformer T2 are respectively connected to two output terminals of the third-stage amplifier circuit, One output terminal of the second transformer T2 is grounded, and the other output terminal outputs a single-ended RF output signal RFout, The differential power amplifier is characterized in that both the first transformer T1 and the second transformer T2 are symmetrical mutual-wound transformers.

2. The first-stage amplifier circuit includes one first transistor Q1, and the second-stage amplifier circuit includes one second transistor Q2. The base, collector, and emitter of the first transistor Q1 are respectively connected to the output terminal of the input matching network, the input terminal of the first inter-stage matching network, and the ground terminal. The base, collector, and emitter of the second transistor Q2 are respectively connected to the output terminal of the first inter-stage matching network, one input terminal of the first transformer T1, and the ground terminal. The bases of the two third transistors Q3 are respectively connected to the two output terminals of the first transformer T1. The collectors of the two third transistors Q3 are respectively connected to the two input terminals of the second transformer T2. The emitters of the two third transistors Q3 are respectively grounded. The differential power amplifier according to claim 1 is characterized by this.

3. The differential power amplifier further includes a negative feedback network connected between the collector and the base of the first transistor Q1. The negative feedback network includes a first resistor R1 and a third capacitor C3 connected in series. The first-stage amplifier circuit further includes a second resistor R2 connected in series between the input matching network and the base of the first transistor Q1 and connected in parallel to the negative feedback network. The differential power amplifier according to claim 2 is characterized by this.

4. The output matching network further includes a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, and a fourth inductor L4. One terminal of the sixth capacitor C6 and one terminal of the seventh capacitor C7 are respectively connected to two input terminals of the second transformer T2, the other terminals of the sixth capacitor C6 and the seventh capacitor C7 are respectively grounded, one terminal of the eighth capacitor C8 is connected to the grounding output terminal of the second transformer T2, the other terminal of the eighth capacitor C8 is grounded, and the fourth inductor L4 is serially connected between the grounding output terminal and the grounding terminal of the second transformer T2. The differential power amplifier according to claim 2, characterized in that.

5. The input matching network includes a ninth capacitor C9, a tenth capacitor C10, a fifth inductor L5, and a sixth inductor L6. One terminal of the ninth capacitor C9 is connected to one terminal of the fifth inductor L5, and the connection node is used to input the single-ended RF input signal RFin. The other terminal of the fifth inductor L5 is grounded, the other terminal of the ninth capacitor C9 is connected to one terminal of the tenth capacitor C10, the other terminal of the tenth capacitor C10 is connected to the input terminal of the first-stage amplification circuit, one terminal of the sixth inductor L6 is connected between the ninth capacitor C9 and the tenth capacitor C10, and the other terminal of the sixth inductor L6 is grounded. The differential power amplifier according to claim 1, characterized in that.

6. The second-stage amplification circuit further includes a third resistor R3, and the third resistor R3 is serially connected between the output terminal of the first-stage matching network and the input terminal of the second-stage amplification circuit. The differential power amplifier according to claim 1, characterized in that.

7. The differential power amplifier further includes a base bias circuit connected one-to-one to each base of the first transistor Q1, the second transistor Q2, and the two third transistors Q3. The base bias circuit includes a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an eleventh capacitor C11. The base and collector of the fourth transistor Q4, the base of the fifth transistor Q5, one terminal of the fourth resistor R4, and one terminal of the eleventh capacitor C11 are connected. The other terminal of the fourth resistor R4 is connected to the power supply voltage Vreg. The emitter of the fourth transistor Q4, the collector and base of the sixth transistor Q6 are connected. The emitter of the sixth transistor Q6 is connected to one terminal of the fifth resistor R5. The other terminal of the fifth resistor R5 is grounded. The other terminal of the eleventh capacitor C11 is grounded. The collector of the fifth transistor Q5 is connected to the power supply voltage Vbat. The emitter of the fifth transistor Q5 is connected to one terminal of the sixth resistor R6. The other terminal of the sixth resistor R6 is connected to the base of the corresponding transistor. The differential power amplifier according to claim 2, characterized in that.

8. The first-stage matching network includes a seventh inductor L7, an eighth inductor L8, a fourteenth capacitor C14, and a fifteenth capacitor C15. One terminal of the seventh inductor L7 and one terminal of the fourteenth capacitor C14 are both connected to the output terminal of the first-stage amplification circuit. The other terminal of the seventh inductor L7 is connected to the power supply voltage Vcc1. The other terminal of the fourteenth capacitor C14, one terminal of the eighth inductor L8, and one terminal of the fifteenth capacitor C15 are connected. The other terminal of the fifteenth capacitor C15 is connected to the input terminal of the second-stage amplification circuit. The other terminal of the eighth inductor L8 is grounded. The differential power amplifier according to claim 1, characterized in that.

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