Generation of Ion Energy Distribution Function (IEDF)

Abstract

A system and method are provided for generating arbitrarily shaped ion energy distribution functions using shaped pulse bias. In one embodiment, a method includes applying a positive jump voltage to an electrode of a processing chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to generate a predetermined number of pulses to determine an ion energy distribution function. In another embodiment, a method includes applying a positive jump voltage to an electrode of a processing chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set the wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or that undercompensates for ion current on the wafer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to systems and methods for processing substrates, and more particularly, to systems and methods for plasma processing substrates. Background

[0002] A typical reactive ion etching (RIE) plasma processing chamber includes an RF bias generator that supplies a radio frequency (RF) voltage to a "power electrode" and a metal base plate embedded in an "electrostatic chuck" (ESC), more commonly referred to as a "cathode". FIG. 1(a) shows a plot of a typical RF voltage supplied to the power electrode within a typical processing chamber. The power electrode is capacitively coupled to the plasma of the processing system through a ceramic layer that is part of the ESC assembly. Due to the non-linear, diode-like nature of the plasma sheath, rectification of the applied RF electric field occurs, resulting in a direct current (DC) voltage drop, i.e., a "self-bias", between the cathode and the plasma. This voltage drop determines the average energy of the plasma ions accelerated towards the cathode and thus the etching anisotropy.

[0003] More specifically, the ion directivity, feature profile, and selectivity of the mask and the stop layer are controlled by the ion energy distribution function (IEDF). In a plasma with an RF bias, the IEDF usually has two peaks at low energy and high energy, and has an ion group in the middle. The existence of an ion group in the middle of the two peaks of the IEDF reflects the fact that the voltage drop between the cathode and the plasma oscillates at the bias frequency. When a higher self-bias voltage is obtained using a lower frequency, for example, a 2 MHz RF bias generator, the energy difference between these two peaks can be quite large. Etching by ions at the low energy peak is more isotropic and may lead to curvature of the feature walls. Compared with high energy ions, low energy ions are less effective in reaching the corners at the bottom of the feature (e.g., due to charging effects), but the sputtering of the mask material is reduced. This is important in high aspect ratio etching applications (e.g., hard mask openings, etc.).

[0004] As the feature size continues to shrink and the aspect ratio increases, the feature profile control requirements become more stringent, while it becomes more desirable to have an appropriately controlled IEDF on the substrate surface during processing. Any IEDF can be constructed using a single-peak IEDF, including a two-peak IEDF with independently controlled peak height and peak energy, which is very beneficial for high-precision plasma processing. To generate a single-peak IEDF, it is necessary for the voltage of the substrate surface with respect to the plasma to be substantially constant, that is, to have a sheath voltage that determines the ion energy. Assuming that the plasma potential (usually close to zero or ground potential in the processing plasma) is constant over time, it is necessary to maintain the voltage of the substrate with respect to ground, i.e., the substrate voltage, substantially constant. Since the ion current is constantly charging the substrate surface, this cannot be achieved simply by applying a DC voltage to the power electrode. As a result, the total applied DC voltage drops across the two ends of the substrate and the ceramic part of the ESC (i.e., the chuck capacitance), rather than across the plasma sheath (i.e., the sheath capacitance). To address this, a special-shaped pulse bias method has been developed such that the applied voltage is shared between the chuck capacitance and the sheath capacitance (usually, the substrate capacitance is much larger than the sheath capacitance, so the inventors have ignored the voltage drop across the substrate). In this method, compensation is made for the ion current, which enables the sheath voltage and the substrate voltage to be kept constant up to 90% of the maximum of each bias voltage cycle. More precisely, this bias method enables the maintenance of a specific substrate voltage waveform, which can be described as a series of periodic short positive pulses on top of a negative DC offset (Figure 1(b)). During each pulse, the substrate potential reaches the plasma potential and the sheath collapses in a short time, but for ~90% of each cycle, the sheath voltage remains constant and equal to the negative voltage jump at the end of each pulse, so the average ion energy is determined. Figure 1(a) shows a plot of the special-shaped pulse bias voltage waveform developed to generate this specific substrate voltage waveform and thereby keep the sheath voltage substantially constant.As shown in FIG. 2, the shaped pulse bias waveform includes: (1) a positive jump to remove the extra charge accumulated in the chuck capacitance during the compensation phase; (2) a negative jump (V SH ) to set the sheath voltage (V OUT ) value - that is, since V OUT is shared between the chuck capacitance and the sheath capacitance connected in series, the negative jump in the substrate voltage waveform is determined (where V OUT is generally larger than the negative jump in the substrate voltage waveform), (3) a negative voltage ramp to compensate for the ion current and keep the sheath voltage constant during this long "ion current compensation phase". The inventors emphasize that other shaped pulse bias waveforms may exist that can maintain the specific substrate voltage waveform shown in FIG. 1(b) (characterized by a substantially constant sheath voltage), and thus can generate a single energy IEDF. For example, when the electrostatic chuck capacitance is much larger than the sheath capacitance, the negative voltage ramp phase described in (3) above can be replaced with a constant voltage phase. Some of the systems and methods proposed below can be implemented using these other shaped pulse bias waveforms, and in such cases, the inventors will note that.

[0005] A single peak IEDF is widely considered to be a highly desirable IEDF shape that provides improved selectivity and feature profile, but in some etching applications, IEDFs with different shapes (such as wider shaped IEDFs) are required. Overview

[0006] Provided herein are systems and methods for generating an ion energy distribution function of any shape using a shaped pulse bias.

[0007] In some embodiments, the method includes applying a shaped pulse bias to the electrodes of a processing chamber in a predetermined manner and the amplitude of the negative voltage jump (V OUT ), and thus the sheath voltage (V SH) includes modulating to determine the relative ion fraction at the ion energy corresponding to this amplitude based on the relative number of pulses at a specific amplitude. The inventors emphasize that this method can be implemented using any shaped pulse bias waveform (not necessarily the waveform shown in Fig. 1(a)) that can maintain a specific substrate voltage waveform (characterized by a substantially constant sheath voltage), and thus can generate a single energy IEDF.

[0008] In some other embodiments, the method includes applying a shaped pulse bias of the voltage waveform shown in Fig. 1(a) and generating a voltage ramp during the ion compensation phase that has a larger negative gradient (dV / dt) than required to maintain the substrate voltage constant, i.e., overcompensates the ion current. In some other embodiments, the method includes applying a shaped pulse bias of the voltage waveform shown in Fig. 1(a) and generating a voltage ramp during the ion compensation phase that has a smaller negative gradient (dV / dt) than required to maintain the substrate voltage constant, i.e., undercompensates the ion current.

[0009] Other and further embodiments of the present disclosure are described below.

Brief Description of the Drawings

[0010] The embodiments of the present disclosure briefly summarized above and described in more detail below can be understood by referring to the exemplary embodiments of the present disclosure shown in the accompanying drawings. However, the accompanying drawings only show typical embodiments of the present disclosure and should not be construed as limiting the scope. The present disclosure may include other equally effective embodiments.

[0011]

Fig. 1(a)

Fig. 1(b)

Fig. 1(c)

Fig. 2

Fig. 3

Fig. 4

Fig. 5

Fig. 6

Fig. 7

Fig. 8

Fig. 9

Fig. 10

[0012] For the sake of facilitating understanding, the same reference numbers are used as much as possible when indicating the same elements common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. The elements and configurations of one embodiment can be beneficially incorporated into other embodiments without further explanation. Detailed description

[0013] Systems and methods are provided herein for generating an ion energy distribution function of any shape using a shaped pulse bias. The systems and methods of the present invention advantageously facilitate the generation of an ion energy distribution function (IEDF) of any shape by amplitude modulation of a shaped pulse bias waveform. Embodiments of the method of the present invention advantageously perform shaping of the voltage waveform and can provide any IEDF shape, such as an IEDF having a wider profile. In the description herein, the terms wafer and substrate are used interchangeably.

[0014] FIG. 2 shows a high-level schematic diagram of a substrate processing system 200 to which embodiments according to this principle can be applied. The substrate processing system 200 of FIG. 2 illustratively includes a substrate support assembly 205 and a bias power supply 230. In the embodiment of FIG. 2, the substrate support assembly 205 includes a substrate support pedestal 210, a power electrode 213, and a ceramic layer 214 that separates the power electrode 213 from the surface 207 of the substrate support assembly 205. In various embodiments, the system 200 of FIG. 2 can include components of a plasma processing chamber (e.g., SYM3®, DPS®, ENABLER®, ADVANTEDGE™, and AVATAR™ processing chambers available from Applied Materials, Inc., Santa Clara, Calif., or other processing chambers).

[0015] In some embodiments, the bias power supply 230 includes a memory for storing a control program and a processor for executing the control program, and the control program controls the voltage supplied to the power electrode 213 by the bias power supply 230, at least modulates the amplitude of the wafer voltage to generate a predetermined number of pulses, and alternatively or additionally, applies a negative jump voltage to the electrode to set the wafer voltage for the wafer, or applies a ramp voltage that overcompensates or undercompensates the ion current on the wafer according to the embodiments of the present principles described herein to the electrode. In an alternative embodiment, the substrate processing system 200 of FIG. 2 comprises any controller 220 including a memory for storing a control program and a processor for executing the control program to communicate with the bias power supply 230, and the control program at least controls the voltage supplied to the power electrode 213 by the bias power supply 230 by at least modulating the amplitude of the wafer voltage to generate a predetermined number of pulses, and alternatively or additionally, applies a negative jump voltage to the electrode to set the wafer voltage for the wafer, or applies a ramp voltage that overcompensates or undercompensates the ion current on the wafer according to the embodiments of the present principles described herein to the electrode.

[0016] During operation, the substrate to be processed is placed on the surface of the substrate support pedestal 210. In the system 200 of FIG. 2, a voltage (shaped pulse bias) from the bias power supply 230 is supplied to the power electrode 213. Due to the non-linear, diode-like nature of the plasma sheath, the applied RF electric field is rectified, and a direct current (DC) voltage drop, i.e., "self-bias", appears between the cathode and the plasma. This voltage drop determines the average energy of the plasma ions accelerated towards the cathode. The ion directionality and feature profile are controlled by the ion energy distribution function (IEDF). According to an embodiment of the present principle described herein, the bias power supply 230 can supply a specially shaped pulse bias to the power electrode 213. With this biasing method, a specific substrate voltage waveform can be maintained that can be described as a series of short positive pulses on a negative DC offset (FIG. 1(b)). Between each pulse, the substrate potential reaches the plasma potential and the sheath collapses in a short time, but for ~90% of each cycle, the sheath voltage remains constant and equal to the negative voltage jump at the end of each pulse, so the average ion energy is determined.

[0017] Referring back to FIG. 1(a), the amplitude of the shaped pulse bias signal, and thus the wafer voltage, is represented by Vout. The inventors have determined that in at least some embodiments according to this principle, the shape of the IEDF can be controlled by modulating the amplitude and frequency of the shaped pulse bias signal. This method involves applying the shaped pulse bias to the electrodes of the processing chamber in a predetermined manner, and the amplitude of the negative voltage jump (V OUT ), and thus the sheath voltage (V SH) includes modulating, and the relative number of pulses at a particular amplitude determines the relative ion fraction at the ion energy corresponding to this amplitude. The number of pulses at each amplitude must be sufficient to constitute a transition from one sheath voltage to the next, during which each ESC charge is established. Thereafter, a burst (Figure 3) containing a pulse train having a given amplitude is repeated many times over the processing step period. Active bursts (on - phase) can be interleaved with silent periods (off - phase). The duration of each on - phase relative to the total duration of the burst (the combination of on - phase and off - phase) is determined by the duty cycle, and the total duration (period) of the burst is equal to the reciprocal of the burst frequency. Alternatively, each burst may be composed of a series of pulses having a given (and the same) amplitude, and then an IEDF is defined using a series of bursts having different amplitudes. The relative number of bursts (within the series) having a given amplitude determines the relative amount of ions at a particular energy, and the negative jump amplitude (V OUT(0) determines the ion energy. Thereafter, during the recipe step, the defined burst sequence is repeated many times. For example, to generate a two-peak IEDF where 25% of the ions are in the low energy peak and 75% of the ions are in the high energy peak, the burst sequence needs to be composed of 3 bursts of pulses with a negative jump amplitude corresponding to the high ion energy and 1 burst of pulses with an amplitude corresponding to the low ion energy. Such a sequence can be represented as "HHHL". Next, to generate an IEDF with three energy peaks (high (H), medium (M), low (L)) of the same height, a sequence of 3 bursts of different amplitudes corresponding to the ion energies of H, M, and L is required, which can be represented as "HML". A single-peak IEDF is generated by a sequence composed of a single burst of pulses (including both the on-phase and off-phase) with a defined negative jump amplitude. The inventors emphasize that this method can be implemented using any shaped pulse bias waveform (not necessarily the waveform shown in FIG. 1(a)) that can maintain a specific substrate voltage waveform (characterized by a substantially constant sheath voltage) as shown in FIG. 1(b), and thus can generate a single-energy IEDF.

[0018] For example, FIG. 3 shows a plot of the voltage pulses that the power supply should supply to the electrodes of the processing chamber to set the value of the substrate voltage according to an embodiment of this principle. In the embodiment of FIG. 3, the full jump of the wafer voltage determines the ion energy, and the number of pulses (e.g., the total duration) corresponding to the voltage jump determines the relative ion fraction (i.e., IEDF) at this energy.

[0019] FIG. 4 shows a graph of the resulting IEDF for the selected voltage pulses of FIG. 3 according to an embodiment of this principle. As shown in FIG. 4, the multiple voltage pulses of FIG. 3 result in a wider IEDF, which can be effective in applications such as high aspect ratio etching of hard mask openings that require a wider ion energy distribution.

[0020] According to this principle, by controlling the amplitude and frequency of the voltage pulse supplied by the power source to the electrodes of the processing chamber, an appropriately controlled and clearly defined IEDF shape required for specific etching processes and applications can be obtained.

[0021] In another embodiment according to this principle, the method includes applying a shaped pulse bias of the voltage waveform shown in FIG. 1(a), and generating a voltage ramp during the ion compensation phase that has a larger negative gradient (dV / dt) than is required to keep the substrate voltage constant, i.e., overcompensates the ion current. This results in the substrate voltage waveform shown in FIG. 6, and the magnitude of the substrate voltage (and thus the sheath voltage and instantaneous ion energy) increases during the ion current compensation phase. Thereby, the IEDF width is controlled by the negative gradient of the applied shaped pulse bias waveform to produce the spread of ion energy width and non-uniform energy IEDF shown in FIG. 7. For example, FIG. 5 shows a plot of the special shaped pulse of FIG. 1(a) modified to overcompensate the ion current that charges the wafer, according to one embodiment of this principle. As shown in FIG. 5, the voltage ramp of FIG. 1(a) for the purpose of compensating the ion current that charges the wafer is modified to overcompensate the ion current that charges the wafer in the special shaped pulse of FIG. 5 of this principle. As shown in FIG. 5, the positive jump of FIG. 1 for the purpose of neutralizing the wafer surface no longer neutralizes the wafer surface in the special shaped pulse of FIG. 5 of this principle.

[0022] FIG. 6 shows a plot of the induced voltage pulse on the wafer resulting from the special shaped pulse of FIG. 5. As shown in FIG. 6, the voltage jump determines the ion energy, and the energy width is determined by the minimum and maximum wafer voltage jumps during the cycle.

[0023] Figure 7 shows, according to one embodiment of the present principle, the resulting IEDF pattern for the voltage pulse of FIG. 6. As shown in FIG. 7, the IEDF obtained from the application of the overcompensation special shaping pulse of FIG. 5 includes a wider double-peak profile, but the Vmin and Vmax that determine the IEDF width do not necessarily coincide with the energy peaks in the profile. Due to the overcompensation according to the present principle, control with higher precision than that achievable by mixing two RF frequencies (e.g., 2 MHz and 13.56 MHz) becomes possible.

[0024] In another embodiment according to the present principle, the method includes applying a shaping pulse bias of the voltage waveform shown in FIG. 1(a) and generating a voltage ramp during the ion compensation phase that has a smaller negative gradient (dV / dt) than required to keep the substrate voltage constant, i.e., undercompensating the ion current. As a result, the substrate voltage waveform shown in FIG. 6 is generated, and the magnitude of the substrate voltage (and thus the sheath voltage and instantaneous ion energy) decreases during the ion current compensation phase. Thereby, the IEDF width is controlled by the negative gradient of the applied shaping pulse bias, and a widened ion energy width and non-single energy IEDF as shown in FIG. 7 are generated. For example, referring back to FIG. 5, FIG. 5 shows a plot of the special shaping pulse of FIG. 1 modified to undercompensate the ion current for charging the wafer according to one embodiment of the present principle. As shown in FIG. 5, the voltage ramp of FIG. 1 for the purpose of compensating the ion current for charging the wafer is modified to undercompensate the ion current for charging the wafer within the special shaping pulse of FIG. 5 of the present principle. As shown in FIG. 5, the positive jump of FIG. 1 for the purpose of neutralizing the wafer surface no longer neutralizes the wafer surface within the special shaping pulse of FIG. 5 of the present principle.

[0025] Referring back to FIG. 7, the resulting IEDF pattern is shown for the undercompensation of one embodiment of the present principle. As shown in FIG. 7, the IEDF resulting from the application of the undercompensation special shaping pulse of FIG. 5 includes a wider single-peak profile.

[0026] FIG. 8 shows a flowchart of a method for generating an ion energy distribution function of an arbitrary shape according to an embodiment of the present principle. Method 800 can start from 802, and during 802, a negative jump voltage is applied to the electrode to set the wafer voltage. Next, method 800 can proceed to 804.

[0027] At 804, the amplitude of the wafer voltage is modulated to generate a predetermined number of pulses, and the ion energy distribution function is determined.

[0028] Next, method 800 can end.

[0029] FIG. 9 shows a flowchart of a method for generating an ion energy distribution function of an arbitrary shape according to another embodiment of the present principle. Method 900 can start from 902, and during 902, a positive jump voltage is applied to the electrode of the processing chamber to neutralize the wafer surface. Next, method 900 can proceed to 904.

[0030] At 904, a negative jump voltage is applied to the electrode to set the wafer voltage. Next, method 900 can proceed to 906.

[0031] At 906, a ramp voltage that overcompensates the ion current on the wafer is applied to the electrode. Next, method 900 can end.

[0032] FIG. 10 shows a flowchart of a method for generating an ion energy distribution function of an arbitrary shape according to another embodiment of the present principle. Method 1000 can start from 1002, and during 1002, a positive jump voltage is applied to the electrode of the processing chamber to neutralize the wafer surface. Next, method 1000 can proceed to 1004.

[0033] At 1004, a negative jump voltage is applied to the electrode to set the wafer voltage. Next, method 1000 can proceed to 1006.

[0034] At 1006, a lamp voltage that compensates for the shortage of the ion current on the wafer is applied to the electrode. Next, the method 1000 can be terminated.

[0035] The foregoing is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure can be made without departing from the basic scope of the present disclosure.

Claims

1. (a) A step of supplying a first burst of pulses to an electrode of a processing chamber, wherein the first burst of pulses includes a first plurality of voltage pulses supplied during a first burst period, each pulse of the first plurality of voltage pulses sequentially includes a positive jump amplitude for neutralizing the surface of the wafer, a first negative jump amplitude for setting the wafer voltage, and a ramp voltage slope for overcompensating the ion current on the wafer; (b) A step of supplying a second burst of pulses to an electrode of a processing chamber, wherein the second burst of pulses includes a second plurality of voltage pulses supplied during a second burst period, each pulse of the second plurality of voltage pulses sequentially includes a positive jump amplitude for neutralizing the surface of the wafer, a second negative jump amplitude for setting the wafer voltage, and a ramp voltage slope for overcompensating the ion current on the wafer; (c) A method comprising the step of repeating (a) and (b) a plurality of times, wherein the step of repeating (a) and (b) a plurality of times is configured to generate an ion energy distribution function (IEDF), the ion energy distribution function (IEDF) has a plurality of energy peaks in the plasma formed in the processing chamber, and the first negative jump amplitude is different from the second negative jump amplitude.

2. The method according to claim 1, comprising a duty cycle including a first burst of pulses provided during a first burst period, a second burst of pulses provided during a second burst period, and a period during which no voltage pulses are provided to the electrode.

3. The method according to claim 1, wherein the first negative jump amplitude is greater than the second negative jump amplitude.

4. The method according to claim 3, wherein the first burst period is longer than the second burst period.

5. (d) Further comprising a step of supplying a third burst of pulses to an electrode of a processing chamber, wherein the third burst of pulses includes a third plurality of voltage pulses supplied during a third burst period, each pulse of the third plurality of voltage pulses sequentially includes a positive jump amplitude for neutralizing the surface of the wafer, a third negative jump amplitude for setting the wafer voltage, and a ramp voltage slope for overcompensating the ion current on the wafer, and including a step of repeating (a), (b) and (d) a plurality of times instead of the step of repeating (a) and (b) a plurality of times. The method according to claim 1, wherein the first negative jump amplitude, the second negative jump amplitude, and the third negative jump amplitude are each different. **Claim 6** The first negative jump amplitude is greater than the second negative jump amplitude and the third negative jump amplitude, The method according to claim 5, wherein the second negative jump amplitude is greater than the third negative jump amplitude. **Claim 7** The first negative jump amplitude is smaller than the second negative jump amplitude, The method according to claim 5, wherein the second negative jump amplitude is smaller than the third negative jump amplitude. **Claim 8** The first and second negative jump voltages are applied to the electrodes of the processing chamber to set the wafer voltage on the wafer, The method according to claim 1, wherein the wafer voltage formed by applying the first plurality of voltage pulses and the second plurality of voltage pulses to the electrodes of the processing chamber generates an ion energy distribution function having two or more energy peaks. **Claim 9** The method according to claim 8, wherein the positive jump voltage is applied to the electrodes of the processing chamber to neutralize the surface of the wafer. **Claim 10** The method according to claim 1, wherein the generated ion energy distribution function induces a specific bias voltage waveform on the wafer disposed above the electrodes. **Claim 11** The method according to claim 1, wherein the ion fraction of each of the plurality of energy peaks is determined by the number of pulses generated during the first burst period and the second burst period. **Claim 12** A method of forming an ion energy distribution function (IEDF) having two or more peaks in a plasma, (a) A step of supplying a first burst of pulses to the electrodes of the processing chamber, The first burst of pulses includes a first plurality of voltage pulses supplied during the first burst period, Each pulse of the first plurality of voltage pulses sequentially includes a positive jump amplitude for neutralizing the surface of the wafer, a first negative jump amplitude for setting the wafer voltage, and a ramp voltage slope for overcompensating the ion current on the wafer. (b) A step of supplying a second burst of pulses to the electrodes of the processing chamber, The second burst of pulses includes a second plurality of voltage pulses supplied during the second burst period, Each pulse of the second plurality of voltage pulses includes a step of sequentially including a positive jump amplitude for neutralizing the surface of the wafer, a second negative jump amplitude for setting the wafer voltage, and a ramp voltage slope for overcompensating the ion current on the wafer, (c) repeating (a) and (b) a plurality of times, A method in which the first negative jump amplitude and the second negative jump amplitude are different.

13. A first burst of pulses provided during the first burst period, A second burst of pulses provided during the second burst period, The method according to claim 12, comprising a duty cycle including a period during which no voltage pulse is provided to the electrode.

14. The method according to claim 12, wherein the first negative jump amplitude is greater than the second negative jump amplitude.

15. The method according to claim 14, wherein the first burst period is longer than the second burst period.

16. (d) further comprising a step of supplying a third burst of pulses to the electrodes of the processing chamber, The third burst of pulses includes a third plurality of voltage pulses supplied during the third burst period, Each pulse of the third plurality of voltage pulses includes a positive jump amplitude for neutralizing the surface of the wafer, a third negative jump amplitude for setting the wafer voltage, and a ramp voltage slope for overcompensating the ion current on the wafer in sequence, Instead of repeating (a) and (b) a plurality of times, it includes a step of repeating (a), (b) and (d) a plurality of times, The method according to claim 12, wherein the first negative jump amplitude, the second negative jump amplitude, and the third negative jump amplitude are different from each other.

17. The first negative jump amplitude is greater than the second negative jump amplitude and the third negative jump amplitude, The method according to claim 16, wherein the second negative jump amplitude is greater than the third negative jump amplitude.

18. The first negative jump amplitude is smaller than the second negative jump amplitude and the third negative jump amplitude, The method according to claim 16, wherein the second negative jump amplitude is smaller than the third negative jump amplitude.

Images