Indicates the driver

Abstract

To provide a display driver that can reduce the adverse effect of noise at the latch timing of display data on an initialization operation of an amplifier circuit.SOLUTION: A display driver 10 includes: a line latch circuit; a first D / A conversion circuit; a second D / A conversion circuit; a first amplifier circuit 41 in which the electric charge of a capacitor of a first switched capacitor circuit SC1 is initialized in a first initialization period, and outputs data voltage in a first output period; a second amplifier circuit 42 in which the electric charge of a capacitor of a second switched capacitor circuit SC2 is initialized in a second initialization period, and outputs data voltage in a second output period; and a control circuit 50. The control circuit 50 ends the second initialization period of the second amplifier circuit before display data is latched by the line latch circuit 20 at the latch timing and output of the first amplifier circuit 41 changes.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display driver and the like.

Background Art

[0002] Conventionally, display drivers for driving display panels such as color liquid crystal panels have been known. As conventional technologies of display drivers, for example, those disclosed in Patent Documents 1 and 2 are available. In the display drivers of Patent Documents 1 and 2, an initialization operation for initializing the capacitor of the amplifier circuit is performed during the initialization period. And during the output period, a data voltage is output by the operational amplifier of the amplifier circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a display driver in which the initialization operation of the amplifier circuit is performed, it has been found that the display quality of the display panel deteriorates due to noise caused by the latch operation of display data in the line latch circuit.

Means for Solving the Problems

[0005] One aspect of the present disclosure includes a line latch circuit that latches one line of display data, a first D / A conversion circuit that D / A-converts the display data from the line latch circuit, a second D / A conversion circuit that D / A-converts the display data from the line latch circuit, a first switch capacitor circuit and a first operational amplifier, wherein the charge of the capacitor of the first switch capacitor circuit is initialized during a first initialization period, and during a first output period, the first operational amplifier amplifies the output voltage of the first D / A conversion circuit based on the charge of the capacitor of the first switch capacitor circuit to output a data voltage; a second switch capacitor circuit and a second operational amplifier, wherein the charge of the capacitor of the second switch capacitor circuit is initialized during a second initialization period, and during a second output period, the second operational amplifier amplifies the output voltage of the second D / A conversion circuit based on the charge of the capacitor of the second switch capacitor circuit to output a data voltage; and a control circuit that controls the line latch circuit, the first amplifier circuit, and the second amplifier circuit, wherein the control circuit is related to a display driver that ends the second initialization period of the second amplifier circuit before the display data is latched by the line latch circuit at a latch timing and the output of the first amplifier circuit changes.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

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Figure 10

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Mode for Carrying Out the Invention

[0007] Hereinafter, this embodiment will be described. Note that the embodiment described below does not unduly limit the content described in the claims. Also, not all of the configurations described in this embodiment are essential constituent elements.

[0008] 1. Display driver FIG. 1 shows a configuration example of the display driver 10 of this embodiment. The display driver 10 includes a line latch circuit 20, a first D / A conversion circuit 31, a second D / A conversion circuit 32, a first amplifier circuit 41, a second amplifier circuit 42, and a control circuit 50. The display driver 10 can also include a power supply circuit 60. Note that the display driver 10 is not limited to the configuration of FIG. 1, and various modifications such as omitting some of these constituent elements or adding other constituent elements are possible. For example, other circuit blocks may be provided between the line latch circuit 20 and the first D / A conversion circuit 31 and the second D / A conversion circuit 32, or between the first D / A conversion circuit 31, the second D / A conversion circuit 32 and the first amplifier circuit 41, the second amplifier circuit 42.

[0009] The line latch circuit 20 is a circuit that latches display data. For example, the line latch circuit 20 latches one line of display data. For example, the line latch circuit 20 latches the display data based on the latch pulse LP from the control circuit 50. One line of display data is, for example, the number of display data corresponding to a plurality of source lines driven by the display driver 10 during the horizontal scanning period. Note that the line latch circuit 20 only needs to be able to latch at least one line of display data. The line latch circuit 20 can be configured by a plurality of latches each realized by a storage circuit such as a flip-flop circuit.

[0010] The first D / A conversion circuit 31 and the second D / A conversion circuit 32 perform D / A conversion on the display data from the line latch circuit 20. For example, the first D / A conversion circuit 31 performs D / A conversion on the display data corresponding to the source lines driven by the first amplifier circuit 41 provided in the subsequent stage of the first D / A conversion circuit 31. The second D / A conversion circuit 32 performs D / A conversion on the display data corresponding to the source lines driven by the second amplifier circuit 42 provided in the subsequent stage of the second D / A conversion circuit 32. The first D / A conversion circuit 31 and the second D / A conversion circuit 32 output, as an output voltage, a gradation voltage selected based on the display data from the line latch circuit 20 from among a plurality of gradation voltages from a gradation voltage generation circuit (not shown).

[0011] The first amplifier circuit 41 includes a first switch capacitor circuit SC1 and a first operational amplifier OP1. The first switch capacitor circuit SC1 is a circuit composed of at least one capacitor and at least one switch. By turning the switch on and off, the voltage applied to the capacitor is controlled. The first operational amplifier OP1 has an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, at least one of these terminals is connected to the charge storage node of the capacitor of the first switch capacitor circuit SC1. In the first amplifier circuit 41, during the first initialization period TI1 (to be described later with reference to FIG. 7), the charge of the capacitor of the first switch capacitor circuit SC1 is initialized. By initializing the charge stored in the capacitor during the first initialization period TI1 in this way, it becomes possible to cancel, for example, the offset variation of the first operational amplifier OP1. For example, during the first initialization period TI1, a given voltage such as a reference voltage is applied to the capacitor of the first switch capacitor circuit SC1, and charge storage for initialization is performed on the capacitor. In the first amplifier circuit 41, during the first output period TQ1, the first operational amplifier OP1 amplifies the output voltage of the first D / A conversion circuit 31 based on the charge of the capacitor of the first switch capacitor circuit SC1 and outputs a data voltage VD1. The first output period TQ1 is a period following the first initialization period TI1. For example, in a state where charge is stored in the capacitor during the first initialization period TI1, during the first output period TQ1, when the output voltage of the first D / A conversion circuit 31 is input to the first amplifier circuit 41, the first operational amplifier OP1 outputs a data voltage VD1 corresponding to the output voltage of the first D / A conversion circuit 31. For example, the data voltage VD1 is a voltage that changes according to the output voltage of the first D / A conversion circuit 31.

[0012] The second amplifier circuit 42 includes a second switch capacitor circuit SC2 and a second operational amplifier OP2. The second switch capacitor circuit SC2 is a circuit composed of at least one capacitor and at least one switch. By turning the switch on and off, the voltage applied to the capacitor is controlled. The second operational amplifier OP2 has an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, at least one of these terminals is connected to the charge storage node of the capacitor of the second switch capacitor circuit SC2. In the second amplifier circuit 42, the charge of the capacitor of the second switch capacitor circuit SC2 is initialized during the second initialization period TI2 in FIG. 7. By initializing the charge accumulated in the capacitor during the second initialization period TI2 in this way, it becomes possible to cancel, for example, the offset variation of the second operational amplifier OP2. For example, during the second initialization period TI2, a given voltage such as a reference voltage is applied to the capacitor of the second switch capacitor circuit SC2, and charge storage for initialization is performed on the capacitor. In the second amplifier circuit 42, during the second output period TQ2, the second operational amplifier OP2 amplifies the output voltage of the second D / A conversion circuit 32 based on the charge of the capacitor of the second switch capacitor circuit SC2 and outputs a data voltage VD2. The second output period TQ2 is a period following the second initialization period TI2. For example, in a state where charge is accumulated in the capacitor during the second initialization period TI2, during the second output period TQ2, when the output voltage of the second D / A conversion circuit 32 is input to the second amplifier circuit 42, the second operational amplifier OP2 outputs a data voltage VD2 corresponding to the output voltage of the second D / A conversion circuit 32. For example, the data voltage VD2 is a voltage that changes according to the output voltage of the second D / A conversion circuit 32.

[0013] The control circuit 50 controls the line latch circuit 20, the first amplifier circuit 41, and the second amplifier circuit 42. The control circuit 50 also controls other circuit blocks of the display driver 10 such as the power supply circuit 60. For example, the control circuit 50 controls the latch operation of the line latch circuit 20 by outputting a latch pulse LP to the line latch circuit 20. Also, the control circuit 50 outputs a control signal such as a switch control signal to the first amplifier circuit 41 and the second amplifier circuit 42, thereby controlling the switch capacitor operation of the first switch capacitor circuit SC1 and the second switch capacitor circuit SC2. The control circuit 50 is, for example, a logic circuit and is a circuit realized by automatic placement and wiring such as a gate array.

[0014] Then, as will be described with reference to FIG. 7 below, the control circuit 50 ends the second initialization period TI2 of the second amplifier circuit 42 before the display data is latched by the line latch circuit 20 at the latch timing and before the output of the first amplifier circuit 41 changes. For example, at the latch timing tm of the line latch circuit 20 based on the latch pulse LP from the control circuit 50, the display data of the line latch circuit 20 changes, so that the output voltage of the first D / A conversion circuit 31 changes, and thereby the output of the first amplifier circuit 41 also changes. Then, so that the change in the output of the first amplifier circuit 41 does not adversely affect the initialization operation during the second initialization period TI2 of the second amplifier circuit 42, the control circuit 50 ends the second initialization period TI2 of the second amplifier circuit 42 before the latch timing tm of the line latch circuit 20. Specifically, the control circuit 50 performs control to end the second initialization period TI2 using, for example, a control signal for the initialization operation of the second amplifier circuit 42.

[0015] By doing so, it becomes possible to prevent noise caused by changes in the output of the first amplifier circuit 41 due to latching of display data in the line latch circuit 20 from adversely affecting the initialization operation of the second amplifier circuit 42. For example, during the second initialization period TI2 of the second amplifier circuit 42, a voltage such as a reference voltage applied to the capacitor of the second switch capacitor circuit SC2 can be prevented from fluctuating due to noise caused by changes in the output of the first amplifier circuit 41, and the charge accumulated in the capacitor can be prevented from fluctuating.

[0016] Similarly, the control circuit 50 ends the first initialization period TI1 of the first amplifier circuit 41 before the display data is latched in the line latch circuit 20 at the latch timing and the output of the second amplifier circuit 42 changes. For example, at the latch timing tm of the line latch circuit 20 based on the latch pulse LP from the control circuit 50, when the display data of the line latch circuit 20 changes, the output voltage of the second D / A conversion circuit 32 also changes, and thereby the output of the second amplifier circuit 42 also changes. Then, before the latch timing tm of the line latch circuit 20, the control circuit 50 ends the first initialization period TI1 of the first amplifier circuit 41 so that the change in the output of the second amplifier circuit 42 does not adversely affect the initialization operation during the first initialization period TI1 of the first amplifier circuit 41. Specifically, the control circuit 50 performs control to end the first initialization period TI1, for example, using a control signal for the initialization operation of the first amplifier circuit 41.

[0017] By doing so, it becomes possible to prevent noise caused by changes in the output of the second amplifier circuit 42 due to latching of display data in the line latch circuit 20 from adversely affecting the initialization operation of the first amplifier circuit 41. For example, during the first initialization period TI1 of the first amplifier circuit 41, a voltage such as a reference voltage applied to the capacitor of the first switch capacitor circuit SC1 can be prevented from fluctuating due to noise caused by changes in the output of the second amplifier circuit 42, and the charge accumulated in the capacitor can be prevented from fluctuating.

[0018] Also, the power supply circuit 60 has a switching regulator 62 and supplies a power supply voltage to the first amplifier circuit 41 and the second amplifier circuit 42. The power supply circuit 60 also supplies a power supply voltage to circuit blocks other than the first amplifier circuit 41 and the second amplifier circuit 42. The switching regulator 62 of the power supply circuit 60 performs a switching regulation operation for boosting a voltage based on the power supply voltage, and the power supply voltage based on the voltage generated by this switching regulation operation is supplied to the first amplifier circuit 41 and the second amplifier circuit 42. The power supply voltages supplied to the first amplifier circuit 41 and the second amplifier circuit 42 may be different power supply voltages or the same power supply voltage. The switching regulator 62 is a DC-DC converter that performs a switching regulation operation using, for example, an inductor or the like to convert an input voltage into an output voltage different from the input voltage. The inductor may be an external component of the display driver 10 or may be built-in.

[0019] Then, as shown in FIG. 7 described later, the control circuit 50 stops the operation of the switching regulator 62 at least during the second initialization period TI2. For example, during the second initialization period TI2 of the second amplifier circuit 42, the control circuit 50 outputs a mask signal MSK, which is a control signal for disabling the operation of the switching regulator 62, to stop the operation of the switching regulator 62. That is, when the mask signal MSK becomes active level during the mask period TMK in FIG. 7, the operation of the switching regulator 62 stops during the second initialization period TI2.

[0020] In this way, it is possible to prevent the noise caused by the switching regulation operation of the switching regulator 62 from adversely affecting the initialization operation of the second amplifier circuit 42 during the second initialization period TI2. For example, it is possible to prevent a situation where a voltage such as a reference voltage applied to the capacitor of the second switch capacitor circuit SC2 during the second initialization period TI2 of the second amplifier circuit 42 fluctuates due to the noise caused by the switching regulation operation, and the charge accumulated in the capacitor fluctuates.

[0021] Also, the control circuit 50 stops the operation of the switching regulator 62, for example, even during the first initialization period TI1. For example, during the first initialization period TI1 of the first amplifier circuit 41, the control circuit 50 outputs a mask signal MSK, which is a control signal for disabling the operation of the switching regulator 62, to stop the operation of the switching regulator 62. That is, when the mask signal MSK becomes active level during the mask period TMK in FIG. 7, the operation of the switching regulator 62 stops during the first initialization period TI1.

[0022] In this way, it is possible to prevent the noise caused by the switching regulation operation of the switching regulator 62 from adversely affecting the initialization operation of the first amplifier circuit 41 during the first initialization period TI1. For example, it is possible to prevent a situation where the voltage such as the reference voltage applied to the capacitor of the first switch capacitor circuit SC1 during the first initialization period TI1 of the first amplifier circuit 41 fluctuates due to the noise caused by the switching regulation operation, and the charge accumulated in the capacitor fluctuates.

[0023] FIG. 2 shows a configuration example of an electro-optical device 100 including the display driver 10 of the present embodiment. The display driver 10 includes a source driver 120 that drives a plurality of source lines of the display panel 110. The display driver 10 may also include a gate driver 130 that drives a plurality of gate lines of the display panel 110. The electro-optical device 100 includes the display driver 10 and the display panel 110. The electro-optical device 100 can also include a controller 140.

[0024] The display panel 110 is, for example, a liquid crystal panel. For example, the display panel 110 is an active matrix type TFT liquid crystal panel. The display panel 110 includes a plurality of source lines, a plurality of gate lines, and a plurality of pixels provided such that each pixel corresponds to an intersection position of each source line and each gate line. The source driver 120 outputs data voltages to the plurality of source lines of the display panel 110, and the gate driver 130 performs gate line selection to sequentially select the plurality of gate lines of the display panel 110. The source lines correspond to data lines, the gate lines correspond to scanning lines, and the gate line selection corresponds to scanning line selection.

[0025] FIG. 3 shows a detailed configuration example of the display driver 10 of the present embodiment. In FIG. 3, an input latch circuit 22 is provided on the front stage side of the line latch circuit 20. The input latch circuit 22 includes a plurality of latches LB1 and LB2. The input latch circuit 22 latches these display data based on a latch signal based on a decode signal from an address decoder 24 that decodes an address AD and a clock signal CK, into which display data DTR1, DTG1, DTB1, DTR2, DTG2, and DTB2 are input. DTR1, DTG1, and DTB1 are 8-bit display data of R, G, and B of the first pixel, respectively. DTR2, DTG2, and DTB2 are 8-bit display data of R, G, and B of the second pixel, respectively.

[0026] The display data latched by the input latch circuit 22 is latched by the line latch circuit 20 based on a latch pulse LP. The line latch circuit 20 includes a plurality of latches LA1 and LA2. The switch circuit SWB performs a display data swapping process of outputting the display data from the latches LA1 and LA2 to the conversion circuits DEP and DEM, respectively, in the Nth frame, and outputting the display data from the latches LA1 and LA2 to the conversion circuits DEM and DEP, respectively, in the (N + 1)th frame. That is, the switch circuit SWB performs a display data swapping process based on a polarity signal POL. The display data from the conversion circuits DEP and DEM is subjected to voltage level shifting by level shifters LVP and LVM and input to D / A conversion circuits DAP and DAM.

[0027] The D / A conversion circuit DAP for positive polarity outputs the gradation voltage selected based on the display data from the gradation voltage VGP for positive polarity as the output voltage to the amplifier circuit AMP for positive polarity. The D / A conversion circuit DAM for negative polarity outputs the gradation voltage selected based on the display data from the gradation voltage VGM for negative polarity as the output voltage to the amplifier circuit AMM for negative polarity. For example, the amplifier circuit AMP in FIG. 3 corresponds to the first amplifier circuit 41 in FIG. 1, and the amplifier circuit AMM corresponds to the second amplifier circuit 42, but the reverse may also be true. Also, the D / A conversion circuit DAP in FIG. 3 corresponds to the first D / A conversion circuit 31 in FIG. 1, and the D / A conversion circuit DAM corresponds to the second D / A conversion circuit 32, but the reverse may also be true.

[0028] In the Nth frame, the switch circuit SWA outputs the data voltage from the amplifier circuit AMP for positive polarity to the terminal TS1 and outputs the data voltage from the amplifier circuit AMM for negative polarity to the terminal TS2. Also, in the (N + 1)th frame, the switch circuit SWA outputs the data voltage from the amplifier circuit AMM for negative polarity to the terminal TS1 and outputs the data voltage from the amplifier circuit AMP for positive polarity to the terminal TS2.

[0029] As shown in FIG. 3, by switching the display data by the switch circuit SWB for each frame and switching the data voltages of positive and negative polarities by the switch circuit SWA, column inversion driving of the display driver 10 as shown in FIG. 4 is realized. In FIG. 4, SL1 to SLn are source lines corresponding to data lines, and GL1 to GLm are gate lines corresponding to scanning lines. For example, in FIG. 4, in the Nth frame, the odd-numbered source lines are driven with positive polarity, and the even-numbered source lines are driven with negative polarity. Driving with positive polarity means being driven with a data voltage of positive polarity, for example, and driving with negative polarity means being driven with a data voltage of negative polarity, for example. Also, in the (N + 1)th frame, the odd-numbered source lines are driven with negative polarity, and the even-numbered source lines are driven with positive polarity. In this way, column inversion driving is performed in FIG. 4.

[0030] Thus, in this embodiment, the first amplifier circuit 41 is an amplifier circuit AMP for positive polarity that outputs a positive-polarity voltage, and the second amplifier circuit 42 is an amplifier circuit AMM for negative polarity that outputs a negative-polarity voltage. By doing so, the display driver 10 can be reversely driven by the positive-polarity drive by the amplifier circuit AMP for positive polarity and the negative-polarity drive by the amplifier circuit AMM for negative polarity. Specifically, for example, reverse driving such as column reverse driving as shown in FIG. 4 becomes possible. Note that the reverse driving of the display driver 10 is not limited to such column reverse driving, and may be reverse driving for each of a plurality of dots such as 3-dot reverse driving shown in FIG. 5. For example, in FIG. 5, pixels corresponding to the intersections of the source line SL1 and the gate lines GL1, GL2, GL3 are driven with positive polarity in the Nth frame and are driven with negative polarity in the (N + 1)th frame. Also, pixels corresponding to the intersections of the source line SL2 and the gate lines GL1, GL2, GL3 are driven with negative polarity in the Nth frame and are driven with positive polarity in the (N + 1)th frame. On the other hand, pixels corresponding to the intersections of the source line SL1 and the gate lines GL4, GL5, GL6 are driven with negative polarity in the Nth frame and are driven with positive polarity in the (N + 1)th frame. Also, pixels corresponding to the intersections of the source line SL2 and the gate lines GL4, GL5, GL6 are driven with positive polarity in the Nth frame and are driven with negative polarity in the (N + 1)th frame.

[0031] 2. Operation Next, the detailed operation of the display driver 10 of this embodiment will be described. First, the operation of the comparative example of this embodiment will be described with reference to FIG. 6. In FIG. 6, in the first initialization period TI1, the source line SLi becomes a high-impedance state, and the initialization operation of the first amplifier circuit 41 is performed. Also, in the second initialization period TI2, the source line SLi+1 adjacent to the source line SLi becomes a high-impedance state, and the initialization operation of the second amplifier circuit 42 is performed.

[0032] In the comparative example of FIG. 6, within the first initialization period TI1, the latch pulse LP becomes active, and the display data is latched into the line latch circuit 20. Also within the second initialization period TI2, the latch pulse LP becomes active, and the display data is latched into the line latch circuit 20.

[0033] In this case, for example, when display data is latched into the line latch circuit 20 during the second initialization period TI2, this display data is output to the first D / A conversion circuit 31, and the output voltage of the first D / A conversion circuit 31 is output to the first amplifier circuit 41, whereby the output of the first amplifier circuit 41 changes. Then, the noise due to the change in the output of the first amplifier circuit 41 has an adverse effect on the second amplifier circuit 42 that is performing the initialization operation during the second initialization period TI2, resulting in a deterioration of the display quality. For example, a situation occurs where noise due to the change in the output of the first amplifier circuit 41 is superimposed on the voltage such as a reference voltage described later that is applied to the capacitor of the second switch capacitor circuit SC2 of the second amplifier circuit 42 for initialization. As a result, the charge accumulated in the capacitor of the second switch capacitor circuit SC2 fluctuates, and the data voltage output by the second amplifier circuit 42 during the second output period TQ2 fluctuates, thereby deteriorating the display quality of the display image on the display panel 110.

[0034] Similarly, for example, when display data is latched in the line latch circuit 20 during the first initialization period TI1, this display data is output to the second D / A conversion circuit 32, and the output voltage of the second D / A conversion circuit 32 is output to the second amplifier circuit 42, so that the output of the second amplifier circuit 42 changes. Then, the noise caused by the change in the output of the second amplifier circuit 42 has an adverse effect on the first amplifier circuit 41 that is performing the initialization operation during the first initialization period TI1, resulting in a decrease in display quality. For example, noise caused by the change in the output of the second amplifier circuit 42 is superimposed on the voltage such as the reference voltage described later applied to the capacitor of the first switch capacitor circuit SC1 of the first amplifier circuit 41 for the initialization operation. As a result, the charge stored in the capacitor of the first switch capacitor circuit SC1 fluctuates, and the data voltage output by the first amplifier circuit 41 during the first output period TQ1 fluctuates, thereby degrading the display quality of the display image on the display panel 110.

[0035] For example, when column inversion driving is performed as shown in FIG. 4, when display data is latched in the line latch circuit 20 while the even-numbered second amplifier circuits 42 connected to the even-numbered source lines are performing the initialization operation, the output of the odd-numbered first amplifier circuits 41 connected to the odd-numbered source lines changes. Then, the noise caused by the change in the output of the odd-numbered first amplifier circuits 41 is transmitted to the power supply circuit 60, and the voltage such as the reference voltage supplied by the power supply circuit 60 to the second amplifier circuit 42 fluctuates. As a result, the charge stored in the capacitor of the second switch capacitor circuit SC2 of the even-numbered second amplifier circuits 42 during the second initialization period TI2 fluctuates, and the data voltage output by the second amplifier circuit 42 during the second output period TQ2 fluctuates, resulting in a decrease in display quality. For example, a situation such as the occurrence of two horizontal stripes on the display panel 110 occurs.

[0036] Similarly, when the odd-numbered first amplifier circuit 41 is performing the initialization operation, if display data is latched in the line latch circuit 20, the output of the even-numbered second amplifier circuit 42 changes. Then, noise due to the change in the outputs of the plurality of even-numbered second amplifier circuits 42 is transmitted to the power supply circuit 60, causing the voltage such as the reference voltage supplied by the power supply circuit 60 to the first amplifier circuit 41 to fluctuate. As a result, the charge accumulated in the capacitor of the first switch capacitor circuit SC1 of the odd-numbered first amplifier circuit 41 during the first initialization period TI1 fluctuates, and the data voltage output by the first amplifier circuit 41 during the first output period TQ1 fluctuates, deteriorating the display quality.

[0037] Therefore, in the present embodiment, a method of ending the initialization period is adopted before the display data is latched in the line latch circuit 20 at the latch timing. FIG. 7 is a signal waveform diagram for explaining the operation of the present embodiment.

[0038] In FIG. 7, the period between timings t1 and t2 is the first horizontal scanning period TH1, and the period between timings t2 and t3 is the second horizontal scanning period TH2. In the first horizontal scanning period TH1, the gate line GLj is in a selected state during the first gate line selection period TG1, and data voltage is written to the corresponding pixel. Also, in the second horizontal scanning period TH2, the gate line GLj+1 is in a selected state during the second gate line selection period TG2, and data voltage is written to the corresponding pixel. The first gate line selection period TG1 and the second gate line selection period TG2 respectively correspond to the first scanning line selection period and the second scanning line selection period.

[0039] During the first initialization period TI1, the source line SLi is in a high-impedance state. For example, the output of the first amplifier circuit 41 that drives the source line SLi is in a high-impedance state. This high-impedance state is realized by turning off the output switch provided at the output node of the first amplifier circuit 41. Then, for example, based on the first initialization signal INP from the control circuit 50, the initialization operation of the first amplifier circuit 41 is performed during the first initialization period TI1. That is, the charge accumulated in the capacitor of the first switch capacitor circuit SC1 of the first amplifier circuit 41 is initialized during the first initialization period TI1. And during the first output period TQ1 after the first initialization period TI1, the source line SLi is driven with a positive polarity. That is, the first amplifier circuit 41 drives the source line SLi with a positive-polarity voltage. Note that the first amplifier circuit 41 also drives the source line SLi with a positive polarity during the second horizontal scanning period TH2 following the first horizontal scanning period TH1.

[0040] During the second initialization period TI2, the source line SLi+1 adjacent to the source line SLi is in a high-impedance state. For example, the output of the second amplifier circuit 42 that drives the source line SLi+1 is in a high-impedance state. This high-impedance state is realized by turning off the output switch provided at the output node of the second amplifier circuit 42. Then, for example, based on the second initialization signal INM from the control circuit 50, the initialization operation of the second amplifier circuit 42 is performed during the second initialization period TI2. That is, the charge accumulated in the capacitor of the second switch capacitor circuit SC2 of the second amplifier circuit 42 is initialized during the second initialization period TI2. And during the second output period TQ2 after the second initialization period TI2, the source line SLi+1 is driven with a negative polarity. That is, the second amplifier circuit 42 drives the source line SLi+1 with a negative-polarity voltage. Note that the second amplifier circuit 42 also drives the source line SLi with a negative polarity during the horizontal scanning period following the second horizontal scanning period TH2.

[0041] Then, as shown in FIG. 7, in the present embodiment, before the latch timing tm at which the display data is latched by the line latch circuit 20, the second initialization period TI2 of the second amplifier circuit 42 is terminated. Similarly, before the latch timing tm at which the display data is latched by the line latch circuit 20, the first initialization period TI1 of the first amplifier circuit 41 is terminated.

[0042] For example, in the comparative example of FIG. 6, during the second initialization period TI2 of the second amplifier circuit 42, since the display data is latched by the line latch circuit 20, noise due to the change in the output of the first amplifier circuit 41 caused by the latch of this display data has an adverse effect on the initialization operation of the second amplifier circuit 42 and degrades the display quality. In contrast, in the present embodiment, before the latch timing tm at which the display data is latched by the line latch circuit 20, the second initialization period TI2 of the second amplifier circuit 42 is terminated. Therefore, at the latch timing tm of the display data, since the initialization operation of the second amplifier circuit 42 has been completed, it is possible to prevent noise due to the change in the output of the first amplifier circuit 41 caused by the latch of the display data from having an adverse effect on the initialization operation of the second amplifier circuit 42, and the display quality can be improved. Also, in the comparative example of FIG. 6, during the first initialization period TI1 of the first amplifier circuit 41, since the display data is latched by the line latch circuit 20, noise due to the change in the output of the second amplifier circuit 42 caused by the latch of this display data has an adverse effect on the initialization operation of the first amplifier circuit 41 and degrades the display quality. In contrast, in the present embodiment, before the latch timing tm at which the display data is latched by the line latch circuit 20, the first initialization period TI1 of the first amplifier circuit 41 is terminated. Therefore, at the latch timing tm of the display data, since the initialization operation of the first amplifier circuit 41 has been completed, it is possible to prevent noise due to the change in the output of the second amplifier circuit 42 caused by the latch of the display data from having an adverse effect on the initialization operation of the first amplifier circuit 41, and the display quality can be improved.

[0043] As shown in FIG. 1, the display driver 10 includes a switching regulator 62 and a power supply circuit 60 that supplies a power supply voltage to the first amplifier circuit 41 and the second amplifier circuit 42. The control circuit 50 stops the operation of the switching regulator 62 at least during the second initialization period TI2. Specifically, as shown in FIG. 7, the control circuit 50 sets the mask signal MSK to the active level, which is the high level, during the second initialization period TI2. When the mask signal MSK becomes the active level in this way, the operation of the switching regulator 62 stops. As a result, it is possible to prevent the noise caused by the switching regulation operation of the switching regulator 62 from adversely affecting the initialization operation of the second amplifier circuit 42, and it becomes possible to prevent a decrease in display quality caused by the noise. Similarly, the control circuit 50 stops the operation of the switching regulator 62 at least during the first initialization period TI1. Specifically, as shown in FIG. 7, the control circuit 50 stops the operation of the switching regulator 62 by setting the mask signal MSK to the active level during the first initialization period TI1. As a result, it is possible to prevent the noise caused by the switching regulation operation of the switching regulator 62 from adversely affecting the initialization operation of the first amplifier circuit 41, and it becomes possible to prevent a decrease in display quality caused by the noise. Note that the switching regulator 62 only needs to stop operating at least during the first initialization period TI1 and the second initialization period TI2. For example, in FIG. 7, the mask period TMK during which the operation of the switching regulator 62 stops is longer than the first initialization period TI1 and the second initialization period TI2. Also, even when the operation of the switching regulator 62 stops, the regulated voltage by the switching regulation operation is held and output.

[0044] Also, in this embodiment, as shown in FIG. 7, the control circuit 50 alternately performs the initialization operation of the first amplifier circuit 41 during the first initialization period TI1 and the initialization operation of the second amplifier circuit 42 during the second initialization period TI2 for each horizontal scanning period. For example, in FIG. 7, every time the horizontal scanning period switches from the first horizontal scanning period TH1 to the second horizontal scanning period TH2, the initialization operation of the first amplifier circuit 41 during the first initialization period TI1 and the initialization operation of the second amplifier circuit 42 during the second initialization period TI2 are alternately performed. For example, if the initialization operations of both the first amplifier circuit 41 and the second amplifier circuit 42 are performed in the same initialization period, there may be problems such as a decrease in display quality due to fluctuations in the power supply voltage. In this regard, by alternately performing the initialization operation of the first amplifier circuit 41 and the initialization operation of the second amplifier circuit 42 for each horizontal scanning period as shown in FIG. 7, such problems can be prevented. In FIG. 7, the initialization operation of the first amplifier circuit 41 is performed before the timing t1 when the first horizontal scanning period TH1 starts, and the initialization operation of the second amplifier circuit 42 is performed before the timing t2 when the second horizontal scanning period TH2 starts.

[0045] Also, in this embodiment, as shown in FIG. 7, after the first gate line selection period TG1 in the first horizontal scanning period TH1, the control circuit 50 performs the initialization operation of the second amplifier circuit 42 during the second initialization period TI2. Then, the control circuit 50 ends the second initialization period TI2 of the second amplifier circuit 42 before the display data is latched by the line latch circuit 20 at the latch timing tm and the output of the first amplifier circuit 41 changes. Also, after the second gate line selection period TG2 in the second horizontal scanning period TH2, the control circuit 50 performs the initialization operation of the first amplifier circuit 41 during the first initialization period TI1. Then, the control circuit 50 ends the first initialization period TI1 of the first amplifier circuit 41 before the display data is latched by the line latch circuit 20 at the latch timing tm and the output of the second amplifier circuit 42 changes.

[0046] In this way, after the data voltage is written to the pixels selected during the first gate line selection period TG1 of the first horizontal scanning period TH1, the initialization operation of the second amplifier circuit 42 can be performed during the second initialization period TI2. Then, at the latch timing tm after the second initialization period TI2, the display data is latched by the line latch circuit 20, so that the noise caused by the change in the output of the first amplifier circuit 41 due to the latching of the display data can be prevented from adversely affecting the initialization operation of the second amplifier circuit 42. After the display data is latched by the line latch circuit 20 at the latch timing tm, the data voltage is written to the pixels selected during the second gate line selection period TG2 of the second horizontal scanning period TH2, and then, during the subsequent first initialization period TI1, the initialization operation of the first amplifier circuit 41 can be performed. Then, at the latch timing tm after the first initialization period TI1, the display data is latched by the line latch circuit 20, so that the noise caused by the change in the output of the second amplifier circuit 42 due to the latching of the display data can be prevented from adversely affecting the initialization operation of the first amplifier circuit 41.

[0047] Also, in this embodiment, as shown in FIG. 7, the control circuit 50 ends the second initialization period TI2 before switching from the first horizontal scanning period TH1 to the second horizontal scanning period TH2. Then, after switching from the first horizontal scanning period TH1 to the second horizontal scanning period TH2, the control circuit 50 causes the line latch circuit 20 to perform a latch operation in the second horizontal scanning period TH2. That is, the initialization operation of the second amplifier circuit 42 is ended by the timing t2 when the horizontal scanning period switches from the first horizontal scanning period TH1 to the second horizontal scanning period TH2. Then, after the timing t2 when the horizontal scanning period has switched, the line latch circuit 20 is caused to perform a latch operation. Similarly, the initialization operation of the first amplifier circuit 41 is ended by the timing t1 when the horizontal scanning period switches. Then, after the timing t1 when the horizontal scanning period has switched, the line latch circuit 20 is caused to perform a latch operation. In this way, the latch operation of the line latch circuit 20 can be ended as soon as possible, and it becomes possible to write the data voltage to the pixels in the subsequent second gate line selection period TG2 and the first gate line selection period TG1, and it becomes possible to lengthen the writing time of the data voltage.

[0048] For example, in the comparative example of FIG. 6, if the timing of the latch pulse LP is only delayed so as to be after the initialization operation, the writing time of the data voltage is shortened by the amount of the delay of the timing of the latch pulse LP. When the writing time of the data voltage is shortened in this way, the suitability for the pixel becomes such that the data voltage cannot be written, leading to a deterioration in image quality.

[0049] In this regard, in FIG. 7, before the timings t1 and t2 when the horizontal scanning period switches, the initialization operations of the respective amplifier circuits are ended, and after the timings t1 and t2, the line latch circuit 20 is caused to perform a latch operation. That is, the initialization operations of the respective amplifier circuits are performed in the horizontal scanning period before the horizontal scanning period in which each amplifier circuit outputs a data voltage. In this way, while preventing the adverse effect of the noise caused by the latching of the display data to the line latch circuit 20 on the initialization operation, it becomes possible to lengthen the writing time of the data voltage and improve the display quality of the display panel 110.

[0050] 3. Amplifier Circuit, Power Supply Circuit Next, with reference to FIGS. 8 to 10, a detailed configuration example and operation of each amplifier circuit of the first amplifier circuit 41 and the second amplifier circuit 42 will be described.

[0051] In FIG. 8, the display driver 10 is provided with switch circuits SWA1 and SWA2, amplifier circuits AMP and AMM for positive and negative polarities, D / A conversion circuits DAP and DAM for positive and negative polarities, switch circuits SWB1 and SWB2, and a gradation voltage generation circuit 44. The positive-polarity amplifier circuit AMP and D / A conversion circuit DAP correspond to, for example, the first amplifier circuit 41 and the first D / A conversion circuit 31. The negative-polarity amplifier circuit AMM and D / A conversion circuit DAM correspond to, for example, the second amplifier circuit 42 and the second D / A conversion circuit 32. The switch circuit SWA1 includes switches SPA1 and SMA1, and the switch circuit SWA2 includes switches SMA2 and SPA2. The switch circuit SWB1 includes switches SPB1 and SMB1, and the switch circuit SWB2 includes switches SMB2 and SPB2. The gradation voltage generation circuit 44 includes a positive-polarity gradation voltage generation circuit GCP that outputs a plurality of positive-polarity gradation voltages and a negative-polarity gradation voltage generation circuit GCM that outputs a plurality of negative-polarity gradation voltages.

[0052] In the first state in which the source lines SL1 and SL2 connected to the terminals TS1 and TS2 are driven in positive and negative polarities, respectively, the switches SPA1, SMA2, SPB1, and SMB2 are turned on. In this case, the positive-polarity D / A conversion circuit DAP selects a voltage corresponding to the display data for the source line SL1 from among a plurality of positive-polarity gradation voltages. The positive-polarity amplifier circuit AMP drives the source line SL1 with the positive-polarity data voltage VD1 based on the selected voltage. On the other hand, the negative-polarity D / A conversion circuit DAM selects a voltage corresponding to the display data for the source line SL2 from among a plurality of negative-polarity gradation voltages. The negative-polarity amplifier circuit AMM drives the source line SL2 with the negative-polarity data voltage VD2 based on the selected voltage.

[0053] On the other hand, in the second state where the source lines SL1 and SL2 are driven with negative and positive polarities, the switches SMA1, SPA2, SMB1, and SPB2 are turned on. In this case, the D / A conversion circuit DAM for negative polarity selects a voltage corresponding to the display data for the source line SL1 from among a plurality of negative-polarity gradation voltages. The amplifier circuit AMM for negative polarity drives the source line SL1 with the negative-polarity data voltage VD1 based on the selected voltage. On the other hand, the D / A conversion circuit DAP for positive polarity selects a voltage corresponding to the display data for the source line SL2 from among a plurality of positive-polarity gradation voltages. The amplifier circuit AMP for positive polarity drives the source line SL2 with the positive-polarity data voltage VD2 based on the selected voltage.

[0054] Next, the configuration and operation of the amplifier circuit AMP for positive polarity will be described with reference to FIGS. 9 and 10. As shown in FIG. 9, the amplifier circuit AMP for positive polarity includes a first operational amplifier OP1 and a first switched-capacitor circuit SC1 composed of capacitors CIA, CFA, and switches SA1 to SA5. The amplifier circuit AMP for positive polarity receives the output voltage VDAP of the D / A conversion circuit DAP for positive polarity and outputs a data voltage VD1, and is a circuit that drives the data line. The output voltage VDAP of the D / A conversion circuit DAP is, for example, 0V to +6V.

[0055] The capacitor CIA is provided between a sampling node NEGA connected to the inverting input terminal of the first operational amplifier OP1 and a node NA1. The inverting input terminal is the first input terminal. The capacitor CFA is provided between the sampling node NEGA and a node NA2. Each of these capacitors CIA and CFA can be composed of, for example, a plurality of unit capacitors.

[0056] Switch SA1 is provided between the input node NIA of the amplifier circuit AMP for positive polarity and node NA1. Switch SA2 is provided between the input node of the reference voltage VDDRMP and node NA1. Switch SA3 is provided between node NA2 and the output node NQA. Switch SA4 is provided between node NA2 and the input node of the reference voltage VDDRMP. Switch SA5 is provided between the sampling node NEGA and the output node NQA. These switches SA1 to SA5 can be constituted by, for example, CMOS transistors, specifically, a transfer gate composed of a P-type transistor and an N-type transistor. And these transistors are turned on or off by the switch control signal output from the control circuit 50. Also, the reference voltage VDDRMP is, for example, the voltage between the power supply voltage VDD on the high potential side and the power supply voltage VSS on the low potential side. VDD is, for example, +6V, and VSS is, for example, 0V. For example, VDDRMP = (VDD + VSS) / 2, and for example, VDDRMP = +3V.

[0057] Also, for the first operational amplifier OP1, the sampling node NEGA is connected to its inverting input terminal, the reference voltage VDDRMP is input to its non-inverting input terminal, and the data voltage VD1 is output to the output node NQA. The non-inverting input terminal is the second input terminal. The power supply on the high potential side of the first operational amplifier OP1 is, for example, +6V, and the power supply on the low potential side is, for example, 0V.

[0058] Then, as shown in FIG. 9, in the amplifier circuit AMP for positive polarity, during the initialization period, switches SA2, SA4, and SA5 are turned on. When switch SA2 is turned on during the initialization period, the other end of capacitor CIA, one end of which is electrically connected to the sampling node NEGA, is set to the reference voltage VDDRMP. Similarly, when switch SA4 is turned on, the other end of capacitor CFA, one end of which is electrically connected to the sampling node NEGA, is set to the reference voltage VDDRMP. Also, when the feedback switch SA5 is turned on, the output of the first operational amplifier OP1 is fed back to the inverting input terminal, and due to the imaginary short function of the first operational amplifier OP1, the sampling node NEGA is set to VDDRMP. As a result, during the initialization period, the data voltage VD1 becomes the same voltage as the reference voltage VDDRMP.

[0059] Also, as shown in FIG. 10, in the amplifier circuit AMP for positive polarity, during the output period, switches SA1 and SA3 are turned on. When switch SA1 is turned on during the output period, the other end of capacitor CIA, one end of which is connected to the sampling node NEGA, is set to VDAP. Also, when switch SA3 is turned on, the other end of capacitor CFA, one end of which is connected to the sampling node NEGA, is set to the data voltage VD1. As a result, during the output period, the data voltage VD1 becomes the voltage represented by the following equation (1). In equation (1) and equation (2) described later, CCIA is the capacitance of capacitor CIA, and CCFA is the capacitance of capacitor CFA.

[0060] VD1 = VDDRMP - (CCIA / CCFA) × (VDAP - VDDRMP)…(1)

[0061] Next, the configuration and operation of the amplifier circuit AMM for negative polarity will be described with reference to FIGS. 11 and 12. As shown in FIG. 11, the amplifier circuit AMM for negative polarity includes a second operational amplifier OP2, and a second switch capacitor circuit SC2 composed of capacitors CIA, CFA, and switches SA1 to SA5. As shown in FIGS. 11 and 12, the configuration and operation of the amplifier circuit AMM for negative polarity are the same as those of the amplifier circuit AMP for positive polarity. However, in the amplifier circuit AMM for negative polarity, a reference voltage VDDRMN is also input as a reference voltage. VDDRMN is, for example, -3V. Further, the output voltage VDAM of the D / A conversion circuit DAM for negative polarity is input to the amplifier circuit AMM for negative polarity, and the output voltage VDAM is, for example, 0V to 6V. Note that the power supply on the high potential side of the second operational amplifier OP2 is, for example, 0V, and the power supply on the low potential side is, for example, -6V. Thereby, in the initialization period, the data voltage VD2 becomes the same voltage as the second reference power supply VDDRMN, and in the output period, the data voltage VD2 becomes the voltage represented by the following formula (2).

[0062] VD2 = VDDRMN - (CCIA / CCFA) × (VDAM - VDDRMP)…(2)

[0063] The amplifier circuit AMP for the positive polarity in FIGS. 9 and 10 corresponds to, for example, the first amplifier circuit 41 in FIG. 1, and has a first operational amplifier OP1 and a first switch capacitor circuit SC1 composed of capacitors CIA and CFA and switches SA1 to SA5. Then, in the first initialization period TI1 in FIG. 7, the charges of the capacitors CIA and CFA in the first switch capacitor circuit SC1 are initialized. For example, by setting the reference voltage VDDRMP at one end and the other end of the capacitors CIA and CFA, the charges accumulated in the capacitors CIA and CFA are initialized. Then, in the first output period TQ1, the first operational amplifier OP1 amplifies the output voltage VDAP of the D / A conversion circuit DAP for the positive polarity, which is the first D / A conversion circuit 31, based on the charges of the capacitors CIA and CFA in the first switch capacitor circuit SC1, and outputs the data voltage VD1. For example, as shown in the above formula (1), the data voltage VD1 expressed as VD1 = VDDRMP - (CCIA / CCFA) × (VDAP - VDDRMP) is output.

[0064] Also, the amplifier circuit AMM for the negative polarity in FIGS. 11 and 12 corresponds to, for example, the second amplifier circuit 42 in FIG. 1, and has a second operational amplifier OP2 and a second switch capacitor circuit SC2 composed of capacitors CIA and CFA and switches SA1 to SA5. Then, in the second initialization period TI2 in FIG. 7, the charges of the capacitors CIA and CFA in the second switch capacitor circuit SC2 are initialized. For example, by setting the reference voltage VDDRMP or the reference voltage VDDRMN at one end and the other end of the capacitors CIA and CFA, the charges accumulated in the capacitors CIA and CFA are initialized. Then, in the second output period TQ2, the second operational amplifier OP2 amplifies the output voltage VDAM of the D / A conversion circuit DAM for the negative polarity corresponding to the second D / A conversion circuit 32, based on the charges of the capacitors CIA and CFA in the second switch capacitor circuit SC2, and outputs the data voltage VD2. For example, as shown in the above formula (2), the data voltage VD2 expressed as VD2 = VDDRMN - (CCIA / CCFA) × (VDAM - VDDRMP) is output.

[0065] Thus, the capacitors CIA and CFA of the first switch capacitor circuit SC1 and the second switch capacitor circuit SC2 are capacitors that are initialized by applying the reference voltages VDDRMP and VDDRMN. For example, as shown in FIG. 9, the capacitors CIA and CFA of the first switch capacitor circuit SC1 have the accumulated charges initialized by applying the reference voltage VDDRMP to one end and the other end during the first initialization period TI1. Also, as shown in FIG. 11, the capacitor CIA of the second switch capacitor circuit SC2 has the accumulated charges initialized by applying the reference voltage VDDRMP to one end and the reference voltage VDDRMN to the other end during the second initialization period TI2. The capacitor CFA of the second switch capacitor circuit SC2 has the accumulated charges initialized by applying the reference voltage VDDRMN to one end and the other end during the second initialization period TI2. In this way, the charges accumulated in the capacitors CIA and CFA can be initialized using the reference voltages VDDRMP and VDDRMN of a constant voltage with a stable potential. As a result, during the output period, it becomes possible to output an appropriate data voltage set based on the charges accumulated in the capacitors CIA and CFA during the initialization period. For example, it becomes possible to output an appropriate data voltage with the offset voltages of the first operational amplifier OP1 and the second operational amplifier OP2 canceled out.

[0066] For example, when the latch operation of the display data is performed by the line latch circuit 20 during the initialization period as in the comparative example of FIG. 6, noise is generated in the reference voltages VDDRMP and VDDRMN used for the initialization operation of the capacitors CIA and CFA. As a result, the charges accumulated in the capacitors CIA and CFA fluctuate, causing a problem of deterioration in display quality. In this regard, in the present embodiment, the initialization period of each amplifier circuit is ended before the latch timing of the display data by the line latch circuit 20. Therefore, it becomes possible to effectively prevent the deterioration in display quality caused by the noise generated in the reference voltages VDDRMP and VDDRMN.

[0067] Fig. 13 shows a detailed configuration example of the power supply circuit 60. The power supply circuit 60 includes boost circuits BC1 to BC5 and regulators RG1 to RG13. For example, the boost circuit BC1 is a circuit that boosts the voltage by a switching regulation operation, and the boost circuits BC2 to BC5 are charge pump circuits. Also, the regulators RG1 to RG13 are linear regulators. In Fig. 13, the vertical positional relationship of each voltage in the drawing represents approximately the magnitude relationship of the voltages. For example, VDDL, VLDO, etc. are voltages between VDD and VSS, VOUTM, VOUT3, etc. are voltages lower than VSS, for example, negative voltages, and VOUT, etc. are voltages higher than VDD.

[0068] Regulators RG1, RG2, and RG3 step down VDD to generate VDDL, VLDO1, and VLDO2. VDDL is the power supply voltage of the control circuit 50 which is a logic circuit.

[0069] The boost circuit BC1 boosts VLDO1 by a factor of 2 with respect to VSS to generate VOUT. Regulators RG4, RG5, RG6, RG7, RG8, and RG9 step down VOUT to generate VREG, VDDHSP, VDDRHP, VDDRMP, VOFREG, and VONREG. The regulator RG4 generates VREG based on the output voltage of a bandgap circuit (not shown). The other regulators RG1 to RG3, RG5 to RG13 output each voltage based on VREG. VDDHSP and VDDRMP are voltages used for positive electrode driving. For example, VDDHSP is the power supply voltage of the first operational amplifier OP1 for positive polarity, and VDDRMP is the reference voltage described above. VDDRHP is the power supply voltage of the tone voltage generation circuit.

[0070] The boost circuit BC2 generates VOUTM, which is a negative voltage, by inverting VLDO2 with respect to VSS. The regulator RG10 generates VCOM from VLDO2 and VOUTM. VCOM is the common voltage of the display panel 110. The boost circuit BC3 generates VOUT3, which is a negative voltage, by inverting and boosting VDD four times with respect to VSS. The regulator RG11 steps down VOUT3 to generate VDDHSN, and the regulator RG12 steps down VDDHSN to generate VDDRMN. VDDHSN and VDDRMN are voltages used for negative electrode driving. For example, VDDHSN is the power supply voltage of the second operational amplifier OP2 for negative polarity, and VDDRMN is the reference voltage described above.

[0071] The boost circuit BC4 generates VEE, which is a negative voltage, by inverting and boosting VOFREG three times with respect to VSS. VEE is the substrate voltage of, for example, the P-type semiconductor substrate of the display driver 10. The regulator RG13 steps down VEE to generate VGL. VGL is the negative power supply voltage of the gate driver 130. The boost circuit BC5 generates VDDHG = VONREG × 2 - VGL from VONREG and VGL. VDDHG is the positive power supply voltage of the gate driver 130.

[0072] The switching regulator 62 described with reference to FIG. 1 is provided in the boost circuit BC1 as shown in FIG. 13, for example. In this embodiment, as described with reference to FIG. 7, the operation of the switching regulator 62 is stopped during the first initialization period TI1 and the second initialization period TI2. By doing so, it is possible to prevent the noise caused by the switching regulation operation of the switching regulator 62 from adversely affecting the initialization operation of the first amplifier circuit 41 during the first initialization period TI1 and the initialization operation of the second amplifier circuit 42 during the second initialization period TI2.

[0073] Note that the configurations of the amplifier circuits of the first amplifier circuit 41 and the second amplifier circuit 42 in the present embodiment are not limited to the configurations described with reference to FIGS. 9 to 12, and various modifications can be made. For example, FIGS. 14 and 15 show other configuration examples of the amplifier circuit AM. The amplifier circuit AM in FIGS. 14 and 15 includes an operational amplifier OP and a switched-capacitor circuit SC composed of capacitors C1, C2, CC and switches SW1 to SW7. As shown in FIG. 14, during the initialization period, switches SW2, SW4, and SW7 are turned on, and an initialization operation is performed to initialize the charges of, for example, capacitors C1, C2, and CC. For example, one end or the other end of capacitors C1, C2, and CC is set to AGND, which is a reference voltage, and the charges are initialized. Also, as shown in FIG. 15, during the output period, switches SW3 and SW4 are turned on. As a result, the amplifier circuit AM amplifies the output voltage VDAC of the previous D / A conversion circuit based on the charges of capacitors C1, C2, and CC of the switched-capacitor circuit SC and outputs a data voltage VD. For example, when the voltage of AGND is VA, the amplifier circuit AM outputs a data voltage VD expressed as VD = VA - (C1 / C2) × (VDAC - VA). According to the amplifier circuit AM having the configuration shown in FIGS. 14 and 15, offset-free cancellation of the offset voltage of the operational amplifier OP can be achieved.

[0074] As described above, the display driver of the present embodiment includes a line latch circuit that latches display data for one line, a first D / A conversion circuit that D / A-converts the display data from the line latch circuit, and a second D / A conversion circuit that D / A-converts the display data from the line latch circuit. Further, the display driver has a first switch capacitor circuit and a first operational amplifier. In the first initialization period, the charge of the capacitor of the first switch capacitor circuit is initialized. In the first output period, the first operational amplifier amplifies the output voltage of the first D / A conversion circuit based on the charge of the capacitor of the first switch capacitor circuit to output a data voltage, including a first amplifier circuit. The display driver also has a second switch capacitor circuit and a second operational amplifier. In the second initialization period, the charge of the capacitor of the second switch capacitor circuit is initialized. In the second output period, the second operational amplifier amplifies the output voltage of the second D / A conversion circuit based on the charge of the capacitor of the second switch capacitor circuit to output a data voltage, including a second amplifier circuit. The display driver also includes a control circuit that controls the line latch circuit, the first amplifier circuit, and the second amplifier circuit. The control circuit ends the second initialization period of the second amplifier circuit before the display data is latched by the line latch circuit at the latch timing and the output of the first amplifier circuit changes.

[0075] According to this embodiment, display data from the line latch circuit is D / A converted by the first D / A conversion circuit and the second D / A conversion circuit. Also, in the first initialization period, the charge of the capacitor of the first switch capacitor circuit is initialized, in the first output period, a data voltage is output from the first amplifier circuit, in the second initialization period, the charge of the capacitor of the second switch capacitor circuit is initialized, and in the second output period, a data voltage is output from the second amplifier circuit. Then, before the display data is latched by the line latch circuit at the latch timing, the second initialization period of the second amplifier circuit is controlled to end. In this way, it becomes possible to prevent noise caused by a change in the output of the first amplifier circuit due to latching of the display data in the line latch circuit from adversely affecting the initialization operation of the second amplifier circuit, and it becomes possible to prevent a decrease in display quality due to the noise.

[0076] Also, in this embodiment, it has a switching regulator and includes a power supply circuit that supplies a power supply voltage to the first amplifier circuit and the second amplifier circuit, and the control circuit may stop the operation of the switching regulator at least in the second initialization period.

[0077] In this way, it becomes possible to prevent noise caused by the switching regulation operation of the switching regulator from adversely affecting the initialization operation of the second amplifier circuit in the second initialization period, and it becomes possible to prevent a decrease in display quality due to the noise.

[0078] Also, in this embodiment, the first amplifier circuit may be an amplifier circuit for positive polarity that outputs a positive polarity voltage, and the second amplifier circuit may be an amplifier circuit for negative polarity that outputs a negative polarity voltage.

[0079] In this way, reverse driving of the display driver by driving with positive polarity by the amplifier circuit for positive polarity and driving with negative polarity by the amplifier circuit for negative polarity becomes possible.

[0080] Also, in this embodiment, the control circuit may alternately perform the initialization operation of the first amplifier circuit during the first initialization period and the initialization operation of the second amplifier circuit during the second initialization period for each horizontal scanning period.

[0081] In this way, it is possible to prevent problems that occur when the initialization operations of both the first amplifier circuit and the second amplifier circuit are performed in the same initialization period.

[0082] Also, in this embodiment, the control circuit performs the initialization operation of the second amplifier circuit during the second initialization period after the gate line selection period in the first horizontal scanning period, and ends the second initialization period of the second amplifier circuit before the display data is latched by the line latch circuit at the latch timing and the output of the first amplifier circuit changes. Then, the control circuit performs the initialization operation of the first amplifier circuit during the first initialization period after the gate line selection period in the second horizontal scanning period, and ends the first initialization period of the first amplifier circuit before the display data is latched by the line latch circuit at the latch timing and the output of the second amplifier circuit changes.

[0083] In this way, it becomes possible to prevent noise caused by the change in the output of the first amplifier circuit due to the latching of the display data from affecting the initialization operation of the second amplifier circuit, and also to prevent noise caused by the change in the output of the second amplifier circuit due to the latching of the display data from affecting the initialization operation of the first amplifier circuit.

[0084] Also, in this embodiment, the control circuit may end the second initialization period before switching from the first horizontal scanning period to the second horizontal scanning period, and cause the line latch circuit in the second horizontal scanning period to perform a latching operation after switching from the first horizontal scanning period to the second horizontal scanning period.

[0085] By doing so, it becomes possible to end the latch operation of the line latch circuit as soon as possible, and then write the data voltage to the pixel during the subsequent second gate line selection period or the like, making it possible to lengthen the writing time of the data voltage.

[0086] Also, in this embodiment, the capacitors of the first switch capacitor circuit and the second switch capacitor circuit may be capacitors that are initialized by applying a reference voltage.

[0087] By doing so, the charge accumulated in the capacitor can be initialized using the reference voltage, and during the output period, it becomes possible to output an appropriate data voltage set based on the charge accumulated in the capacitor during the initialization period.

[0088] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novel matters and effects of the present invention. Therefore, all such modified examples are considered to be included in the scope of the present invention. For example, in the specification or drawings, a term described at least once together with a broader or synonymous different term can be replaced with that different term anywhere in the specification or drawings. Also, the configurations and operations of the display driver, electro-optical device, etc. are not limited to those described in this embodiment, and various modified implementations are possible.

Explanation of Reference Numerals

[0089] 10... display driver, 20... line latch circuit, 22... input latch circuit, 24... address decoder, 31... first D / A conversion circuit, 32... second D / A conversion circuit, 41... first amplifier circuit, 42... second amplifier circuit, 44... gradation voltage generation circuit, 50... control circuit, 60... power supply circuit, 62... switching regulator, 100... electro-optical device, 110... display panel, 120... source driver, 130... gate driver, 140... controller AM, AMM, AMP... amplifier circuit, BC1~BC5... boost circuit, C1, C2, CFA, CIA... capacitor, CK... clock signal, DAM, DAP... D / A conversion circuit, DEM, DEP... conversion circuit, GCM, GCP... tone voltage generation circuit, GL1~GLj... gate line, LP... latch pulse, MSK... mask signal, OP... operational amplifier, OP1... first operational amplifier, OP2... second operational amplifier, RG1~RG13... regulator, SA1~SA5... switch, SC... switch capacitor circuit, SC1... first switch capacitor circuit, SC2... second switch capacitor circuit, SL1~SLi... source line, SMA1, SMA2, SMB2, SPA1, SPB1, SW1~SW7... switch, SWA, SWA1, SWA2, SWB, SWB1, SWB2... switch circuit, TG1... first gate line selection period, TG2... second gate line selection period, TH1... first horizontal scanning period, TH2... second horizontal scanning period, TI1... first initialization period, TI2... second initialization period, TMK... mask period, TQ1... first output period, TQ2... second output period, TS1, TS2... terminal, VD, VD1, VD2... data voltage, VDAM, VDAP... output voltage, VGM, VGP... tone voltage, t1~t3... timing, tm... latch timing

Claims

1. A line latch circuit for latching display data of one line by a latch pulse; A first D / A conversion circuit for D / A converting the display data from the line latch circuit; A second D / A conversion circuit for D / A converting the display data from the line latch circuit; A first amplifier circuit having a first switch capacitor circuit and a first operational amplifier, wherein the charge of the capacitor of the first switch capacitor circuit is initialized in a first initialization period, and in a first output period following the first initialization period, the first operational amplifier amplifies the output voltage of the first D / A conversion circuit based on the charge of the capacitor of the first switch capacitor circuit to output a data voltage; A second amplifier circuit having a second switch capacitor circuit and a second operational amplifier, wherein the charge of the capacitor of the second switch capacitor circuit is initialized in a second initialization period after the first initialization period, and in a second output period following the second initialization period, the second operational amplifier amplifies the output voltage of the second D / A conversion circuit based on the charge of the capacitor of the second switch capacitor circuit to output a data voltage; A control circuit for controlling the line latch circuit, the first amplifier circuit, and the second amplifier circuit; comprising; The control circuit is configured to: By changing the latch pulse of the line latch circuit after the end of the second initialization period, before the display data is latched by the line latch circuit at the latch timing based on the latch pulse and the output of the first amplifier circuit changes, the second initialization period of the second amplifier circuit is terminated. A display driver characterized by this.

2. In the display driver according to claim 1, It has a switching regulator and includes a power supply circuit for supplying a power supply voltage to the first amplifier circuit and the second amplifier circuit, The control circuit is configured to: A display driver characterized by stopping the operation of the switching regulator at least in the second initialization period.

3. In the display driver according to claim 1 or 2, The first amplifier circuit is an amplifier circuit for positive polarity that outputs a positive polarity voltage, The second amplifier circuit is an amplifier circuit for negative polarity that outputs a negative polarity voltage. A display driver characterized by this.

4. In the display driver according to any one of claims 1 to 3, The control circuit The display driver is characterized in that the initialization operation of the first amplifier circuit in the first initialization period and the initialization operation of the second amplifier circuit in the second initialization period are alternately performed for each horizontal scanning period. **Claim 5** In the display driver according to any one of claims 1 to 4, The control circuit Performs the initialization operation of the second amplifier circuit in the second initialization period after the gate line selection period in the first horizontal scanning period, Ends the second initialization period of the second amplifier circuit before the display data is latched by the line latch circuit at the latch timing and the output of the first amplifier circuit changes, Performs the initialization operation of the first amplifier circuit in the first initialization period after the gate line selection period in the second horizontal scanning period, The display driver is characterized in that the first initialization period of the first amplifier circuit is ended before the display data is latched by the line latch circuit at the latch timing and the output of the second amplifier circuit changes. **Claim 6** In the display driver according to any one of claims 1 to 4, The control circuit Ends the second initialization period before switching from the first horizontal scanning period to the second horizontal scanning period, and causes the line latch circuit in the second horizontal scanning period to perform a latching operation after switching from the first horizontal scanning period to the second horizontal scanning period. The display driver is characterized by this. **Claim 7** In the display driver according to any one of claims 1 to 6, The capacitors of the first switch capacitor circuit and the second switch capacitor circuit are capacitors that are initialized by applying a reference voltage. The display driver is characterized by this.

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