Memory control device, portable electronic device

Abstract

To provide a memory controller and electronic equipment that shorten a time necessary for preparation before ready to read out.SOLUTION: A memory controller comprises: storage means (flash EEPROM) for storing logical address information allocated to a physical block and physical address information indicating a physical address of the physical block to which a logical address next to the logical address is allocated in a redundant area of a page in a physical block for each physical block; and table creation means for acquiring a logical address and a physical address for a plurality of physical blocks from the redundant area of the page when initialization of the storage means so as to create an address conversion table indicating a relationship between a physical address of each of the plurality of physical blocks and a logical address allocated to each of the plurality of physical blocks. The storage means stores data by type, and stores the logical address of the physical block sequentially after preparing physical blocks the number of which is larger than those required for the data to be stored to sort them in the order of their physical address.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a memory control device at the time of reading from a non-volatile memory.

Background Art

[0002] In recent years, non-volatile memories composed of flash EEPROMs have been used as storage devices in many portable electronic devices such as personal computers, smartphones, and digital cameras.

[0003] A non-volatile memory is composed of a plurality of blocks each composed of a plurality of pages. Data erasure is performed in units of each block, and data writing is performed in units of pages. Note that a page has a data storage area and a redundant area.

[0004] For such a non-volatile memory, a method of controlling using a logical address and a physical address is known. Specifically, a memory control method is known in which a logical address can be converted into a physical address by using a conversion table called a logical table that records the correspondence between the logical address and the physical address for each physical block.

[0005] The memory control device described in Patent Document 1 does not perform a search process for a physical block from which physical address information can be obtained. In this case, a control method is disclosed in which at least N / 2 search processes are required to create an address conversion table for a memory composed of N blocks.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, the memory control described in Patent Document 1 has a problem that, considering the writing process to the memory, it is necessary to perform N / 2 search processes because all address translation tables need to be completed.

[0008] Furthermore, the memory control described in Patent Document 1 has a problem that, even when only one block is desired to be rewritten, all blocks are rewritten in the worst case, which is unrealistic in terms of memory operation.

[0009] Here, the conversion table, the Lun object table, will be described. The conversion table is generally configured on a volatile memory such as RAM. Therefore, each time the power of the memory device is turned off, the content of the Lun object table disappears. Also, it is necessary to newly create the Lun object table each time the non-volatile memory is initialized.

[0010] Then, when the power of the memory device is turned on and the Lun object table is created, it is necessary to access the physical blocks of the non-volatile memory to obtain the logical address information. Therefore, the increase in the number of accesses means that it takes a lot of time until the memory device is actually in a readable state after the power is turned on.

[0011] The present invention has been made in view of such a situation, and an object thereof is to provide a memory control device and a portable electronic device that can shorten the time required for preparation until it becomes readable.

Means for Solving the Problem

[0012] A first invention, which is a means for solving the above problems, is a memory control device that controls a non-volatile memory having a page having a data storage area and a redundant area, a physical block having a plurality of the pages, and the physical block. For each physical block, in the redundant area of the page in the physical block, a logical address assigned to the physical block s andThe physical address of the physical block to which the next logical address of the logical address is assigned s and Storage means for storing, the storage means stores data by type, prepares more physical blocks than necessary for the data to be stored, sorts them in ascending order of the physical addresses, and then sequentially stores the logical addresses of the physical blocks in ascending or descending order. When initializing the non-volatile memory, the logical address and the physical address are obtained from the redundant area of the page for a plurality of the physical blocks, and according to each obtained logical address and physical address, a table creation means for creating an address conversion table showing the relationship between the physical address of each of the plurality of physical blocks and the logical address assigned to each of the plurality of physical blocks and An access means for converting a logical address of an access target into a physical address using the address conversion table created by the table creation means and accessing a physical block designated by the converted physical address. A memory control device characterized by having

[0013] Further, a second invention, which is a means for solving the above-described problems, is the first invention, wherein the address conversion table created by the table creation means is partially completed by tracing the physical address, and the completed portion can be accessed by a read access. A memory control device characterized by that

[0014] Further, a third invention, which is a means for solving the above-described problems, is the first or second invention, wherein when the table creation means creates the address conversion table, the memory control device traces only the physical address corresponding to a specific logical address in the redundant area

[0015] Further, a fourth invention, which is a means for solving the above-described problems, is an imaging device characterized by including the memory control device according to any one of the first to third inventions

Effect of the Invention

[0016] According to the present invention, it is possible to provide a memory control device and a portable electronic device that can shorten the time required for preparation until readability.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Modes for Carrying Out the Invention

[0018] Hereinafter, the best mode for carrying out the present invention will be described with reference to the accompanying drawings. Also, the present invention is not limited by this embodiment.

[0019] FIG. 1 is a configuration example of a non-volatile memory by a memory control device according to an embodiment of the present invention. Specifically explaining the non-volatile memory, it is a NAND type flash memory which is a kind of flash EEPROM. The flash EEPROM is composed of a plurality of blocks (Block 1 to Block M). Each block is composed of a plurality of pages (Page 0 to Page N). When erasing stored data, it is executed in units of blocks.

[0020] Next, the page will be described. One page is composed of a user area that can be freely used by the user for data storage and the like, and a redundant area. Note that for the flash EEPROM, writing and reading of data are executed in units of pages.

[0021] The redundant area of each page is used for storing information such as whether the user area of the block to which the corresponding page belongs is an empty block, defect information including whether it is congenital or acquired, the logical address corresponding to the data part of the user area, and the calculation result of an error correction code (ECC) for checking the validity of the data stored in the data area.

[0022] The flash EEPROM has a lifespan which is the upper limit of the number of rewrites per block. When updating data, if a specific block is used in an abusive way, the specific block will reach its lifespan. Therefore, in order to extend the lifespan of the flash EEPROM which is an aggregate of blocks, it is ideal to use all blocks evenly. Such a usage method is called wear leveling. Also, there may be blocks that cannot be used due to initial defects. Then, as described above, blocks that cannot record data due to lifespan or initial defects are recorded to that effect in the redundant area.

[0023] Specifically, in Physical Blocks 1 to Physical Block M, the logical addresses assigned to the physical blocks corresponding to the redundant areas of specific pages such as the 0th page of each block are stored. The correspondence between this physical address and the logical address is managed in a logical object table.

[0024] In addition, in the redundant area of a specific page in each physical block, in addition to the logical address assigned to the corresponding physical block, the physical address of the physical block to which the next logical address is assigned is also stored.

[0025] Figure 2 shows the stored content of the redundant area of page 0 of the physical block.

[0026] As shown in Figure 2, the redundant area of page 0 of the physical block stores the logical address (LBA), the next physical address (PBA+1), and ECC data. The logical address (LBA) is the logical address assigned to the physical block. The next physical address (PBA+1) is the physical address to which the next logical address (LBA+1) is assigned. In this embodiment, the address of the physical block is PBA and the logical address is LBA. Specifically, when the physical address assigned to the physical block is n, it is denoted as PBA(n), and similarly, when the logical address is n, it is denoted as LBA(n).

[0027] If the physical block to which the next logical address (LBA+1) is assigned is undetermined, nothing is stored. In the description of this embodiment, "×" is described.

[0028] Figure 3 shows a configuration example of the memory control device 1 of this embodiment.

[0029] The memory control device 1 is provided inside portable electronic devices such as personal computers, smartphones, and digital cameras. The memory control device 1 executes read and write accesses to the flash EEPROM 11 in response to access requests sent from the CPU 10 of the portable electronic device.

[0030] The memory control device 1 includes a CPU 10, a flash EEPROM 11, and a RAM 12, and each part is connected by a bus.

[0031] The CPU 10 creates the object table 13 in the RAM 12 during the initialization of the flash EEPROM 11.

[0032] As described above, the flash EEPROM 11 is composed of a plurality of blocks each composed of a plurality of pages. Each block is a physical block, and the logical address assigned to the physical block is stored in the redundant area of a specific page of the physical block. Other data is also stored in the redundant area as shown in FIG. 2 and described above. Also, various data can be stored in the user area. The flash EEPROM 11 corresponds to the storage means.

[0033] By referring to the object table 13, the CPU 10 converts the logical address specified from the CPU 10 into a physical address and executes read and write accesses to the flash EEPROM 11.

[0034] The CPU 10 includes an access execution unit 101, a writing unit 102, and an object table creation unit 103. Also, it controls each unit.

[0035] The access execution unit 101 converts the logical address (LBA) specified from the CPU 10 into a physical address (PBA) from the object table 13. It accesses the physical block in the flash EEPEOM 11 specified by the converted physical address (PBA). Also, the logical address specified by the CPU 10 includes the address of the logical block and the page address within the block. Also, in the lower bits of the address of the physical block, a physical address for accessing the flash EEPROM 11 is formed by adding the page address within the block. The access execution unit 101 corresponds to the access means.

[0036] Also, when the page of the physical address obtained by converting the logical address (LBA) specified by the CPU 10 from the object table 13 already has data written therein, the access execution unit 101 performs a process of writing the content stored in all the pages within the physical block including the specified page and the content to be written to the page requested to be written into a physical block whose content has been erased in the flash EEPROM 11.

[0037] The writing unit 102 stores, for each redundant area of page 0 of each physical block in the flash EEPROM 11, the logical address (LBA) assigned to the physical block and the physical address (PBA) to which the next logical address (LBA + 1) of the logical address is assigned. Similarly, when a data write request is made from the CPU 10 to a physical block, the same writing process is performed on the specified physical block.

[0038] When initializing the flash EEPROM 11, the object table creation unit 103 can obtain the correspondence between the physical addresses (PBA) and the logical addresses (LBA) of physical blocks 1 to M by acquiring the logical address (LBA) and the physical address (PBA + 1) to which the next logical address is assigned from the redundant area of page 0 of each physical block, and the object table 13 is created. The object table creation unit 103 corresponds to table creation means.

[0039] Although it is common to complete the object table 13 before reading data, in this application, reading is enabled when the object correspondence of the data required for reading is known even during the creation of the object table 13. Further, by sequentially accessing the physical blocks of the physical addresses assigned to the next logical addresses in the redundant part, only the object information required for reading can be updated. That is, it is possible to reduce the number of accesses required for creating the necessary part of the object table 13, which has the effect of shortening the time from the initialization of the flash EEPROM 11 until it becomes readable.

[0040] Figure 4 is a flowchart of a method for allocating logical addresses when newly writing data to a physical block. This will be described with reference to Figure 4. Figure 5 is a specific example for explaining Figure 4.

[0041] Write n logical addresses from logical address M to M + n - 1.

[0042] As described above, in step #1, considering wear leveling, assume n physical blocks are required for writing data, and secure m physical blocks as write candidates. Note that the number of physical blocks m as write candidates is more than the n physical blocks required for writing. This is because among the physical blocks secured as write candidates, it is necessary to consider the possibility that data cannot be written due to lifespan or initial defects.

[0043] Also, if the number of physical blocks as write candidates, m, is not sufficient and the physical blocks as write candidates run out during writing, new physical blocks must be selected. In this case, even if writing to all physical blocks is completed, the physical block addresses will not be in ascending order. However, for those that have been written before depletion, they will be in ascending order. Therefore, up to the ascending part, a singly-linked list can be created, so the effect of the present application is achieved.

[0044] In step #2, set i = 0 and j = 0 for the logical address LBA(i) and the physical address (PBA) of the write candidate C(j).

[0045] In step #3, sort the m physical blocks as write candidates secured in step #1 in descending order by physical address (PBA). Assign C(0) to C(m - 1) to the sorted physical blocks in descending order from the beginning.

[0046] In step #4, write data such as the user setting value of LBA(M + n - 1 - i) to the user area of the physical address (PBA) of C(j).

[0047] Step #5 checks whether the data of LBA (M + n - 1 - i) has been written to the user area of the physical address (PBA) in Step #4. If the data is successfully written, proceed to Step #6. If it fails, proceed to Step #9.

[0048] Step #6 writes the physical address (PBA) of C´(i - 1), which forms a singly-linked list, together with the logical address (LBA) to the redundant area of page 0 of the physical block. When i = 0, since there is no singly-linked list, nothing is written.

[0049] Step #7 performs C´(i) = C(j) and i = i++.

[0050] Step #8 compares i < n to determine whether all logical addresses (LBAs) have been written. If i < n, there are unwritten logical addresses (LBAs), so proceed to Step #9 to continue the writing process. On the other hand, if i ≥ n, the writing is complete, so complete the writing process.

[0051] Step #9 performs j = j++ and returns to Step #4.

[0052] The flowchart of FIG. 4 described above will be explained using the specific example of FIG. 5. FIG. 5 - A shows the physical blocks to be written and their physical addresses, and FIG. 5 - B shows the physical address (PBA) of the physical block, the logical address (LBA) stored in its redundant area, and the singly-linked list.

[0053] In this embodiment, the logical addresses (LBAs) of the physical blocks to be written are 0 to 2. Therefore, M = 0, and the number of physical blocks n required for writing the data is 3. Next, in Step #1, as shown in FIG. 5 - A - 1, m = 5 physical blocks to which this data is to be written are secured. The physical addresses (PBAs) of the secured physical blocks are PBA(2), PBA(4), PBA(8), PBA(6), and PBA(1). In Step #2, i = 0 and j = 0.

[0054] In step #3, as shown in FIG. 5-A-2, when sorting the physical addresses (PBAs) of the secured physical blocks in descending order, the order is 8, 6, 4, 2, 1. That is, the candidates for writing are in the order of C(0)=PBA(8), C(1)=PBA(6), C(2)=PBA(4), C(3)=PBA(2), C(4)=PBA(1).

[0055] In step #4, having sorted in descending order in the previous step #3, the largest C(0)=PBA(8) among the physical addresses (PBAs) where writing has not been performed becomes the physical address of the write candidate. Write the data of LBA(2) to the user area of PBA(8).

[0056] In step #5, since the writing of LBA(2) to the user area of PBA(8) is successful, proceed to step #6.

[0057] In step #6, as shown in FIG. 5-B, write the logical address LBA(2) to the redundant area of page 0 of C(0)=PBA(8) and write a singly-linked list. Since j = 0, there is no writing of the singly-linked list and it becomes ×.

[0058] In step #7, set C‘(0)=C(0)=PBA(8) and increment i, so i changes from 0 to 1. In step #8, compare i and n. Since i = 1 and n = 3, i < n, so proceed to step #9. In step #9, j changes from 0 to 1 and return to step #4.

[0059] In step #4, which returns from step #9, write the data of LBA(1) to the user area of C(1)=PBA(6) because i = 1 and proceed to step #4.

[0060] In step #5, determine whether the writing in step #4 was successful. Assume that the writing of the data of LBA(1) to the user area of PBA(6) was not successful due to a defect in the user area or the like. Then, proceed to step #9 again. In step #9, j changes from 1 to 2 and return to step #4.

[0061] Return to step #4, change the write target to C(2)=PBA(4), and attempt to write the data of LBA(1) to the user area of PBA(4) again. Proceed to step #5.

[0062] Step #5 checks whether the writing of the data of LBA(1) to the user area of PBA(4) in step #4 was successful. Since it was successful, proceed to step #6.

[0063] As shown in Figure 5-B, step #6 writes LBA(1) and C´(0)=C(0)=PBA(8) (where i = 1, j = 2 and since j≠0, it forms a unidirectional list) to the redundant area of page 0 of the physical block of C(2)=PBA(4). Perform i++. So i changes from 1 to 2.

[0064] In step #7, set C‘(1)=C(2)=PBA(4) and perform i++. So i becomes 2. In step #8, since i < n, return to step #9 to continue the writing process. In step #9, perform j++. So j changes from 2 to 3.

[0065] In step #4 which we return to again, change the write target to C(3)=PBA(2), and attempt to write the data of LBA(0) to the user area of PBA(2).

[0066] In step #5, check whether the writing of the data of LBA(0) to the user area of PBA(2) in step #4 was successful. Since it was successful, proceed to step #6.

[0067] As shown in Figure 5-B, step #6 writes LBA(0) and C´(1)=C(2)=PBA(4) (where i = 2, j = 3 and since j≠0, it forms a unidirectional list) to the redundant area of page 0 of the physical block of C(3)=PBA(2).

[0068] Step #7 performs i++, so i changes from 2 to 3. Therefore, when proceeding to Step #8, i < n holds. From the above, since the writing of all logical addresses from 0 to 2 of the logical block address (LBA) is completed, the main flow of data writing ends.

[0069] Next, the method of creating an object table will be described using the flowchart of object table creation in FIG. 6.

[0070] In creating the object table, the relationship between the logical block address (LBA), the physical block address (PBA), and the redundant area is used to create the object table based on the assignment of logical addresses to physical blocks performed in the aforementioned Steps #1 to #6. Specifically, the logical addresses (LBA) "0 to 2" are user-set values, and "3 to 4" are adjustment values. The steps of creating an object table until the logical addresses (LBA) "0 to 2", which are user-set values, are read out will be described. In the case of an imaging device such as a digital camera, the user-set values are values that the user can set on the menu screen, such as the ISO sensitivity, and the adjustment values are individual adjustment values stored in the mass production process of the digital camera and the imaging device, such as defective pixel information.

[0071] FIG. 6 shows a flowchart of object table creation when reading the logical block address (LBA) for M to n blocks.

[0072] In Step #11, set i = 0 for the logical block address LBA(i) and j = 0 for the physical block address PBA.

[0073] In Step #12, determine whether information on the physical block address PBA already exists in the object table of LBA(M + i). If it does not exist, proceed to Step #13. If it exists, proceed to Step #20.

[0074] In Step #13, determine whether LBA(i) is i = 0. If i = 0, proceed to Step #14. If i ≠ 0, proceed to Step #22.

[0075] Step #14 checks whether PBA(j) has been checked. If it has been checked, proceed to Step #18. If it has not been checked, proceed to Step #15.

[0076] Step #15 reads the redundant area of PBA(j) and marks it as checked in the corresponding PBA of the check table. Step #16 determines whether there is an LBA(X) corresponding to the redundant area of the read PBA(j). If data exists, proceed to Step #17. If no data exists, proceed to Step #18.

[0077] Step #17 reads the LBA(X) stored in the redundant area of PBA(j) and updates the argument table. Also, if the information of the singly linked list is stored in the redundant area, since the PBA storing the next LBA (hereinafter referred to as LBA(X + 1)) of the LBA(X) read earlier can be known, update the argument table for this as well.

[0078] Step #18 performs j = j++ until the unchecked PBA in the check table.

[0079] Step #19 determines whether the information of the argument table of LBA(M + i) has been obtained. If it has been obtained, proceed to Step #20. If it has not been obtained, proceed to Step #14.

[0080] Step #20 performs i = i++. Step #21 compares the new i after performing i++ in Step #20 with the number of blocks n to be read. If i < n, return to Step #12. Otherwise, the flowchart for creating the argument table ends.

[0081] Step #22 determines whether the information of the PBA corresponding to LBA(M + i - 1) in the argument table exists. If it exists, proceed to Step #23. If it does not exist, proceed to Step #14.

[0082] Step #23 reflects and updates the PBA for LBA (M + i - 1) in the item table. Further, the redundant area of the PBA is read, and the corresponding PBA in the check table is marked as checked.

[0083] Step #24 checks whether unidirectional list information is stored in the redundant area of the PBA for LBA (M + i - 1). If the information of the unidirectional list is stored in the redundant area, since the PBA storing LBA (M + i) can be known, the item table is also updated here. Proceed to Step #20.

[0084] Figure 7 shows various data written by A to each physical block, B as the item table, and C as the check table. More specifically, from the various data of A, the addresses of each physical block are from PBA(0) to PBA(9), the logical addresses corresponding to each PBA are described in the LBA, and the address of the PBA where the next LBA is written is described in the unidirectional list. As an example, the logical address corresponding to PBA(0) which is the physical address 0 is LBA(3), and it can be seen that the physical address where LBA(4), which is the next logical address of LBA(3) from the unidirectional list, is stored is PBA(3).

[0085] Next, the numbers in the item table of B indicate that the leftmost column shows the physical address corresponding to LBA(0), and as you move to the right, the numbers of the logical addresses increase and the right end shows the physical address corresponding to LBA(9). The check table of C indicates the check status of PBA(0) in the leftmost column, and similarly, as you move to the right, the numbers of the addresses increase and the right end shows the check status of PBA(9). Note that the ○ in the check table of C indicates checked, and the × in the item table of B and the check table of C indicate that no data is written and unchecked, respectively.

[0086] Figure 7 specifically explains each step according to the flowchart described in FIG. 6 for the above embodiment.

[0087] This embodiment creates an argument table using the data of the physical block written with reference to FIG. 4. Specifically, an argument table for logical addresses (LBAs) “0 to 2” is created. Therefore, since three blocks from logical address (LBA) 0 to 2 are read, M = 0 and n = 3. Hereinafter, the steps will proceed along the flowchart of FIG. 6.

[0088] In step #11, i = 0 and j = 0 are set and the process proceeds to step #12. In step #12, since the information of the argument table of LBA(0) has not been acquired, the process proceeds to step #13. In step #13, since i = 0 was set in step #11, the process proceeds to step #14.

[0089] The embodiment that proceeds to step #14 reads the redundant area of PBA(0) from j = 0. It is confirmed whether the PBA(0) in the check table has been checked. Since the check table has not been checked in the previous steps, of course PBA(0) has not been checked either. The process proceeds to step #15.

[0090] The embodiment that proceeds to step #15 reads the redundant area of PBA(0) from j = 0. As shown in FIG. 7-C-1, a checked mark is attached to PBA(0) in the check table. The process proceeds to step #16. Since LBA(3) is stored in the redundant area of PBA(0) from FIG. 7-A, the process proceeds to step #17.

[0091] In step #17, it can be seen from FIG. 7-A that LBA(3) is stored in the redundant area of PBA(0). It is updated to be reflected in the argument table. Further, a singly-linked list exists in the redundant area of PBA(0) and “3” is stored. This indicates that LBA(4) is stored in PBA(3). This is also updated to be reflected in the argument table (FIG. 7-B-1). Step #17 is completed here. The process proceeds to step #18.

[0092] In step #18, when looking at the next PBA(1) of PBA(0) in the check table from Figure 7-C-1, since it is unchecked, 1 is added to j = 0, and j becomes 1. Proceed to step #19.

[0093] In step #19, it is determined whether the information of the item table of LBA(0) can be obtained. Since it cannot be obtained for LBA(0) from Figure 7-B-1, proceed to step #14.

[0094] In step #15, since j = 1, the redundant area of PBA(1) is read, and a checked mark is placed on PBA(1) in the check table (Figure 7-C-2). In step #16, it can be seen from Figure 7-A that neither the LBA nor the singly-linked list information is stored in the redundant area of PBA(1). Therefore, proceed to step #18.

[0095] In step #18, when looking at the next PBA(2) of PBA(1) in the check table from Figure 7-C-2, since it is unchecked, 1 is added to j = 1, and j becomes 2. Proceed to step #19.

[0096] In step #19, it is again determined whether the information of the item table of LBA(0) can be obtained. Since it cannot be obtained for LBA(0) from Figure 7-B-1, proceed to step #14. In step #14, it is confirmed whether PBA(2) has been checked. When looking at PBA(2) in the check table from Figure 7-C-2, it is unchecked, so proceed to step #15.

[0097] In step #15, since j = 2, the redundant area of PBA(2) is read, and a checked mark is placed on PBA(2) in the check table (Figure 7-C-3). In step #16, it can be seen from Figure 7-A that both the LBA and the singly-linked list information are stored in the redundant area of PBA(2). Therefore, proceed to step #17.

[0098] In step #17, it can be seen from Figure 7-A that LBA(0) is stored in the redundant area of PBA(2). Update it to reflect in the argument table. Furthermore, there is a singly-linked list in the redundant area of PBA(2), and "4" is stored. This indicates that LBA(1) is stored in PBA(4). Update this as well to reflect in the argument table (Figure 7-B-2). Thus, step #17 is completed. Proceed to step #18.

[0099] In step #18, when looking at PBA(3) which is the next of PBA(2) in the check table from Figure 7-C-3, it is unchecked. Since 1 is added to j = 2, j becomes 3. Proceed to step #19.

[0100] In step #19, it is determined whether the information of the argument table of LBA(0) can be obtained again. Since the information about LBA(0) can be obtained from Figure 7-B-2, proceed to step #20.

[0101] In step #20, i changes from 0 to 1, and proceed to step #21. In step #21, since the number of blocks to be read this time n = 3, and i < n, proceed to step #12.

[0102] In step #12, it is determined whether there is information in the argument table of LBA(1). Since there is information in the argument table of LBA(1) from Figure 7-B-2, proceed to step #20.

[0103] In step #20, i changes from 1 to 2, and proceed to step #21. In step #21, since the number of blocks to be read this time n = 3, and i < n, proceed to step #12.

[0104] In step #12, it is determined whether there is information in the argument table of LBA(2). Since there is no information in the argument table of LBA(2) from Figure 7-B-2, proceed to step #13.

[0105] Since i = 2 in step #13, it proceeds to step #22. Since i = 2 in step #22, it checks the redundant area of LBA(1). Looking at the LBA(1) in the argument table from Figure 7-A, since the corresponding PBA(4) and the singly-linked list are stored, it proceeds to step #23.

[0106] In step #23, since the PBA(4) corresponding to LBA(1) is stored, it marks the PBA(4) in the check table as checked (Figure 7-C-4). It proceeds to step #24.

[0107] In step #24, there is also a singly-linked list in the redundant area of LBA(1), and "8" is stored. This indicates that LBA(2), which is the next of LBA(1), is stored in PBA(8). This is also updated to be reflected in the argument table (Figure 7-B-3). Thus, step #24 is completed. It proceeds to step #20.

[0108] In step #20, i changes from 2 to 3, and it proceeds to step #21. In step #21, since the number of blocks n to be read this time is 3, i < n does not hold, so the flow of creating the argument table is completed.

[0109] Through the above flow, using the information of the LBA stored in the redundant area of the PBA and the singly-linked list, an argument table of LBA(0) to LBA(2) as described in Figure 7-B-3 is completed.

[0110] In the embodiment of the present application, by making the PBA monotonically increase with respect to the LBA during writing, the singly-linked list also becomes monotonically increasing. Although it is monotonically increasing in this embodiment, it is also okay to be monotonically decreasing.

[0111] By doing as described above, in the invention of the present application, when the entire NAND is N blocks and the data to be read is n blocks, the expected value of the number of read times of the redundant area until the creation of the argument table is N / 2 times in the method described in the prior art document. Also, the expected value of the method that only reads as much as desired is (N + 1) * n / (n + 1). On the other hand, the expected value of the present invention is given by the following formula. (Formula) TIFF0007704408000001.tif19131

[0112] When taking the expected value on the vertical axis and n on the horizontal axis, it becomes as shown in FIG. 8. From the graph, when the number of n blocks of data to be read is less than a certain number in the present application, the expected value of the number of read times is the least. Therefore, the problem of shortening the creation time of the argument table, which is the preparation time when reading from the NAND of the present invention, is solved by storing the LBA corresponding to the redundant area of the PBA and the singly-linked list, and reducing the number of read times to the redundant area that takes time by using two pieces of information, the LBA and the singly-linked list, when creating the argument table.

[0113] Also, as described above, since the read access is started as soon as the argument table is partially completed, the present invention, in which the expected value of the number of read times of the redundant area until the argument table is partially completed is the least, realizes high speed.

[0114] Particularly, in the case of a NAND in which solid adjustment values and user settings are recorded like in a digital camera and reading is always required at startup, but writing is limited to specific conditions such as adjustment processes at the time of factory shipment or when the power is turned off, and the main use of the NAND is mainly reading, the present invention is particularly effective in solving the problem.

[0115] Also, even during the creation of the argument table in the present invention, as described in the above-described embodiment, as soon as the argument table for the logical addresses (LBAs) “0 to 2” that store the user setting values is completed, read access can be made possible, thereby enabling high speed.

[0116] Furthermore, as another example, the LBAs to be read as described in A of FIG. 9 are classified. Assume that LBA(0) to LBA(2) are Data1, and LBA(3) to LBA(4) are Data2, and a physical object table for Data1 is created and read.

[0117] In the embodiments described so far, the physical address corresponding to the logical address to be read is determined based on the singly-linked list stored in the redundant area. On the other hand, in another embodiment, the physical address corresponding to the logical address to be read is further determined based on the class and the singly-linked list using classification.

[0118] Also, the classification of LBAs such as Date1 and Date2 is controlled by the CPU10. Specifically, classification corresponding to the logical address may be performed and stored at the time of data writing.

[0119] Furthermore, step #17 is changed as follows.

[0120] In step #17, the LBA(X) stored in the redundant area of PBA(j) is read, and the physical object table is updated. At this time, it is determined whether the read LBA(X) corresponds to the physical object table to be created this time. If it does not correspond, proceed to the next step. If it corresponds, it is confirmed whether the information of the singly-linked list is stored in the redundant area. If it is stored, the PBA in which the next LBA of the previously read LBA(X) (hereinafter referred to as LBA(X + 1)) is stored can be known. Therefore, the physical object table is also updated here, and proceed to the next step.

[0121] By making the changes as described above, taking the modified Step #17 as a specific example, since LBA(3) is stored in the redundant area of PBA(0), and the target LBAs to be read this time, LBA(0) to LBA(2), are Data1, there is no need to know the PBA in which LBA(4) is stored, so there is no need to read the singly-linked list. From the above, by changing the steps, compared with the above-described embodiment, the reading of the singly-linked list in the redundant area of PBA(0) and the redundant area of PBA(3) described in the singly-linked list is reduced, so that the time can be shortened accordingly. Also, the object table becomes Figure 9-B-1, and the check table becomes Figure 9-C-1.

[0122] The memory control device described so far can be implemented in portable electronic devices such as personal computers, smartphones, and digital cameras.

Explanation of Signs

[0123] 1 Memory control device 10 CPU 11 Flash EEPROM 12 RAM 13 Object table 101 Access execution unit 102 Writing unit 103 Object table creation unit

Claims

1. A page having a data storage area and a redundant area, A physical block having a plurality of the pages, In a memory control device that controls a non-volatile memory having the physical block, For each physical block, in the redundant area of the page in the physical block, storage means for storing the logical address assigned to the physical block and the physical address of the physical block to which the next logical address of the logical address is assigned; The storage means stores data by type, prepares the physical blocks more than necessary for the stored data, sorts them in ascending order of the physical addresses, and then sequentially stores the logical addresses of the physical blocks in ascending or descending order. At the time of initializing the non-volatile memory, the logical address and the physical address are acquired from the redundant area of the page for a plurality of the physical blocks, and according to each acquired logical address and physical address, a table creation means for creating an address conversion table showing the relationship between the physical address of each of the plurality of physical blocks and the logical address assigned to each of the plurality of physical blocks; Access means for converting the logical address of the access target into a physical address using the address conversion table created by the table creation means and accessing the physical block specified by the converted physical address A memory control device characterized by comprising.

2. The address conversion table created by the table creation means is partially completed by tracing the physical address, and the completed part can be read-accessed. The memory control device according to claim 1.

3. The memory control device according to claim 1 or 2, wherein when the table creation means creates the address conversion table, only the physical address corresponding to a specific logical address in the redundant area is traced.

4. A portable electronic device characterized by comprising the memory control device according to any one of claims 1 to 3.

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