Shift register unit, gate driving circuit, display device, and driving method

Abstract

To provide a shift register unit satisfying severe requirements with respect to the production of a high-resolution OLED display panel with a narrow frame and a driving method for the shift register unit.SOLUTION: A shift register unit (10) includes a first sub-unit (100) and a second sub-unit (200). The first sub-unit includes a first input circuit (110) connected to a first output circuit (120) through a first node (Q1), the voltage level of the first node is controlled in response to a first input signal (STU1), and the first output circuit is configured so as to output a shift register signal (CR) and a first output signal (OUT1) in response to the voltage level of the first node. The second sub-unit includes a second input circuit (210) connected to a second output circuit (220) through a second node (Q2), the voltage level of the second node is controlled in response to the first input signal, and the second output circuit outputs a second output signal (OUT2) according to the voltage level of the second node.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - reference to related applications This application claims priority to Chinese Patent Application No. 201810966800.7, filed with the China National Intellectual Property Administration on August 23, 2018, the entire content of which is incorporated herein by reference.

[0002] The present invention relates to display technology, and more specifically, to a shift register unit, a gate driving circuit, a display device, and a driving method.

Background Art

[0003] In a display panel, especially in the case of an organic light - emitting diode (OLED) - based display panel, the driving circuit is usually integrated in a gate integrated circuit (gate IC). When designing the chip of the gate IC, the cost of the chip mainly depends on the area of the chip. The existing OLED gate driving circuit includes three sub - circuits, namely, a sensing unit circuit, a scanning unit circuit, and a connection circuit or gate circuit for outputting signals from both the sensing unit circuit and the scanning unit circuit, resulting in a very complex circuit structure of the gate IC, which is difficult to meet the increasingly stringent requirements for the production of narrow - bezel high - resolution OLED display panels. Therefore, there is a need for an improvement in the circuit design of the shift register unit forming the gate driving circuit of the display panel.

Summary of the Invention

[0004] On one aspect, the present disclosure provides a shift register unit. The shift register unit includes a first sub - circuit including a first input circuit connected to a first output circuit via a first node. It includes a unit. The first input circuit controls the voltage level of the first node in response to a first input signal. It is configured to control a bell. The first output circuit is configured to output a shift register signal and a first output signal in response to the voltage level of the first node. The shift register circuit further includes a second subunit including a second input circuit connected to a second output circuit via a second node. The second input circuit is configured to control the voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. Optionally, the shift register unit further includes a blank input subunit connected to the first node and the second node and configured to receive a selection control signal and control the voltage levels of the first node and the second node respectively. Optionally, the blank input subunit includes a common input circuit, a first transmission circuit, and a second transmission circuit. The common input circuit is configured to control the voltage level of a third node and the voltage level of a fourth node in response to the selection control signal. The first transmission circuit is connected to the first node and the fourth node and is configured to control the voltage level of the first node in response to the voltage level of the fourth node or a first transmission signal. The second transmission circuit is connected to the second node and the fourth node and is configured to control the voltage level of the second node in response to the voltage level of the fourth node and a second transmission signal.

[0005]

[0006]

[0007] ​​​​​​​​​​​​Optionally, the common input circuit further includes a selection control circuit and a third input circuit. The selection control circuit is configured to control the voltage level of the third node using the second input signal in response to the selection control signal, and to maintain the voltage level of the third node. The third input circuit is configured to control the voltage level of the fourth node in response to the voltage level of the third node. Optionally, the selection control circuit includes a first transistor and a first capacitor. The first transistor has a gate terminal configured to receive the selection control signal, a first terminal configured to receive the second input signal, and a second terminal connected to the third node. The first capacitor has a first terminal connected to the third node.

[0008] Optionally, the third input circuit includes a second transistor having a gate connected to the third node, a first terminal configured to receive a first clock signal, and a second terminal connected to the fourth node. Optionally, the first transmission circuit includes a third transistor, and the second transmission circuit includes a fourth transistor. The third transistor has a gate terminal connected to the fourth node, a first terminal configured to receive a first voltage, and a second terminal connected to the first node. The fourth transistor has a gate terminal connected to the fourth node, a first terminal configured to receive the first voltage, and a second terminal connected to the second node.

[0009]

[0010]

[0011] ​​​​​​​​​​​​Optionally, the first input circuit includes a fifth transistor, and the first output circuit includes a sixth transistor, a seventh transistor, and a second capacitor. The fifth trans istor has a gate terminal configured to receive the first input signal, a first terminal con figured to receive a first voltage, and a second terminal connected to the first node. The sixth transistor has a gate terminal connected to the first node, a first terminal config ured to receive a second clock signal as a shift register signal, and a second terminal configured to output the shift register signal. The seventh transistor has a gate termi nal connected to the first node, a first terminal configured to receive a third clock sig nal as the first output signal, and a second terminal configured to output the first out put signal. The second capacitor has a first terminal connected to the first node and a second terminal connected to the second terminal of the seventh transistor.

[0012] Optionally, the second input circuit includes an eighth transistor, and the second out put circuit includes a ninth transistor and a third capacitor. The eighth transistor has a gate terminal configured to receive the first input signal, a first terminal configured to receive the first voltage, and a second terminal connected to the second node. The ninth transistor has a gate terminal connected to the second node, a first terminal con figured to receive a fourth clock signal as the second output signal, and a second termi nal configured to output the second output signal. The third capacitor has a first termi nal connected to the second node and a second terminal connected to the second terminal

[0013] Optionally, the first subunit comprises a first control circuit, a first reset circuit, and a second The first control further includes a reset circuit, a shift register output terminal, and a first output terminal. The circuitry adjusts a voltage level at a fifth node in response to a voltage level at the first node and a second voltage. The first reset circuit is configured to control a voltage level at the fifth node. responsive to a voltage at the first node, the shift register output terminal, and the first output terminal. The second reset circuit is configured to reset the voltage level at the sixth node. at the first node, the shift register output terminal and the first output terminal in response to a level The voltage level of the input terminal is configured to be reset.

[0014] Optionally, the second subunit comprises a second control circuit, a third reset circuit, and a fourth The second output terminal outputs the second output signal. The second control circuit is configured to output a voltage level at the second node and The third link is configured to control a voltage level of the sixth node in response to a third voltage. A set circuit is configured to set the second node and the second output in response to a voltage level of the sixth node. The fourth reset circuit is configured to reset the voltage level at the terminal. 5. Responsive to a voltage level at the node, the voltage level at the second node and the second output terminal is controlled. It is configured to reset.

[0015] Optionally, the blank input subunit is connected to the fourth node, the fifth node and and the sixth node, and is connected to a voltage level at the fifth node or the sixth node. A common reset circuit configured to reset the voltage level of the fourth node in response is further included.

[0016] Optionally, the common reset circuit includes a tenth transistor and an eleventh transistor . The tenth transistor has a gate terminal connected to the fifth node, a first terminal connected to the fourth node, and a second terminal configured to receive a fourth voltage. The eleventh transistor has a gate terminal connected to the sixth node, a first terminal connected to the fourth node, and a second terminal configured to receive the fourth voltage.

[0017] Optionally, the first control circuit includes a twelfth transistor and a thirteenth transistor. The first reset circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor. The second reset circuit includes a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor. The twelfth transistor has a gate terminal and a first terminal both configured to receive the second voltage, and a second terminal connected to the fifth node. The thirteenth transistor has a gate terminal connected to the first node, a first terminal connected to the fifth node, and a second terminal configured to receive the fourth voltage. The fourteenth transistor has a gate terminal connected to the fifth node, a first terminal connected to the first node, and a second terminal configured to receive the fourth voltage. The fifteenth transistor has a gate terminal connected to the fifth node, a first terminal connected to the shift register output terminal, and a second terminal configured to receive the fourth voltage. It has a second terminal configured as a sea urchin. The 16th transistor is connected to the 5th node A gate terminal connected thereto, a first terminal connected to the first output terminal, and a fifth voltage are received It has a second terminal configured as such. The 17th transistor is connected to the 6th node A gate terminal connected thereto, a first terminal connected to the first node, and the fourth voltage are received It has a second terminal configured to receive. The 18th transistor is connected to the 6th node A gate terminal connected thereto, a first terminal connected to the shift register output terminal, and the fourth It has a second terminal configured to receive voltage. The 19th transistor is the A gate terminal connected to the 6th node, a first terminal connected to the first output terminal, and the It has a second terminal configured to receive the fifth voltage.

[0018] Optionally, the second control circuit includes a 20th transistor and a 21st transistor The third reset circuit includes a 22nd transistor and a 23rd transistor, The fourth reset circuit includes a 24th transistor and a 25th transistor. The The 20th transistors both have a gate terminal and a first terminal configured to receive the third voltage, And a second terminal connected to the 6th node. The 21st transistor Has a gate terminal connected to the second node, a first terminal connected to the 6th node, And a second terminal configured to receive the fourth voltage. The 22nd transistor Has a gate terminal connected to the 6th node, a first terminal connected to the second node, and A second terminal configured to receive the fourth voltage as described above. The 23rd transistor , a gate terminal connected to the sixth node, and a first terminal connected to the second output terminal , and a second terminal configured to receive a fifth voltage. The twenty-fourth transistor , has a gate terminal connected to the fifth node, a first terminal connected to the second node, and a second terminal configured to receive the fourth voltage. The twenty-fifth transistor has a gate terminal connected to the fifth node, a first terminal connected to the second output terminal and a second terminal configured to receive the fifth voltage.

[0019] Optionally, the first sub-unit further includes a third output terminal configured to output a third output signal. The second sub-unit further includes a fourth output terminal configured to output a fourth output signal. The first reset circuit and the second reset circuit are configured to reset the voltage level at the third output terminal. The third reset circuit and the fourth reset circuit are configured to reset the voltage level at the fourth output terminal.

[0020] Optionally, the first sub-unit further includes a third control circuit and a fourth control circuit. The third control circuit is configured to control the voltage level of the fifth node in response to the first clock signal, and the fourth control circuit is configured to control the voltage level of the fifth node in response to the first input signal. The second sub-unit further includes a fifth control circuit and a sixth control circuit. The fifth control circuit is configured to control the voltage level of the sixth node in response to the first clock signal, and the sixth control circuit is configured to control the voltage level of the sixth node in response to the first input signal. ​

[0021] Optionally, the first sub-unit includes a fifth reset circuit and a sixth reset circuit further. The fifth reset circuit is configured to reset the voltage level at the first node in response to a display reset signal, and the sixth reset circuit is configured to reset the voltage level at the first node in response to a full-scale reset signal. The second sub-unit further includes a seventh reset circuit and an eighth reset circuit. The seventh reset circuit is configured to reset the voltage level at the second node in response to the display reset signal, and the eighth reset circuit is configured to reset the voltage level at the second node in response to the full-scale reset signal.

[0022] Optionally, the shift register unit further includes a common leakage prevention circuit, a first leakage prevention circuit, and a second leakage prevention circuit. The common leakage prevention circuit is connected to the first node and the seventh node, and is configured to control the voltage level at the seventh node in response to the voltage level at the first node. The first leakage prevention circuit is connected to the seventh node, the first reset circuit, the second reset circuit, the fifth reset circuit, and the sixth reset circuit, and is configured to prevent leakage from occurring at the first node in response to the voltage level at the seventh node. The second leakage prevention circuit is connected to the seventh node, the third reset circuit, the fourth reset circuit, the seventh reset circuit, and the eighth reset circuit, and is configured to prevent leakage from occurring at the second node in response to the voltage level at the seventh node.

[0023] ​​​​​​​​​​​​​​ In another aspect, the present disclosure provides a gate driving circuit including a plurality of shift register units cascade-connected in series. Each of the plurality of shift register units is a shift register unit described herein, and includes a first sub-unit in an odd stage and a second sub-unit in the next even stage, each of which is controlled by voltage levels of a first node and a second node. The voltage levels of the first node and the second node are respectively controlled by a first transmission circuit and a second transmission circuit both connected from a common input circuit. The first sub-unit of each shift register unit outputs a shift register signal as a first input signal to drive both the first sub-unit and the second sub-unit in the next shift register unit, or outputs it as a display reset signal to drive both the first sub-unit and the second sub-unit in the previous shift register unit. In another aspect, the present disclosure provides a display device including the gate driving circuit described herein and a plurality of sub-pixel units arranged in an array. The first output signal and the second output signal respectively output from the first output circuit and the second output circuit of each one shift register unit in the gate driving circuit are provided to the sub-pixel units in different rows of the array. In yet another aspect, the present disclosure provides a driving method for the shift register unit described herein. The method includes applying a first input signal to the first input circuit of the first sub-unit of the shift register unit and the second input circuit of the second sub-unit of the same shift register unit.

[0024] In another aspect, the present disclosure provides a display device including the gate driving circuit described herein and a plurality of sub-pixel units arranged in an array. The first output signal and the second output signal respectively output from the first output circuit and the second output circuit of each one shift register unit in the gate driving circuit are provided to the sub-pixel units in different rows of the array.

[0025] In yet another aspect, the present disclosure provides a driving method for the shift register unit described herein. The method includes applying a first input signal to the first input circuit of the first sub-unit of the shift register unit and the second input circuit of the second sub-unit of the same shift register unit. ​​​​​​​​​​​​​​ including the step of inputting an input signal. The method includes driving the first subunit to control the voltage level of the first node of the first subunit based on the first input signal and further includes the step of connecting a first output circuit to the first node. Furthermore, the method includes driving the first subunit to output a shift register signal and a first output signal in response to the voltage level of the first node by controlling the first output circuit, driving the second subunit to control the voltage level of the second node of the second subunit based on the first input signal, and connecting a second output circuit to the second node. In addition, the method includes driving the second subunit to control the second output circuit to output a second output signal in response to the voltage level of the second node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit uses a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and uses a first transmission circuit to control the voltage level of the first

[0026] node in response to the voltage level of the fourth node. The step of controlling the voltage level of the second node by driving the second subunit uses the blank input circuit further having a second transmission circuit to control the voltage level of the second node in response to the voltage level of the fourth node. level in response to the voltage level of the fourth node. Including. The step of controlling the voltage level of the second node by driving the second subunit uses the blank input circuit further having a second transmission circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Including.

[0027] ​Optionally, the step of controlling the first output circuit by driving the first sub-unit includes resetting the voltage levels at the shift register output force terminal and the first output terminal using at least a first reset circuit and a second reset circuit, and controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage at the first node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. The step of resetting the voltage levels at the shift register output force terminal and the first output terminal using at least a first reset circuit and a second reset circuit, and controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage at the first node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. resetting the voltage levels at the shift register output force terminal and the first output terminal using at least a first reset circuit and a second reset circuit, and controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage at the first node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. resetting the voltage levels at the shift register output force terminal and the first output terminal using at least a first reset circuit and a second reset circuit, and controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage at the first node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. resetting the voltage levels at the shift register output force terminal and the first output terminal using at least a first reset circuit and a second reset circuit, and controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage at the first node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. The step of driving the second sub-unit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node.

Brief Description of the Drawings

[0028] The following drawings are examples for illustrative purposes only relating to various disclosed embodiments and are not intended to limit the scope of the present invention. The following drawings are examples for illustrative purposes only relating to various disclosed embodiments and are not intended to limit the scope of the present invention.

[0029]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0051] Next, the present disclosure will be described more specifically with reference to the following embodiments. It should be noted that the following description of several embodiments is presented in this specification solely for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the exact form disclosed.

[0052] In the following detailed description, many specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to those of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures, devices, and circuits are shown in block diagram form rather than in detail to avoid obscuring the present invention. It should be noted that the attention of the reader is directed to all papers and documents that are filed with this specification and are publicly disclosed in this specification. The contents of all such papers and documents are hereby incorporated by reference into this specification.

[0053] papers and documents that are filed with this specification and are publicly disclosed in this specification. The contents of all such papers and documents are hereby incorporated by reference into this specification. papers and documents that are filed with this specification and are publicly disclosed in this specification. The contents of all such papers and documents are hereby incorporated by reference into this specification. All features disclosed herein (including any accompanying claims) are incorporated herein by reference in their entirety. All other parts of the specification, including the abstract and drawings, unless expressly stated otherwise, serve the same, equivalent or similar purpose. Accordingly, unless expressly stated otherwise, each feature disclosed may be replaced by any alternative feature. , is but one example of a generic series of equivalent or similar features.

[0054] Furthermore, the term "means" for performing a particular function or "steps" for performing a particular function may be used. Any element in a claim that does not expressly recite a "top" is In particular, the specific aspects of this specification should not be construed as meaningless or step-based clauses. The use of "steps" or "actions" in the claims is in accordance with 35 U.S.C. ... This document is not intended to enforce any provision of this Agreement.

[0055] As used in this disclosure, the words "first," "second," and similar words do not denote any particular order, quantity, or importance. Please note that the terms are not intended to denote, but are used to distinguish between different components. Similarly, "include" or "includes" or "including" or "one" or "an and words such as "coupled" or "connected" are limited to physical or mechanical connections. "Top," "bottom," "left," "right," "top," "bottom ... " are used only to indicate the relative position relationship, and if the absolute position of the object changes, The relative positional relationship may change depending on the

[0056] Generally, the words "a," "an," "said," and "the," as well as the term "including" and "including" is intended to include only the steps and elements specified, The element does not form an exclusive list, and the method or apparatus may also include other steps or elements. It is possible.

[0057] When compensating the sub-pixel unit of the OLED display panel, in addition to setting the pixel compensation circuit for internal compensation in the sub-pixel unit, an external compensation may also be performed by setting a sensing transistor. When the external compensation is performed, the gate driving circuit composed of the shift register unit needs to supply the driving signals of the scanning transistor and the sensing transistor in the sub-pixel unit of the display panel respectively. For example, during one cycle of the display period for displaying one frame of an image, the scanning driving signal of the scanning transistor is provided, and during the blank period of the cycle, the sensing driving signal of the sensing transistor is provided. In the external compensation method, the sensing driving signal output by the gate driving circuit is scanned sequentially row by row. For example, during the blank period of the cycle for displaying the first frame, the sensing driving signal is output to the sub-pixel unit of the first row of the display panel, and during the blank period of the cycle for displaying the second frame, another sensing driving signal is output to the sub-pixel unit of the second row of the display panel, and so on. Therefore, by outputting the sensing driving signal of the corresponding one row of sub-pixel units for each frame, the sequential compensation for each row of the display panel is completed. Therefore, the present disclosure particularly provides a shift register unit configured to form a gate driving circuit that is connected in series in cascade and can output a scanning driving signal during one cycle of the display period for displaying one frame, and can output a sensing driving signal during the blank period of the cycle. The gate driving circuit formed by the shift register unit needs to supply the driving signals of the scanning transistor and the sensing transistor in the sub-pixel unit of the display panel respectively. For example, during one cycle of the display period for displaying one frame of an image, the scanning driving signal of the scanning transistor is provided, and during the blank period of the cycle, the sensing driving signal of the sensing transistor is provided. For example, during one cycle of the display period for displaying one frame of an image, the scanning driving signal of the scanning transistor is provided, and during the blank period of the cycle, the sensing driving signal of the sensing transistor is provided. The scanning driving signal of the scanning transistor is provided, and during the blank period of the cycle, the sensing driving signal of the sensing transistor is provided. During the blank period of the cycle, the sensing driving signal of the sensing transistor is provided.

[0058] In the external compensation method, the sensing driving signal output by the gate driving circuit is scanned sequentially row by row. For example, during the blank period of the cycle for displaying the first frame, the sensing driving signal is output to the sub-pixel unit of the first row of the display panel. During the blank period of the cycle for displaying the first frame, the sensing driving signal is output to the sub-pixel unit of the first row of the display panel. During the blank period of the cycle for displaying the second frame, another sensing driving signal is output to the sub-pixel unit of the second row of the display panel. During the blank period of the cycle for displaying the second frame, another sensing driving signal is output to the sub-pixel unit of the second row of the display panel. By outputting the sensing driving signal of the corresponding one row of sub-pixel units for each frame, the sequential compensation for each row of the display panel is completed. By outputting the sensing driving signal of the corresponding one row of sub-pixel units for each frame, the sequential compensation for each row of the display panel is completed.

[0059] Therefore, the present disclosure particularly provides a shift register unit configured to form a gate driving circuit that is connected in series in cascade and can output a scanning driving signal during one cycle of the display period for displaying one frame, and can output a sensing driving signal during the blank period of the cycle. During one cycle of the display period for displaying one frame, the scanning driving signal is output, and during the blank period of the cycle, the sensing driving signal can be output. The shift register unit is configured to form a gate driving circuit that can output a scanning driving signal during one cycle of the display period for displaying one frame, and can output a sensing driving signal during the blank period of the cycle. To provide a shift register unit, a display device, and a driving method, which substantially avoid one or more problems caused by the limitations and weaknesses of related technologies. In one aspect, the present disclosure provides a shift register unit suitable for use in a display device with a reduced frame size and an increased pixels per inch (PPI), enabling random compensation to avoid non-uniformity of luminance during a display operation. For the purpose of explanation, the definitions of "one frame", "per frame", or "a specific frame" include a sequentially executed display period and a blank period. For example, a gate driving circuit outputs a gate driving signal during the foregoing display period, and the gate driving signal is used to drive a display panel to complete a display of one frame by scanning from the first row to the last row. During the blank period, the gate driving circuit outputs a sensing driving signal, and the sensing driving signal is used to drive sense transistors in a sub-pixel unit of one row in the display panel to complete external compensation of the sub-pixel unit of the row.

[0060]

[0061] FIG. 1 is a block diagram of a shift register unit according to an embodiment of the present disclosure. Referring to FIG. 1, the shift register unit 10 includes a first sub-unit 100 and a second sub-unit 200. A plurality of such shift register units 10 can be cascaded to form a gate driving circuit according to some embodiments of the present disclosure. The gate driving circuit is applied to a display device and can provide a scanning signal to display an image of one frame in the display device during a display operation.

[0062] ​​​​​​​​​​​​​​​The first sub-unit 100 includes a first input circuit 110 and a first output circuit 120 that are connected to each other via a first node Q1. The first input circuit 110 is configured to control the voltage level at the first node Q1 in response to the received first input signal S TU1. For example, the first input circuit 110 can charge the first node Q1. Optionally, the first input circuit 11 0 is configured to receive the first input signal STU1 and the first voltage VDD. Optionally , the first input circuit 110 becomes conductive in response to the first input signal STU1, and as a result , it can charge the first node Q1 using the first voltage VDD. Optionally, the voltage level at the first node Q1 is charged to the level of the first voltage VDD with an error of at least within 10%. Optionally , the first voltage VDD is set to be a high voltage supplied from a power source .

[0063] The first output circuit 120 is configured to output a shift register signal CR and a first output signal OUT1 in response to the voltage level at the first node Q1. For example, the first output circuit 12 0 can be configured to receive a second clock signal CLKB and a third clock signal CLKC. The first output circuit 120 becomes conductive in response to the voltage level at the first node Q1, and as a result , it can output the second clock signal CLKB as the shift register signal CR and output the third clock signal CLKC as the first output signal OUT1.

[0064] Optionally, during one frame of image or a single cycle display period for displaying one frame , the shift register signal CR output from the first output circuit 120 is provided as the first input signal STU1 to other shift register units (in the gate driving circuit).​​ It can complete the shift scanning for each row during the operation. The first output signal OUT1 output from the first output circuit 120 can drive the sub-pixel units of one row of the display panel to execute the display scanning. Optionally, during the blank period of one frame, the first output signal OUT1 output from the first output circuit 120 can drive the sensing transistors in the sub-pixel units of one row of the display panel and can be used to complete the external compensation for the sub-pixel units of one row. The first output signal OUT1 output from the first output circuit 120 can drive the sub-pixel units of one row of the display panel to execute the display scanning. Optionally, during the blank period of one frame, the first output signal OUT1 output from the first output circuit 120 can drive the sensing transistors in the sub-pixel units of one row of the display panel and can be used to complete the external compensation for the sub-pixel units of one row. It can complete the shift scanning for each row during the operation. The first output signal OUT1 output from the first output circuit 120 can drive the sub-pixel units of one row of the display panel to execute the display scanning. Optionally, during the blank period of one frame, the first output signal OUT1 output from the first output circuit 120 can drive the sensing transistors in the sub-pixel units of one row of the display panel and can be used to complete the external compensation for the sub-pixel units of one row. The first output signal OUT1 output from the first output circuit 120 can drive the sub-pixel units of one row of the display panel to execute the display scanning. Optionally, during the blank period of one frame, the first output signal OUT1 output from the first output circuit 120 can drive the sensing transistors in the sub-pixel units of one row of the display panel and can be used to complete the external compensation for the sub-pixel units of one row. The first output signal OUT1 output from the first output circuit 120 can drive the sub-pixel units of one row of the display panel to execute the display scanning. Optionally, during the blank period of one frame, the first output signal OUT1 output from the first output circuit 120 can drive the sensing transistors in the sub-pixel units of one row of the display panel and can be used to complete the external compensation for the sub-pixel units of one row. It can complete the shift scanning for each row during the operation. The first output signal OUT1 output from the first output circuit 120 can drive the sub-pixel units of one row of the display panel to execute the display scanning. Optionally, during the blank period of one frame, the first output signal OUT1 output from the first output circuit 120 can drive the sensing transistors in the sub-pixel units of one row of the display panel and can be used to complete the external compensation for the sub-pixel units of one row.

[0065] Optionally, during the display period of the frame, the shift register signal output from the first output circuit 120 can have the same or different waveforms compared with the first output signal OUT1 output from the same first output circuit 120. Optionally, during the display period of the frame, the shift register signal output from the first output circuit 120 can have the same or different waveforms compared with the first output signal OUT1 output from the same first output circuit 120. Optionally, during the display period of the frame, the shift register signal output from the first output circuit 120 can have the same or different waveforms compared with the first output signal OUT1 output from the same first output circuit 120.

[0066] Referring to FIG. 1, the second sub-unit 200 includes a second input circuit 210 and a second output circuit 220 that are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1. As a result, the first voltage VDD can be used to charge the second node Q2. Referring to FIG. 1, the second sub-unit 200 includes a second input circuit 210 and a second output circuit 220 that are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1. As a result, the first voltage VDD can be used to charge the second node Q2. Referring to FIG. 1, the second sub-unit 200 includes a second input circuit 210 and a second output circuit 220 that are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1. As a result, the first voltage VDD can be used to charge the second node Q2. Referring to FIG. 1, the second sub-unit 200 includes a second input circuit 210 and a second output circuit 220 that are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1. As a result, the first voltage VDD can be used to charge the second node Q2. Referring to FIG. 1, the second sub-unit 200 includes a second input circuit 210 and a second output circuit 220 that are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1. As a result, the first voltage VDD can be used to charge the second node Q2. Referring to FIG. 1, the second sub-unit 200 includes a second input circuit 210 and a second output circuit 220 that are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1. As a result, the first voltage VDD can be used to charge the second node Q2. Referring to FIG. 1, the second sub-unit 200 includes a second input circuit 210 and a second output circuit 220 that are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1. As a result, the first voltage VDD can be used to charge the second node Q2.

[0067] Optionally, the second output circuit 220 is configured to output a second output signal OUT2 in response to the voltage level at the second node Q2. For example, the second output circuit 220 is the fourth clock. Optionally, the second output circuit 220 is configured to output a second output signal OUT2 in response to the voltage level at the second node Q2. For example, the second output circuit 220 is the fourth clock. It is configured to receive a lock signal CLKD. And the second output circuit 220 is turned on by the voltage level at the second node Q2, and as a result, the fourth clock signal CLKD can be output as the second output signal OUT2.

[0068] During the display period of one frame, the second output circuit 220 outputs the second output signal OUT2 to drive the sub-pixel units of one row of the display panel to perform display scanning. During the blank period of one frame the second output circuit 220 outputs the second output signal OUT2 to drive the sense transistors in the sub-pixel units of one row of the display panel to complete external compensation for the sub-pixel units of one row.

[0069] When a plurality of the shift register units 10 are connected in series in cascade to form a gate drive circuit, some of the shift register units 10 are connected to the clock signal line and can receive the first input signal STU1 provided by the clock signal line. Optionally, some of the shift register units 10 can receive the shift register signal CR output from other stages of the shift register units 10 in the same gate drive circuit as the first input signal STU1 and believe it. Optionally, controlling the voltage level of a node (for example, the first node Q1, the second node Q2, etc.) includes charging the node to increase the voltage level of the node or discharging the node to lower the voltage level of the node. Optionally, a capacitor may be electrically connected to the node, and charging the node means charging the capacitor electrically connected to the node. Similarly, discharging the node means discharging the node connected to the node.

[0070] Optionally, controlling the voltage level of a node (e.g., the first node Q1, the second node Q2, etc.) includes charging the node to raise the voltage level of the node or discharging the node to lower the voltage level of the node. Optionally, a capacitor may be electrically connected to the node, and charging the node means charging the capacitor electrically connected to the node. Similarly, discharging the node means discharging the node connected to the node. connected to the node. Charging the node means charging the capacitor electrically connected to the node. Similarly, discharging the node means discharging the node connected to the node. means discharging a capacitor electrically connected thereto. The capacitor can maintain the high level or low level of the node .

[0071] The shift register unit 10 of the present disclosure can simultaneously charge a plurality of sub-units (such as the first sub-unit 10 0 and the second sub-unit 200, etc.). FIG. 1 shows only two sub-units in the shift register unit. Optionally, the shift register unit may include three, four or more sub-units in a similar circuit structure according to the actual setup under different applications . At one time, only one of the plurality of sub-units (for example, the first sub-unit 100) needs to output a shift register signal , and the other sub-units (for example, the second sub-unit 200 ) of the plurality of sub-units do not need to output a shift register signal. Therefore, the number of clock signal lines and transistors in the gate driving circuit can be saved, the size of the bezel of the display device adopting the shift register unit 10 can be reduced, and thereby the PPI of the display device can be improved .

[0072] FIG. 2 is a block diagram of a shift register unit according to another embodiment of the present disclosure. Referring to FIG 2, the shift register unit 10A includes a blank input sub-unit 300 , the blank input sub-unit 300 is connected to the first sub-unit 100 via the first node Q1, connected to the second sub-unit 200 via the second node Q2, and configured to receive a selection control signal OE . The blank input sub-unit 300 is configured to control the voltage levels of the first node Q1 and the second node Q2 in response to the selection control signal OE ​​​is configured. For example, the blank input subunit 300 is configured to charge the first node Q1 and the second node Q2 respectively.

[0073] Optionally, during the display period of one frame, the blank input subunit 300 can charge the first node Q1 and can also charge the second node Q2. Then, the first output circuit 120 can output the first output signal OUT1 in response to the voltage level charged on the first node Q1 , or the second output circuit 220 can output the second output signal OUT2 in response to the voltage level charged on the second node Q2. The first output signal OUT1 or the second output signal OUT2 can drive the sense transistors in the sub-pixel units of one row of the display panel to complete external compensation for the sub-pixel units of that row.

[0074] FIG. 3 is a block diagram of a blank input subunit of a shift register unit according to an embodiment of the present disclosure. In one embodiment, referring to FIG. 3, the blank input subunit 300 includes a common input circuit 310 connected to a first transmission circuit 320 and a second transmission circuit 330 via a fourth node N. The common input circuit 310 further includes a selection control circuit 311 connected to a third input circuit 312 via a third node H. The common input circuit 310 is configured to control the voltage level of the third node H in response to a selection control signal OE and further control the voltage level of the fourth node N. The selection control circuit 311 is configured to charge the third node H using the second input signal STU2 in response to the selection control signal OE and maintain the voltage level at the third node H. For example, during the display period of a frame, the selection control circuit 31 1 is turned on by the selection control signal OE, and as a result, the third node H can be charged using the second input signal STU2. The voltage level at the third node H (e.g., high voltage level) can be maintained throughout the display period until the blank period after the display period of the same frame. When a plurality of shift register units 10A are cascade-connected in multiple stages in series to form a gate driving circuit, one stage of the shift register unit 10A can receive the shift register signal CR output from another stage of the shift register unit 10A as the second input signal STU2. For example, when one stage of the shift register unit 10A is selected to output a driving signal during the blank period of one frame, preferably, the same timing waveform is provided to both the selection control signal OE and the second input signal STU2, and the selection control circuit 311 in the shift register unit 10A of that stage is turned on so that the above corresponding charging operation can be performed. Furthermore, the third input circuit 312 is configured to control the voltage level at the fourth node N in response to the voltage level charged at the third node H. Optionally, the third input circuit 312 is configured to receive the first clock signal CLKA. When the third input circuit 312 is in a conductive state controlled by the voltage level at the third node H, the first clock signal CLKA can be passed to the fourth node N to control the voltage level of the fourth node N. For example, during the blank period of one frame, when a high voltage level is provided to the first clock signal CLKA, the third input circuit 312 passes the high voltage level to the fourth node N to make the fourth node N at a high voltage level.

[0075] When a plurality of shift register units 10A are cascade-connected in multiple stages in series to form a gate driving circuit, one stage of the shift register unit 10A can receive the shift register signal CR output from another stage of the shift register unit 10A as the second input signal STU2. For example, when one stage of the shift register unit 10A is selected to output a driving signal during the blank period of one frame, preferably, the same timing waveform is provided to both the selection control signal OE and the second input signal STU2, and the selection control circuit 311 in the shift register unit 10A of that stage is turned on so that the above corresponding charging operation can be performed. Furthermore, the third input circuit 312 is configured to control the voltage level at the fourth node N in response to the voltage level charged at the third node H. Optionally, the third input circuit 312 is configured to receive the first clock signal CLKA. When the third input circuit 312 is in a conductive state controlled by the voltage level at the third node H, the first clock signal CLKA can be passed to the fourth node N to control the voltage level of the fourth node N. For example, during the blank period of one frame, when a high voltage level is provided to the first clock signal CLKA, the third input circuit 312 passes the high voltage level to the fourth node N to make the fourth node N at a high voltage level. When a plurality of shift register units 10A are cascade-connected in multiple stages in series to form a gate driving circuit, one stage of the shift register unit 10A can receive the shift register signal CR output from another stage of the shift register unit 10A as the second input signal STU2. For example, when one stage of the shift register unit 10A is selected to output a driving signal during the blank period of one frame, preferably, the same timing waveform is provided to both the selection control signal OE and the second input signal STU2, and the selection control circuit 311 in the shift register unit 10A of that stage is turned on so that the above corresponding charging operation can be performed.

[0076] Furthermore, the third input circuit 312 is configured to control the voltage level at the fourth node N in response to the voltage level charged at the third node H. Optionally, the third input circuit 312 is configured to receive the first clock signal CLKA. When the third input circuit 312 is in a conductive state controlled by the voltage level at the third node H, the first clock signal CLKA can be passed to the fourth node N to control the voltage level of the fourth node N. For example, during the blank period of one frame, when a high voltage level is provided to the first clock signal CLKA, the third input circuit 312 passes the high voltage level to the fourth node N to make the fourth node N at a high voltage level. When a plurality of shift register units 10A are cascade-connected in multiple stages in series to form a gate driving circuit, one stage of the shift register unit 10A can receive the shift register signal CR output from another stage of the shift register unit 10A as the second input signal STU2. For example, when one stage of the shift register unit 10A is selected to output a driving signal during the blank period of one frame, preferably, the same timing waveform is provided to both the selection control signal OE and the second input signal STU2, and the selection control circuit 311 in the shift register unit 10A of that stage is turned on so that the above corresponding charging operation can be performed. Furthermore, the third input circuit 312 is configured to control the voltage level at the fourth node N in response to the voltage level charged at the third node H. Optionally, the third input circuit 312 is configured to receive the first clock signal CLKA.

[0077] Referring to FIG. 3, the first transmission circuit 320 is connected to the first node Q1 and the fourth node N, and is configured to control the voltage level at the first node Q1 in response to the voltage level at the fourth node N or the first transmission signal TS1 (not shown) received by the first transmission circuit 320. In some embodiments, the first transmission circuit 320 can receive a first voltage VDD at a high voltage level. When the first transmission circuit 320 is turned on by the voltage level at the fourth node N, the high voltage level of the first voltage VDD can be used to charge the first node Q1. Optionally, the voltage level at the first node Q1 is charged to the level of the first voltage VDD with an error of at most 10%. In some other embodiments, the first transmission circuit 320 is turned on by the first transmission signal TS1 (not shown), thereby establishing an electrical connection between the fourth node N and the first node Q1, and as a result, the first node Q1 can be charged by the third input circuit 312. Furthermore, the second transmission circuit 330 is connected to the second node Q2 and the fourth node N, and is configured to control the voltage level at the second node Q2 in response to the voltage level at the fourth node N or the second transmission signal TS2 (not shown) received by the second transmission circuit 330. In some embodiments, the second transmission circuit 330 can receive a first voltage VDD at a high voltage level. When the second transmission circuit 330 is turned on by the voltage level at the fourth node N, the high voltage level of the first voltage VDD can be used to charge the second node Q2. The voltage level at the second node Q2 is charged to the level of the first voltage VDD with an error of at most 10%. In some other embodiments, the second transmission circuit 330 is turned on by the second transmission signal TS2 (not shown), thereby establishing an electrical connection between the fourth node N and the second node Q2, and as a result, the second node Q2 can be charged by the third input circuit 312. In some embodiments, the first transmission circuit 320 can receive a first voltage VDD at a high voltage level. When the first transmission circuit 320 is turned on by the voltage level at the fourth node N, the high voltage level of the first voltage VDD can be used to charge the first node Q1. Optionally, the voltage level at the first node Q1 is charged to the level of the first voltage VDD with an error of at most 10%. In some other embodiments, the first transmission circuit 320 is turned on by the first transmission signal TS1 (not shown), thereby establishing an electrical connection between the fourth node N and the first node Q1, and as a result, the first node Q1 can be charged by the third input circuit 312. Furthermore, the second transmission circuit 330 is connected to the second node Q2 and the fourth node N, and is configured to control the voltage level at the second node Q2 in response to the voltage level at the fourth node N or the second transmission signal TS2 (not shown) received by the second transmission circuit 330. In some embodiments, the second transmission circuit 330 can receive a first voltage VDD at a high voltage level. When the second transmission circuit 330 is turned on by the voltage level at the fourth node N, the high voltage level of the first voltage VDD can be used to charge the second node Q2. The voltage level at the second node Q2 is charged to the level of the first voltage VDD with an error of at most 10%.

[0078] Furthermore, the second transmission circuit 330 is connected to the second node Q2 and the fourth node N, and is configured to control the voltage level at the second node Q2 in response to the voltage level at the fourth node N or the second transmission signal TS2 (not shown) received by the second transmission circuit 330. In some embodiments, the second transmission circuit 330 can receive a first voltage VDD at a high voltage level. When the second transmission circuit 330 is turned on by the voltage level at the fourth node N, the high voltage level of the first voltage VDD can be used to charge the second node Q2. The voltage level at the second node Q2 is charged to the level of the first voltage VDD with an error of at most 10%. (not shown), thereby establishing an electrical connection between the fourth node N and the second node Q2, and as a result, the second node Q2 can be charged by the third input circuit 312. In some embodiments, the second transmission circuit 330 can receive a first voltage VDD at a high voltage level. When the second transmission circuit 330 is turned on by the voltage level at the fourth node N, the high voltage level of the first voltage VDD can be used to charge the second node Q2. The voltage level at the second node Q2 is charged to the level of the first voltage VDD with an error of at most 10%. When the second transmission circuit 330 is turned on by the voltage level at the fourth node N, the high voltage level of the first voltage VDD can be used to charge the second node Q2. The voltage level at the second node Q2 is charged to the level of the first voltage VDD with an error of at most 10%. In some other embodiments, the second transmission circuit 330 is turned on by the second transmission signal TS2 (not shown), thereby establishing an electrical connection between the fourth node N and the second node Q2, and as a result, the second node Q2 can be charged by the third input circuit 312. By becoming conductive according to the illustration), the electrical connection between the fourth node N and the second node Q2 can be established, and as a result, the second node Q2 can be charged by the third input circuit 312. Optionally, the first transmission signal TS1 and the second transmission TS2 can be the same signal, for example, the first clock signal CLKA or the first voltage VDD. Therefore, the number of clock signal lines can be reduced. Optionally, different signals can be provided for the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330 respectively. For example, when it is not necessary to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption.

[0079] Optionally, the first transmission signal TS1 and the second transmission TS2 can be the same signal, for example, the first clock signal CLKA or the first voltage VDD. Therefore, the number of clock signal lines can be reduced. Optionally, different signals can be provided for the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330 respectively. For example, when it is not necessary to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption. Optionally, the first transmission signal TS1 and the second transmission TS2 can be the same signal, for example, the first clock signal CLKA or the first voltage VDD. Therefore, the number of clock signal lines can be reduced. Optionally, different signals can be provided for the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330 respectively. For example, when it is not necessary to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption. Optionally, the first transmission signal TS1 and the second transmission signal TS2 can be the same signal, for example, the first clock signal CLKA or the first voltage VDD. Therefore, the number of clock signal lines can be reduced. Optionally, different signals can be provided for the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330 respectively. For example, when it is not necessary to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption. Optionally, different signals can be provided for the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330 respectively. For example, when it is not necessary to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption. Optionally, different signals can be provided for the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330 respectively. For example, when it is not necessary to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption. Optionally, different signals can be provided for the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330 respectively. For example, when it is not necessary to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption.

[0080] Optionally, when the shift register unit 10A includes three, four, or more sub-units, three, four, or more transmission circuits need to be installed to perform the function of the blank input sub-unit 300. The three, four, or more sub-units in the shift register unit 10A can share one blank input sub-unit 300 to reduce the area of the shift register unit 10A, thereby reducing the size of the bezel of the display device using the shift register unit 10A and improving the PPI of the display device. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, when the shift register unit 10A includes three, four, or more sub-units, three, four, or more transmission circuits need to be installed to perform the function of the blank input sub-unit 300. The three, four, or more sub-units in the shift register unit 10A can share one blank input sub-unit 300 to reduce the area of the shift register unit 10A, thereby reducing the size of the bezel of the display device using the shift register unit 10A and improving the PPI of the display device. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, when the shift register unit 10A includes three, four, or more sub-units, three, four, or more transmission circuits need to be installed to perform the function of the blank input sub-unit 300. The three, four, or more sub-units in the shift register unit 10A can share one blank input sub-unit 300 to reduce the area of the shift register unit 10A, thereby reducing the size of the bezel of the display device using the shift register unit 10A and improving the PPI of the display device. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, when the shift register unit 10A includes three, four, or more sub-units, three, four, or more transmission circuits need to be installed to perform the function of the blank input sub-unit 300. The three, four, or more sub-units in the shift register unit 10A can share one blank input sub-unit 300 to reduce the area of the shift register unit 10A, thereby reducing the size of the bezel of the display device using the shift register unit 10A and improving the PPI of the display device. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, when the shift register unit 10A includes three, four, or more sub-units, three, four, or more transmission circuits need to be installed to perform the function of the blank input sub-unit 300. The three, four, or more sub-units in the shift register unit 10A can share one blank input sub-unit 300 to reduce the area of the shift register unit 10A, thereby reducing the size of the bezel of the display device using the shift register unit 10A and improving the PPI of the display device. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, when the shift register unit 10A includes three, four, or more sub-units, three, four, or more transmission circuits need to be installed to perform the function of the blank input sub-unit 300. The three, four, or more sub-units in the shift register unit 10A can share one blank input sub-unit 300 to reduce the area of the shift register unit 10A, thereby reducing the size of the bezel of the display device using the shift register unit 10A and improving the PPI of the display device. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, when the shift register unit 10A includes three, four, or more sub-units, three, four, or more transmission circuits need to be installed to perform the function of the blank input sub-unit 300. The three, four, or more sub-units in the shift register unit 10A can share one blank input sub-unit 300 to reduce the area of the shift register unit 10A, thereby reducing the size of the bezel of the display device using the shift register unit 10A and improving the PPI of the display device. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period. Optionally, installing the blank input sub-unit 300 in the shift register unit 10A is to enable the shift register unit to output a driving signal during the blank period of one frame. "Blank" is only related to the blank period of the frame. The blank input sub-unit 300 is not limited to operating only during the blank period.

[0081] FIG. 4 is a circuit diagram of a blank input subunit according to an embodiment of the present disclosure. FIGS. 5A to FIGS. 5F are circuit diagrams of a blank input subunit according to an embodiment of the present disclosure. In some embodiments, the selection control circuit 311 can be implemented by including a first transistor M1 and a first capacitor C 1. The first transistor M1 has a gate terminal configured to receive the selection control signal OE . The first transistor M1 has a first terminal configured to receive a second input signal ST U2. The first transistor M1 has a second terminal connected to a third node H. For example, when the selection control signal OE is provided as a high voltage turn-on signal , the first transistor M1 turns on, and as a result, the second input signal S TU2 can be used to charge the third node H.

[0082] The first capacitor C1 has a first terminal connected to the third node H and a second terminal configured to receive a fourth voltage VGL1 or a first voltage VDD. By providing the first capacitor C1, the voltage level at the third node H can be maintained. For example, during the display period of a frame, the selection control circuit 311 can charge the third node H to raise the voltage level of the third node H to a high voltage level. The first capacitor C1 can maintain the high voltage level at the third node H until the blanking period of the frame. In some other embodiments, the first capacitor C1 has a second terminal connected to a fourth node N. Optionally , the fourth voltage VGL1 is a low voltage level or a turn-off signal.

[0083] Referring to FIG. 4, the third input circuit 312 can be implemented by including a second transistor M2 is possible. The second transistor M2 has a gate terminal connected to the third node H, and the first clock a first terminal CLKA configured to receive a clock signal, and a second terminal connected to the fourth node N. When the third node H is set to a high voltage level, the second transistor M2 turns on, and as a result, the first clock signal CLKA is passed to the fourth node N, where the voltage level can be pulled up to the high voltage level.

[0084] Referring to FIG. 4, the first transmission circuit 320 includes a third transistor M3, and the second transmission circuit 330 includes a fourth transistor M4. The third transistor M3 has a gate terminal connected to the fourth node N, a first terminal configured to receive a first voltage VDD, and a second terminal connected to the first node Q1. For example, when the fourth node N is set to a high voltage level, the third transistor M3 turns on, and as a result, the first node Q1 can be charged using the first voltage VDD. Optionally, the voltage level at the first node Q1 is charged to the level of the first voltage VDD with an error of at most 10%. The fourth transistor M4 has a gate terminal connected to the fourth node N, a first terminal configured to receive a first voltage VDD, and a second terminal connected to the second node Q2. For example, when the fourth node N is set to a high voltage level, the fourth transistor M4 turns on, and as a result, the second node Q2 can be charged using the first voltage VDD.

[0085] Referring to FIG. 5A, in a specific embodiment, the blank input subunit 300A has a second transistor M having a first terminal configured to receive a first voltage VDD. ​​​​​​​​​​​​​2 and a third transistor M3 having a gate terminal configured to receive the first transmission signal TS1 and a fourth transistor M4 having a gate terminal configured to receive the second transmission signal TS2 . The third transistor M3 further has a first terminal connected to the fourth node N , and the fourth transistor M4 further has a first terminal connected to the fourth node N . During the display period of the frame, when it is necessary to charge the first node Q1, optionally , a high voltage may be supplied to the first transmission signal TS1 to turn on the third transistor M3 . Therefore, the first voltage VDD at a high voltage level can charge the first node Q1 through the second transistor M2, the fourth node N and the third transistor M3. During the blank period of the frame, when it is necessary to charge the second node Q2, optionally , a high voltage may be supplied to the second transmission signal TS2 to turn on the fourth transistor M4, and as a result , the first voltage VDD at a high voltage level can charge the second node Q2 through the second transistor M2, the fourth node N and the fourth transistor M4.

[0086] Referring to FIG. 5B, in another specific embodiment, the blank input subunit 300B includes the third transistor M3 and the fourth transistor M4 . The third transistor M3 and the fourth transistor M4 are each configured such that their gate terminals receive the first clock signal CLKA . In other words, TS1 = TS2 = CLKA. For example, during the blank period of the frame, when a high voltage level is provided to the first clock signal CLKA , the third transistor M3 and the fourth transistor M4 are turned on simultaneously, and the first voltage VDD at a high voltage level can charge the first node Q1 and the second node Q2 simultaneously. ​

[0087] Referring to FIG. 5C, in another specific embodiment, a blank input subunit 300C includes a first clock signal CLKA having a first terminal configured to receive the first clock signal CLKA. The third transistor M3 and the fourth transistor M4 each include The gate terminal of the second transistor M2 is connected to the first terminal of the second transistor M3 to receive the first clock signal CLK. A. Therefore, the first transistor M2 in FIG. The first terminal is connected to a first voltage VDD at a high voltage level, as shown in FIG. The high voltage level can be set in a shorter time than with the transistor M1. 5C, the second transistor M2 has a longer lifetime and is This ensures stability of the system.

[0088] Referring to FIG. 5D, in yet another specific embodiment, the blank input subunit In addition to the circuit shown in FIG. 5C, the third embodiment 300D further includes a first coupling capacitor CST1. The coupling capacitor CST1 is adapted to receive the first clock signal CLKA. and a second terminal connected to a third node H. When the clock signal CLKA changes from a low voltage level to a high voltage level, the first clock signal CL KA is connected to the third node by the coupling effect of the first coupling capacitor CST1. H to push the voltage level of the third node H even higher. This ensures that the second transistor M2 is fully turned on.

[0089] Referring to FIG. 5E, in yet another specific embodiment, a blank input subunit In addition to the circuit shown in FIG. 5D, the TR300E further includes a second coupling capacitor CST2. The second coupling capacitor CST2 has a first terminal connected to the third node H and a second terminal connected to the fourth node N. When the first clock signal CLKA changes from a low voltage level to a high voltage level and the second transistor M2 is turned on, the high voltage level of the first clock signal CLKA can be passed to the fourth node N through the second transistor M2. The voltage level at the second terminal of the second coupling capacitor CST2 is pulled up. Due to the bootstrap effect of the coupling capacitor, the voltage level at the third node H is further pushed up to ensure that the second transistor M2 is fully turned on. Referring to FIG. 5F, in yet another specific embodiment, the blank input subunit 300F further includes a 42nd transistor M42 in addition to the circuit shown in FIG. 5E. The 42nd transistor M42 has a gate terminal connected to the third node H, a first terminal configured to receive the first clock signal CLKA, and a second terminal connected to the first terminal of the first coupling capacitor CST1. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. When the first clock signal CLKA changes from a low voltage level to a high voltage level and the second transistor M2 is turned on, the high voltage level of the first clock signal CLKA can be passed to the fourth node N through the second transistor M2. The voltage level at the second terminal of the second coupling capacitor CST2 is pulled up. Due to the bootstrap effect of the coupling capacitor, the voltage level at the third node H is further pushed up to ensure that the second transistor M2 is fully turned on. When the first clock signal CLKA changes from a low voltage level to a high voltage level and the second transistor M2 is turned on, the high voltage level of the first clock signal CLKA can be passed to the fourth node N through the second transistor M2. The voltage level at the second terminal of the second coupling capacitor CST2 is pulled up. Due to the bootstrap effect of the coupling capacitor, the voltage level at the third node H is further pushed up to ensure that the second transistor M2 is fully turned on. When the first clock signal CLKA changes from a low voltage level to a high voltage level and the second transistor M2 is turned on, the high voltage level of the first clock signal CLKA can be passed to the fourth node N through the second transistor M2. The voltage level at the second terminal of the second coupling capacitor CST2 is pulled up. Due to the bootstrap effect of the coupling capacitor, the voltage level at the third node H is further pushed up to ensure that the second transistor M2 is fully turned on. When the first clock signal CLKA changes from a low voltage level to a high voltage level and the second transistor M2 is turned on, the high voltage level of the first clock signal CLKA can be passed to the fourth node N through the second transistor M2. The voltage level at the second terminal of the second coupling capacitor CST2 is pulled up. Due to the bootstrap effect of the coupling capacitor, the voltage level at the third node H is further pushed up to ensure that the second transistor M2 is fully turned on. When the first clock signal CLKA changes from a low voltage level to a high voltage level and the second transistor M2 is turned on, the high voltage level of the first clock signal CLKA can be passed to the fourth node N through the second transistor M2. The voltage level at the second terminal of the second coupling capacitor CST2 is pulled up. Due to the bootstrap effect of the coupling capacitor, the voltage level at the third node H is further pushed up to ensure that the second transistor M2 is fully turned on. When the first clock signal CLKA changes from a low voltage level to a high voltage level and the second transistor M2 is turned on, the high voltage level of the first clock signal CLKA can be passed to the fourth node N through the second transistor M2. The voltage level at the second terminal of the second coupling capacitor CST2 is pulled up. Due to the bootstrap effect of the coupling capacitor, the voltage level at the third node H is further pushed up to ensure that the second transistor M2 is fully turned on.

[0090] Referring to FIG. 6, FIG. 6 is a circuit diagram of a blank input subunit including a leakage prevention structure according to an embodiment of the present disclosure. In addition to the circuit shown in FIG. 5E, the blank input subunit 300F further includes a 42nd transistor M42. The 42nd transistor M42 has a gate terminal connected to the third node H, a first terminal configured to receive the first clock signal CLKA, and a second terminal connected to the first terminal of the first coupling capacitor CST1. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. The 42nd transistor M42 has a gate terminal connected to the third node H, a first terminal configured to receive the first clock signal CLKA, and a second terminal connected to the first terminal of the first coupling capacitor CST1. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. The 42nd transistor M42 has a gate terminal connected to the third node H, a first terminal configured to receive the first clock signal CLKA, and a second terminal connected to the first terminal of the first coupling capacitor CST1. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. The 42nd transistor M42 has a gate terminal connected to the third node H, a first terminal configured to receive the first clock signal CLKA, and a second terminal connected to the first terminal of the first coupling capacitor CST1. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on. When the third node H is set to a high voltage level, the 42nd transistor M42 is turned on. Then, due to the coupling effect of the first coupling capacitor CST1, the first clock signal CLKA can pull up the third node H, and the third node H is pushed up to an even higher voltage level to ensure that the second transistor M2 is fully turned on.

[0091] Referring to FIG. 6, FIG. 6 is a circuit diagram of a blank input subunit including a leakage prevention structure according to an embodiment of the present disclosure. It is a diagram. Referring to FIG. 6, in an alternative embodiment, the blank input subunit 30 0’ further includes a 43rd transistor M43, transistors M1 _b, M3_b, and M4_b in addition to the circuit shown in FIG. 5E. The 43rd transistor M43 has a gate terminal connected to the 3rd node H, a first terminal configured to receive the 6th voltage VB, and a second terminal connected to the second terminal of the first transistor M1 . The transistor M1_b has a gate terminal configured to receive the aforementioned selection control signal OE, a first terminal connected to the second terminal of the first transistor M1, and a second terminal connected to the 3rd node H . The transistors M3_b and M4_b both have gate terminals configured to receive the first clock signal CL KA. The transistors M3_b and M4_b both have a first terminal connected to the 7th node OF. The transistor M3_b further has a second terminal connected to the 1st node Q1 , and the transistor M4_b further has a second terminal connected to the 2nd node Q2 . Combining the 43rd transistor M43 and the transistor M1_b provides a leakage prevention function for preventing leakage at the 3rd node H . The transistor M3_b can also prevent leakage at the 1st node Q1 . The transistor M4_b can also prevent leakage at the 2nd node Q2 . Optionally, the 6th voltage VB is set to a high voltage level. Optionally, more details about the leakage prevention function realized by the blank input subunit and its relevance to the 7th node OF will be described in the following specification . Optionally, the transistors used in the blank input subunit shown in FIGS. 4, 5A - 5F, and 6

[0092] The combination of the 43rd transistor M43 and the transistor M1_b provides a leakage prevention function for preventing leakage at the 3rd node H . The transistor M3_b can also prevent leakage at the 1st node Q1 . The transistor M4_b can also prevent leakage at the 2nd node Q2 . Optionally, the 6th voltage VB is set to a high voltage level. Optionally, more details about the leakage prevention function realized by the blank input subunit and its relevance to the 7th node OF will be described in the following specification . Optionally, more details about the leakage prevention function realized by the blank input subunit and its relevance to the 7th node OF will be described in the following specification. Optionally . More details regarding the leakage prevention function and the relationship with the 7th node OF realized by the blank input subunit will be described in the following specification. Optionally . The transistors used in the blank input subunit shown in FIGS. 4, 5A - 5F, and 6 The example assumes that all the transistors are N-type transistors.

[0093] FIG. 7 is a block diagram of a shift register unit according to another embodiment of the present disclosure. Referring to FIG. 7, in addition to the circuit shown in FIG. 2, the shift register unit 10B includes a first control circuit 130, a first reset circuit 140, a second reset circuit 150, a shift register output terminal CRT, and a first output terminal OP1. The shift register output terminal CR T is provided to output a shift register signal CR. The first output terminal OP1 is provided to output a first output signal OUT1.

[0094] The first control circuit 1130 is configured to control the voltage level QB_A of the fifth node in response to the voltage level at the first node Q1 and the second voltage VDD_A. For example, the first control circuit 130 is connected to the first node Q1 and the fifth node QB_A and is configured to receive the second voltage VDD_ A and the fourth voltage VGL1. When the first node Q1 is set to a high voltage level (allowing a 10% error), the first control circuit 130 can use the low voltage level fourth voltage V GL1 to lower the voltage level QB_A of the fifth node to a low voltage level. Optionally, when the first node Q1 is set to a low voltage level (allowing a 10% error), the first control circuit 130 can charge the fifth node QB_A using the high voltage level second voltage VDD_A to raise the voltage level QB_A of the fifth node to a high voltage level. When the first node Q1 is set to a high voltage level (allowing a 10% error), the first control circuit 130 can use the low voltage level fourth voltage V GL1 to lower the voltage level QB_A of the fifth node to a low voltage level. Optionally, when the first node Q1 is set to a low voltage level (allowing a 10% error), the first control circuit 130 can raise the voltage level QB_A of the fifth node to a high voltage level and charge the fifth node QB_A using the high voltage level second voltage VDD_A. When the first node Q1 is set to a low voltage level (allowing a 10% error), the first control circuit 130 can charge the fifth node QB_A using the high voltage level second voltage VDD_A to raise the voltage level QB_A of the fifth node to a high voltage level. When the first node Q1 is set to a low voltage level (allowing a 10% error), the first control circuit 130 can charge the fifth node QB_A using the high voltage level second voltage VDD_A to raise the voltage level QB_A of the fifth node to a high voltage level. When the first node Q1 is set to a low voltage level (allowing a 10% error), the first control circuit 130 can charge the fifth node QB_A using the high voltage level second voltage VDD_A to raise the voltage level QB_A of the fifth node to a high voltage level.

[0095] The first reset circuit 140 responds to the voltage level at the fifth node QB_A to control the first node Q1. Reset the voltage levels at the shift register output terminal CRT and the first output terminal OP1 It is configured to do so. The first reset circuit 140 is connected to the first node Q1, the fifth node QB_A, the shift register output terminal CRT, and the first output terminal OP1, respectively, and is configured to receive the fourth voltage VGL1 and the fifth voltage VGL2. When the first reset circuit 1 40 is turned on by the voltage level QB_A at the fifth node, the fourth voltage VGL1 (low voltage level) can be used to pull down or reset the voltage levels of the first node Q1 and the shift register output terminal CR T to a low voltage level. At the same time, the fifth voltage VGL2 (also a low voltage level) can be used to pull down or reset the voltage level of the first output terminal OP1 to a low voltage level . Optionally, the first reset circuit 140 can also use the fourth voltage VGL1 to pull down or reset the voltage level of the first output terminal OP1 to a low voltage level .

[0096] The second reset circuit 150 is configured to reset the voltage levels of the first node Q1, the shift register output terminal CRT, and the first output terminal OP1 in response to the voltage level at the sixth node QB_B . Referring to FIG. 7, the second reset circuit 150 is connected to the first node Q1, the sixth node QB_B, the shift register output terminal CRT, and the first output terminal OP1, respectively, and is configured to receive the fourth voltage VGL1 and the fifth voltage VGL2. The second reset circuit 150, when turned on by the voltage level at the sixth node QB_B, as an option, uses the fourth voltage VGL1 (low voltage level) to pull down or reset the voltage levels of the first node Q1 and the shift register output terminal CRT to a low voltage level ​​​ At the same time, a fifth voltage VGL2 (low voltage level) can be used as an option. The voltage level of the first output terminal OP1 can be pulled down to a low voltage level or reset. can.

[0097] Referring to FIG. 7, the second sub-unit 200B includes a second control circuit 230 and a third reset circuit. The second output terminal OP2 further includes a fourth reset circuit 240, a fourth reset circuit 250, and a second output terminal OP2. The input terminal OP2 is configured to output a second output signal OUT2.

[0098] The second control circuit 230 is responsive to the voltage level at the second node Q2 and the third voltage VDD_B. 7, the sixth node QB-B is configured to control the voltage level of the sixth node QB-B. The second control circuit 230 is connected to the second node Q2 and the sixth node QB_B, and is connected to the third The second node Q2 is configured to receive a high voltage VDD_B and a fourth voltage VGL1. When the voltage level is set to the low voltage level, the second control circuit 230 uses the fourth voltage VGL1 at a low voltage level. As a result, the voltage level of the sixth node QB_B can be pulled down to a low voltage level. When the node Q2 is set to a low voltage level, the second control circuit 230 also supplies a low voltage A third voltage VDD_B (high voltage level) is used to raise the voltage level of _B. The sixth node QB_B can be charged.

[0099] The third reset circuit 240 resets the second node QB_B in response to the voltage level at the sixth node QB_B. Q2 and the second output terminal OP2 are configured to reset to a low voltage level. For example, The third reset circuit 240 includes a second node Q2, a sixth node QB_B, and a second output terminal OP Connected to 2 and configured to receive a fourth voltage VGL1 and a fifth voltage VGL2 When the third reset circuit 240 is turned on by the voltage level at the sixth node QB_B, Optionally, the fourth voltage VGL1 can be used to lower the voltage level at the second node Q2 to a low voltage level. At the same time, optionally, the fifth voltage VGL2 can be used to lower the voltage level at the second output terminal OP2. Optionally, the fourth voltage VGL1 can be used to lower or reset the second output terminal OP2 to a low voltage level .

[0100] The fourth reset circuit 250 is configured to reset the second node Q2 and the second output terminal OP2 in response to the voltage level at the fifth node QB_A. For example, the fourth reset circuit 250 is connected to the second node Q2, the fifth node QB_A, and the second output terminal OP2 and is configured to receive the fourth voltage VGL1 and the fifth voltage VGL2. When the fourth reset circuit 250 is turned on by the voltage level at the fifth node QB_A, optionally, the fourth voltage VGL1 (at a low voltage level) can be used to lower or reset the second node Q2 to a low voltage level . At the same time, optionally, the fifth voltage VGL2 (at a low voltage level) can be used to lower or reset the second output terminal OP2 to a low voltage level .

[0101] Optionally, the second voltage VDD_A and the third voltage VDD_B can be set as two inverted-phase voltage signals, i.e., when a high voltage level is applied to the second voltage VDD_A, a low voltage level is applied to the third voltage VD D_B, and when the second voltage VDD_A is at a low voltage level, the third voltage The voltage VDD_B may be at a high voltage level. By setting it in this way, the first control circuit 1 30 and the second control circuit 230 can operate only one of the circuits in the active mode at a time . This can avoid the functional drift of the circuit due to long-term operation and improve the stability of the circuit .

[0102] Referring to FIG. 7, the blank input subunit 300 of the shift register unit 10B further includes a common reset circuit 340. The common reset circuit 340 is connected to the fourth node N, the fifth node QB_A, and the sixth node QB_B, respectively, and resets the voltage level of the fourth node N in response to the voltage level at the fifth node QB_A or the sixth node QB_B. For example, the common reset circuit 340 may be configured to receive the fourth voltage VGL1 . When the common reset circuit 340 is turned on by the voltage level at the fifth node QB_A or the sixth node QB_ B, the fourth node N can be pulled down to a low voltage level or reset using the fourth voltage VGL1. By installing the common reset circuit 340 in the blank input subunit, the voltage level at the fourth node N can be better controlled . When it is not necessary to charge the first node Q1 or the second node Q2, the fourth node N can be set to a low voltage level to turn off the first transmission circuit 320 and the second transmission circuit 330. Thus , the high voltage level from the first voltage VDD is prevented from charging the first node Q1 and the second node Q2 . In this way, abnormal signal output can be avoided and the stability of the circuit can be improved . .

[0103] FIG. 8 is a block diagram of a shift register unit according to still another embodiment of the present disclosure ​​​Refer to FIG. 8. In addition to the circuit shown in FIG. 7, the shift register unit 10C includes a first sub-unit 100 further including a third control circuit 160 and a fourth control circuit 170. The third control circuit 160 is configured to control the voltage level of the fifth node QB_A in response to the first clock signal CLKA. The fourth control circuit 170 is configured to control the voltage level of the fifth node QB_A in response to the first input signal STU1. In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In another embodiment, the third control circuit 160 is also connected to the third node H. During the blank period of a frame, when the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, and as a result, the low voltage level fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. The fourth control circuit 170 is connected to the fifth node QB_A and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame, the fourth control circuit 170 is turned on in response to the first input signal STU1, and the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level.

[0104] In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In another embodiment, the third control circuit 160 is also connected to the third node H. During the blank period of a frame, when the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, and as a result, the low voltage level fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. Refer to FIG. 8. In addition to the circuit shown in FIG. 7, the shift register unit 10C includes a first sub-unit 100 further including a third control circuit 160 and a fourth control circuit 170. The third control circuit 160 is configured to control the voltage level of the fifth node QB_A in response to the first clock signal CLKA. The fourth control circuit 170 is configured to control the voltage level of the fifth node QB_A in response to the first input signal STU1. In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In another embodiment, the third control circuit 160 is also connected to the third node H. During the blank period of a frame, when the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, and as a result, the low voltage level fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. The fourth control circuit 170 is connected to the fifth node QB_A and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame, the fourth control circuit 170 is turned on in response to the first input signal STU1, and the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In another embodiment, the third control circuit 160 is also connected to the third node H. During the blank period of a frame, when the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, and as a result, the low voltage level fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. The fourth control circuit 170 is connected to the fifth node QB_A and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame, the fourth control circuit 170 is turned on in response to the first input signal STU1, and the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In another embodiment, the third control circuit 160 is also connected to the third node H. During the blank period of a frame, when the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, and as a result, the low voltage level fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. The fourth control circuit 170 is connected to the fifth node QB_A and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame, the fourth control circuit 170 is turned on in response to the first input signal STU1, and the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level.

[0105] The fourth control circuit 170 is connected to the fifth node QB_A and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame, the fourth control circuit 170 is turned on in response to the first input signal STU1, and the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In another embodiment, the third control circuit 160 is also connected to the third node H. During the blank period of a frame, when the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, and as a result, the low voltage level fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. The fourth control circuit 170 is connected to the fifth node QB_A and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame, the fourth control circuit 170 is turned on in response to the first input signal STU1, and the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. In another embodiment, the third control circuit 160 is also connected to the third node H. During the blank period of a frame, when the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, and as a result, the low voltage level fourth voltage VGL1 can be used to pull down the fifth node QB_A to a low voltage level. When B_A is pulled down to a low voltage level, the influence that the fifth node QB_A exerts on the first node Q1 can be avoided, and as a result, the charging of the first node Q1 during the display period becomes more sufficient.

[0106] Referring to FIG. 8, in addition to the circuit shown in FIG. 7, the second sub-unit 200 further includes a fifth control circuit 260 and a sixth control circuit 270. The fifth control circuit 260 is configured to control the voltage level of the sixth node QB_B in response to the first clock signal CLKA. The sixth control circuit 270 is configured to control the voltage level of the sixth node QB_B in response to the first input signal STU1.

[0107] In one embodiment, the fifth control circuit 260 is connected to the sixth node QB_B and is configured to receive the first clock signal CLKA and the fifth voltage VGL1. For example, during the blank period of a frame, the fifth control circuit 260 can be turned on in response to the first clock signal CLKA. Therefore, the voltage level at the sixth node QB_B can be pulled down using the low voltage level of the fourth voltage VLG1. In another embodiment, the fifth control circuit 260 is also connected to the third node H. For example, during the blank period of a frame, when the third node H is set to a high voltage level and a high voltage level is provided to the first clock signal CLKA, the fifth control circuit 260 is turned on, and as a result, the fourth voltage VGL1 can be used to pull down the sixth node QB_B to a low voltage level.

[0108] The sixth control circuit 270 is connected to the sixth node QB_B and is configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame , the sixth control circuit 270 turns on in response to the first input signal STU1. Using the fourth voltage VGL1 of a low voltage level, the sixth node QB_B can be pulled down. Pulling down the sixth node QB_B to a low voltage level prevents the influence that the sixth node QB_B exerts on the second node Q2. As a result, the charging of the second node Q2 during the display period becomes more sufficient. Referring to FIG. 8, the first sub-unit 100C further includes a fifth reset circuit 180 and a sixth reset circuit 190. The fifth reset circuit 180 is configured to reset the first node Q1 in response to the display reset signal STD. The sixth reset circuit 190 is configured to reset the first node Q1 in response to the full-scale reset signal TRST. In one embodiment, the fifth reset circuit 180 is connected to the first node Q1 and is configured to receive the display reset signal STD and the fourth voltage VGL1. During the display period of the frame, when the fifth reset circuit 180 turns on in response to the display reset signal STD, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. For example, when a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit, one stage of the shift register unit 10C can receive the shift register signal CR output from other stages of the shift register units as the display reset signal STD. In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level.

[0109] Referring to FIG. 8, the first sub-unit 100C further includes a fifth reset circuit 180 and a sixth reset circuit 190. The fifth reset circuit 180 is configured to reset the first node Q1 in response to the display reset signal STD. The sixth reset circuit 190 is configured to reset the first node Q1 in response to the full-scale reset signal TRST. In one embodiment, the fifth reset circuit 180 is connected to the first node Q1 and is configured to receive the display reset signal STD and the fourth voltage VGL1. During the display period of the frame, when the fifth reset circuit 180 turns on in response to the display reset signal STD, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. For example, when a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit, one stage of the shift register unit 10C can receive the shift register signal CR output from other stages of the shift register units as the display reset signal STD. In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. Referring to FIG. 8, the first sub-unit 100C further includes a fifth reset circuit 180 and a sixth reset circuit 190. The fifth reset circuit 180 is configured to reset the first node Q1 in response to the display reset signal STD. The sixth reset circuit 190 is configured to reset the first node Q1 in response to the full-scale reset signal TRST. In one embodiment, the fifth reset circuit 180 is connected to the first node Q1 and is configured to receive the display reset signal STD and the fourth voltage VGL1. During the display period of the frame, when the fifth reset circuit 180 turns on in response to the display reset signal STD, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. For example, when a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit, one stage of the shift register unit 10C can receive the shift register signal CR output from other stages of the shift register units as the display reset signal STD.

[0110] In one embodiment, the fifth reset circuit 180 is connected to the first node Q1 and is configured to receive the display reset signal STD and the fourth voltage VGL1. During the display period of the frame, when the fifth reset circuit 180 turns on in response to the display reset signal STD, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. For example, when a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit, one stage of the shift register unit 10C can receive the shift register signal CR output from other stages of the shift register units as the display reset signal STD. In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. During the display period of the frame, when the fifth reset circuit 180 turns on in response to the display reset signal STD, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. For example, when a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit, one stage of the shift register unit 10C can receive the shift register signal CR output from other stages of the shift register units as the display reset signal STD. In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. For example, when a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit, one stage of the shift register unit 10C can receive the shift register signal CR output from other stages of the shift register units as the display reset signal STD. In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level.

[0111] In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. During the display period of the frame, when the sixth reset circuit 190 turns on in response to the full-scale reset signal TRST, as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 of a low voltage level. It is configured to receive a full-scale reset signal TRST and a fourth voltage VGL1. Multiple When a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit, during the display period of a frame, the sixth reset circuit 190 in each stage of the shift register unit 10C turns on in response to the full-scale reset signal TRST. Therefore, the first node Q1 of each stage of the shift register unit 10C can be pulled down or reset using the low-voltage-level fourth voltage VGL1, and as a result, a full-scale reset for the gate driving circuit is realized. Referring to FIG. 8, the second sub-unit 200C further includes a seventh reset circuit 280 and an eighth reset circuit 290. The seventh reset circuit 280 is configured to reset the second node Q2 in response to a display reset signal STD. The eighth reset circuit 290 is configured to reset the second node Q2 in response to the full-scale reset signal TRST.

[0112] Referring to FIG. 8, the second sub-unit 200C further includes a seventh reset circuit 280 and an eighth reset circuit 290. The seventh reset circuit 280 is configured to reset the second node Q2 in response to a display reset signal STD. The eighth reset circuit 290 is configured to reset the second node Q2 in response to the full-scale reset signal TRST.

[0113] In one embodiment, the seventh reset circuit 280 is connected to the second node Q2 and is configured to receive the display reset signal STD and the fourth voltage VGL1. For example, during the display period of a frame, the seventh reset circuit 280 turns on in response to the display reset signal STD, and as a result, the second node Q2 can be pulled down or reset using the low-voltage-level fourth voltage VGL1.

[0114] In one embodiment, the eighth reset circuit 290 is connected to the second node Q2 and is configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. For example, ​ For example, when a plurality of shift register units 10C are cascade-connected to form a multi-stage gate driving circuit during the display period of the frame, in each stage of the shift register unit The eighth reset circuit 290 can be turned on in response to the full-scale reset signal TRST. Therefore, the second node Q2 in each stage of the shift register unit 10C can be pulled down or reset using the low-voltage level fourth voltage VGL1, and as a result, full-scale reset of the gate driving circuit can be achieved.

[0115] FIGS. 9A and 9B are circuit diagrams of the first sub-unit and the second sub-unit of the shift register unit according to an embodiment of the present disclosure. In particular, FIG. 9A shows a part of the shift register unit including the first sub-unit 100 and the blank input sub-unit 300. FIG. 9B shows a part of the shift register unit including the second sub-unit 200 and the second transmission circuit 330. Referring to FIGS. 9A and 9B, the shift register unit includes many transistors M1 to M41, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Here, all the transistors used are taken as an example of N-type transistors. FIGS. 10A to 10C are circuit diagrams of three types of first input circuits of the shift register unit according to an embodiment of the present disclosure.

[0116] and a second terminal connected to the first node Q1.

[0117] In another embodiment, referring to FIG. 10A, the fifth transistor M5 has its gate terminal and its first terminal configured to receive a first input signal STU1 together, and thus when the first input signal STU1 is a high voltage signal, the fifth transistor M5 can charge the first node Q1 using the high voltage first input signal STU1.

[0118] In yet another embodiment, referring to FIG. 10B, the first input circuit 110 further includes a transistor M5_b. The transistor M5_b has a gate terminal and a first terminal both connected to the second terminal of the fifth transistor M5. The transistor M5_b further has a second terminal connected to the first node Q1. Since the transistor M5_b uses a diode connection method, current can only flow from the first terminal of the transistor M5_b to the second terminal and not vice versa. Thus, it prevents leakage from the first node Q1 through the fifth transistor M5. Q1. Since the transistor M5_b uses a diode connection method, current can only flow from the first terminal of the transistor M5_b to the second terminal and not vice versa. Thus, it prevents leakage from the first node Q1 through the fifth transistor M5. from the first node Q1 through the fifth transistor M5. prevents leakage.

[0119] In still another embodiment, referring to FIG. 10C, the transistor M5_b has a gate terminal connected to the gate terminal of the fifth transistor M5, and both are configured to receive the first input signal STU1. The transistor M5_b has a first terminal connected to the seventh node OF. The first input circuit 110 shown in FIG. 10C adopts a leakage prevention circuit structure to prevent leakage of the first node Q1. signal STU1. The transistor M5_b has a first terminal connected to the seventh node OF. The first input circuit 110 shown in FIG. 10C adopts a leakage prevention circuit structure to prevent leakage of the first node Q1. connected to the seventh node OF. The first input circuit 110 shown in FIG. 10C adopts a leakage prevention circuit structure to prevent leakage of the first node Q1. prevents leakage of the first node Q1.

[0120] Referring back to FIG. 9A, the first output circuit 120 includes a sixth transistor M6 and a seventh transistor It can be realized by including the transistor M7 and the second capacitor C2. The sixth transistor M 6 has a gate terminal connected to the first node Q1. The sixth transistor M6 is the second configured to receive the clock signal CLKB as the shift register signal CR at a first terminal it has. The sixth transistor M6 has a second terminal connected to the shift register output terminal CRT and configured to output the shift register signal CR.

[0121] The seventh transistor M7 has a gate terminal connected to the first node Q1. The seventh transistor M 7 is configured to receive the third clock signal CLKC as the first output signal OUT1 at a first terminal it has. The seventh transistor M7 has a second terminal connected to the first output terminal OP1 and configured to output the first output signal OUT1. The second capacitor C 2 has a first terminal connected to the first node Q1 and a second terminal connected to the second terminal of the seventh transistor M7 which is also the first output terminal OP1.

[0122] Referring to FIG. 9B again, the second input circuit 210 can be realized by including the eighth transistor M8. The eighth transistor M8 has a gate terminal configured to receive the first input signal STU1. The eighth transistor M8 has a first terminal configured to receive the first voltage VDD. The eighth transistor M8 has a second terminal connected to the second node Q2. Alternatively, the second input circuit 210 may adopt a similar circuit shown in FIGS. 10A to 10C.

[0123] Referring to FIG. 9B, the second output circuit 220 includes the ninth transistor M9 and the third capacitor It can be realized by including C3. The ninth transistor M9 has a gate terminal connected to the second node Q2. The ninth transistor M9 has a first terminal configured to receive the fourth clock signal CLKD as the second output signal OUT2. The ninth transistor M9 has a second terminal connected to the second output terminal OP2 and configured to output the second output signal OUT2. The third capacitor C3 has a first terminal connected to the second node Q2 and a second terminal connected to the second terminal of the ninth transistor M9 which is also the second output terminal OP2.

[0124] Referring to FIG. 9A, the common reset circuit 340 can be realized by including the tenth transistor M10 and the eleventh transistor M11. The tenth transistor M10 has a gate terminal connected to the fifth node QB_A. The tenth transistor M10 has a first terminal connected to the fourth node N. The tenth transistor M10 has a second terminal configured to receive the fourth voltage VGL1. The eleventh transistor M11 has a gate terminal connected to the sixth node QB_B. The eleventh transistor M11 has a first terminal connected to the fourth node N. The eleventh transistor M11 has a second terminal configured to receive the fourth voltage VGL1.

[0125] Referring to FIG. 9A, the first control circuit 130 can be realized by including the twelfth transistor M12 and the thirteenth transistor M13. The twelfth transistor M12 has a gate terminal and a first terminal both configured to receive the second voltage VDD_A. The twelfth transistor M12 further has a second terminal connected to the fifth node QB_A. The thirteenth transistor M13 has a gate terminal and a first terminal both configured to receive the second voltage VDD_A. The thirteenth transistor M13 further has a second terminal connected to the fifth node QB_A. Transistor M13 has a gate terminal connected to the first node Q1. The 13th trans istor M13 has a first terminal connected to the fifth node QB_A. The 13th trans istor M13 further has a second terminal configured to receive the fourth voltage VGL1.

[0126] Referring to FIG. 9A, the first reset circuit 140 can be implemented by including the 14th transistor M14, the 15th transistor M15, and the 16th transistor M16. The second reset circuit 150 can be implemented by including the 17th transistor M17, the 18th transistor M18, and the 19th transistor M19.

[0127] The 14th transistor M14 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the first node Q1, and a second terminal configured to receive the fourth voltage VGL1. The 15th transistor M15 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the shift register output terminal CRT, and a second terminal configured to receive the fourth voltage VGL1. The 16th transistor M16 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the first output terminal OP1, and a second terminal configured to receive the fifth voltage VGL2.

[0128] The 17th transistor M17 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the first node Q1, and a second terminal configured to receive the fourth voltage VGL1. The 18th transistor M18 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the shift register output terminal CRT, and a second terminal configured to receive the fourth voltage VGL1. It has a second terminal configured to do so. The 19th transistor M19 is the 6th node Q A gate terminal connected to B_B, a first terminal connected to the first output terminal OP1, and a fifth electrical It has a second terminal configured to receive the voltage VGL2.

[0129] Referring to FIG. 9B again, the second control circuit 230 can be realized by including a 20th transistor M20 and a 2 1st transistor M21. The 20th transistor M20 has a gate terminal and a first terminal both configured to receive the third voltage VDD_B. The 20th transistor M20 has a second terminal connected to the 6th node QB_B. The 21st transistor M21 has a gate terminal connected to the 2nd node Q2. The 21st transistor M21 has a first terminal connected to the 6th node QB_B. The 21st transistor M21 further has a second terminal configured to receive the fourth voltage VGL1.

[0130] Referring to FIG. 9B, the third reset circuit 240 includes a 22nd transistor M22 and a 2 3rd transistor M23. The fourth reset circuit 250 includes a 24th transistor M24 and a 25th transistor M25.

[0131] The 22nd transistor M22 has a gate terminal connected to the 6th node QB_B, a first terminal connected to the 2nd node Q2, and a second terminal configured to receive the fourth voltage VGL1. The 23rd transistor M23 has a gate terminal connected to the 6th node QB_B, a first terminal connected to the second output terminal OP2, and a second terminal configured to receive the fifth voltage VGL2.

[0132] The 24th transistor M24 has a gate terminal connected to the 5th node QB_A, a first terminal connected to the 2nd node Q2, and a second terminal configured to receive the 4th voltage VGL1. The 25th transistor M25 has a gate terminal connected to the 5th node QB_A, a first terminal connected to the 2nd output terminal OP2, and a second terminal configured to receive the 5th voltage VGL2.

[0133] Optionally, the 2nd voltage VDD_A and the 3rd voltage VDD_B can be set as two inverted-phase voltage signals. That is, when a high voltage level is applied to the 2nd voltage VDD_A, a low voltage level is applied to the 3rd voltage VDD_B, and when the 2nd voltage VDD_A is at a low voltage level, the 3rd voltage VDD_B may be at a high voltage level. By setting it in this way, the 1st control circuit 130 and the 2nd control circuit 230 can conduct only one of them at a time. Therefore, the performance drift of the transistor due to being set in the conducting state for a long time can be avoided, and the stability of the circuit can be improved.

[0134] Referring to FIGS. 9A and 9B, the 1st control circuit 130 installed in the 1st sub-unit 100 is used to control the voltage level of the 5th node QB_A, and the 2nd control circuit 230 installed in the 2nd sub-unit 200 is used to control the voltage level of the 6th node QB_B. In this way, the number of transistors in the shift register unit can be reduced, the size of the frame of the display device using the shift register unit can be decreased, and its PPI can be improved.

[0135] Referring to FIG. 9A, the 3rd control circuit 160 includes the 32nd transistor M32 and the 33rd transistor​​​​​​​​​​​​​​​ including the transistor M33. The 32nd transistor M32 has a gate terminal configured to receive the first clock signal CLKA, a first terminal connected to the fifth node QB_A, and a second terminal connected to the first terminal of the 33rd transistor M13. The 33rd transistor M33 has a gate terminal connected to the third node H and a second terminal configured to receive the fourth voltage VGL1. The fourth control circuit 170 includes the 34th transistor M34. The 34th transistor M34 has a gate terminal configured to receive the first input signal STU1, a first terminal connected to the fifth node QB_A, and a second terminal configured to receive the fourth voltage VGL1. Referring to FIG. 9B, the fifth control circuit 260 includes the 35th transistor M35 and the 36th transistor M36. The 35th transistor M35 has a gate terminal configured to receive the first clock signal CLKA, a first terminal connected to the sixth node QB_B, and a second terminal connected to the first terminal of the 36th transistor M36. The 36th transistor M36 has a gate terminal connected to the third node H and further has a second terminal configured to receive the fourth voltage VGL1. The sixth control circuit 270 includes the 37th transistor M37. The 37th transistor M37 has a gate terminal configured to receive the first input signal STU1, a first terminal connected to the sixth node QB_B, and a second terminal configured to receive the fourth voltage VGL1.

[0136] Referring to FIG. 9A, the fifth reset circuit 180 includes the 38th transistor M38. The 38th transistor M38 has a gate terminal configured to receive the first clock signal CLKA, a first terminal connected to the sixth node QB_B, and a second terminal connected to the first terminal of the 36th transistor M36. The 36th transistor M36 has a gate terminal connected to the third node H and further has a second terminal configured to receive the fourth voltage VGL1. The sixth control circuit 270 includes the 37th transistor M37. The 37th transistor M37 has a gate terminal configured to receive the first input signal STU1, a first terminal connected to the sixth node QB_B, and a second terminal configured to receive the fourth voltage VGL1. The sixth control circuit 270 includes the 37th transistor M37. The 37th transistor M37 has a gate terminal configured to receive the first input signal STU1, a first terminal connected to the sixth node QB_B, and a second terminal configured to receive the fourth voltage VGL1. The 37th transistor M37 has a gate terminal configured to receive the first input signal STU1, a first terminal connected to the sixth node QB_B, and a second terminal configured to receive the fourth voltage VGL1.

[0137] Referring to FIG. 9A, the fifth reset circuit 180 includes the 38th transistor M38. The sixth reset circuit 190 includes a fortieth transistor M40. The thirty-eighth transistor M3 8 has a gate terminal configured to receive a display reset signal STD, a first terminal connected to the first node Q 1, and a second terminal configured to receive a fourth voltage VGL1. The fortieth transistor M40 has a gate terminal configured to receive a full-scale reset signal TRST, a first terminal connected to the first node Q1, and a second terminal configured to receive a fourth voltage VGL 1. Referring to FIG. 9B, the seventh reset circuit 280 includes a thirty-ninth transistor M39, and the eighth reset circuit 290 includes a forty-first transistor M41. The thirty-ninth transistor M3 9 has a gate terminal configured to receive a display reset signal STD, a first terminal connected to the second node Q

[0138] 2, and a second terminal configured to receive a fourth voltage VGL1. The forty-first transistor M41 has a gate terminal configured to receive a full-scale reset signal TRST, a first terminal connected to the second node Q2, and a second terminal configured to receive a fourth voltage VGL 1. In an alternative embodiment, FIGS. 11A and 11B are circuit diagrams of respective first and second sub-units of a shift register unit that is slightly different from the shift register unit shown in FIGS. 9A and 9B. Referring to FIGS. 11A and 11B, the first sub-unit 100 further includes a third output terminal OP3 in addition to the circuit shown in FIGS. 9A and 9B. The third output terminal OP3 is configured to output a third output signal OUT3. Referring to FIGS. 11A and 11B, the first sub-unit 100 further includes a third output terminal OP3 in addition to the circuit shown in FIGS. 9A and 9B. The third output terminal OP3 is configured to output a third output signal OUT3. Referring to FIGS. 11A and 11B, the first sub-unit 100 further includes a third output terminal OP3 in addition to the circuit shown in FIGS. 9A and 9B. The third output terminal OP3 is configured to output a third output signal OUT3. Referring to FIGS. 11A and 11B, the first sub-unit 100 further includes a third output terminal OP3 in addition to the circuit shown in FIGS. 9A and 9B. The third output terminal OP3 is configured to output a third output signal OUT3.

[0139] In an alternative embodiment, FIGS. 11A and 11B are circuit diagrams of respective first and second sub-units of a shift register unit that is slightly different from the shift register unit shown in FIGS. 9A and 9B. Referring to FIGS. 11A and 11B, the first sub-unit 100 further includes a third output terminal OP3 in addition to the circuit shown in FIGS. 9A and 9B. The third output terminal OP3 is configured to output a third output signal OUT3. sub-unit 100 and the second sub-unit of a shift register unit that is slightly different from the shift register unit shown in FIGS. 9A and 9B. Referring to FIGS. 11A and 11B, the first sub-unit 100 further includes a third output terminal OP3 in addition to the circuit shown in FIGS. 9A and 9B. The third output terminal OP3 is configured to output a third output signal OUT3. The third output terminal OP3 is configured to output a third output signal OUT3. . In addition to the circuits shown in FIGS. 9A and 9B, the second sub-unit 200 further includes a fourth output terminal OP4 configured to output a fourth output signal OUT4. Accordingly , the first reset circuit 140 and the second reset circuit 150 are also configured to reset the third output terminal OP3 . The third reset circuit 240 and the fourth reset circuit 250 are also configured to reset the fourth output terminal OP4.

[0140] Referring to FIG. 11A, in addition to the circuit shown in FIG. 9A, the first output circuit 120 further includes a twenty-sixth transistor M26 and a fourth capacitor C4. The twenty-sixth transistor M26 has a gate terminal connected to the first node Q1, a first terminal configured to receive the fifth clock signal CLKE , and a second terminal connected to the third output terminal OP3. The fourth capacitor C4 has a first terminal connected to the first node Q1 and a second terminal connected to the third output terminal OP3 .

[0141] In one example, the fifth clock signal CLKE is configured to be the same as the third clock signal CLKC . In another example, the fifth clock signal CLKE is configured to be different from the third clock signal C LKC, such that the first output terminal OP1 and the third output terminal OP3 can output different signals, enhancing the diversity of the shift register unit that provides a plurality of different drive signals.

[0142] The first reset circuit 140 in FIG. 11A further includes a twenty-seventh transistor M27, and the twenty-seventh transistor M27 has a gate terminal connected to the fifth node QB_A and a third output A first terminal connected to terminal OP3 and a second terminal configured to receive a fifth voltage VGL2. The second reset circuit 150 in FIG. 11A further includes a twenty-eighth transistor M2 8. The twenty-eighth transistor M28 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the third output terminal OP3, and a second terminal configured to receive a fifth voltage VGL2.

[0143] Referring to FIG. 11B, the second output circuit 220 further includes a twenty-ninth transistor M29 and a fifth capacitor C5 in addition to the circuit of FIG. 9B. The twenty-ninth transistor M29 has a gate terminal connected to the second node Q2, a first terminal configured to receive a sixth clock signal CLKF, and a second terminal connected to the fourth output terminal OP4. The fifth capacitor C5 has a first terminal connected to the second node Q2 and a second terminal connected to the fourth output terminal OP4.

[0144] In one embodiment, the sixth clock signal CLKF is configured to be the same as the fourth clock signal CLKD. In another embodiment, the sixth clock signal CLKF is configured to be different from the fourth clock signal CLKD. As a result, the second output terminal OP2 and the fourth output terminal OP4 can each output different signals, enhancing the diversity of the shift register unit that provides a plurality of different drive signals.

[0145] The third reset circuit 240 in FIG. 11B further includes a thirtieth transistor M30. The thirtieth transistor M30 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the fourth output terminal OP4, and a second terminal configured to receive a fifth voltage VGL2. ​ has terminals. The fourth reset circuit 250 in FIG. 11B further includes a thirty-first transistor M3 1, and the thirty-first transistor M31 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the fourth output terminal OP4, and a second terminal configured to receive the fifth voltage VGL2. has a second terminal configured to receive the fifth voltage VGL2. As described above, in the shift register unit 10 (or 10A, 10B, 10C) according to the embodiment of the present disclosure, the voltage level at the third node H can be maintained by the first capacitor C1. The voltage level at the first node Q1 can be maintained by the second capacitor C2 and the fourth capacitor C4 (with an error of at most 10%). The voltage level at the second node Q2 can be maintained by the third capacitor C3 and the fifth capacitor C5. The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be capacitor elements manufactured by a thin film process. For example, dedicated capacitor electrodes may be manufactured to realize the capacitor elements. The electrodes can be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc., or in some examples, by designing circuit routing parameters, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by the parasitic capacitance between various elements. The connection method of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 is not limited to the above method. Any other suitable connection method may be used as long as the charge can be written into the voltage levels of the third node H, the first node Q1, and the second node Q2.

[0146] As described above, in the shift register unit 10 (or 10A, 10B, 10C) according to the embodiment of the present disclosure, the voltage level at the third node H can be maintained by the first capacitor C1. The voltage level at the first node Q1 can be maintained by the second capacitor C2 and the fourth capacitor C4 (with an error of at most 10%). The voltage level at the second node Q2 can be maintained by the third capacitor C3 and the fifth capacitor C5. The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be capacitor elements manufactured by a thin film process. For example, dedicated capacitor electrodes may be manufactured to realize the capacitor elements. The electrodes can be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc., or in some examples, by designing circuit routing parameters, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by the parasitic capacitance between various elements. The connection method of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 is not limited to the above method. Any other suitable connection method may be used as long as the charge can be written into the voltage levels of the third node H, the first node Q1, and the second node Q2. The voltage level at the first node Q1 can be maintained by the second capacitor C2 and the fourth capacitor C4 (with an error of at most 10%). The voltage level at the second node Q2 can be maintained by the third capacitor C3 and the fifth capacitor C5. The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be capacitor elements manufactured by a thin film process. For example, dedicated capacitor electrodes may be manufactured to realize the capacitor elements. The electrodes can be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc., or in some examples, by designing circuit routing parameters, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by the parasitic capacitance between various elements. The connection method of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 is not limited to the above method. Any other suitable connection method may be used as long as the charge can be written into the voltage levels of the third node H, the first node Q1, and the second node Q2. The voltage level at the second node Q2 can be maintained by the third capacitor C3 and the fifth capacitor C5. The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be capacitor elements manufactured by a thin film process. For example, dedicated capacitor electrodes may be manufactured to realize the capacitor elements. The electrodes can be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc., or in some examples, by designing circuit routing parameters, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by the parasitic capacitance between various elements. The electrodes can be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc., or in some examples, by designing circuit routing parameters, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by the parasitic capacitance between various elements. The electrodes can be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc., or in some examples, by designing circuit routing parameters, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by the parasitic capacitance between various elements. The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by the parasitic capacitance between various elements. The connection method of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 is not limited to the above method. Any other suitable connection method may be used as long as the charge can be written into the voltage levels of the third node H, the first node Q1, and the second node Q2. Any other suitable connection method may be used as long as the charge can be written into the voltage levels of the third node H, the first node Q1, and the second node Q2. Any other suitable connection method may be used as long as the charge can be written into the voltage levels of the third node H, the first node Q1, and the second node Q2. Any other suitable connection method may be used as long as the charge can be written into the voltage levels of the third node H, the first node Q1, and the second node Q2.

[0147] When the first node Q1, the second node Q2, or the third node H is maintained at a high voltage level, Some transistors (the first transistor M1, the fourteenth transistor M14, the seventeenth transistor M17, the thirty-eighth transistor M38, the fortieth transistor M40, the twenty-second transistor M22, the twenty-fourth transistor M24, the thirty-ninth transistor M39, and the forty-first transistor M41, etc.) have their first terminals connected to the first node Q1, the second node Q2, or the third node H, respectively, and their second terminals connected to a low voltage level. The gate terminals of these transistors receive a turn-off signal, but due to the voltage level difference between the first and second terminals, there is still a possibility of leakage between the first and second terminals. Due to this leakage problem, the stability of maintaining the voltage level at the first node Q1, the second node Q2, or the third node H is reduced.

[0148] Figures 12A to 12C are circuit diagrams of a shift register unit including a leakage prevention circuit structure according to some embodiments of the present disclosure. Referring to Figures 12A and 12B, the shift register unit further includes a common leakage prevention circuit, a first leakage prevention circuit, and a second leakage prevention circuit. In particular, the common leakage prevention circuit is electrically connected to the first node Q1 and the seventh node OF, and is configured to control the voltage level of the seventh node OF in response to the voltage level of the first node Q1. The first leakage prevention circuit is connected to the seventh node OF, the first reset circuit 140, the second reset circuit 150, the fifth reset circuit 180, and the sixth reset circuit 190, and is configured to prevent leakage at the first node Q1 in response to the voltage level of configured to prevent. The second leakage prevention circuit is connected to the seventh node OF, the third reset circuit 240, the fourth reset circuit 250, the seventh reset circuit 280, and the eighth reset circuit 29 0, and is configured to prevent leakage at the second node Q2 in response to the voltage level at the seventh node OF.

[0149] For example, as shown in FIGS. 12A and 12B, the common leakage prevention circuit includes a forty-fourth transistor M44, and the forty-fourth transistor M44 has a gate terminal connected to the first node Q1, a first terminal configured to receive a sixth voltage VB, and a second terminal connected to the seventh node OF. The first leakage prevention circuit includes transistors M14_b, M17_b, M38_b, and M40_b. The second leakage prevention circuit includes transistors M22_b, M24_b, M39_b, and M41_b.

[0150] Furthermore, referring to FIG. 12A, in order to prevent leakage from the third node H, a forty-third transistor M43 and a transistor M1_b are added to the circuit. The transistor M1_b has a gate terminal connected to the gate of the first transistor M1. The transistor M1_b has a first terminal connected to the second terminal of the forty-third transistor M43. The transistor M1_b has a second terminal connected to the third node H. The forty-third transistor M43 has a gate terminal connected to the third node H. The forty-third transistor M43 has a first terminal configured to receive a sixth voltage VB (high voltage). When a high voltage level is applied to the third node H, the forty-third transistor M43 turns on, and as a result, the high voltage ​​​​​​​​​​​​​The sixth voltage VB of the level can be input to the first terminal of the transistor M1_b, and both the first terminal and the second terminal of the transistor M1_ b are at a high voltage level, and the charge of the third node H is prevented from leaking through the transistor M1_b. At this time, the gate terminal of the transistor M1_b is connected to the gate terminal of the first transistor M1. The combination of the first transistor M1 and the transistor M1_b realizes the same function as the first transistor M1, and at the same time can prevent leakage.

[0151] Similarly, as shown in FIG. 12A, the transistors M14_b, M17_b, M38_b and M40_b are connected to the 44th transistor M44 via the seventh node OF, and each can realize a leakage prevention function for preventing leakage from the first node Q1. As shown in FIG. 12B, the transistors M22_b, M24_b, M39_b and M41_b are also connected to the 44th transistor M44 via the seventh node OF, and each can realize a leakage prevention function for preventing leakage from the second node Q2. Referring to FIGS. 12A and 12B, the first leakage prevention circuit and the second leakage prevention circuit share one 44th transistor M44, saving the number of transistors, reducing the size of the frame, and improving the PPI of the display device. Referring to FIGS. 12A and 12B, the first leakage prevention circuit and the second leakage prevention circuit share one 44th transistor M44, saving the number of transistors, reducing the size of the frame, and improving the PPI of the display device. In an alternative embodiment shown in FIG. 12C, the second leakage prevention circuit (transistors M22_b, M24_b, M39_

[0152] associated with the second sub-unit of the shift register unit is not connected to the seventh node OF shared with the first sub-unit of the shift register unit. Instead, the second leakage prevention circuit mentioned here is connected to the seventh node OF shared with the first sub-unit of the shift register unit. Instead, the second leakage prevention circuit mentioned here is Connected in common to a separate 45th transistor M45 and coupled to a single 8th node to form a leakage prevention structure is set.

[0153] Similarly, as shown in FIG. 6, in the case of the 3rd transistor M3 and the 4th transistor M4 a leakage prevention structure can be realized by installing two different transistors M3_b and M4_b. In particular, the transistors M3_b and M4_b are configured such that their gate terminals receive the 1st clock signal CL KA, and their 1st terminals are coupled to the 7th node OF to connect to the 44th transistor M44 in FIG. 1 2A to establish a leakage prevention structure. This leakage prevention structure can prevent leakage from both the 1st node Q1 and the 2nd node Q2.

[0154] Similarly, as shown in FIG. 10C, in the case of the 5th transistor M5, a leakage prevention structure can be installed by adding the transistor M5 _b. In particular, the gate terminal of the transistor M5_b is configured to receive the 1st input signal STU1, and the 1st terminal of the transistor M5_b is coupled to the 7th node OF to establish a connection with the 44th transistor M44 in FIG. 12A . The leakage prevention structure can prevent leakage from the 1st node Q1.

[0155] In an alternative embodiment, the scanning transistor and the sensing transistor in the sub-pixel unit of the display panel may be selected as P-type transistors. In this case, FIGS. 1 3A and 13B show the circuit diagrams of the respective 1st sub-unit and 2nd sub-unit of a shift register unit according to another embodiment of the present disclosure. The shift register units shown in FIGS. 13A and 13 B are cascaded to form a gate driving circuit ​​used as one of a plurality of units to drive display scanning and external compensation, the can be implemented on a display panel.

[0156] All transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other switching elements having the same characteristics. In the embodiments of the present disclosure, thin-film transistors will be described as an example. Since the source and drain of the transistors used here can be structurally symmetric, the source and drain are structurally indistinguishable. In the embodiments of the present disclosure, to distinguish the two terminals of the transistor excluding the gate terminal, one of the two terminals is referred to as the first terminal and the other is referred to as the second terminal. Also, the transistor can be divided into an N-type transistor and a P-type transistor according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltage). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltage). or other suitable voltage), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0157] In another aspect, the present disclosure provides a gate driving circuit fabricated by cascading a plurality of shift register units in multiple stages in series. FIG. 14 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure. Referring to FIG. 14, the gate driving circuit 20 includes multiple stages of shift register units 10. Here, each of the plurality of shift register units ​ 々 is substantially the shift register unit 1 described in this specification throughout the entire specification is 0. The notations A1, A2, A3, A4, A5, and A6 in FIG. 14 respectively represent the sub-units of the shift register unit 10. For example, A1, A3, and A5 respectively represent the three first sub-units of three shift register units, and A2, A4, and A 6 respectively represent the three second sub-units of three shift register units.

[0158] Referring to FIG. 14, each shift register unit 10 includes a first sub-unit and a second sub-unit, and outputs a first output signal OUT1 and a second output signal OUT2 respectively. When the gate driving circuit 20 is applied to drive the display panel, the first output signal OUT1 and the second output signal OUT2 can drive the sub-pixel units of one row of the display panel individually. For example, A1, A2, A3, A4, A5, and A6 can drive the sub-pixel units of the first row, the second row, the third row, the fourth row, the fifth row, and the sixth row in the display panel respectively.

[0159] The gate driving circuit 20 of the present disclosure shares a blank input sub-unit to reduce the size of the frame of the display device using the gate driving circuit and improve the PPI of the display device. At the same time, the gate driving circuit provides external compensation to the driving transistors in the sub-pixel units of randomly selected rows, and avoids the luminance non-uniformity caused by the exposure of virtual scanning lines and sequential compensation for each row on the display panel.

[0160] Referring to FIG. 14, cascaded by a multi-stage shift register unit 10 ​​​​​The gate driving circuit 20 includes a first sub - clock signal line CLK_1, a second sub - clock signal line CLK_2, and a third sub - clock signal line CLK_3. The (3n - 2)-th stage shift register unit is connected to the first sub - clock signal line CLK_1 and receives the second clock signal CLKB at the (3n - 2)-th stage shift register unit has a first sub - unit that receives the second clock signal CLKB. The (3n - 1)-th stage shift register unit is connected to the second sub - clock signal line CLK_2 and has a first sub - unit that receives the second clock signal CLKB of the (3n - 1)-th stage shift register unit. The 3n - th stage shift register unit is connected to the third sub - clock signal line CLK_3 and has a first sub - unit that receives the second clock signal CLKB of the 3n - th stage shift register unit. Here, n is a positive integer. As shown optionally, the second clock signal CLKB can be provided to each first sub - unit of each stage shift register unit that functions as a cascaded member of the gate driving circuit. The second clock signal CLKB can be used as the shift register signal CR output to drive the shift scanning through the display panel. Referring to FIG. 14, the gate driving circuit 20 further includes a fourth sub - clock signal line CLK_4, a fifth sub - clock signal line CLK_5, a sixth sub - clock signal line CLK_6, a seventh sub - clock signal line CLK_7, an eighth sub - clock signal line CLK_8, and a ninth sub - clock signal line CLK_9. The first sub - unit of the (3n - 2)-th stage shift register unit is the fourth sub - clock signal line CLK_4.

[0161]

[0162] ​​​​​​Connected to the signal line CLK_4, it receives the third clock signal CLKC of the (3n - 2)-th stage shift register unit. The second sub-unit of the (3n - 2)-th stage shift register unit is connected to the fifth sub-clock signal line CLK_5 and receives the fourth clock signal CLKD of the (3n - 2)-th stage shift register unit.

[0163] The first sub-unit of the (3n - 1)-th stage shift register unit is connected to the sixth sub-clock signal line CLK_6 and receives the third clock signal CLKC of the (3n - 1)-th stage shift register unit. The second sub-unit of the (3n - 1)-th stage shift register unit is connected to the seventh sub-clock signal line CLK_7 and receives the fourth clock signal CLKD of the (3n - 1)-th stage shift register unit.

[0164] The first sub-unit of the 3n-th stage shift register unit is connected to the eighth sub-clock signal line CLK_8 and receives the third clock signal CLKC of the 3n-th stage shift register unit. The second sub-unit of the 3n-th stage shift register unit is connected to the ninth sub-clock signal line CLK_9 and receives the fourth clock signal CLKD of the 3n-th stage shift register unit.

[0165] Through the six clock signal lines of the fourth sub-clock signal line CLK_4, the fifth sub-clock signal line CLK_5, the sixth sub-clock signal line CLK_6, the seventh sub-clock signal line CLK_7, the eighth sub-clock signal line CLK_8, and the ninth sub-clock signal line CLK_9, signals are sequentially provided to each stage of the shift register unit one by one and output as respective drive signals. Therefore, the drive signals output from the gate drive circuit have overlapping waveforms. Optionally, the pre-charge time of the sub-pixel units in each row can be effectively increased, and as a result, the gate drive circuit can be suitable for high-frequency scanning display. Alternatively, the gate drive circuit 20 employs eight clock signals. Optionally, the gate drive circuit 20 employs ten clock signals.

[0166] Referring to FIG. 14, the gate drive circuit 20 further includes a 10th sub-clock signal line CLK_10 and an 11th sub-clock signal line CLK_11 and a 12th sub-clock signal line CLK_12. The first sub-unit and the second sub-unit of each stage of the shift register unit 10 are commonly connected to the 10th sub-clock signal line CLK_10 to receive a full-scale reset signal TRST. Each stage of the shift register unit 10 has a common input circuit 310 commonly connected to the 11th sub-clock signal line CLK_11 to receive a selection control signal OE. The first sub-unit, the second sub-unit and the common input circuit 310 of each stage of the shift register unit 10 are commonly connected to the 12th sub-clock signal line CLK_12 to receive a first clock signal CLKA.

[0167] Referring to FIG. 14, the gate drive circuit 20 further includes a 13th sub-clock signal line CLK_13 and a 14th sub-clock signal line CLK_14. The first sub-unit of each stage of the shift register unit 10 is connected to the 13th sub-clock signal line CLK_13 to receive a second voltage VDD_A. The second sub-unit of each stage of the shift register unit 10 is connected to the 14th sub-clock signal line CLK_14 to receive a third voltage VDD_B.

[0168] Referring to FIG. 14, the gate driving circuit 20 further includes a 15th sub - clock signal line CLK_15 The first sub - unit and the second sub - unit of the first - stage shift register unit 10 are both connected to the 15th sub - clock signal line CLK_15 to receive the first input signal S TU1.

[0169] Referring to FIG. 14, except for the first - stage shift register unit 10, the first sub - unit and the second sub - unit of each other stage of the shift register unit are connected to the first sub - unit in the shift register unit 10 of the previous stage and are configured to receive the shift register signal CR as their own first input signal STU1. Except for the last two - stage shift register units, the first sub - unit and the second sub - unit of each other stage of the shift register unit 10 are connected to the first sub - unit of the next two - stage shift register unit 10 and are configured to receive the shift register signal CR as their own display reset signal STD.

[0170] FIG. 14 is just one of many examples regarding the cascading method from stage to stage. In one embodiment, the shift register unit 10 in the gate driving circuit 20 may adopt the circuit structures shown in FIGS. 9A and 9B.

[0171] FIG. 15 is a timing diagram for operating the gate driving circuit of FIG. 14 according to an embodiment of the present disclosure. Referring to FIG. 15, H<5> represents the third node H in the third - stage shift register unit 10. The third - stage shift register unit 10 is the third one in the display panel ​​​​​​​​​​​​It corresponds to the sub-pixel units of the 5th and 6th rows. N<5> is the shift register of the 3rd stage It represents the 4th node N in the shift register unit 10. Q1<1> and Q2<2> are respectively the 1st node Q1 and the 2nd node Q2 of the shift register unit 10 in the 1st stage. Q1<5> and Q2<6> are respectively the 1st node Q1 of the shift register unit 10 in the 3rd stage and the 2nd node Q2. The numbers within the < > brackets represent the number of rows of the sub-pixel units in the display panel corresponding to the nodes Q1 and Q2.

[0172] OUT1<1> and OUT2<2> respectively represent the 1st output signal OUT1 and the 2nd output signal OUT2 output from the shift register unit 10 in the 1st stage Similarly, OUT1<3> and OUT2<4> respectively represent the 1st output signal OUT1 and the 2nd output signal OUT2 output from the shift register unit 10 in the 2nd stage OUT1<5> and OUT2<6> respectively represent the 1st output signal OUT1 and the 2nd output signal OUT2 output from the shift register unit 10 in the 3rd stage CR<1>, CR<3> and CR<5> respectively represent the shift register signals CR output from the shift register units 10 in the 1st stage, the 2nd stage and the 3rd stage Referring to FIG. 15, in one example, CR<1> is the same as OUT1<1>. CR<3> is the same as OUT1<3>. CR<5> is the same as OUT 1<5>. 1F represents the 1st frame (cycle time for displaying one frame of an image). DS is the display period in the 1st frame. BL is the blank period in the 1st frame In the example shown in FIG. 15, the second voltage VDD_A is provided as a low voltage, and the third

[0173] voltage VDD_B is provided as a high voltage. represents the high voltage. In the example shown in FIG. 15, the second voltage VDD_A is provided as a low voltage, and the third The voltage VDD_B is provided as a high voltage.

[0174] Before the start of the first frame (displaying one frame of an image) 1F, the tenth sub-block The signal line CLK_10 and the eleventh sub-block signal line CLK_11 both provide high voltage signals. The fortieth transistor M40 and the forty-first transistor M41 in each stage of the shift register unit 10 both turn on. The voltage levels at the first node Q1 and the second node Q2 in each stage of the shift register unit 10 are reset. The first transistor M1 in each stage of the shift register unit 10 also turns on. At this time, the second input signal STU2 received is a low voltage signal, which is used to reset the voltage level of the third node H in each stage of the shift register unit 10, thereby achieving a full-scale reset before the start of the first frame 1F.

[0175] During the display period DS of the first frame 1F, the operation of the third-stage shift register unit 10 (corresponding to the sub-pixel units in the fifth and sixth rows on the display panel) is cited here as an example to explain how the gate driving circuit 20 drives the display panel for displaying images frame by frame.

[0176] In the first period 1 of DS, the second-stage shift register unit 10 has a first sub-unit that outputs the shift register signal CR<3> as a high voltage signal. This is then used as the third-stage shift register unit 10. In other words, the third-stage shift register unit receives the high voltage first input signal STU1. Therefore, the third ​​​​​​​​​​​The fifth transistor M5 and the eighth transistor M8 in the shift register unit 10 of the segment both turn on. The first voltage VDED to which a high voltage is supplied from the power supply charges the first node Q1<5> through the fifth transistor M5 and charges the second node Q2<6> through the eighth transistor M8. Therefore, both the first node Q1<5> and the second node Q2<6> are pulled up to the high voltage level.

[0177] The seventh transistor M7 in the shift register unit 10 of the third stage is turned on by the high voltage at the first node Q1<5>. However, at this time, the third clock signal CLKC provided through the eighth subclock signal line CLK_8 is a low voltage signal. Therefore, the first output signal OUT1<5> from the shift register unit 10 of the third stage is a low voltage signal . The ninth transistor M9 in the shift register unit 10 of the third stage is turned on by the high voltage at the second node Q2<6>. However, at this time, the fourth clock signal CLKD provided through the ninth subclock signal line CLK _9 is a low voltage signal. Therefore, the second output signal OUT2<6> from the shift register unit 10 of the third stage is a low voltage signal . During this period 1, the pre-charging operations for both the first node and the second node in the shift register unit of the third stage are completed.

[0178] In the second period 1 of DS, the third clock signal CLKC provided through the eighth subclock signal line CLK_8 is changed to a high voltage signal. The voltage level at the first node Q1<5> is further pulled up higher by the bootstrap effect, maintaining the seventh transistor M7 in the conducting state. The first output signal OUT from the shift register unit 10 of the third stage ​​​​​1<5> is also changed to a high - voltage signal from CLKC. However, at this time, the fourth clock signal CLKD provided via the signal line CLK_9 of the ninth sub - clock is still a low - voltage signal. Therefore, the second output signal OUT 2<6> from the third - stage shift register unit 10 remains a low - voltage signal. 2<6> is still a low - voltage signal.

[0179] In the third period 3 of DS, the fourth clock signal CLKD provided via the ninth sub - clock signal line CLK_9 is changed to a high - voltage signal. The voltage level <6> at the second node Q2 is pulled up higher by the bootstrap effect. The ninth transistor M9 is maintained in the conducting state. Therefore, the second output signal OUT2<6> output from the third - stage shift register unit 10 becomes a high - voltage signal. is maintained in the conducting state. Therefore, the second output signal OUT2<6> output from the third - stage shift register unit 10 becomes a high - voltage signal. is a high - voltage signal.

[0180] In the fourth period 4 of DS, due to the charge - holding effect of the second capacitor C2, the first node Q 1<5> remains at a high - voltage level. Therefore, the seventh transistor M7 is in the conducting state. However, the third clock signal CLKC provided via the eighth sub - clock signal line CLK_8 is changed to a low - voltage signal. Therefore, the first output signal OUT1<5> from the third - stage shift register unit 10 is also changed to a low - voltage signal. At the same time, due to the bootstrap effect of the second capacitor C2, the voltage level at the first node Q1<5> also relatively decreases. relatively decreases. relatively decreases.

[0181] In the fifth period 5 of DS, due to the charge - holding effect of the third capacitor C3, the second node Q 2<6> remains at a high - voltage level. Therefore, the ninth transistor M9 is in the conducting state. However, the fourth clock provided via the ninth sub - clock signal line CLK_9 The clock signal CLKD is changed to a low voltage signal. Therefore, the third-stage shift register unit The second output signal OUT2<6> from the tenth unit is also changed to a low voltage signal. At the same time, the third Due to the bootstrap effect of the capacitor C3, the voltage level at the second node Q2<6> also relatively decreases.

[0182] In the sixth period 6 of DS, based on the assumption that six clock signals are adopted in the gate driving circuit 20, the signals output from the shift register unit 10 every three stages (that is, the first output signal OUT1 and the second output signal OUT2 from each stage) are repeated in cycles . At the same time, the third-stage shift register unit 10 is configured to receive the shift register signal CR from the fifth-stage shift register unit as its own display reset signal STD. During the sixth period 6, the third clock signal CLKC provided via the sixth sub-clock signal line CLK_6 is changed to a high voltage signal. Here, the display reset signal STD received by the third-stage shift register unit 10 is also a high voltage signal, and both the 38th transistor M38 and the 39th transistor M39 are in a conductive state. Therefore, the first node Q1<5> and the second node Q2<6> can complete the pulling-down or reset operation using the fourth voltage VGL1 provided with a low voltage.

[0183] After the third-stage shift register unit 10 drives the sub-pixel units in the fifth row and the sub-pixel units in the sixth row on the display panel to be displayed in their respective rows, the gate driving circuit 20 drives the fourth-stage shift register unit, or subsequently the fifth-stage shift register Activate the distortion unit (the same applies hereinafter) until the display period DS of the first frame 1F ends. Drive all the sub-pixel units in all rows of the display panel until the display of one frame of image is completed.

[0184] Furthermore, during the display period DS of the first frame 1F, the gate drive circuit 20 is also configured to charge the third node H For example, when compensation for the sub-pixel units in the fifth row during the display operation within the first frame 1F is required, the compensation operation is performed as follows . .

[0185] During the second period 2 and the third period 3 of DS, the 11th sub-clock signal line CLK_11 is configured to provide the same signal as the shift register signal CR<5> output from the three-stage shift register unit 10, turning on the first transistor M1. At the same time, the second input signal STU2 received by the three-stage shift register unit 10 can be configured to be the same as the shift register signal CR<5>. Therefore, by charging the third node H<5> using the high voltage from the second input signal STU2, the voltage level of the third node H<5> can be pulled up to the high voltage level.

[0186] In an alternative embodiment, the second input signal STU2 received by the three-stage shift register unit 10 is selectively the same as the shift register signal CR output from other stages of the shift register unit, and at the same time, the signal provided via the 11th sub-clock signal line CLK_11 has the same signal timing as the second input signal STU2.

[0187] The high voltage at the third node H<5> remains until the blank period BL of the first frame 1F starts. It may be maintained constantly. When the sub-pixel unit in the 5th row requires external compensation during the first frame 1F the operation of the shift register unit in the 3rd stage in the gate driving circuit is performed as follows.

[0188] In the 7th period 7(BL) of the first frame 1F, due to the coupling effect of the first capacitor C1, the fourth node N<5> changes its voltage level from low voltage to high voltage, and this raises the voltage level of the third node H<5>. Therefore, the voltage level at the third node H<5> is maintained at a relatively high level, ensuring that the second transistor M2 is in a fully conductive state During this period, the first clock signal CLKA provided via the 12th sub-clock signal line CLK_12 is changed from a high voltage signal to a low voltage signal. Therefore, the fourth node N<5> also becomes low voltage. Due to the coupling effect of the first capacitor C1 the voltage level at the third node H<5> also decreases.

[0189] In the 8th period 8(BL) of the first frame 1F, the third clock signal CLKC provided via the 8th sub-clock signal line CLK_8 is changed to a high voltage signal. The voltage level at the first node Q1<5> is further pushed up higher by the bootstrap effect to maintain the seventh transistor M7 in a conductive state. Therefore, the first output signal OUT1<5> output from the shift register unit 10 in the 3rd stage is changed to a high voltage signal. However, since the fourth clock signal CLKD provided via the 9th sub-clock signal line CLK_9 is still a low voltage signal, the output from the shift register unit 10 in the 3rd stage The second output signal OUT2<6> is a low voltage signal. In one example, the first output signal OUT1<5> in the eighth period 8 is used to drive the sense transistors in the sub-pixel units of the display panel to drive the display panel to display an image frame with uniform luminance, thereby realizing external compensation.

[0190] In the ninth period 9 (BL) of the first frame 1F, due to the charge holding effect of the second capacitor C2, the first node Q1<5> remains at a high voltage, and the seventh transistor M7 is held in the conducting state. However, since the third clock signal CLKC provided via the eighth sub-clock signal line CLK_8 is changed to a low voltage signal, the first output signal OUT1<5> output from the third-stage shift register unit 10 also changes to a low voltage signal. At the same time, due to the bootstrap effect of the second capacitor C2, the voltage level at the first

[0191] node Q1<5> also decreases. In the tenth period 10 (BL) of the first frame 1F, both the tenth sub-clock signal line CLK_10 and the eleventh sub-clock signal line CLK_11 provide high voltage signals. The fortieth transistor M40 and the forty-first transistor M41 in each stage of the shift register unit 10 of the gate drive circuit 20 are turned on. As a result, the first node Q1 and the second node Q2 of each stage of the shift register unit 10 can be reset at their voltage levels. Further, the first transistor M1 in each stage of the shift register unit 10 is turned on. Since the A full-scale reset for the gate drive circuit can be completed by Frame 1F ends. The game in the following frames 2 and 3 (and so on) The driving operation of the light driver is substantially the same and will not be described repeatedly.

[0192] In one embodiment, the gate drive circuit drives the first gate of the display panel during a blank period of one frame. Output a driving signal for driving a sensing transistor in the sub-pixel unit of n rows. If necessary, the third node H is pulled up to a high voltage level during the display period of the same frame. At the same time, during the blank period of the one frame, the first clock of high voltage must be Providing a signal CLKA to raise the voltage levels of the first node Q1 and the second node Q2; If a high-voltage driving signal needs to be output, a high-voltage third clock is required. A signal CLKC or a fourth clock signal CLKD is required, where n is any positive integer. Optionally, the timing of two signals is the same, i.e., they are synchronized in time. This means that the signal amplitudes are the same, but not necessarily the same.

[0193] FIG. 16 illustrates a timing diagram for operating the gate drive circuit of FIG. 14 according to another embodiment of the present disclosure. In one embodiment, the gate drive circuit 20 operates according to the timing diagram. 13A and 13B, a plurality of shift register units based on the circuit shown in FIG. The timing sequence and operation principle are shown in Figure 15. Similar to the description.

[0194] FIG. 17 is a schematic diagram of a gate drive circuit according to another embodiment of the present disclosure. In this case, the gate drive circuit 20A is provided by cascade-connecting a plurality of shift register units based on the circuits shown in FIG. 11A or FIG. 12A and FIG. 11B or FIG. 12B. The shift register units in the odd-numbered stages (for example, A1, A3, A5) respond to the clock signals from the clock signal lines CLKE_N (N = 1, 3, 5) and output a first output signal OUT1. <n>Outputs, and is configured to output a second output signal OUT2 in response to a clock signal from a clock signal line CLKF_N (N = 1, 3, 5). Different from the odd-stage shift register units in the gate drive circuit 20 simply outputs one output signal OUT1. Here, CLKE_1h is configured to supply the third clock signal CLKC (see FIG. 11A or FIG. 12A), and CLKF_1 is configured to supply the fifth clock signal CLKE (see FIG. 11A or FIG. 12A). Each shift register unit (for example, A2, A4, A6) in the even stage outputs the first output signal OUT1 in response to a clock signal from a clock signal line CLKE_N (N = 2, 4 , 6). (see FIG. 11A or FIG. 12A). <n>Outputs and the clock signal The second output signal OUT is configured to be output in response to the clock signal from the clock signal line CLKF_N (N = 2, 4, 6). Unlike the even-stage shift register units in the gate drive circuit 20, it simply outputs one output signal OUT2. Here, CLKE_2 is configured to supply the fourth clock signal CLKD (see FIG. 11B or FIG. 12B), and CLKF_2 is configured to supply the sixth clock signal CLKF (see FIG. 11B or FIG. 12B). FIG. 18 shows a timing diagram for operating the gate drive circuit 20A according to an embodiment of the present disclosure. Referring to FIG. 18, the operation of the gate drive circuit 20A adopts a similar method to that described for the gate drive circuit 20 in FIG. 15, except that the waveforms of Q1<3> and Q2<4> are added during the DS period of one frame 1F. However, Q1<3> and Q2<4> are substantially the same as the waveforms of Q1<1> and Q2<2> except for the time shift determined by the clocks on the clock signal lines CLKE_4 and CLKF_4, respectively.

[0195] FIG. 19 is a schematic diagram of a gate drive circuit according to another embodiment of the present disclosure. The gate drive circuit 20B is provided as shown in FIG. 19. FIG. 20 shows a timing diagram for operating the gate drive circuit of FIG. 19 according to an embodiment of the present disclosure. Some differences between the gate drive circuit 20B in FIG. 19 and the gate drive circuit 20 in FIG. 14 are shown below.

[0196] Referring to FIGS. 19 and 20, in this embodiment, the gate drive circuit 20B employs 1 0 clock signal lines. The fourth sub-clock signal line CLK_4 and the fifth sub-clock The clock signal line CLK_5, the sixth sub-clock signal line CLK_6, and the seventh sub-clock signal line CLK_7, the eighth sub-clock signal line CLK_8, and the ninth sub-clock signal line CLK_9 and the fifteenth sub-clock signal line CLK_15, the sixteenth sub-clock signal line CLK_16, and the seventeenth sub-clock signal line CLK_17 and the eighteenth sub-clock signal line CLK_18 are adopted, and a total of 10 clock signal lines are used to provide drive signals output row by row from each stage of the shift register unit in the cascaded gate drive circuit. In this embodiment, since 10 clock signal lines are used, the pre-charge time of the sub-pixel units in each row is further increased. As a result, the gate drive circuit 20B is more suitable for driving scanning display at a higher frequency. In this embodiment, since 10 clock signal lines are used, the pre-charge time of the sub-pixel units in each row is further increased. As a result, the gate drive circuit 20B is more suitable for driving scanning display at a higher frequency. In this embodiment, since 10 clock signal lines are used, the pre-charge time of the sub-pixel units in each row is further increased, and as a result, the gate drive circuit 20B is more suitable for driving scanning display at a higher frequency. In this embodiment, since 10 clock signal lines are used, the pre-charge time of the sub-pixel units in each row is further increased, and as a result, the gate drive circuit 20B is more suitable for driving scanning display at a higher frequency.

[0197] In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units connected in series in cascade, each other stage of shift register unit is connected to the first sub-unit of the previous two stages of shift register units and is configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units connected in series in cascade, each other stage of shift register unit is also connected to the first sub-unit in each of the next four stages and receives the shift register signal CR as its indicated reset signal STD. In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units connected in series in cascade, each other stage of shift register unit is connected to the first sub-unit of the previous two stages of shift register units and is configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units connected in series in cascade, each other stage of shift register unit is also connected to the first sub-unit in each of the next four stages and receives the shift register signal CR as its indicated reset signal STD. In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units connected in series in cascade, each other stage of shift register unit is connected to the first sub-unit of the previous two stages of shift register units and is configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units connected in series in cascade, each other stage of shift register unit is also connected to the first sub-unit in each of the next four stages and receives the shift register signal CR as its indicated reset signal STD. In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units connected in series in cascade, each other stage of shift register unit is connected to the first sub-unit of the previous two stages of shift register units and is configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units connected in series in cascade, each other stage of shift register unit is also connected to the first sub-unit in each of the next four stages and receives the shift register signal CR as its indicated reset signal STD. In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units connected in series in cascade, each other stage of shift register unit is connected to the first sub-unit of the previous two stages of shift register units and is configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units connected in series in cascade, each other stage of shift register unit is also connected to the first sub-unit in each of the next four stages and receives the shift register signal CR as its indicated reset signal STD. In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units connected in series in cascade, each other stage of shift register unit is connected to the first sub-unit of the previous two stages of shift register units and is configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units connected in series in cascade, each other stage of shift register unit is also connected to the first sub-unit in each of the next four stages and receives the shift register signal CR as its indicated reset signal STD. In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units connected in series in cascade, each other stage of shift register unit is connected to the first sub-unit of the previous two stages of shift register units and is configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units connected in series in cascade, each other stage of shift register unit is also connected to the first sub-unit in each of the next four stages and receives the shift register signal CR as its indicated reset signal STD.

[0198] Referring to FIG. 19, the tenth sub-clock signal line CLK_10 is connected to the first sub-unit and the second sub-unit (i.e., A1, A2, A of each of the previous two stages of shift register units 3 and A4) to provide the first input signal STU1 (for the third stage shift register unit At the same time, the tenth sub-clock signal line CLK_10 provides , and is connected to the shift register unit of another stage to provide a full-scale reset signal TRST. This signal line layout can reduce the number of clock signal lines and reduce the number of clock signal lines. This facilitates reducing the size of the picture frame of a display device using the circuit, and can improve the PPI of the display device. In one example, the first two stages of the shift register unit may optionally include a fourth The 0th transistor M40 and the 41st transistor M41 may not be included.

[0199] Referring to FIG. 20, the sub-pixel unit in the 11th row is selected to perform external compensation. The sub-pixel unit in the 11th row is shown in FIG. During the display period DS of the first frame 1F, the third node H <11> Charge During the blank period BL (following the display period), the first clock signal C The first node Q1 provides LKA. <11> and the second node Q2 <12> Charging for Then, the high voltage signal provided via the fourth sub-clock signal line CLK_4 is , supplies a high-voltage third clock signal CLKC, and outputs the sixth shift register unit The first output signal OUT1 <11> This high voltage signal OUT1<11> is used to drive the sub-pixel unit of the 11th row to complete its external compensation. Figure 21 shows the simulation data of the signal output from the gate drive circuit of Figure 19. This shows the data.

[0200] In another aspect, the present disclosure provides a display device. It shows a schematic diagram of a display device. The display device 1 includes the gate drive circuit 2 described in the present disclosure 0 (or 20B) and a plurality of sub-pixel units 410 arranged in an array on the display panel 40 and so on.

[0201] The gate drive circuit 20 has a plurality of shift register units described in the present disclosure connected in series in cascade. Each shift register unit outputs a first output signal OUT1 and a second output signal OUT2 respectively supplied to the sub-pixel units 410 in different rows in the array. For example, the gate drive circuit 20 is connected to each sub-pixel unit 410 via the gate line GL. The gate drive circuit 20 is used to provide a drive signal to the array of sub-pixel units 410. For example, using the drive signal to drive the scanning transistor and the sensing transistor in each row of sub-pixel units 410 respectively. respectively. In one embodiment, the display device 1 further includes a data drive circuit 30 configured to provide a data signal to the array of sub-pixel units 410. Optionally, the data drive circuit 30 is connected to each sub-pixel unit 410 via the data line DL.

[0202] Optionally, the display device 1 of the present disclosure can be one selected from a liquid crystal display panel, a liquid crystal television, a display, an OLE D display panel, an OLED television, an electronic paper display device, a smartphone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and any product or component having a display function. It can be one of the above. connected.

[0203] Optionally, the display device 1 of the present disclosure can be one selected from a liquid crystal display panel, a liquid crystal television, a display, an OLE D display panel, an OLED television, an electronic paper display device, a smartphone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and any product or component having a display function. puter, a notebook computer, a digital photo frame, a navigator, and any product or component having a display function. It can be one selected from any of the above.

[0204] In another aspect, the present disclosure provides a method for driving the shift register unit described herein. The shift register unit 10 shown in some of the figures herein can be used as a unit member for cascade-connecting gate drive circuits including multi-stage shift register units, and the multi-stage shift register units are configured to drive a display panel to display at least one frame of an image. The driving method includes operating a first input circuit of the shift register unit to control a voltage level at a first node connected between the first input circuit and a first output circuit in response to a first input signal. And the method includes causing the first output circuit to output a shift register signal and a first output signal in response to the voltage level at the first node. The driving method further includes operating a second input circuit of the shift register unit to control a voltage level at a second node connected between the second input circuit and a second output circuit in response to the first input signal. And the method includes causing the second output circuit to output a second output signal in response to the voltage level at the second node. Optionally, in one specific embodiment, the method includes inputting a first input signal to a first input circuit of a first sub-unit of the shift register unit described herein and a second input circuit of a second sub-unit of the same shift register unit. The method further includes driving the first sub-unit to control the voltage level of a first node of the first sub-unit based on the first input signal. Further, the method includes a first

[0205]

[0206] ​​​​​​​​​​​​​​​Including connecting the output circuit to a first node in the first subunit. The method controls the first output circuit to output a shift register signal and a first output signal in response to the voltage level of the first node by driving the first subunit. Further included is controlling the first output circuit to output a shift register signal and a first output signal in response to the voltage level of the first node by driving the first subunit. Further, the method includes controlling the voltage level of a second node in the second subunit based on the first input signal by driving the second subunit, and connecting an output circuit to the second node in the second subunit. Further, the method includes controlling the second output circuit to output a second output signal in response to the voltage level of the second node by driving the second subunit. Further included is controlling the voltage level of a second node in the second subunit based on the first input signal by driving the second subunit, and connecting an output circuit to the second node in the second subunit. Further, the method includes controlling the second output circuit to output a second output signal in response to the voltage level of the second node by driving the second subunit. Further included is controlling the voltage level of a second node in the second subunit based on the first input signal by driving the second subunit, and connecting an output circuit to the second node in the second subunit. Further, the method includes controlling the second output circuit to output a second output signal in response to the voltage level of the second node by driving the second subunit. Further included is controlling the voltage level of a second node in the second subunit based on the first input signal by driving the second subunit, and connecting an output circuit to the second node in the second subunit. Further, the method includes controlling the second output circuit to output a second output signal in response to the voltage level of the second node by driving the second subunit. Further included is controlling the voltage level of a second node in the second subunit based on the first input signal by driving the second subunit, and connecting an output circuit to the second node in the second subunit. Further, the method includes controlling the second output circuit to output a second output signal in response to the voltage level of the second node by driving the second subunit. Further included is controlling the voltage level of a second node in the second subunit based on the first input signal by driving the second subunit, and connecting an output circuit to the second node in the second subunit. Further, the method includes controlling the second output circuit to output a second output signal in response to the voltage level of the second node by driving the second subunit.

[0207] Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node. Optionally, the step of controlling the voltage level of the first node by driving the first subunit includes using a blank input circuit having a common input circuit to receive a second input signal and a first clock signal to determine the voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node in response to the voltage level of the fourth node. At the same time, the step of controlling the voltage level of the second node by driving the second subunit includes further using a second transmission circuit in the blank input circuit to control the voltage level of the second node in response to the voltage level of the fourth node.

[0208] Optionally, the step of controlling the first output circuit by driving the first subunit includes using at least a first reset circuit and a second reset circuit to control the shift register Reset the voltage level at the first output terminal in the output terminal and the first output circuit including that. This step outputs as a shift register signal in response to the voltage of the first node and further includes controlling a second clock signal that is forced and a third clock signal that is output as the first output signal Alternatively, by driving the second sub-unit, the step of controlling the second output circuit includes resetting the voltage level at the second output terminal in the second output circuit using at least a third reset circuit This step further includes controlling a fourth clock signal that is output as the second output signal in response to the voltage level of the second node

[0209] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed or to the exemplary embodiments shown. Accordingly, the foregoing description is not limiting but is to be regarded as illustrative. It will be obvious to those skilled in the art that various modifications and changes are possible This embodiment has been selected and described to explain the principles of the invention and its practical application in its optimal form so that those skilled in the art will be able to understand various embodiments and various modifications suitable for a particular application or intended embodiment of the invention. The scope of the invention is intended to be defined by the claims appended hereto and their equivalents in which all terms are to be given the broadest reasonable meaning unless otherwise specifically defined. Accordingly, terms such as "invention", "the present invention", etc do not necessarily limit the scope of the claims to specific embodiments, and references to exemplary embodiments of the invention are references to the invention in general and are not intended to limit the invention to those specific embodiments. Therefore, terms such as "invention", "the present invention", etc are not necessarily limited to specific embodiments of the claims, and references to exemplary embodiments of the invention are references to the invention ​It is not intended to imply a limitation thereto, nor should such a limitation be inferred. The present invention is limited only by the spirit and scope of the appended claims. Note that these claims may use terms such as "first", "second", etc. before a noun or element. In this way such terms should be understood as nomenclature and, unless a specific quantity has already been given, should not be construed as a limitation on the quantity of the element modified by such nomenclature. The described effects and advantages do not apply to all embodiments of the present invention. It should be understood that those skilled in the art can make modifications to the described embodiments without departing from the scope of the present invention as defined by the following claims. Note that any element and component part in the present disclosure, whether or not the element or component part is explicitly listed in the following claims, is not intended to be dedicated to the public.< / n> ​​​< / n>

Claims

1. A shift register unit, comprising: a first circuit and a second circuit, wherein the first circuit includes a first input circuit connected to a first output circuit via a first node, the first input circuit is configured to control the voltage level of the first node, and the first output circuit is configured to output a first output signal in response to the voltage level of the first node; the second circuit includes a second input circuit connected to a second output circuit via a second node, the second input circuit is configured to control the voltage level of the second node, and the second output circuit is configured to output a second output signal in response to the voltage level of the second node, and the shift register unit further includes: a blank input circuit connected to the first node and the second node and configured to receive a selection control signal and control the voltage levels of the first node and the second node respectively; the first input circuit and the second input circuit have the same circuit structure; the first output signal and the second output signal are different from each other; the blank input circuit includes a common input circuit, a first transmission circuit, and a second transmission circuit; the common input circuit is configured to control the voltage level of a fourth node; the first transmission circuit is connected to the first node and the fourth node and is configured to control the voltage level of the first node; the second transmission circuit is connected to the second node and the fourth node and is configured to control the voltage level of the second node. A shift register unit.

2. The common input circuit further includes a selection control circuit and a third input circuit; the selection control circuit is configured to control the voltage level of a third node using a second input signal in response to the selection control signal and maintain the voltage level of the third node; the third input circuit is configured to control the voltage level of the fourth node in response to the voltage level of the third node. The shift register unit according to Claim 1.

3. The selection control circuit includes a first transistor and a first capacitor. The first transistor has a gate terminal configured to receive the selection control signal, a first terminal configured to receive the second input signal, and a second terminal connected to the third node. The first capacitor has a first terminal connected to the third node. The shift register unit according to claim 2.

4. The third input circuit includes a second transistor having a gate connected to the third node and a second terminal connected to the fourth node. The shift register unit according to claim 2.

5. The first input circuit includes a fifth transistor. The first output circuit includes a sixth transistor, a seventh transistor, and a second capacitor. The fifth transistor has a gate terminal configured to receive a first input signal and a second terminal connected to the first node. The sixth transistor has a gate terminal connected to the first node, a first terminal configured to receive a second clock signal as a shift register signal, and a second terminal configured to output the shift register signal. The seventh transistor has a gate terminal connected to the first node, a first terminal configured to receive a third clock signal as the first output signal, and a second terminal configured to output the first output signal. The second capacitor has a first terminal connected to the first node and a second terminal connected to the second terminal of the seventh transistor. The shift register unit according to claim 1.

6. The second input circuit includes an eighth transistor. The second output circuit includes a ninth transistor and a third capacitor. The eighth transistor has a gate terminal configured to receive a first input signal and a second terminal connected to the second node. The ninth transistor has a gate terminal connected to the second node, a first terminal configured to receive a fourth clock signal as the second output signal, and a second terminal configured to output the second output signal. The third capacitor has a first terminal connected to the second node and a second terminal connected to the second terminal of the ninth transistor. The shift register unit according to claim 1.

7. The first circuit further includes a first control circuit, a first reset circuit, a second reset circuit, a shift register output terminal, and a first output terminal. The first control circuit is configured to control the voltage level of a fifth node in response to the voltage level at the first node and a second voltage. The first reset circuit is configured to reset the voltage levels at the first node, the shift register output terminal, and the first output terminal in response to the voltage level at the fifth node. The second reset circuit is configured to reset the voltage levels at the first node, the shift register output terminal, and the first output terminal in response to the voltage level at a sixth node. The shift register unit according to claim 4.

8. The second circuit further includes a second control circuit, a third reset circuit, a fourth reset circuit, and a second output terminal. The second output terminal is configured to output the second output signal. The second control circuit is configured to control the voltage level of the sixth node in response to the voltage level at the second node and a third voltage. The third reset circuit is configured to reset the voltage levels at the second node and the second output terminal in response to the voltage level of the sixth node. The fourth reset circuit is configured to reset the voltage levels at the second node and the second output terminal in response to the voltage level at the fifth node. The shift register unit according to claim 7.

9. The first circuit further includes a third control circuit and a fourth control circuit. The third control circuit is configured to control the voltage level of the fifth node in response to a first clock signal, and the fourth control circuit is configured to control the voltage level of the fifth node in response to a first input signal. The second circuit further includes a fifth control circuit and a sixth control circuit. The fifth control circuit is configured to control the voltage level of the sixth node in response to the first clock signal, and the sixth control circuit is configured to control the voltage level of the sixth node in response to the first input signal. The shift register unit according to claim 8.

10. The first circuit further includes a fifth reset circuit and a sixth reset circuit. The fifth reset circuit is configured to reset the voltage level at the first node in response to a display reset signal, and the sixth reset circuit is configured to reset the voltage level at the first node in response to a full-scale reset signal. The second circuit further includes a seventh reset circuit and an eighth reset circuit. The seventh reset circuit is configured to reset the voltage level at the second node in response to the display reset signal, and the eighth reset circuit is configured to reset the voltage level at the second node in response to the full-scale reset signal. The shift register unit according to claim 9.

11. The voltage level of the first node is the same as the voltage level of the second node. The shift register unit according to claim 1.

12. A gate driving circuit including a plurality of shift register units connected in cascade in series, The plurality of shift register units are each the shift register unit according to claim 1, and include a pair of a first circuit in an odd stage controlled by the voltage levels of the first node and the second node, respectively, and a second circuit in the next even stage. The voltage levels of the first node and the second node are each controlled by a first transmission circuit and a second transmission circuit connected from a common input circuit. The first circuit of each shift register unit outputs a shift register signal as a first input signal to drive both the first circuit and the second circuit in the next shift register unit, or outputs it as a display reset signal to drive both the first circuit and the second circuit in the previous shift register unit. A gate driving circuit.

13. Among the first four stages of the gate driving circuit, the first input signal of at least one stage is a clock signal. The gate driving circuit according to claim 12.

14. The first input signal of at least one stage includes a carry signal of the corresponding previous stage. The gate driving circuit according to claim 12.

15. The common input circuit further includes a selection control circuit and a third input circuit. The selection control circuit controls the voltage level of the third node using a second input signal in response to the selection control signal, and is configured to maintain the voltage level of the third node. The gate driving circuit according to claim 12, wherein at least one stage of the second input signal includes a carry signal of a corresponding previous stage.

16. A display device including the gate driving circuit according to claim 12 and a plurality of sub-pixel units arranged in an array, wherein a first output signal and a second output signal respectively output from a first output circuit and a second output circuit of each one shift register unit in the gate driving circuit are respectively provided to sub-pixel units in different rows of the array.

17. A driving method for a shift register unit according to claim 1, comprising: inputting a first input signal to a first input circuit of a first circuit of the shift register unit and a second input circuit of a second circuit of the same shift register unit; driving the first circuit to control a voltage level of a first node of the first circuit based on the first input signal; connecting a first output circuit to the first node; driving the first circuit to control the first output circuit to output a shift register signal and a first output signal; driving the second circuit to control a voltage level of a second node of the second circuit based on the first input signal; connecting a second output circuit to the second node; driving the second circuit to control the second output circuit to output a second output signal, wherein controlling the voltage level of the first node by driving the first circuit includes receiving a second input signal and a first clock signal using a blank input circuit having a common input circuit to determine voltage levels of a third node and a fourth node, and using a first transmission circuit to control the voltage level of the first node; and controlling the voltage level of the second node by driving the second circuit includes controlling the voltage level of the second node using the blank input circuit further having a second transmission circuit.

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