Communication device

Abstract

Provided is a communication device with a wide range of potentials of signals which can be transmitted and received. This communication device has an amplifier circuit comprising first to fourth transistors, first to fourth bias transistors, first to fourth loads, and first to fourth terminals. The drains of the first to fourth transistors are electrically connected to the sources of the first to fourth bias transistors, respectively. The sources of the first to fourth transistors are electrically connected to the power supply line. The gates of the first and second bias transistors are electrically connected to first wiring, and the gates of the third and fourth bias transistors are electrically connected to second wiring. The first to fourth terminals are electrically connected to the gates of the first to fourth transistors, respectively, and the drains of the third, fourth, first and second bias transistors are electrically connected to the first to fourth loads, respectively.

Description

Technical Field

[0001] One aspect of the present invention relates to a communication device and an operation method thereof. Alternatively, one aspect of the present invention relates to a semiconductor device and an operation method thereof.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Note that in this specification and the like, the semiconductor device refers to all those that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, and electronic devices may include semiconductor elements or semiconductor circuits. Therefore, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be referred to as semiconductor devices.

Background Art

[0004] The spread of portable information terminals represented by smartphones and tablet terminals is progressing. Along with the spread of information terminals, various communication standards have been established. For example, the operation of the LTE-Advanced standard called the fourth-generation mobile communication system (4G) has been started.

[0005] In recent years, due to the development of information technologies such as IoT (Internet of Things), the amount of data handled by information terminals has a tendency to increase. In addition, an improvement in communication speed is required for electronic devices such as information terminals.

[0006] In order to support various information technologies such as IoT, a new communication standard called the fifth-generation mobile communication system (5G) that realizes a communication speed faster than 4G, a large number of simultaneous connections, and a short delay time is being studied (see Patent Document 1).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention aims to provide a communication device capable of transmitting and receiving signals with a wide potential range. Or, one aspect of the present invention aims to provide a communication device having an amplifier with a large amplification factor. Or, one aspect of the present invention aims to provide a low-power communication device. Or, one aspect of the present invention aims to provide a novel communication device. Or, one aspect of the present invention aims to provide a novel semiconductor device.

[0009] One aspect of the present invention aims to provide an operating method for a communication device capable of transmitting and receiving signals with a wide potential range. Or, one aspect of the present invention aims to provide an operating method for a communication device having an amplifier with a large amplification factor. Or, one aspect of the present invention aims to provide an operating method for a low-power communication device. Or, one aspect of the present invention aims to provide an operating method for a novel communication device. Or, one aspect of the present invention aims to provide an operating method for a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention has an amplification circuit, and the amplification circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first load, a second load, a third load, a fourth load, a first terminal, a second terminal, a third terminal, and a fourth terminal. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. One of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor. One of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor. The other of the source or drain of the first transistor and the other of the source or drain of the third transistor are electrically connected to the first power line. The other of the source or drain of the fifth transistor and the other of the source or drain of the seventh transistor are electrically connected to the second power line. The gate of the second transistor and the gate of the fourth transistor are electrically connected to the first wiring. The gate of the sixth transistor and the gate of the eighth transistor are electrically connected to the second wiring. The first terminal is electrically connected to the gate of the first transistor, the other of the source or drain of the sixth transistor, and the first load. The second terminal is electrically connected to the gate of the third transistor, the other of the source or drain of the eighth transistor, and the second load. The third terminal is electrically connected to the gate of the fifth transistor, the other of the source or drain of the second transistor, and the third load. The fourth terminal is electrically connected to the gate of the seventh transistor, the other of the source or drain of the fourth transistor, and the fourth load, which is a communication device.

[0012] Alternatively, one aspect of the present invention has an amplification circuit, and the amplification circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, a first load, a second load, a third load, a fourth load, a first terminal, a second terminal, a third terminal, and a fourth terminal. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. One of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor. One of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor. The other of the source or drain of the first transistor and the other of the source or drain of the third transistor are electrically connected to the first power line. The other of the source or drain of the fifth transistor and the other of the source or drain of the seventh transistor are electrically connected to the second power line. The non-inverting input terminals of the first operational amplifier and the second operational amplifier are electrically connected to the first wiring. The non-inverting input terminals of the third operational amplifier and the fourth operational amplifier are electrically connected to the second wiring. The inverting input terminal of the first operational amplifier is electrically connected to one of the source or drain of the first transistor. The inverting input terminal of the second operational amplifier is electrically connected to one of the source or drain of the third transistor. The inverting input terminal of the third operational amplifier is electrically connected to one of the source or drain of the fifth transistor. The inverting input terminal of the fourth operational amplifier is electrically connected to one of the source or drain of the seventh transistor. The output terminal of the first operational amplifier is electrically connected to the gate of the second transistor. The output terminal of the second operational amplifier is electrically connected to the gate of the fourth transistor. The output terminal of the third operational amplifier isThe gate of the sixth transistor is electrically connected, the output terminal of the fourth operational amplifier is electrically connected to the gate of the eighth transistor, the first terminal is electrically connected to the gate of the first transistor, the other of the source or drain of the sixth transistor, and the first load, the second terminal is electrically connected to the gate of the third transistor, the other of the source or drain of the eighth transistor, and the second load, the third terminal is electrically connected to the gate of the fifth transistor, the other of the source or drain of the second transistor, and the third load, and the fourth terminal is electrically connected to the gate of the seventh transistor, the other of the source or drain of the fourth transistor, and the fourth load.

[0013] Alternatively, in the above aspect, the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor may have back gates, and the back gate of the second transistor is electrically connected to the first terminal, the back gate of the fourth transistor is electrically connected to the second terminal, the back gate of the sixth transistor is electrically connected to the third terminal, and the back gate of the eighth transistor is electrically connected to the fourth terminal.

[0014] Alternatively, in the above aspect, when a first signal wave is input to the first terminal, the amplifier circuit has a function of outputting a signal wave corresponding to the first signal wave from the third terminal. When a second signal wave is input to the second terminal, the amplifier circuit has a function of outputting a signal wave corresponding to the second signal wave from the fourth terminal. When a third signal wave is input to the third terminal, the amplifier circuit has a function of outputting a signal wave corresponding to the third signal wave from the first terminal. When a fourth signal wave is input to the fourth terminal, the amplifier circuit has a function of outputting a signal wave corresponding to the fourth signal wave from the second terminal.

[0015] Alternatively, in the above aspect, when a first signal wave is input to the first terminal and a second signal wave is input to the second terminal, the potential of the first wiring may be set to a potential at which the second and fourth transistors operate in the saturation region, and the potential of the second wiring may be set to a potential at which the sixth and eighth transistors are in the off state. When a third signal wave is input to the third terminal and a fourth signal wave is input to the fourth terminal, the potential of the first wiring may be set to a potential at which the second and fourth transistors are in the off state, and the potential of the second wiring may be set to a potential at which the sixth and eighth transistors operate in the saturation region.

[0016] Alternatively, in the above aspect, the first signal wave and the second signal wave may be in a phase-inverted relationship with each other, and the third signal wave and the fourth signal wave may be in a phase-inverted relationship with each other.

[0017] Alternatively, in the above aspect, either the source or the drain of the first to eighth transistors may be the source.

Advantages of the Invention

[0018] According to one aspect of the present invention, a communication device capable of transmitting and receiving signals with a wide potential range can be provided. Alternatively, a communication device having an amplifier with a large amplification factor can be provided. Alternatively, a low-power consumption communication device can be provided. Alternatively, a novel communication device can be provided. Alternatively, a novel semiconductor device can be provided.

[0019] According to one aspect of the present invention, a method of operating a communication device capable of transmitting and receiving signals with a wide potential range can be provided. Alternatively, a method of operating a communication device having an amplifier with a large amplification factor can be provided. Alternatively, a method of operating a low-power consumption communication device can be provided. Alternatively, a method of operating a novel communication device can be provided. Alternatively, a method of operating a novel semiconductor device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0021] FIG. 1 is a block diagram showing a configuration example of a communication device. FIG. 2 is a circuit diagram showing a configuration example of a communication device. FIG. 3 is a circuit diagram showing a configuration example of a communication device. FIGS. 4A and 4B are circuit diagrams showing an example of an operation method of a communication device. FIGS. 5A and 5B are circuit diagrams showing a configuration example of a semiconductor device. FIGS. 6A1 to 6A4, and FIGS. 6B1 and 6B2 are diagrams showing a configuration example of a communication device. FIGS. 7A1 and 7A2, and FIGS. 7B1 and 7B2 are circuit diagrams showing a configuration example of a communication device. FIGS. 8A and 8B are circuit diagrams showing a configuration example of a communication device. FIG. 9A is a circuit diagram showing a configuration example of a communication device. FIG. 9B is a circuit diagram showing a configuration example of a semiconductor device. FIG. 10 is a circuit diagram showing a configuration example of a communication device. FIG. 11 is a circuit diagram showing a configuration example of a communication device. FIG. 12 is a circuit diagram showing a configuration example of a communication device. FIGS. 13A and 13B are circuit diagrams showing an example of an operation method of a communication device. FIGS. 14A and 14B are circuit diagrams showing a configuration example of a semiconductor device. FIGS. 15A and 15B are circuit diagrams showing a configuration example of a communication device. FIG. 16A is a circuit diagram showing a configuration example of a communication device. FIG. 16B is a circuit diagram showing a configuration example of a semiconductor device. FIG. 17 is a circuit diagram showing a configuration example of a communication device. FIG. 18A and FIG. 18B are circuit diagrams showing an example of an operation method of a communication device. FIG. 19 is a circuit diagram showing a configuration example of a semiconductor device. FIGS. 20A and 20B are circuit diagrams showing a configuration example of a communication device. FIG. 21 is a diagram showing a configuration example of a semiconductor device. FIGS. 22A and 22B are diagrams showing a configuration example of a transistor. FIGS. 23A to 23C are diagrams showing a configuration example of a transistor. FIGS. 24A to 24C are diagrams showing a configuration example of a transistor. FIG. 25A is a diagram for explaining the classification of the crystal structure of IGZO. FIG. 25B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film. FIG. 25C is a diagram for explaining the selected area electron diffraction pattern of a CAAC-IGZO film. FIG. 26A is a top view of a semiconductor wafer. FIG. 26B is an enlarged view of a chip. FIG. 27A is a flowchart for explaining an example of a manufacturing process of an electronic component. FIG. 27B is a perspective schematic diagram of an electronic component. FIG. 28 is a diagram showing an example of an electronic device. FIGS. 29A to 29F are diagrams showing an example of an electronic device. FIG. 30 is a diagram showing the hierarchical structure of an IoT network and trends in required specifications. FIG. 31 is an image diagram of factory automation.

Embodiments for Carrying Out the Invention

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof is omitted.

[0023] In addition, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the purpose of facilitating the understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but this may not be reflected in the drawing for the purpose of facilitating understanding.

[0024] In addition, in a top view (also referred to as a "plan view") or a perspective view, etc., for the purpose of making the drawing easier to understand, the description of some components may be omitted.

[0025] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0026] In addition, in this specification and the like, the "terminal" in an electric circuit refers to a part where current input or output, voltage input or output, or signal reception or transmission is performed. Therefore, a part of a wiring or an electrode may function as a terminal.

[0027] Note that in this specification and the like, the terms "upper" and "lower" do not limit the positional relationship of the components to be directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be directly formed in contact with insulating layer A. Components other than insulating layer A and electrode B are not excluded from being included between them.

[0028] In addition, the functions of the source and drain can be interchanged depending on operating conditions such as when transistors with different polarities are employed or when the direction of current changes during circuit operation. Therefore, it is difficult to limit which one is the source or the drain. For this reason, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0029] In this specification and the like, "electrically connected" includes both the case of direct connection and the case of connection via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring extends.

[0030] In this specification and the like, when referring to count values and measured values as "identical", "the same", "equal", or "uniform", etc., unless otherwise specified, they shall include an error of plus or minus 20%.

[0031] Also, voltage often indicates the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged with each other. In this specification and the like, unless otherwise explicitly stated, voltage and potential can be interchanged.

[0032] Even when denoted as "semiconductor", for example, when the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "insulator" in place of "semiconductor". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be interchangeable with each other.

[0033] Also, even when referred to as a "semiconductor," for example, when its conductivity is sufficiently high, it has the characteristics of a "conductor." Therefore, it is also possible to use it by replacing "semiconductor" with "conductor." In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be mutually interchangeable in some cases.

[0034] Note that ordinal numbers such as "first," "second," etc. in this specification and the like are attached to avoid confusion of components, and do not indicate any order or rank such as the process order or the stacking order. Also, even for terms without ordinal numbers in this specification and the like, ordinal numbers may be attached in the claims to avoid confusion of components. Also, even for terms with ordinal numbers in this specification and the like, different ordinal numbers may be attached in the claims. Also, even for terms with ordinal numbers in this specification and the like, ordinal numbers may be omitted in the claims and the like.

[0035] Note that in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited. Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected.

[0036] Also, in this specification and the like, "on-current" may refer to the current flowing between the source and drain when the transistor is in the on state. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is in the off state.

[0037] Also, in this specification and the like, "gate" refers to part or all of the gate electrode and the gate wiring. The gate wiring refers to the wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0038] In addition, in this specification and the like, the source refers to part or all of a source region, a source electrode, and a source wiring. The source region refers to a region in the semiconductor layer where the resistivity is equal to or less than a certain value. The source electrode refers to a conductive layer portion connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0039] In addition, in this specification and the like, the drain refers to part or all of a drain region, a drain electrode, and a drain wiring. The drain region refers to a region in the semiconductor layer where the resistivity is equal to or less than a certain value. The drain electrode refers to a conductive layer portion connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0040] In this specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be paraphrased as a transistor having an oxide or an oxide semiconductor.

[0041] (Embodiment 1) In this embodiment, a communication device which is one aspect of the present invention will be described.

[0042] FIG. 1 is a diagram showing a configuration example of a communication device 10 which is a communication device according to one aspect of the present invention. The communication device 10 includes an antenna 11, an amplifier 12, an amplifier 13, a phase shifter 14, an amplifier 15, an inductor 16, and an inductor 17. Note that an inductor is also referred to as a coil. Also, the inductor 16 and the inductor 17 are provided so as to face each other.

[0043] The communication device 10 has a function of performing wireless communication. For example, by transmitting and receiving signals between the communication device 10 and a base station, the exchange of information represented by the signals can be performed.

[0044] The antenna 11 has a function of receiving signals from outside the communication device 10. Also, the antenna 11 has a function of transmitting signals to the outside of the communication device 10. For example, the antenna 11 has a function of receiving a signal transmitted by a base station as a radio wave. Also, for example, the antenna 11 has a function of transmitting a signal to the outside of the communication device 10 as a radio wave.

[0045] From the above, the signals transmitted and received by the communication device 10 can be regarded as waves. In this specification and the like, a signal that is a wave may be referred to as a signal wave.

[0046] The amplifier 12 has a function of amplifying the signal received by the antenna 11 and outputting it to the amplifier 13. Also, the amplifier 12 has a function of amplifying the signal input from the amplifier 13 and outputting it to the antenna 11. The amplifier 12 has a function as a power amplifier and can greatly amplify the signal received by the antenna 11 and the signal input from the amplifier 13. Also, the amplifier 12 has a function as a low-noise amplifier and can amplify the signal received by the antenna 11 and the signal input from the amplifier 13 with high precision.

[0047] The amplifier 13 has a function of amplifying the signal input from the amplifier 12 and outputting it to the phase shifter 14. Also, the amplifier 13 has a function of amplifying the signal input from the phase shifter 14 and outputting it to the amplifier 12. The amplifier 13 has a function as an RF (Radio Frequency) amplifier and can amplify high-frequency signals. Therefore, by providing the amplifier 13, the communication device 10 can perform the transmission and reception of high-frequency signals. Thus, by providing the amplifier 13 in the communication device 10, the communication device 10 can perform wireless communication using, for example, the fifth-generation mobile communication system (5G).

[0048] The phase shifter 14 has a function of changing the phase shift of a signal. By having the phase shifter 14 in the communication device 10, even when the communication device 10 transmits and receives high-frequency signals, the phase of the signal can be controlled with high precision. Therefore, even when the communication device 10 transmits and receives high-frequency signals, beamforming can be performed. As a result, the communication device 10 can receive signals transmitted from a distance. Also, the communication device 10 can transmit signals to a distance. Therefore, by providing the phase shifter 14 in the communication device 10, the communication device 10 can perform wireless communication using, for example, 5G.

[0049] The amplifier 15 has a function of amplifying the signal input from the phase shifter 14 and outputting it to the inductor 16. Also, the amplifier 15 has a function of amplifying the signal input from the inductor 16 and outputting it to the phase shifter 14. The amplifier 15 has a function as an isolation amplifier. Therefore, noise included in the signal input to the amplifier 15 can be removed.

[0050] The signal input to the inductor 16 is supplied to the inductor 17 by electromagnetic induction. By providing the inductor 16 and the inductor 17 in the communication device 10, for example, impedance matching can be performed. As a result, signal transmission can be performed efficiently.

[0051] One terminal of the inductor 17 is electrically connected to the wiring 18. The other terminal of the inductor 17 is electrically connected to the wiring 19. The wiring 19 has a function as a power line. The potential of the wiring 19 can be, for example, a low potential and can be, for example, a ground potential.

[0052] Figure 2 is a diagram showing a configuration example of the amplifier circuit 20. The amplifier 12, the amplifier 13, the phase shifter 14, and the amplifier 15 shown in Figure 1 can be configured to have the amplifier circuit 20.

[0053] The amplification circuit 20 includes a transistor 21a, a transistor 21b, a transistor 22a, a transistor 22b, a load 23a, a load 23b, a transistor 31a, a transistor 31b, a transistor 32a, a transistor 32b, a load 33a, a load 33b, a terminal 40a, a terminal 40b, a potential generation circuit 44, a terminal 50a, a terminal 50b, and a potential generation circuit 54. Note that the potential generation circuit 44 and the potential generation circuit 54 may be provided outside the amplification circuit 20.

[0054] Hereinafter, the transistor 21a, the transistor 21b, the transistor 22a, the transistor 22b, the transistor 31a, the transistor 31b, the transistor 32a, and the transistor 32b will all be described as n-channel transistors. However, if necessary or by appropriately changing the magnitude relationship of the potentials, any or all of the above transistors may be p-channel transistors. For example, as shown in FIG. 3, the transistor 21a, the transistor 21b, the transistor 22a, the transistor 22b, the transistor 31a, the transistor 31b, the transistor 32a, and the transistor 32b may all be p-channel transistors.

[0055] One of the source or drain of the transistor 21a is electrically connected to one of the source or drain of the transistor 22a. One of the source or drain of the transistor 21b is electrically connected to one of the source or drain of the transistor 22b. One of the source or drain of the transistor 31a is electrically connected to one of the source or drain of the transistor 32a. One of the source or drain of the transistor 31b is electrically connected to one of the source or drain of the transistor 32b.

[0056] The other of the source or drain of transistor 21a and the other of the source or drain of transistor 21b are electrically connected to wiring 41. The gates of transistor 22a and the gate of transistor 22b are electrically connected to wiring 42. The other of the source or drain of transistor 31a and the other of the source or drain of transistor 31b are electrically connected to wiring 51. The gates of transistor 32a and the gate of transistor 32b are electrically connected to wiring 52.

[0057] The potential generation circuit 44 is electrically connected to wiring 42. The potential generation circuit 54 is electrically connected to wiring 52.

[0058] Terminal 40a is electrically connected to the gate of transistor 21a, the other of the source or drain of transistor 32a, and load 33a. Terminal 40b is electrically connected to the gate of transistor 21b, the other of the source or drain of transistor 32b, and load 33b. Terminal 50a is electrically connected to the gate of transistor 31a, the other of the source or drain of transistor 22a, and load 23a. Terminal 50b is electrically connected to the gate of transistor 31b, the other of the source or drain of transistor 22b, and load 23b. Loads 23a and 23b are electrically connected to wiring 43. Loads 33a and 33b are electrically connected to wiring 53.

[0059] Wiring 41, wiring 43, wiring 51, and wiring 53 have the function as a power supply line. The potentials of wiring 41, wiring 43, wiring 51, and wiring 53 can be, for example, a fixed potential. For example, the potentials of wiring 41 and wiring 51 can be set to a low potential, and the potentials of wiring 43 and wiring 53 can be set to a high potential.

[0060] Here, power supply lines to which the same potential is supplied can be electrically connected to each other. For example, wiring 41 and wiring 51 can be electrically connected to each other. Also, wiring 43 and wiring 53 can be electrically connected to each other. That is to say, it can be said that wiring 41 and wiring 51 can be the same wiring, and it can be said that wiring 43 and wiring 53 can be the same wiring.

[0061] A bias potential can be supplied to wiring 42 and wiring 52. Therefore, transistors 22a, 22b, 32a, and 32b can function as bias transistors. Here, the bias potential can be a potential at which the transistors functioning as bias transistors operate in the saturation region.

[0062] The potential supplied to wiring 42 can be generated by potential generation circuit 44. The potential supplied to wiring 52 can be generated by potential generation circuit 54.

[0063] Also, although details will be described later, when a signal is input to terminal 40a, a signal corresponding to the signal is output from terminal 50a, and when a signal is input to terminal 40b, a signal corresponding to the signal is output from terminal 50b. In this case, terminals 40a and 40b become input terminals, and terminals 50a and 50b become output terminals. On the other hand, when a signal is input to terminal 50a, a signal corresponding to the signal is output from terminal 40a, and when a signal is input to terminal 50b, a signal corresponding to the signal is output from terminal 40b. In this case, terminals 40a and 40b become output terminals, and terminals 50a and 50b become input terminals. From the above, it can be said that terminals 40a, 40b, 50a, and 50b have both the function as an input terminal and the function as an output terminal.

[0064] Here, it is preferable that the ratio of the channel width to the channel length of transistors 22a, 22b, 32a, and 32b that can function as bias transistors is large. For example, the ratio of the channel width to the channel length (channel width / channel length) of transistor 22a is preferably equal to or greater than the ratio of the channel width to the channel length of transistor 21a. Also, the ratio of the channel width to the channel length of transistor 22b is preferably equal to or greater than the ratio of the channel width to the channel length of transistor 21b. Further, the ratio of the channel width to the channel length of transistor 32a is preferably equal to or greater than the ratio of the channel width to the channel length of transistor 31a. Moreover, the ratio of the channel width to the channel length of transistor 32b is preferably equal to or greater than the ratio of the channel width to the channel length of transistor 31b. By increasing the ratio of the channel width to the channel length of transistors 22a, 22b, 32a, and 32b that can function as bias transistors, the mirror effect can be suppressed.

[0065] Alternatively, it is preferable that the product of the channel width and the channel length of transistors 22a, 22b, 32a, and 32b, which can function as bias transistors, is large. For example, it is preferable that the product of the channel width and the channel length of transistor 22a is equal to or greater than the product of the channel width and the channel length of transistor 21a. Also, it is preferable that the product of the channel width and the channel length of transistor 22b is equal to or greater than the product of the channel width and the channel length of transistor 21b. Also, it is preferable that the product of the channel width and the channel length of transistor 32a is equal to or greater than the product of the channel width and the channel length of transistor 31a. Furthermore, it is preferable that the product of the channel width and the channel length of transistor 32b is equal to or greater than the product of the channel width and the channel length of transistor 31b. Transistors 22a, 22b, 32a, and 32b, which can function as bias transistors, are such that even if the channel length or the channel width is increased, the frequency characteristics do not deteriorate.

[0066] Alternatively, it is preferable that the channel length of transistors 22a, 22b, 32a, and 32b, which can function as bias transistors, is large. For example, it is preferable that the channel length of transistor 22a is greater than the channel length of transistor 21a. Also, it is preferable that the channel length of transistor 22b is greater than the channel length of transistor 21b. Also, it is preferable that the channel length of transistor 32a is greater than the channel length of transistor 31a. Furthermore, it is preferable that the channel length of transistor 32b is greater than the channel length of transistor 31b. By increasing the channel length of transistors 22a, 22b, 32a, and 32b, which can function as bias transistors, even if the voltage Vds, which is the difference between the drain potential and the source potential of the transistor, increases, if the gate potential is constant, an increase in the drain current flowing through the transistor can be suppressed.

[0067] Also, the threshold voltage of transistor 21a is higher than that of transistor 22a, the threshold voltage of transistor 21b is higher than that of transistor 22b, the threshold voltage of transistor 31a is higher than that of transistor 32a, and the threshold voltage of transistor 31b is higher than that of transistor 32b, which is preferable. In particular, transistors 21a, 21b, 31a, and 31b are preferably normally-off, and transistors 22a, 22b, 32a, and 32b are preferably normally-on. Thereby, the gate-source voltage Vgs of transistor 22a, the voltage Vgs of transistor 22b, the voltage Vgs of transistor 32a, and the voltage Vgs of transistor 32b become small. Therefore, the range of the drain-source voltage Vds in which transistors 22a, 22b, 32a, and 32b, which can function as bias transistors, operate in the saturation region can be widened.

[0068] An example of the operation method of the amplifier circuit 20 having the configuration shown in FIG. 2 will be described with reference to FIGS. 4A and 4B. FIG. 4A is a diagram showing an example of the operation method of the amplifier circuit 20 having the configuration shown in FIG. 2 when terminal 40a is the input terminal INa, terminal 40b is the input terminal INb, terminal 50a is the output terminal OUTa, and terminal 50b is the output terminal OUTb. FIG. 4B is a diagram showing an example of the operation method of the amplifier circuit 20 having the configuration shown in FIG. 2 when terminal 50a is the input terminal INa, terminal 50b is the input terminal INb, terminal 40a is the output terminal OUTa, and terminal 40b is the output terminal OUTb. Here, a signal having a phase opposite to that of the signal input to the input terminal INa can be input to the input terminal INb.

[0069] Note that in FIGS. 4A and 4B, the potential VDD indicates a high potential, and the potential VSS indicates a low potential. The same description will be made in other figures.

[0070] First, the case of inputting signals to terminal 40a and terminal 40b will be described. In this case, as shown in FIG. 4A, the potential of wiring 42 is set to the bias potential Vb, and the potential of wiring 52 is set to the low potential. Thereby, transistors 22a and 22b function as bias transistors. On the other hand, transistors 32a and 32b are in the off state.

[0071] In FIGS. 4A and 4B, transistors, loads, circuits, and wirings that do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb are indicated by dotted lines. For example, as shown in FIG. 4A, since transistors 32a and 32b are in the off state, they do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. Further, since transistors 32a and 32b are in the off state, no current flows through transistors 31a and 31b either, and they do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. Furthermore, load 33a electrically connected to the other of the source or drain of off-state transistor 32a, and load 33b electrically connected to the other of the source or drain of off-state transistor 32b also do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. From the above, in FIG. 4A, transistors 31a, 31b, 32a, 32b, load 33a, and load 33b, and a part of the circuits and wirings electrically connected to them are indicated by dotted lines.

[0072] FIG. 5A is a diagram showing the transistor 21 (transistor 21a or transistor 21b), transistor 22 (transistor 22a or transistor 22b), load 23 (load 23a or load 23b), terminal 40 (terminal 40a or terminal 40b), wiring 41, wiring 42, wiring 43, and terminal 50 (terminal 50a or terminal 50b) shown in FIG. 4A. Here, the terminal 40 is used as the input terminal IN (input terminal INa or input terminal INb), and the terminal 50 is used as the output terminal OUT (output terminal OUTa or output terminal OUTb).

[0073] FIG. 5B is a diagram showing a circuit configuration in which the transistor 22 and the wiring 42 are omitted from the circuit shown in FIG. 5A. In the circuit having the configuration shown in FIG. 5B, the terminal 50 is electrically connected to one of the source or drain of the transistor 21 and the load 23.

[0074] First, consider the configuration shown in FIG. 5B. In the case shown in FIG. 5B, the transistor 21 is an n-channel transistor. Also, the potential of the wiring 43 electrically connected to one of the source or drain of the transistor 21 via the load 23 is a high potential, and the potential of the wiring 41 electrically connected to the other of the source or drain of the transistor 21 is a low potential. Therefore, one of the source or drain of the transistor 21 can be used as the drain, and the other of the source or drain of the transistor 21 can be used as the source.

[0075] In the case shown in FIG. 5B, when the potential of the input terminal IN increases, since the source potential of the transistor 21 is fixed at a low potential, the voltage Vgs, which is the difference between the gate potential and the source potential of the transistor 21, increases. As a result, the on-resistance of the transistor 21 decreases, so the voltage Vds, which is the difference between the drain potential and the source potential of the transistor 21, decreases. As described above, since the source potential of the transistor 21 is fixed at a low potential, the drain potential of the transistor 21 decreases. Here, when the transistor 21 operates in the linear region, the transconductance gm (Ids / Vgs, where Ids is the drain current) of the transistor 21 is smaller than when it operates in the saturation region. Therefore, the amplification factor (also referred to as "gain" or "gain") of the potential of the signal output from the output terminal OUT with respect to the potential of the signal input from the input terminal IN becomes smaller. Therefore, it is preferable to operate the transistor 21 in the saturation region. From the above, when the potential of the input terminal IN becomes too large, the voltage Vds decreases significantly, and since the transistor 21 operates in the linear region, in order to operate the transistor 21 in the saturation region, the potential of the input terminal IN needs to be below a predetermined value.

[0076] Next, consider the case shown in FIG. 5A. Even in the case shown in FIG. 5A, if the transistor 21 is an n-channel type transistor as in the case shown in FIG. 5B, either the source or the drain of the transistor 21 can be the drain, and the other of the source or the drain of the transistor 21 can be the source. Also, either the source or the drain of the transistor 22 can be the source, and the other of the source or the drain of the transistor 22 can be the drain.

[0077] In the case shown in FIG. 5A, when the potential of the input terminal IN increases, the on-resistance of the transistor 21 decreases. Here, the transistor 21 and the transistor 22 are connected in series. Therefore, the magnitude of the drain current of the transistor 21 and the magnitude of the drain current of the transistor 22 are equal. Accordingly, the difference between the gate potential (bias potential Vb) of the transistor 22 and the source potential (the drain potential of the transistor 21) is equal to the difference between the gate potential of the transistor 21 (the potential of the input terminal IN) and the source potential (low potential). For example, when the electrical characteristics of the transistor 22 are equal to those of the transistor 21, the difference between the gate potential and the source potential of the transistor 22 is equal to the difference between the gate potential and the source potential of the transistor 21. Here, for example, when the channel length, channel width, constituent material, etc. of the transistor 21 and the transistor 22 are all equal, the electrical characteristics of the transistor 21 and the transistor 22 become equal.

[0078] From the above, even when the on-resistance of the transistor 21 decreases, the voltage Vds, which is the difference between the drain potential and the source potential of the transistor 21, does not decrease compared to the case shown in FIG. 5B. Therefore, the upper limit value of the potential of the input terminal IN for operating the transistor 21 in the saturation region becomes larger than the case shown in FIG. 5B. As described above, since the amplifier circuit 20 has the transistor 22 that can function as a bias transistor, the width of the potential of the signal that can be input to the input terminal IN can be widened. Therefore, the width of the potential of the signal that the communication device 10 can transmit and receive can be widened.

[0079] Next, the case of inputting signals to the terminals 50a and 50b will be described. In this case, as shown in FIG. 4B, the potential of the wiring 42 is set to a low potential, and the potential of the wiring 52 is set to a bias potential. As a result, the transistors 22a and 22b are turned off. On the other hand, the transistors 32a and 32b function as bias transistors.

[0080] As shown in FIG. 4B, since transistors 22a and 22b are in the off state, they do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. Also, since transistors 22a and 22b are in the off state, no current flows through transistors 21a and 21b either, and they do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. Furthermore, load 23a electrically connected to the other of the source or drain of transistor 22a in the off state and load 23b electrically connected to the other of the source or drain of transistor 22b in the off state also do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. From the above, in FIG. 4B, transistors 21a, 21b, 22a, 22b, load 23a, and load 23b, and a part of the circuits and wirings electrically connected to them are indicated by dotted lines.

[0081] FIGS. 6A1 to 6A4 are diagrams showing a configuration example of load 23. In FIGS. 6A1 to 6A4, wiring 43 and terminal 50 are also shown for convenience of explanation.

[0082] As shown in FIG. 6A1, the load 23 may have a resistance. Also, as shown in FIG. 6A2, the load 23 may have a transistor. Further, as shown in FIG. 6A3, the load 23 may have a transistor, and the gate of the transistor may be electrically connected to the terminal 50. Additionally, as shown in FIG. 6A4, the load 23 may have a transistor, and the gate of the transistor may be electrically connected to the wiring 43. Note that in FIGS. 6A2 and 6A3, the transistor included in the load 23 is a p-channel transistor, and in FIG. 6A4, the transistor included in the load 23 is an n-channel transistor. However, one aspect of the present invention is not limited to this. Even when the load 23 is as shown in FIGS. 6A2 and 6A3, the transistor included in the load 23 may be an n-channel transistor. Also, even when the load 23 is as shown in FIG. 6A4, the transistor included in the load 23 may be a p-channel transistor.

[0083] Also, a passive element may be provided between the transistor 21 and the wiring 41. For example, as shown in FIG. 6B1, an inductor 101 may be provided. In the configuration shown in FIG. 6B1, one terminal of the inductor 101 is electrically connected to the other of the source or drain of the transistor 21, and the other terminal of the inductor 101 is electrically connected to the wiring 41.

[0084] Also, as shown in FIG. 6B2, an inductor 101 and a capacitor 102 may be provided. In the configuration shown in FIG. 6B2, one terminal of the inductor 101 and one terminal of the capacitor 102 are electrically connected to the other of the source or drain of the transistor 21. Also, the other terminal of the inductor 101 and the other terminal of the capacitor 102 are electrically connected to the wiring 41.

[0085] The descriptions shown in FIGS. 5A, 5B, 6A1 to 6A4, 6B1, and 6B2 can also be applied to the case shown in FIG. 4B by replacing transistor 21 with transistor 31 (transistor 31a or transistor 31b), transistor 22 with transistor 32 (transistor 32a or transistor 32b), load 23 with load 33 (load 33a or load 33b), terminal 40 with terminal 50, wiring 41 with wiring 51, wiring 42 with wiring 52, wiring 43 with wiring 53, and terminal 50 with terminal 40 respectively. Note that the circuit having the configuration shown in FIG. 5A can also be applied to semiconductor devices other than communication devices. For example, it can be used as part of an operational amplifier.

[0086] As shown in FIGS. 4A and 4B, by switching the potential of wiring 42, the conduction / non - conduction state between wiring 41 and terminals 50a and 50b can be switched. Also, by switching the potential of wiring 52, the conduction / non - conduction state between wiring 51 and terminals 40a and 40b can be switched. From the above, even if the switch 24 shown in FIG. 7A1 and the switch 34 shown in FIG. 7A2 are omitted, the amplifier circuit 20 can operate normally. Specifically, when signals are input to terminals 40a and 40b, signals corresponding to the input signals can be output from terminals 50a and 50b. Also, when signals are input to terminals 50a and 50b, signals corresponding to the input signals can be output from terminals 40a and 40b. Note that switches 24 and 34 may be provided. In this case, the potential of wiring 42 and the potential of wiring 52 can be fixed to the bias potential Vb.

[0087] Note that a transistor 28 may be provided as the switch 24, and a transistor 38 may be provided as the switch 34. In this case, as shown in FIG. 7B1, one of the source or drain of the transistor 28 can be electrically connected to the other of the source or drain of the transistor 21a and the other of the source or drain of the transistor 21b, and the other of the source or drain of the transistor 28 can be electrically connected to the wiring 41. Also, as shown in FIG. 7B2, one of the source or drain of the transistor 38 can be electrically connected to the other of the source or drain of the transistor 31a and the other of the source or drain of the transistor 31b, and the other of the source or drain of the transistor 38 can be electrically connected to the wiring 51. Note that when the amplifier circuit 20 includes the transistor 28 and the transistor 38, as shown in FIGS. 7B1 and 7B2, the gate of the transistor 28 can be electrically connected to the wiring 42, and the gate of the transistor 38 can be electrically connected to the wiring 52. In this case, the potential of the wiring 42 can be the bias potential Vb or a low potential.

[0088] FIG. 8A is a diagram showing a configuration example of the amplifier circuit 20, which is a modification of the configuration shown in FIG. 2. The amplifier circuit 20 having the configuration shown in FIG. 8A is different from the amplifier circuit 20 having the configuration shown in FIG. 2 in that the gate of the transistor 22a and the gate of the transistor 22b are electrically connected to different wirings, and the gate of the transistor 32a and the gate of the transistor 32b are electrically connected to different wirings.

[0089] In the amplifier circuit 20 having the configuration shown in FIG. 8A, the gate of the transistor 22a and the potential generation circuit 44a are electrically connected via the wiring 42a. Also, the gate of the transistor 22b and the potential generation circuit 44b are electrically connected via the wiring 42b. Further, the gate of the transistor 32a and the potential generation circuit 54a are electrically connected via the wiring 52a. Moreover, the gate of the transistor 32b and the potential generation circuit 54b are electrically connected via the wiring 52b.

[0090] In the amplifier circuit 20 configured as shown in FIG. 8A, the potential supplied to the wiring 42a can be generated by the potential generation circuit 44a, and the potential supplied to the wiring 42b can be generated by the potential generation circuit 44b. Also, the potential supplied to the wiring 52a can be generated by the potential generation circuit 54a, and the potential supplied to the wiring 52b can be generated by the potential generation circuit 54b.

[0091] FIG. 8B is a diagram showing a configuration example of the amplifier circuit 20, which is a modified example of the configuration shown in FIG. 2. The amplifier circuit 20 configured as shown in FIG. 8B is different from the amplifier circuit 20 configured as shown in FIG. 2 in that the load 23a, the load 23b, the load 33a, the load 33b, the wiring 43, and the wiring 53 are not provided.

[0092] FIG. 9A is a diagram showing a configuration example of the amplifier circuit 20, which is a modified example of the configuration shown in FIG. 2. The amplifier circuit 20 configured as shown in FIG. 9A is different from the amplifier circuit 20 configured as shown in FIG. 2 in that back gates are provided for the transistors 22a, 22b, 32a, and 32b.

[0093] In this specification and the like, when simply referring to "gate", it may indicate the front gate. Or it may indicate one or both of the front gate and the back gate.

[0094] The back gate of the transistor 22a is electrically connected to the terminal 40a. The back gate of the transistor 22b is electrically connected to the terminal 40b. The back gate of the transistor 32a is electrically connected to the terminal 50a. The back gate of the transistor 32b is electrically connected to the terminal 50b.

[0095] FIG. 9B is a diagram extracting the transistors 21, 22, the load 23, the terminal 40, the wirings 41, 42, 43, and the terminal 50 shown in FIG. 9A. Here, the terminal 40 is used as the input terminal IN, and the terminal 50 is used as the output terminal OUT.

[0096] In the case shown in FIG. 9B, when the potential of the input terminal IN increases, the voltage Vgs, which is the difference between the gate potential (the potential of the input terminal IN) and the source potential (low potential) of the transistor 21, increases. Therefore, the on-resistance of the transistor 21 decreases, and the drain current of the transistor 21 increases. Thus, the drain current of the transistor 22 connected in series with the transistor 21 also increases. Here, since the back gate of the transistor 22 is electrically connected to the input terminal IN, the threshold voltage of the transistor 22 decreases as the potential of the input terminal IN increases. Therefore, for example, even when the channel lengths, channel widths, constituent materials, etc. of the transistor 21 and the transistor 22 are all equal, the increase width of the difference between the gate potential and the source potential of the transistor 22 accompanying the increase in the potential of the input terminal IN can be made smaller than the increase width of the difference between the gate potential and the source potential of the transistor 21.

[0097] From the above, since the decrease in the drain potential (the source potential of the transistor 22) of the transistor 21 accompanying the increase in the potential of the input terminal IN can be suppressed, the decrease in the voltage Vds, which is the difference between the drain potential and the source potential of the transistor 21, can be suppressed. Therefore, the upper limit value of the potential of the input terminal IN for operating the transistor 21 in the saturation region can be increased. As a result, the width of the potential of the signal that can be input to the input terminal IN can be widened. Thus, the width of the potential of the signal that the communication device 10 can transmit and receive can be widened.

[0098] Note that the circuit having the configuration shown in FIG. 9B can also be applied to semiconductor devices other than communication devices. For example, it can be used as part of an amplifier circuit included in an operational amplifier.

[0099] FIG. 10 is a diagram showing a configuration example of the amplifier 12. For convenience of explanation, the antenna 11 is also shown in FIG. 10.

[0100] The amplifier 12 can be configured to include, in addition to the amplification circuit 20, a phase shifter 61, a capacitor 62, a switch 63, a phase shifter 64, an inductor 65, and an inductor 66. Here, the inductor 65 and the inductor 66 are provided so as to face each other.

[0101] In FIG. 10, the amplification circuit 20 is configured as shown in FIG. 2. Note that the configuration of the amplification circuit 20 included in the amplifier 12 may be other configurations shown in this embodiment. Further, the amplification circuit 20 included in the amplifier 12 may be configured as shown in the following embodiments.

[0102] The antenna 11 is electrically connected to one terminal of the phase shifter 61. The other terminal of the phase shifter 61 is electrically connected to one terminal of the capacitor 62. One terminal of the capacitor 62 is electrically connected to one terminal of the phase shifter 64. The other terminal of the capacitor 62 is electrically connected to one terminal of the switch 63. The other terminal of the switch 63 is electrically connected to the wiring 73. The other terminal of the phase shifter 64 is electrically connected to one terminal of the inductor 65. The other terminal of the inductor 65 is electrically connected to the wiring 75. One terminal of the inductor 66 is electrically connected to the terminal 40a. The other terminal of the inductor 66 is electrically connected to the terminal 40b.

[0103] The wiring 73 and the wiring 75 have a function as a power supply line. The potential of the wiring 73 and the potential of the wiring 75 can be, for example, a low potential, and can be, for example, a ground potential.

[0104] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0105] (Embodiment 2) In this embodiment, a modification of the communication device shown in Embodiment 1 will be described. Specifically, a modification of the amplification circuit 20 will be described. Note that, in this embodiment, descriptions of the same configurations as those of the communication device shown in Embodiment 1 will be omitted as appropriate.

[0106] FIG. 11 is a diagram showing a configuration example of the amplifier circuit 20, which is a modified example of the configuration shown in FIG. 2. The amplifier circuit 20 having the configuration shown in FIG. 11 is different from the amplifier circuit 20 having the configuration shown in FIG. 2 in that it includes an operational amplifier 25a, an operational amplifier 25b, an operational amplifier 35a, and an operational amplifier 35b.

[0107] In FIG. 11, all of the transistors 21a, 21b, 22a, 22b, 31a, 31b, 32a, and 32b are n-channel transistors. However, any one or all of the above transistors may be p-channel transistors. For example, as shown in FIG. 12, all of the transistors 21a, 21b, 22a, 22b, 31a, 31b, 32a, and 32b may be p-channel transistors.

[0108] One of the source or drain of the transistor 21a is electrically connected to one of the source or drain of the transistor 22a. One of the source or drain of the transistor 21b is electrically connected to one of the source or drain of the transistor 22b. One of the source or drain of the transistor 31a is electrically connected to one of the source or drain of the transistor 32a. One of the source or drain of the transistor 31b is electrically connected to one of the source or drain of the transistor 32b.

[0109] The other of the source or drain of the transistor 21a and the other of the source or drain of the transistor 21b are electrically connected to the wiring 41. The other of the source or drain of the transistor 31a and the other of the source or drain of the transistor 31b are electrically connected to the wiring 51.

[0110] The potential generation circuit 44 is electrically connected to the wiring 42. The potential generation circuit 54 is electrically connected to the wiring 52.

[0111] The non-inverting input terminals of the operational amplifiers 25a and 25b are electrically connected to the wiring 42. The non-inverting input terminals of the operational amplifiers 35a and 35b are electrically connected to the wiring 52. The inverting input terminal of the operational amplifier 25a is electrically connected to either the source or the drain of the transistor 21a and either the source or the drain of the transistor 22a. The inverting input terminal of the operational amplifier 25b is electrically connected to either the source or the drain of the transistor 21b and either the source or the drain of the transistor 22b. The inverting input terminal of the operational amplifier 35a is electrically connected to either the source or the drain of the transistor 31a and either the source or the drain of the transistor 32a. The inverting input terminal of the operational amplifier 35b is electrically connected to either the source or the drain of the transistor 31b and either the source or the drain of the transistor 32b. The output terminal of the operational amplifier 25a is electrically connected to the gate of the transistor 22a. The output terminal of the operational amplifier 25b is electrically connected to the gate of the transistor 22b. The output terminal of the operational amplifier 35a is electrically connected to the gate of the transistor 32a. The output terminal of the operational amplifier 35b is electrically connected to the gate of the transistor 32b.

[0112] Terminal 40a is electrically connected to the gate of transistor 21a, the other of the source or drain of transistor 32a, and load 33a. Terminal 40b is electrically connected to the gate of transistor 21b, the other of the source or drain of transistor 32b, and load 33b. Terminal 50a is electrically connected to the gate of transistor 31a, the other of the source or drain of transistor 22a, and load 23a. Terminal 50b is electrically connected to the gate of transistor 31b, the other of the source or drain of transistor 22b, and load 23b. Loads 23a and 23b are electrically connected to wiring 43. Loads 33a and 33b are electrically connected to wiring 53.

[0113] The potential of the output terminal of the operational amplifier changes so that the potential of the non-inverting input terminal and the potential of the inverting input terminal become equal. Therefore, when a predetermined potential is supplied to the non-inverting input terminal of the operational amplifier, the potential of the output terminal of the operational amplifier becomes a potential corresponding to the predetermined potential. Accordingly, when a bias potential is supplied to wiring 42, transistors 22a and 22b function as bias transistors. Also, when a bias potential is supplied to wiring 52, transistors 32a and 32b function as bias transistors. Here, as described above, the bias potential can be a potential at which the transistors functioning as bias transistors operate in the saturation region.

[0114] Using FIGS. 13A and 13B, an example of the operation method of the amplifier circuit 20 configured as shown in FIG. 11 will be described. FIG. 13A is a diagram showing an example of the operation method of the amplifier circuit 20 configured as shown in FIG. 11 when the terminal 40a is the input terminal INa, the terminal 40b is the input terminal INb, the terminal 50a is the output terminal OUTa, and the terminal 50b is the output terminal OUTb. FIG. 13B is a diagram showing an example of the operation method of the amplifier circuit 20 configured as shown in FIG. 11 when the terminal 50a is the input terminal INa, the terminal 50b is the input terminal INb, the terminal 40a is the output terminal OUTa, and the terminal 40b is the output terminal OUTb. Here, a signal having an inverted phase relationship with the signal input to the input terminal INa can be input to the input terminal INb.

[0115] FIG. 14A is a diagram extracted from the transistor 21 (transistor 21a or transistor 21b), transistor 22 (transistor 22a or transistor 22b), load 23 (load 23a or load 23b), operational amplifier 25 (operational amplifier 25a or operational amplifier 25b), terminal 40 (terminal 40a or terminal 40b), wiring 41, wiring 42, wiring 43, and terminal 50 (terminal 50a or terminal 50b) shown in FIG. 13A. Note that the terminal 40 is used as the input terminal IN (input terminal INa or input terminal INb), and the terminal 50 is used as the output terminal OUT (output terminal OUTa or output terminal OUTb).

[0116] FIG. 14B is a diagram showing a circuit having a configuration in which the transistor 22, the operational amplifier 25, and the wiring 42 are omitted from the circuit shown in FIG. 14A. In the circuit having the configuration shown in FIG. 14B, the terminal 50 is electrically connected to one of the source or drain of the transistor 21 and the load 23.

[0117] The configuration shown in FIG. 14B is the same as the configuration shown in FIG. 5B. In the configuration shown in FIG. 14B, as described in the explanation of FIG. 5B, in order to operate the transistor 21 in the saturation region, the potential of the input terminal IN needs to be equal to or lower than a predetermined value.

[0118] Next, consider the case shown in FIG. 14A. Even in the case shown in FIG. 14A, if the transistor 21 is an n-channel transistor as in the cases shown in FIGS. 5B and 14B, one of the source or drain of the transistor 21 can be the drain, and the other of the source or drain of the transistor 21 can be the source. Also, one of the source or drain of the transistor 22 can be the source, and the other of the source or drain of the transistor 22 can be the drain.

[0119] In the case shown in FIG. 14A, when the potential of the input terminal IN increases, the on-resistance of the transistor 21 decreases. However, the drain of the transistor 21 is electrically connected to the inverting input terminal of the operational amplifier 25, and a bias potential Vb is supplied to the non-inverting input terminal of the operational amplifier 25. Therefore, even if the on-resistance of the transistor 21 decreases, the decrease in the drain potential of the transistor 21 can be suppressed. For example, the drain potential of the transistor 21 can be made the bias potential Vb. Accordingly, the upper limit value of the potential of the input terminal IN for operating the transistor 21 in the saturation region becomes larger than the case shown in FIG. 14B. As described above, by the amplifier circuit 20 having the transistor 22 that can function as a bias transistor and the operational amplifier 25, the width of the potential of the signal that can be input to the input terminal IN can be widened. Therefore, the width of the potential of the signal that the communication device 10 can transmit and receive can be widened.

[0120] FIG. 15A is a diagram showing a configuration example of the amplifier circuit 20 and is a modification of the configuration shown in FIG. 11. The amplifier circuit 20 having the configuration shown in FIG. 15A is different from the amplifier circuit 20 having the configuration shown in FIG. 11 in that the non-inverting input terminal of the operational amplifier 25a and the non-inverting input terminal of the operational amplifier 25b are electrically connected to different wirings, and the non-inverting input terminal of the operational amplifier 35a and the non-inverting input terminal of the operational amplifier 35b are electrically connected to different wirings.

[0121] In the amplifier circuit 20 configured as shown in FIG. 15A, the non-inverting input terminal of the operational amplifier 25a and the potential generation circuit 44a are electrically connected via the wiring 42a. Also, the non-inverting input terminal of the operational amplifier 25b and the potential generation circuit 44b are electrically connected via the wiring 42b. Further, the non-inverting input terminal of the operational amplifier 35a and the potential generation circuit 54a are electrically connected via the wiring 52a. Also, the non-inverting input terminal of the operational amplifier 35b and the potential generation circuit 54b are electrically connected via the wiring 52b.

[0122] FIG. 15B is a diagram showing a configuration example of the amplifier circuit 20 and is a modified example of the configuration shown in FIG. 11. The amplifier circuit 20 configured as shown in FIG. 15B is different from the amplifier circuit 20 configured as shown in FIG. 11 in that the load 23a, the load 23b, the load 33a, the load 33b, the wiring 43, and the wiring 53 are not provided.

[0123] FIG. 16A is a diagram showing a configuration example of the amplifier circuit 20 and is a modified example of the configuration shown in FIG. 11. The amplifier circuit 20 configured as shown in FIG. 16A is different from the amplifier circuit 20 configured as shown in FIG. 11 in that back gates are provided for the transistors 22a, 22b, 32a, and 32b.

[0124] The back gate of the transistor 22a is electrically connected to the terminal 40a. The back gate of the transistor 22b is electrically connected to the terminal 40b. The back gate of the transistor 32a is electrically connected to the terminal 50a. The back gate of the transistor 32b is electrically connected to the terminal 50b.

[0125] FIG. 16B is a diagram showing the transistor 21, the transistor 22, the load 23, the operational amplifier 25, the terminal 40, the wiring 41, the wiring 42, the wiring 43, and the terminal 50 extracted from FIG. 16A. Here, the terminal 40 is used as the input terminal IN and the terminal 50 is used as the output terminal OUT.

[0126] In the case shown in FIG. 16B, when the potential of the input terminal IN increases, the voltage Vgs, which is the difference between the gate potential of the transistor 21 (the potential of the input terminal IN) and the source potential (low potential), increases. Therefore, the on-resistance of the transistor 21 decreases, and the drain current of the transistor 21 increases. Thus, the drain current of the transistor 22 connected in series with the transistor 21 also increases. Here, since the back gate of the transistor 22 is electrically connected to the input terminal IN, the threshold voltage of the transistor 22 decreases as the potential of the input terminal IN increases. Therefore, for example, even when the channel lengths, channel widths, constituent materials, etc. of the transistor 21 and the transistor 22 are all equal, the increase width of the difference between the gate potential and the source potential of the transistor 22 accompanying the increase in the potential of the input terminal IN can be made smaller than the increase width of the difference between the gate potential and the source potential of the transistor 21.

[0127] From the above, since the decrease in the drain potential of the transistor 21 (the source potential of the transistor 22) accompanying the increase in the potential of the input terminal IN can be suppressed, the decrease in the voltage Vds, which is the difference between the drain potential and the source potential of the transistor 21, can be suppressed. Therefore, the upper limit value of the potential of the input terminal IN for operating the transistor 21 in the saturation region can be increased. Thereby, the width of the potential of the signal that can be input to the input terminal IN can be widened. Thus, the width of the potential of the signal that the communication device 10 can transmit and receive can be widened.

[0128] Note that the circuit having the configuration shown in FIG. 16B can also be applied to semiconductor devices other than communication devices. For example, it can be used as part of an amplifier circuit included in an operational amplifier.

[0129] FIG. 17 is a diagram showing a configuration example of the amplifier circuit 20. The amplifier circuit 20 shown in FIG. 17 includes transistors 21a, 21b, 22a, 22b, loads 23a, 23b, operational amplifiers 25a, 25b, transistors 31a, 31b, 32a, 32b, loads 33a, 33b, operational amplifiers 35a, 35b, terminals 40a, 40b, a potential generation circuit 44, terminals 50a, 50b, and a potential generation circuit 54. In addition, the amplifier circuit 20 further includes switches 26a, 26b, 27a, 27b, 36a, 36b, 37a, 37b, a memory circuit 80, and a memory circuit 90. Although all the switches shown in FIG. 17 are in the off state, they are actually turned on and off as appropriate according to the operation of the amplifier circuit 20. Further, the switches shown in FIG. 17 can be, for example, transistors.

[0130] The memory circuit 80 can be configured to include a transistor 81 and a capacitor 82. The memory circuit 90 can be configured to include a transistor 91 and a capacitor 92.

[0131] One of the source or drain of transistor 21a is electrically connected to one of the source or drain of transistor 22a. One of the source or drain of transistor 22a is electrically connected to one terminal of switch 27a. One of the source or drain of transistor 21b is electrically connected to one of the source or drain of transistor 22b. One of the source or drain of transistor 22b is electrically connected to one terminal of switch 27b. One of the source or drain of transistor 31a is electrically connected to one of the source or drain of transistor 32a. One of the source or drain of transistor 32a is electrically connected to one terminal of switch 37a. One of the source or drain of transistor 31b is electrically connected to one of the source or drain of transistor 32b. One of the source or drain of transistor 32b is electrically connected to one terminal of switch 37b.

[0132] The other of the source or drain of transistor 21a and the other of the source or drain of transistor 21b are electrically connected to wiring 41. The other of the source or drain of transistor 31a and the other of the source or drain of transistor 31b are electrically connected to wiring 51.

[0133] The non-inverting input terminals of operational amplifier 25a and the non-inverting input terminals of operational amplifier 25b are electrically connected to wiring 42. The non-inverting input terminals of operational amplifier 35a and the non-inverting input terminals of operational amplifier 35b are electrically connected to wiring 52. The inverting input terminal of operational amplifier 25a is electrically connected to one terminal of switch 26a and the other terminal of switch 27a. The inverting input terminal of operational amplifier 25b is electrically connected to one terminal of switch 26b and the other terminal of switch 27b. The inverting input terminal of operational amplifier 35a is electrically connected to one terminal of switch 36a and the other terminal of switch 37a. The inverting input terminal of operational amplifier 35b is electrically connected to one terminal of switch 36b and the other terminal of switch 37b. The output terminal of operational amplifier 25a is electrically connected to the gate of transistor 22a. The output terminal of operational amplifier 25b is electrically connected to the gate of transistor 22b. The output terminal of operational amplifier 35a is electrically connected to the gate of transistor 32a. The output terminal of operational amplifier 35b is electrically connected to the gate of transistor 32b.

[0134] The other terminal of switch 26a is electrically connected to wiring 46a. The other terminal of switch 26b is electrically connected to wiring 46b. The other terminal of switch 36a is electrically connected to wiring 56a. The other terminal of switch 36b is electrically connected to wiring 56b.

[0135] Terminal 40a is electrically connected to the gate of transistor 21a, the other of the source or drain of transistor 32a, and load 33a. Terminal 40b is electrically connected to the gate of transistor 21b, the other of the source or drain of transistor 32b, and load 33b. Terminal 50a is electrically connected to the gate of transistor 31a, the other of the source or drain of transistor 22a, and load 23a. Terminal 50b is electrically connected to the gate of transistor 31b, the other of the source or drain of transistor 22b, and load 23b. Loads 23a and 23b are electrically connected to wiring 43. Loads 33a and 33b are electrically connected to wiring 53.

[0136] Wiring 42 is electrically connected to memory circuit 80. Specifically, wiring 42 is electrically connected to one of the source or drain of transistor 81 and one terminal of capacitor 82. Also, the other of the source or drain of transistor 81 is electrically connected to potential generation circuit 44, and the gate of transistor 81 is electrically connected to wiring 84. Further, the other terminal of capacitor 82 is electrically connected to wiring 85.

[0137] Wiring 52 is electrically connected to memory circuit 90. Specifically, wiring 52 is electrically connected to one of the source or drain of transistor 91 and one terminal of capacitor 92. Also, the other of the source or drain of transistor 91 is electrically connected to potential generation circuit 54, and the gate of transistor 91 is electrically connected to wiring 94. Further, the other terminal of capacitor 92 is electrically connected to wiring 85.

[0138] Wiring 46a, wiring 46b, wiring 56a, wiring 56b, wiring 85, and wiring 95 have the function as power lines. The potentials of wiring 46a, wiring 46b, wiring 56a, wiring 56b, wiring 85, and wiring 95 can be, for example, a constant potential. For example, the potentials of wiring 46a, wiring 46b, wiring 56a, and wiring 56b can be set to a high potential, and the potentials of wiring 85 and wiring 95 can be set to a low potential.

[0139] Memory circuit 80 has the function of holding the potential of wiring 42. Memory circuit 90 has the function of holding the potential of wiring 52. By providing memory circuit 80, it is no longer necessary to continuously supply a potential to wiring 42, and by providing memory circuit 90, it is no longer necessary to continuously supply a potential to wiring 52. Therefore, the power consumption of amplifier circuit 20 can be reduced, and thus the power consumption of communication device 10 can be reduced.

[0140] Transistor 81 included in memory circuit 80 has the function of controlling the supply of potential to wiring 42. Specifically, a potential for turning on transistor 81 is supplied to wiring 84 to connect potential generation circuit 44 and wiring 42. Then, the potential generated by potential generation circuit 44 is supplied to wiring 42. The potential generated by potential generation circuit 44 can be a bias potential Vb. Therefore, bias potential Vb can be supplied to wiring 42. After supplying bias potential Vb to wiring 42, a potential for turning off transistor 81 is supplied to wiring 84. By turning off transistor 81, the potential of wiring 42 can be held.

[0141] Transistor 81 is preferably a transistor using a metal oxide in the active layer (OS transistor). Since an oxide semiconductor, which is a kind of metal oxide, has a bandgap of 2 eV or more, the off-current is extremely small. By using transistor 81 as an OS transistor, the potential of wiring 42 can be held for a long period.

[0142] When transistor 81 is an OS transistor, memory circuit 80 can be referred to as an "OS memory".

[0143] The OS memory can retain information written over a period of one year or more, and even over a period of ten years or more, even when the power supply is stopped. Therefore, the OS memory can also be regarded as a non-volatile memory.

[0144] Also, since the OS memory writes charges to the node via the OS transistor, a high voltage that was required in conventional flash memories is not necessary, and a high-speed write operation can also be realized. Further, since charge injection and extraction to the floating gate or charge trapping layer are not performed, the OS memory can perform data writing and reading an almost unlimited number of times. The OS memory has less degradation compared to conventional flash memories and provides high reliability.

[0145] Also, the OS memory does not involve a structural change at the atomic level like a magnetic memory or a resistive change memory. Therefore, the OS memory has better rewrite resistance than magnetic memories and resistive change memories.

[0146] The above description of the memory circuit 80 can also be applied to the memory circuit 90 by respectively replacing the memory circuit 80 with the memory circuit 90, the transistor 81 with the transistor 91, the capacitor 82 with the capacitor 92, the potential generation circuit 44 with the potential generation circuit 54, the wiring 42 with the wiring 52, the wiring 84 with the wiring 94, and the wiring 85 with the wiring 95.

[0147] An example of the operation method of the amplifier circuit 20 having the configuration shown in FIG. 17 will be described with reference to FIGS. 18A and 18B. FIG. 18A is a diagram showing an example of the operation method of the amplifier circuit 20 having the configuration shown in FIG. 17 when the terminal 40a is the input terminal INa, the terminal 40b is the input terminal INb, the terminal 50a is the output terminal OUTa, and the terminal 50b is the output terminal OUTb. FIG. 18B is a diagram showing an example of the operation method of the amplifier circuit 20 having the configuration shown in FIG. 17 when the terminal 50a is the input terminal INa, the terminal 50b is the input terminal INb, the terminal 40a is the output terminal OUTa, and the terminal 40b is the output terminal OUTb.

[0148] When operating the amplifier circuit 20 by the method shown in FIGS. 18A and 18B, the memories 80 and 90 are pre-charged so that the potentials of the wirings 42 and 52 become the bias potential Vb.

[0149] First, the case of inputting signals to the terminals 40a and 40b will be described. In this case, as shown in FIG. 18A, the switches 27a, 27b, 36a, and 36b are turned on. As a result, one of the source or drain of the transistor 21a and the inverting input terminal of the operational amplifier 25a are electrically connected, and one of the source or drain of the transistor 21b and the inverting input terminal of the operational amplifier 25b are electrically connected. Therefore, as shown in FIG. 14A and the like, the transistors 22a and 22b function as bias transistors.

[0150] On the other hand, the switches 26a, 26b, 37a, and 37b are turned off. As a result, the potentials of the inverting input terminals of the operational amplifiers 35a and 35b become high potentials. In the state shown in FIG. 18A, the potentials of the non-inverting input terminals of the operational amplifier 35a and the operational amplifier 35b are the bias potential Vb, which is lower than the high potential. Also, since the switches 37a and 37b are off, there is no feedback to the operational amplifiers 35a and 35b. From the above, in the state shown in FIG. 18A, the operational amplifiers 35a and 35b function as comparators. As described above, the potential of the inverting input terminal of the operational amplifier 35a is higher than the potential of the non-inverting input terminal of the operational amplifier 35a, and the potential of the inverting input terminal of the operational amplifier 35b is higher than the potential of the non-inverting input terminal of the operational amplifier 35b. Therefore, the operational amplifiers 35a and 35b output, for example, a low potential. Accordingly, since the gate potentials of the transistors 32a and 32b become low potentials, the transistors 32a and 32b are turned off.

[0151] In FIGS. 18A and 18B, transistors, loads, switches, circuits, and wirings that do not contribute to the signal transmission from input terminal INa to output terminal OUTa and the signal transmission from input terminal INb to output terminal OUTb are indicated by dotted lines. For example, as shown in FIG. 18A, since switches 26a, 26b, transistors 32a, 32b, switch 37a, and switch 37b are in the off state, they do not contribute to the signal transmission from input terminal INa to output terminal OUTa and the signal transmission from input terminal INb to output terminal OUTb. Also, since transistors 32a and 32b are in the off state, no current flows through transistors 31a and 31b, and they do not contribute to the signal transmission from input terminal INa to output terminal OUTa and the signal transmission from input terminal INb to output terminal OUTb. Further, load 33a electrically connected to the other of the source or drain of transistor 32a in the off state and load 33b electrically connected to the other of the source or drain of transistor 32b in the off state also do not contribute to the signal transmission from input terminal INa to output terminal OUTa and the signal transmission from input terminal INb to output terminal OUTb. From the above, in FIG. 18A, transistors 31a, 31b, transistors 32a, 32b, load 33a, load 33b, switches 26a, 26b, switch 37a, and switch 37b, and a part of the circuits and wirings electrically connected to these are indicated by dotted lines.

[0152] Next, the case of inputting signals to terminals 50a and 50b will be described. In this case, as shown in FIG. 18B, switches 26a, 26b, switch 37a, and switch 37b are turned on. As a result, one of the source or drain of transistor 31a and the inverting input terminal of operational amplifier 35a are electrically connected, and one of the source or drain of transistor 31b and the inverting input terminal of operational amplifier 35b are electrically connected. Therefore, as shown in FIG. 14A and the like, transistors 32a and 32b function as bias transistors.

[0153] On the one hand, turn off switch 27a, switch 27b, switch 36a, and switch 36b. As a result, the potential at the inverting input terminal of operational amplifier 25a and the potential at the inverting input terminal of operational amplifier 25b become high potentials. In the state shown in FIG. 18B, the potentials at the non-inverting input terminals of operational amplifier 25a and operational amplifier 25b are the bias potential Vb, which is lower than the high potential. Also, since switch 27a and switch 27b are in the off state, there is no feedback applied to operational amplifier 25a and operational amplifier 25b. From the above, in the state shown in FIG. 18B, operational amplifier 35a and operational amplifier 35b function as comparators. As described above, the potential at the inverting input terminal of operational amplifier 25a is higher than the potential at the non-inverting input terminal of operational amplifier 25a, and the potential at the inverting input terminal of operational amplifier 25b is higher than the potential at the non-inverting input terminal of operational amplifier 25b. Therefore, operational amplifier 25a and operational amplifier 25b output, for example, a low potential. Accordingly, since the gate potentials of transistor 22a and transistor 22b become low potentials, transistor 22a and transistor 22b are in the off state.

[0154] As shown in FIG. 18B, since switch 27a, switch 27b, transistor 22a, transistor 22b, switch 36a, and switch 36b are in the off state, they do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. Also, since transistor 22a and transistor 22b are in the off state, no current flows through transistor 21a and transistor 21b, and they do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. Further, load 23a electrically connected to the other of the source or drain of transistor 22a in the off state, and load 23b electrically connected to the other of the source or drain of transistor 22b in the off state also do not contribute to the transmission of signals from input terminal INa to output terminal OUTa and from input terminal INb to output terminal OUTb. From the above, in FIG. 18B, transistor 21a, transistor 21b, transistor 22a, transistor 22b, load 23a, load 23b, switch 27a, switch 27b, switch 36a, and switch 36b, and a part of the circuits and wirings electrically connected to them are indicated by dotted lines.

[0155] Note that the explanations shown in FIGS. 14A and 14B can also be applied when the amplifier circuit 20 has the configuration shown in FIG. 17. Also, the configuration shown in FIG. 16A and the explanation shown in FIG. 16B can also be applied when the amplifier circuit 20 has the configuration shown in FIG. 17. Specifically, back gates can be provided for transistor 22a, transistor 22b, transistor 32a, and transistor 32b included in the amplifier circuit 20 having the configuration shown in FIG. 17. And the back gate of transistor 22a can be electrically connected to terminal 40a, the back gate of transistor 22b can be electrically connected to terminal 40b, the back gate of transistor 32a can be electrically connected to terminal 50a, and the back gate of transistor 32b can be electrically connected to terminal 50b.

[0156] FIG. 19 is a diagram showing the transistor 21 (transistor 21a or transistor 21b), transistor 22 (transistor 22a or transistor 22b), load 23 (load 23a or load 23b), operational amplifier 25 (operational amplifier 25a or operational amplifier 25b), switch 26 (switch 26a or switch 26b), switch 27 (switch 27a or switch 27b), terminal 40 (terminal 40a or terminal 40b), wiring 41, wiring 42, wiring 43, and terminal 50 (terminal 50a or terminal 50b) shown in FIG. 18A. Note that the terminal 40 is used as an input terminal IN (input terminal INa or input terminal INb), and the terminal 50 is used as an output terminal OUT (output terminal OUTa or output terminal OUTb).

[0157] The circuit having the configuration shown in FIG. 19 can also be applied to semiconductor devices other than communication devices. For example, it can be used as a part of an amplifier circuit included in an operational amplifier.

[0158] FIG. 20A is a diagram showing a configuration example of the amplifier circuit 20, which is a modified example of the configuration shown in FIG. 17. The amplifier circuit 20 having the configuration shown in FIG. 13A is different from the amplifier circuit 20 having the configuration shown in FIG. 17 in that it does not have the memory circuits 80 and 90.

[0159] In the amplifier circuit 20 having the configuration shown in FIG. 20A, the potential generation circuit 44 and the potential generation circuit 54 generate a bias potential Vb. Thereby, the potentials of the wiring 42 and the wiring 52 are set to the bias potential Vb.

[0160] FIG. 20B is a diagram showing a configuration example of the amplifier circuit 20, which is a modified example of the configuration shown in FIG. 17. The amplifier circuit 20 having the configuration shown in FIG. 20B is different from the amplifier circuit 20 having the configuration shown in FIG. 17 in that the non-inverting input terminals of the operational amplifier 25a and the operational amplifier 25b and the non-inverting input terminals of the operational amplifier 35a and the operational amplifier 35b are electrically connected to each other. Also, the amplifier circuit 20 having the configuration shown in FIG. 20B is different from the amplifier circuit 20 having the configuration shown in FIG. 17 in that the memory circuit 90 and the potential generation circuit 54 are not provided.

[0161] The amplifier circuit 20 configured as shown in FIG. 20B has the non-inverting input terminals of the operational amplifier 25a, the non-inverting input terminals of the operational amplifier 25b, the non-inverting input terminals of the operational amplifier 35a, and the non-inverting input terminals of the operational amplifier 35b electrically connected to the memory circuit 80. Specifically, the non-inverting input terminals of the operational amplifier 25a, the non-inverting input terminals of the operational amplifier 25b, the non-inverting input terminals of the operational amplifier 35a, and the non-inverting input terminals of the operational amplifier 35b are electrically connected to one of the source or drain of the transistor 81 and one of the terminals of the capacitor 82.

[0162] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0163] (Embodiment 3) In this embodiment, a configuration of a transistor applicable to the communication device and the semiconductor device described in the above embodiment will be described.

[0164] A partial cross-sectional configuration of a semiconductor device included in a communication device according to an aspect of the present invention or a semiconductor device according to an aspect of the present invention is shown in FIG. 21. The semiconductor device configured as shown in FIG. 21 has a transistor 550 and a transistor 500. Also, a cross-sectional view in the channel length direction of the transistor 500 and the transistor 550 is shown in FIG. 22A, and a cross-sectional view in the channel width direction of the transistor 500 and the transistor 550 is shown in FIG. 22B. For example, the transistor 500 corresponds to the transistor 21 shown in the above embodiment, and the transistor 550 corresponds to the transistor 22 shown in the above embodiment. Here, the transistor 500 and the transistor 550 can be OS transistors. Note that one or both of the transistor 500 and the transistor 550 may be a transistor other than the OS transistor. For example, one or both of the transistor 500 and the transistor 550 may be a transistor (Si transistor) using silicon in the active layer.

[0165] In the semiconductor device configured as shown in FIG. 21, the transistor 500 is provided above the transistor 550. Note that the transistor 500 and the transistor 550 may be provided in the same layer.

[0166] As shown in FIGS. 22A and 22B, the transistor 500 and the transistor 550 include a conductor 503 arranged to be embedded in insulators 514 and 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged separately from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an insulator 545 arranged to have a region in contact with the bottom surface and the side surface of the opening, and a conductor 560 arranged on the formation surface of the insulator 545.

[0167] Also, as shown in FIGS. 22A and 22B, it is preferable that an insulator 544 is arranged between the oxides 530a, 530b, the conductors 542a, and 542b and the insulator 580. Also, as shown in FIGS. 22A and 22B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided to be embedded inside the conductor 560a. Also, as shown in FIGS. 22A and 22B, it is preferable that an insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 545.

[0168] Note that in this specification and the like, the oxides 530a and 530b may be collectively referred to as the oxide 530.

[0169] Note that, in transistors 500 and 550, a structure in which two layers of oxide 530a and oxide 530b are stacked in the region where the channel is formed and in its vicinity is shown, but the present invention is not limited to this. For example, a single layer of oxide 530b or a stacked structure of three or more layers may be provided.

[0170] Also, in transistors 500 and 550, the conductor 560 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. Also, the transistors 500 and 550 shown in FIGS. 21, 22A, and 22B are examples, and the present invention is not limited to their structures. Appropriate transistors may be used according to the circuit configuration, driving method, etc.

[0171] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistors 500 and 550, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing an alignment margin, the occupied area of the transistors 500 and 550 can be reduced. As a result, miniaturization and high integration of the semiconductor device can be achieved.

[0172] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductors 542a and 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Thus, the switching speed of the transistors 500 and 550 can be improved, and the frequency characteristics can be enhanced.

[0173] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. Further, the conductor 560 may function as a front gate electrode and the conductor 503 may function as a back gate electrode. In that case, the threshold voltage of the transistors 500 and 550 can be controlled by independently changing the potential applied to the conductor 503 without linking it to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistors 500 and 550 can be made greater than 0V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0174] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thereby, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected and can cover the channel formation region formed in the oxide 530.

[0175] In this specification and the like, a configuration of a transistor in which a channel formation region is electrically surrounded by an electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (s-channel) configuration. Further, in this specification and the like, the s-channel configuration has features such that the sides and periphery of the oxide 530 in contact with the conductors 542a and 542b that function as source and drain electrodes are of the same I-type as the channel formation region. Also, since the sides and periphery of the oxide 530 in contact with the conductors 542a and 542b are in contact with the insulator 544, they can be of the I-type similar to the channel formation region. Note that, in this specification and the like, the I-type can be treated as being the same as high-purity intrinsic to be described later. Also, the s-channel configuration disclosed in this specification and the like is different from the Fin-type configuration and the planar-type configuration. By adopting the s-channel configuration, it is possible to enhance resistance to the short-channel effect, in other words, to make a transistor in which the short-channel effect hardly occurs.

[0176] Further, the conductor 503 can be configured to include a conductor 503a and a conductor 503b. The conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is further formed inside. Note that, in this embodiment, the conductor 503 is configured such that the conductor 503a and the conductor 503b are laminated, but the present invention is not limited to this. For example, the conductor 503 may be provided in a single-layer or a laminated configuration of three or more layers.

[0177] Here, it is preferable to use a conductive material for the conductor 503a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that, in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0178] For example, since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity.

[0179] Further, when the conductor 503 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503b.

[0180] The insulators 520, 522, and 524 have a function as a gate insulating film for the conductor 503.

[0181] Here, for the insulator 524 in contact with the oxide 530, it is preferable to use an insulator containing more oxygen than the stoichiometric composition. The oxygen is likely to be released from the film by heating. In this specification and the like, the oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : also referred to as oxygen vacancy) in the oxide 530 can be reduced, and the reliability of the transistors 500 and 550 can be improved. When hydrogen enters the oxygen vacancies in the oxide 530, the defect (hereinafter sometimes referred to as V O H) may function as a donor, and electrons as carriers may be generated. Also, a part of the hydrogen may combine with oxygen that binds to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, it is preferable to reduce V O H in the oxide 530 as much as possible to make it highly pure intrinsic or substantially highly pure intrinsic. Thus, V OIn order to obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment"), and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiencies (also referred to as "oxygen addition treatment"). V O By using an oxide semiconductor with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0182] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. The oxide that desorbs oxygen by heating means that in TDS (Thermkesorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0183] Further, the insulator having the excess oxygen region and the oxide 530 may be brought into contact and subjected to any one or more of heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction in which the bond of VoH is broken occurs, in other words, a reaction of "V O H→Vo+H" occurs, and dehydrogenation can be achieved. A part of the hydrogen generated at this time may combine with oxygen and be removed as H2O from the oxide 530 or the insulator near the oxide 530. Also, a part of the hydrogen may be gettered by the conductor 542a or the conductor 542b.

[0184] In addition, for the above microwave treatment, it is preferable to use, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated. Then, by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Further, for the above microwave treatment, the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. Further, as the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0185] In addition, during the manufacturing process of the transistor 500 and the transistor 550, it is preferable to perform a heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V O ). The heat treatment may also be performed under reduced pressure. Alternatively, after performing the heat treatment in an atmosphere of nitrogen gas or an inert gas, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen. Alternatively, after performing the heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0186] Note that by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 can be repaired with the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with oxygen vacancies to form V O H

[0187] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0188] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen and impurities because the oxygen possessed by the oxide 530 will not diffuse to the insulator 520 side. Also, it is preferable that the conductor 503 can suppress the reaction with the oxygen possessed by the insulator 524 and the oxide 530.

[0189] The insulator 522 is preferably a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0190] In particular, it is preferable to use an insulator containing one or both oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to permeate). As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the periphery of the transistors 500 and 550 into the oxide 530.

[0191] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated and used on the above insulators.

[0192] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0193] Also, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0194] Note that in the transistors 500 and 550 of FIGS. 22A and 22B, insulators 520, 522, and 524 are illustrated as a gate insulating film having a three-layer stacked structure with respect to the conductor 503. However, the gate insulating film may have a single-layer, two-layer, or four-layer or more stacked structure. In that case, it is not limited to a stacked structure made of the same material, and a stacked structure made of different materials may also be used.

[0195] For the transistors 500 and 550, a metal oxide that functions as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used.

[0196] The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0197] In addition, as the metal oxide that functions as the channel formation region in the oxide 530, it is preferable to use one having a bandgap of 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide having a large bandgap in this way, the off-current of the transistor can be reduced.

[0198] The oxide 530 has the oxide 530a under the oxide 530b, so that the diffusion of impurities from the constituent formed below the oxide 530a to the oxide 530b can be suppressed.

[0199] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0200] Also, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0201] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b can also be said to change continuously or be continuously joined. To achieve this, it is advisable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0202] Specifically, by having a common element (as the main component) other than oxygen in the oxide 530a and the oxide 530b, a mixed layer with a low density of defect energy levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is advisable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0203] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxide 530a as described above, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistors 500 and 550 can obtain a high on-current.

[0204] On the oxide 530b, conductors 542a and 542b that function as a source electrode and a drain electrode are provided. As the conductors 542a and 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal elements as components, or an alloy combining the above-described metal elements, etc. are preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0205] In addition, in FIG. 22A, although the conductors 542a and 542b are shown as a single-layer structure, they may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0206] Also, a three-layer structure in which a titanium film or a titanium nitride film is laminated with an aluminum film or a copper film on the titanium film or the titanium nitride film, and then a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film is laminated with an aluminum film or a copper film on the molybdenum film or the molybdenum nitride film, and then a molybdenum film or a molybdenum nitride film is formed thereon, and the like exist. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0207] Also, as shown in FIG. 22A, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0208] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0209] The insulator 544 is provided to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided to cover the side surface of the oxide 530 and contact the insulator 524.

[0210] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, silicon oxynitride or silicon nitride can also be used as the insulator 544.

[0211] In particular, as the insulator 544, it is preferable to use aluminum oxide or hafnium oxide, which is an insulator containing one or both of aluminum and hafnium oxides. Or, it is preferable to use an oxide containing aluminum and hafnium (hafnium aluminate), etc. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in a later process. When the conductor 542a and the conductor 542b are made of a material having oxidation resistance, or when the material does not significantly decrease in conductivity even when absorbing oxygen, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0212] By having the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 to the oxide 530b. Further, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen of the insulator 580.

[0213] The insulator 545 functions as a gate insulating film for the conductor 560. The insulator 545 is preferably formed using an insulator that contains an excessive amount of oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0214] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they are stable against heat.

[0215] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the impurity concentration such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less.

[0216] Further, in order to efficiently supply the excess oxygen possessed by insulator 545 to oxide 530, a metal oxide may be provided between insulator 545 and conductor 560. The metal oxide preferably has a function of suppressing oxygen diffusion from insulator 545 to conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from insulator 545 to conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to oxide 530 can be suppressed. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0217] Note that insulator 545 may have a laminated structure, similar to the gate insulating film for conductor 503. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming the insulator that functions as the gate insulating film into a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a laminated structure that is thermally stable and has a high relative permittivity can be obtained.

[0218] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 22A and 22B, but it may be a single-layer structure or a laminated structure of three or more layers.

[0219] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by oxygen contained in the insulator 545 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0220] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0221] The insulator 580 is provided on the conductor 542a and on the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin or the like is preferably used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Also, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later process.

[0222] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that it is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0223] The opening of the insulator 580 is formed to overlap with the region between the conductor 542a and the conductor 542b. Thereby, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0224] When miniaturizing the semiconductor device, it is required to shorten the gate length. On the other hand, it is necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to prevent the conductivity of the conductor 560 from decreasing, the conductor 560 may have a high aspect ratio shape. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a high aspect ratio shape, it can be formed without collapsing the conductor 560 during the process.

[0225] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0226] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used.

[0227] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0228] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 etc., it is preferable that the concentration of impurities such as water or hydrogen in the film is reduced in the insulator 581.

[0229] Also, the conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductor 546 described later.

[0230] A wiring layer may be provided above the transistor 550. For example, in FIG. 21, on the transistor 550, in addition to the insulators 574 and 581, the insulators 350, 352, and 354 are laminated and provided. Further, a conductor 356 is embedded in the insulators 350, 352, and 354. The conductor 356 has a function as a plug connected to the transistor 550 or a wiring.

[0231] As materials for each plug and wiring, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used singly or in a laminated manner. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0232] A wiring layer may be provided on the insulator 354 and on the conductor 356. For example, in FIG. 21, the insulators 360, 362, and 364 are laminated and provided in this order. Further, a conductor 366 is embedded in the insulators 360, 362, and 364. The conductor 366 has a function as a plug or a wiring.

[0233] A wiring layer may be provided on the insulator 364 and on the conductor 366. For example, in FIG. 21, the insulators 370, 372, and 374 are laminated and provided in this order. Further, a conductor 376 is embedded in the insulators 370, 372, and 374. The conductor 376 has a function as a plug or a wiring.

[0234] A wiring layer may be provided on the insulator 374 and on the conductor 376. For example, in FIG. 8, the insulators 380, 382, and 384 are laminated and provided in this order. Further, a conductor 386 is embedded in the insulators 380, 382, and 384. The conductor 386 has a function as a plug or a wiring.

[0235] The conductor 366, the conductor 376, and the conductor 386 can have the same configuration as the conductor 356.

[0236] In the above, although the semiconductor device according to one aspect of the present invention has a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386, the semiconductor device according to one aspect of the present invention is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or may be five or more.

[0237] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are laminated and provided in this order.

[0238] In addition, conductors such as the conductor 518 and the conductor (for example, the conductor 503) constituting the transistor 500 are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 has a function as a plug or a wiring.

[0239] On the transistor 500, in addition to the insulator 574 and the insulator 581, an insulator 582 and an insulator 586 are laminated and provided. It is preferable to use a material having a barrier property against oxygen and hydrogen for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the insulator 582.

[0240] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable to be used as a protective film for the transistor 500.

[0241] In addition, conductors 546 and the like are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0242] Conductor 546 functions as a plug connected to transistor 500 or transistor 550, or as a wiring.

[0243] After forming transistor 500, an opening may be formed so as to surround transistor 500, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By wrapping transistor 500 with the above-described insulator having high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively wrapped with an insulator having high barrier properties against hydrogen or water. When forming an opening so as to surround transistor 500, for example, an opening reaching insulator 522 or insulator 514 is formed, and the above-described insulator having high barrier properties is formed so as to be in contact with insulator 522 or insulator 514. This is preferable because it can also serve as part of the manufacturing process of transistor 500. As the insulator having high barrier properties against hydrogen or water, for example, the same material as insulator 522 or insulator 514 may be used. Even after forming transistor 550, an opening may be formed so as to surround transistor 550 in the same manner as after forming transistor 500, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening.

[0244] Also, a conductor 610 and a conductor 612 may be provided on the conductor 546 and on the insulator 586. The conductor 610 and the conductor 612 have a function as a plug electrically connected to the transistor 500 or as a wiring. In the configuration shown in FIG. 21, one of the source electrode or the drain electrode of the transistor 550 (the conductor 542b included in the transistor 550) and one of the source electrode or the drain electrode of the transistor 500 (the conductor 542b included in the transistor 500) are electrically connected via the conductor 546, the conductor 356, the conductor 366, the conductor 376, the conductor 386, the conductor 518, and the conductor 610.

[0245] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0246] In the present embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the present invention is not limited to this configuration, and a stacked configuration of two or more layers may be used. For example, a conductor having a barrier property, and a conductor having a high adhesiveness to the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.

[0247] An insulator 640 is provided on the conductor 610, on the conductor 612, and on the insulator 586. The insulator 640 may function as a planarization film covering the uneven shape below it.

[0248] By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0249] <Modified Example 1 of Transistor> With reference to FIGS. 23A, 23B, and 23C, a configuration example of transistor 600A will be described. Transistor 600A is a modified example of transistors 500 and 550 having the configurations shown in FIGS. 22A and 22B. FIG. 23A is a top view of transistor 600A. FIG. 23B is a cross-sectional view of the L1-L2 portion indicated by the dashed line in FIG. 23A. FIG. 23C is a cross-sectional view of the W1-W2 portion indicated by the dashed line in FIG. 23A. In the top view of FIG. 23A, the description of some elements is omitted for clarity of the drawing.

[0250] Transistor 600A differs from transistors 500 and 550 having the configurations shown in FIGS. 22A and 22B in that it has insulator 552, insulator 513, and insulator 404. Also, insulator 552 is provided in contact with the side surface of conductor 540a, and insulator 552 is provided in contact with the side surface of conductor 540b, which is different from transistors 500 and 550 having the configurations shown in FIGS. 22A and 22B. Further, it differs from transistors 500 and 550 having the configurations shown in FIGS. 22A and 22B in that it does not have insulator 520.

[0251] Insulator 513 is provided on insulator 512 in transistor 600A. Also, insulator 404 is provided on insulator 574 and on insulator 513.

[0252] In the transistor 600A, the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 is configured to cover them. That is, the insulator 404 is in contact with the upper surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the upper surface of the insulator 513, respectively. Thereby, the oxide 530 etc. are isolated from the outside by the insulator 404 and the insulator 513.

[0253] It is preferable that the insulator 513 and the insulator 404 have a high function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. For example, as the insulator 513 and the insulator 404, it is preferable to use silicon nitride or silicon oxynitride, which are materials with high hydrogen barrier properties. Thereby, since the diffusion of hydrogen etc. into the oxide 530 can be suppressed, the deterioration of the characteristics of the transistor 600A can be suppressed. Therefore, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0254] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulator 552, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which are materials with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, the diffusion of impurities such as water or hydrogen from the insulator 580 etc. through the conductor 540a or the conductor 540b into the oxide 530 can be suppressed. Also, the absorption of oxygen contained in the insulator 580 by the conductor 540a and the conductor 540b can be suppressed. As described above, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0255] <Modification Example 2 of Transistor> Using FIGS. 24A, 24B, and 24C, a configuration example of transistor 600B will be described. FIG. 24A is a top view of transistor 600B. FIG. 24B is a cross-sectional view of the L1-L2 portion indicated by the dashed line in FIG. 24A. FIG. 24C is a cross-sectional view of the W1-W2 portion indicated by the dashed line in FIG. 24A. In the top view of FIG. 24A, the description of some elements is omitted for clarity of the figure.

[0256] Transistor 600B is a modification of transistor 500 and transistor 550, and is a transistor that can be replaced with transistor 500 and transistor 550. Therefore, to avoid repetition of the description, mainly the differences between transistor 600B and transistor 500 and transistor 550 will be described.

[0257] Conductor 560 that functions as the first gate electrode has conductor 560a and conductor 560b on conductor 560a. It is preferable to use a conductive material for conductor 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0258] Since conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of conductor 560b can be improved. That is, by having conductor 560a, oxidation of conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0259] Further, it is preferable to provide an insulator 544 so as to cover the upper surface and the side surface of the conductor 560 and the side surface of the insulator 545. Note that the insulator 544 is preferably made of an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, other materials such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can also be used.

[0260] By providing the insulator 544, oxidation of the conductor 560 can be suppressed. Further, by having the insulator 544, diffusion of impurities such as water and hydrogen that the insulator 580 has into the transistor 600B can be suppressed.

[0261] Since the conductor 560 overlaps a part of the conductor 542a and a part of the conductor 542b in the transistor 600B, the parasitic capacitance is likely to be larger than that of the transistor 500 and the transistor 550. Therefore, the operating frequency tends to be lower than that of the transistor 500 and the transistor 550. However, since the process of forming an opening in the insulator 580 or the like and embedding the conductor 560, the insulator 545, or the like is unnecessary, the productivity is high as compared with the transistor 500 and the transistor 550.

[0262] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, structures, methods, etc. shown in other embodiments.

[0263] (Embodiment 4) In this embodiment, an oxide semiconductor which is a kind of metal oxide will be described.

[0264] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0265] <Classification of Crystal Structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 25A. FIG. 25A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0266] As shown in FIG. 25A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, "CAAC (c-axis-aligned crystalline)", "nc (nanocrystalline)", and "CAC (cloud-aligned composite)" are included in "Crystalline". Note that "single crystal", "poly crystal", and "completely amorphous" are excluded from the classification of "Crystalline". Further, "single crystal" and "poly crystal" are included in "Crystal".

[0267] Note that the structure within the thick frame shown in Fig. 25A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0268] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in Fig. 25B. Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 25B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 25B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 25B is 500 nm.

[0269] As shown in Fig. 25B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected in the vicinity of 2θ = 31°. Note that, as shown in Fig. 25B, the peak in the vicinity of 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0270] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 25C. FIG. 25C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 25C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0271] As shown in FIG. 25C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0272] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 25A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-described CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0273] Here, the details of the above-described CAAC-OS, nc-OS, and a-like OS will be described.

[0274] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Here, the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Further, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Furthermore, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain indicates a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in the region where the plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor having c-axis orientation and no clear orientation in the a-b plane direction.

[0275] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Further, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be about several tens of nm.

[0276] Also, in an In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and the element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Further, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0277] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type, composition, etc. of the metal element constituting the CAAC-OS.

[0278] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also called the direct spot) as the center of symmetry.

[0279] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0280] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and carriers are likely to be captured, causing a decrease in the on-current of the transistor, a decrease in the field-effect mobility, etc. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0281] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to crystal grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0282] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nano crystals. Also, nc-OS has no regularity in the crystal orientation between different nano crystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than the nano crystal (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nano beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the nano crystal (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0283] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0284] [[Configuration of Oxide Semiconductor]] Next, the details of the above-mentioned CAC-OS will be described. Note that the CAC-OS relates to the material composition.

[0285] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. Hereinafter, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0286] Furthermore, the CAC-OS is a configuration (hereinafter also referred to as a cloud state) in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film. That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0287] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0288] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0289] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0290] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0291] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0292] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0293] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0294] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0295] For a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, still more preferably 1×10 11 cm -3 or less, even more preferably 1×10 10 cm -3 less, and 1×10 -9 cm-3 The above is the case. In order to reduce the carrier concentration of the oxide semiconductor film, it is sufficient to reduce the impurity concentration in the oxide semiconductor film and the density of defect levels. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0296] In addition, since an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the trap level density may also be low.

[0297] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0298] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0299] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0300] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0301] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0302] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5×10 17 atoms / cm 3 or less.

[0303] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen that binds to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons that are carriers may be generated. Also, a part of the hydrogen may bind to oxygen that binds to metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0304] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0305] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0306] (Embodiment 5) In this embodiment, application examples of the semiconductor device described above will be described. In this embodiment, it is assumed that the scope indicated by the term "semiconductor device" includes communication devices. Also, in other embodiments, the scope indicated by the term "semiconductor device" may include communication devices.

[0307] [Semiconductor Wafer, Chip] FIG. 26A shows a top view of a substrate 711 before dicing processing. As the substrate 711, for example, a semiconductor substrate (also referred to as a "semiconductor wafer") can be used. A plurality of circuit regions 712 are provided on the substrate 711. In the circuit region 712, a semiconductor device according to an aspect of the present invention, a CPU, an RF tag, an image sensor, or the like can be provided.

[0308] The plurality of circuit regions 712 are each surrounded by a separation region 713. A separation line (also referred to as a "dicing line") 714 is set at a position overlapping the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. An enlarged view of the chip 715 is shown in FIG. 26B.

[0309] Also, a conductive layer or a semiconductor layer may be provided in the separation region 713. By providing a conductive layer or a semiconductor layer in the separation region 713, ESD that may occur during the dicing process can be alleviated, and a reduction in the yield of the dicing process can be prevented. In general, the dicing process is performed while flowing pure water in which carbon dioxide gas or the like is dissolved to lower the resistivity to the cutting part for the purpose of cooling the substrate, removing chips, preventing charging, and the like. By providing a conductive layer or a semiconductor layer in the separation region 713, the amount of use of the pure water can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Also, the productivity of the semiconductor device can be increased.

[0310] As the semiconductor layer provided in the separation region 713, it is preferable to use a material having a band gap of 2.5 eV or more and 4.2 eV or less, and more preferably a material having a band gap of 2.7 eV or more and 3.5 eV or less. By using such a material, the accumulated charge can be slowly discharged, so that a rapid movement of charge due to ESD can be suppressed, and electrostatic breakdown can be made less likely to occur.

[0311] 〔Electronic Component〕 An example of applying the chip 715 to an electronic component will be described with reference to FIG. 27. Note that the electronic component is also referred to as a semiconductor package or an IC package. There are a plurality of standards and names for electronic components depending on the terminal extraction direction and the shape of the terminals.

[0312] In the assembly process (post-process), the semiconductor device shown in the above embodiment and components other than the semiconductor device are combined to complete the electronic component.

[0313] The post-process will be described using the flowchart shown in FIG. 27A. After the element substrate having the semiconductor device shown in the above embodiment is completed in the pre-process, a "back grinding process" of grinding the back surface (the surface on which the semiconductor device and the like are not formed) of the element substrate is performed (step S721). By thinning the element substrate by grinding, warping and the like of the element substrate can be reduced, and miniaturization of the electronic component can be achieved.

[0314] Next, a "dicing process" of separating the element substrate into a plurality of chips (chip 715) is performed (step S722). Then, a "die bonding process" of individually picking up the separated chips and bonding them onto the lead frame is performed (step S723). For the bonding between the chip and the lead frame in the die bonding process, a method suitable for the product, such as bonding with resin or bonding with tape, is appropriately selected. Note that the chip may be bonded onto an interposer substrate instead of the lead frame.

[0315] Next, a "wire bonding process" of electrically connecting the leads of the lead frame and the electrodes on the chip with a thin metal wire (wire) is performed (step S724). As the thin metal wire, a silver wire or a gold wire can be used. Also, ball bonding or wedge bonding can be used for wire bonding.

[0316] The wire-bonded chip is subjected to a "sealing process (molding process)" in which it is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, and the circuit portion built in the chip and the wires connecting the chip and the leads can be protected from mechanical external forces, and deterioration of characteristics (reduction in reliability) due to moisture and dust can be reduced.

[0317] Next, a "lead plating process" for plating the leads of the lead frame is performed (step S726). The plating process can prevent the leads from rusting and enable more reliable soldering when mounting on a printed circuit board later. Next, a "forming process" for cutting and forming the leads is performed (step S727).

[0318] Next, a "marking process" for performing printing processing (marking) on the surface of the package is performed (step S728). Then, through an "inspection process" (step S729) for examining the quality of the external shape, the presence or absence of malfunction, etc., the electronic component is completed (step S729).

[0319] Further, a perspective schematic view of the completed electronic component is shown in FIG. 27B. In FIG. 27B, a perspective schematic view of a QFP (Quad Flat Package) is shown as an example of the electronic component. The electronic component 750 shown in FIG. 27B shows leads 755 and a semiconductor device 753. As the semiconductor device 753, the semiconductor devices shown in the above embodiments can be used.

[0320] The electronic component 750 shown in FIG. 27B is mounted on a printed circuit board 752, for example. A plurality of such electronic components 750 are combined, and each is electrically connected on the printed circuit board 752 to complete a substrate (mounted substrate 754) on which the electronic components are mounted. The completed mounted substrate 754 is used in electronic devices and the like.

[0321] 〔Electronic device〕 Next, an example of an electronic device including the semiconductor device or the above electronic component according to one aspect of the present invention will be described with reference to FIG. 28.

[0322] As electronic devices using the semiconductor device or electronic component according to one aspect of the present invention, there are a display device such as a television or a monitor, a lighting device, a desktop or notebook personal computer, a word processor, an image playback device for playing back still images or moving images stored in a recording medium such as a DVD (Digital Versatile Disc), a portable CD player, a radio, a tape recorder, a headphone stereo, a stereo, a table clock, a wall clock, a cordless telephone handset, a transceiver, a mobile phone, a car phone, a portable game machine, a tablet terminal, a large game machine such as a pachinko machine, a calculator, a portable information terminal (also referred to as a "portable information device"), an electronic notebook, an e-book terminal, an electronic translator, a voice input device, a video camera, a digital still camera, a high-frequency heating device such as an electric shaver or a microwave oven, an electric rice cooker, an electric washing machine, an electric vacuum cleaner, a water heater, a fan, a hair dryer, air conditioning equipment such as an air conditioner, a humidifier, and a dehumidifier, a dishwasher, a dish dryer, a clothes dryer, a futon dryer, an electric refrigerator, an electric freezer, an electric refrigerator-freezer, a freezer for DNA storage, a flashlight, a tool such as a chain saw, a medical device such as a smoke detector or a dialysis device, and the like. Further, there are industrial devices such as induction lamps, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for load leveling and smart grids.

[0323] In addition, a moving body propelled by an electric motor using the power from a power storage device is also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle obtained by changing the tire wheels of these vehicles to an endless track, a motorized bicycle including an electric assist bicycle, a motorcycle, an electric wheelchair, a golf cart, a small or large ship, a submarine, a helicopter, an aircraft, a rocket, an artificial satellite, a space exploration vehicle or a planetary exploration vehicle, a spaceship, and the like.

[0324] The semiconductor device or electronic component according to one aspect of the present invention can be used for a communication device or the like built in these electronic devices.

[0325] The electronic device may have sensors (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), etc.

[0326] The electronic device can have various functions. For example, it can have functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, touch panel function, calendar, date or time display function, executing various software (programs), wireless communication function, reading programs or data recorded on a recording medium, etc.

[0327] Figures 28 and 29A to 29F show an example of an electronic device. In Figure 28, the display device 8000 is an example of an electronic device using the semiconductor device 8004 according to one aspect of the present invention. Specifically, the display device 8000 corresponds to a display device for receiving TV broadcasts and has a housing 8001, a display unit 8002, a speaker unit 8003, a semiconductor device 8004, a power storage device 8005, etc. The semiconductor device 8004 according to one aspect of the present invention is provided inside the housing 8001. The semiconductor device 8004 can hold control information, control programs, etc. Further, the semiconductor device 8004 has a communication function and can make the display device 8000 function as an IoT device. Also, the display device 8000 can receive power supply from a commercial power source or use the power stored in the power storage device 8005.

[0328] For the display unit 8002, a display device such as a liquid crystal display device, a light-emitting display device having a light-emitting element such as an organic EL element in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), an FED (Field Emission Display), etc. can be used.

[0329] Note that the display device includes all display devices for information display, such as for TV broadcast reception, personal computers, advertisement display, etc.

[0330] In FIG. 28, the installed lighting device 8100 is an example of an electronic device using the semiconductor device 8103 according to one aspect of the present invention. Specifically, the lighting device 8100 includes a housing 8101, a light source 8102, a semiconductor device 8103, a power storage device 8105, etc. In FIG. 28, the case where the semiconductor device 8103 is provided inside the ceiling 8104 where the housing 8101 and the light source 8102 are installed is illustrated, but the semiconductor device 8103 may be provided inside the housing 8101. The semiconductor device 8103 can hold information such as the emission luminance of the light source 8102 and a control program. Further, the semiconductor device 8103 has a communication function and can function the lighting device 8100 as an IoT device. Also, the lighting device 8100 can receive power supply from a commercial power source or use the power stored in the power storage device.

[0331] Note that in FIG. 28, the installed lighting device 8100 provided on the ceiling 8104 is illustrated, but the semiconductor device according to one aspect of the present invention can also be used for installed lighting devices provided on, for example, side walls 8405, floors 8406, windows 8407, etc., other than the ceiling 8104, or for desktop lighting devices, etc.

[0332] Also, as the light source 8102, an artificial light source that artificially obtains light using power can be used. Specifically, an incandescent bulb, a discharge lamp such as a fluorescent lamp, a light emitting element such as an LED or an organic EL element can be cited as an example of the above artificial light source.

[0333] In FIG. 28, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using a semiconductor device 8203 according to an aspect of the present invention. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a semiconductor device 8203, a power storage device 8205, and the like. In FIG. 28, the case where the semiconductor device 8203 is provided in the indoor unit 8200 is illustrated, but the semiconductor device 8203 may be provided in the outdoor unit 8204. Alternatively, the semiconductor device 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The semiconductor device 8203 can hold control information of the air conditioner, a control program, and the like. Further, the semiconductor device 8203 has a communication function and can make the air conditioner function as an IoT device. Further, the air conditioner can receive power supply from a commercial power source or use the power stored in the power storage device 8205.

[0334] Note that in FIG. 28, a separate-type air conditioner composed of an indoor unit and an outdoor unit is illustrated, but a semiconductor device according to an aspect of the present invention can also be used in an integrated-type air conditioner having the functions of the indoor unit and the outdoor unit in one housing.

[0335] In FIG. 28, an electric refrigerator-freezer 8300 is an example of an electronic device using a semiconductor device 8304 according to an aspect of the present invention. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a semiconductor device 8304, a power storage device 8305, and the like. In FIG. 28, the power storage device 8305 is provided inside the housing 8301. The semiconductor device 8304 can hold control information of the electric refrigerator-freezer 8300, a control program, and the like. Further, the semiconductor device 8304 has a communication function and can make the electric refrigerator-freezer 8300 function as an IoT device. Further, the electric refrigerator-freezer 8300 can receive power supply from a commercial power source or use the power stored in the power storage device 8305.

[0336] Fig. 29A shows an example of a wristwatch-type portable information terminal. The portable information terminal 6100 includes a housing 6101, a display unit 6102, a band 6103, operation buttons 6105, etc. Further, the portable information terminal 6100 includes a secondary battery and a semiconductor device or an electronic component according to one aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to one aspect of the present invention in the portable information terminal 6100, the portable information terminal 6100 can function as an IoT device.

[0337] Fig. 29B shows an example of a mobile phone. The portable information terminal 6200 includes an operation button 6203, a speaker 6204, a microphone 6205, etc., in addition to a display unit 6202 incorporated in a housing 6201.

[0338] Further, the portable information terminal 6200 includes a fingerprint sensor 6209 in a region overlapping the display unit 6202. The fingerprint sensor 6209 may be an organic optical sensor. Since fingerprints vary from person to person, a fingerprint pattern can be acquired by the fingerprint sensor 6209 to perform personal authentication. The light emitted from the display unit 6202 can be used as a light source for acquiring a fingerprint pattern by the fingerprint sensor 6209.

[0339] Further, the portable information terminal 6200 includes a secondary battery and a semiconductor device or an electronic component according to one aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to one aspect of the present invention in the portable information terminal 6200, the portable information terminal 6200 can function as an IoT device.

[0340] Fig. 29C shows an example of a cleaning robot. The cleaning robot 6300 has a display unit 6302 arranged on the upper surface of a housing 6301, a plurality of cameras 6303 arranged on the side surface, a brush 6304, operation buttons 6305, various sensors, etc. Although not shown, the cleaning robot 6300 is provided with tires, a suction port, etc. The cleaning robot 6300 can move automatically, detect dust 6310, and suck dust from a suction port provided on the lower surface.

[0341] For example, the cleaning robot 6300 can analyze the images captured by the camera 6303 and determine the presence or absence of obstacles such as walls, furniture, or steps. Also, when an object likely to get caught in the brush 6304, such as wiring, is detected by image analysis, the rotation of the brush 6304 can be stopped. The cleaning robot 6300 includes a secondary battery and a semiconductor device or an electronic component according to one aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to one aspect of the present invention in the cleaning robot 6300, the cleaning robot 6300 can be made to function as an IoT device.

[0342] Figure 29D shows an example of a robot. The robot 6400 shown in Figure 29D includes an arithmetic unit 6409, an illuminance sensor 6401, a microphone 6402, an upper camera 6403, a speaker 6404, a display unit 6405, a lower camera 6406, an obstacle sensor 6407, and a moving mechanism 6408.

[0343] The microphone 6402 has a function of detecting the user's voice, environmental sounds, etc. Also, the speaker 6404 has a function of emitting sound. The robot 6400 can communicate with the user by using the microphone 6402 and the speaker 6404.

[0344] The display unit 6405 has a function of displaying various information. The robot 6400 can display the information desired by the user on the display unit 6405. The display unit 6405 may be equipped with a touch panel. Also, the display unit 6405 may be a removable information terminal, and by installing it at a fixed position of the robot 6400, charging and data transfer can be enabled.

[0345] The upper camera 6403 and the lower camera 6406 have the function of imaging the surroundings of the robot 6400. Also, the obstacle sensor 6407 can detect the presence or absence of obstacles in the traveling direction when the robot 6400 moves forward using the moving mechanism 6408. The robot 6400 can recognize the surrounding environment and move safely using the upper camera 6403, the lower camera 6406, and the obstacle sensor 6407.

[0346] The robot 6400 includes a secondary battery and a semiconductor device or an electronic component according to an aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to an aspect of the present invention in the robot 6400, the robot 6400 can be made to function as an IoT device.

[0347] Figure 29E shows an example of an aircraft. The aircraft 6500 shown in Figure 29E has a propeller 6501, a camera 6502, a battery 6503, etc., and has the function of autonomous flight.

[0348] For example, the image data captured by the camera 6502 is stored in the electronic component 6504. The electronic component 6504 can analyze the image data and detect the presence or absence of obstacles when moving. Also, the remaining battery level can be estimated from the change in the power storage capacity of the battery 6503 by the electronic component 6504. The aircraft 6500 includes a semiconductor device or an electronic component according to an aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to an aspect of the present invention in the aircraft 6500, the aircraft 6500 can be made to function as an IoT device.

[0349] Figure 29F shows an example of an automobile. The automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. The automobile 7160 includes a semiconductor device or an electronic component according to an aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to an aspect of the present invention in the automobile 7160, the automobile 7160 can be made to function as an IoT device.

[0350] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0351] (Embodiment 6) Using the OS transistor shown in this specification, etc., a normally-off CPU (also referred to as "Noff-CPU") can be realized. Note that a Noff-CPU is an integrated circuit including a normally-off type transistor that is in a non-conductive state (also referred to as an off state) even when the gate voltage is 0V.

[0352] The Noff-CPU can stop the power supply to circuits that are not required to operate within the Noff-CPU and put the circuits in a standby state. In the circuits where the power supply is stopped and in the standby state, no power is consumed. Therefore, the Noff-CPU can minimize the power consumption. Also, the Noff-CPU can hold information necessary for operations such as set conditions for a long time even when the power supply is stopped. The return from the standby state only requires restarting the power supply to the circuits, and rewriting of set conditions, etc. is not necessary. That is, a high-speed return from the standby state is possible. In this way, the Noff-CPU can reduce power consumption without significantly reducing the operating speed.

[0353] The Noff-CPU can be suitably used for small-scale systems such as IoT terminal devices (also referred to as "endpoint microcontrollers").

[0354] Fig. 30 shows the hierarchical structure of the IoT network and the trends of the required specifications. In Fig. 30, power consumption 804 and processing performance 805 are shown as the required specifications. The hierarchical structure of the IoT network is roughly divided into an upper layer cloud field 801 and a lower layer embedded field 802. The cloud field 801 includes, for example, servers. The embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, home appliances, etc.

[0355] Higher up in the hierarchy, higher processing performance is required rather than lower power consumption. Therefore, in the cloud field 801, high-performance CPUs, high-performance GPUs, large-scale SoCs (System on a Chip), etc. are used. Also, lower down in the hierarchy, lower power consumption is required rather than processing performance, and the number of devices also explodes. The communication device or semiconductor device according to one aspect of the present invention can be suitably used for the communication device of the IoT terminal device 803 where low power consumption is required.

[0356] Note that the "endpoint" indicates the terminal area of the embedded field 802. Examples of devices used for endpoints include microcontrollers used in factories, home appliances, infrastructure, agriculture, etc.

[0357] Fig. 31 shows an image diagram of factory automation as an application example of the endpoint microcontroller. The factory 884 is connected to the cloud 883 via an Internet line (Internet). Also, the cloud 883 is connected to the home 881 and the office 882 via the Internet line. The Internet line may be a wired communication method or a wireless communication method. For example, in the case of a wireless communication method, wireless communication conforming to a communication standard such as the 4th generation mobile communication system (4G) or the 5th generation mobile communication system (5G) may be performed using the communication device or semiconductor device according to one aspect of the present invention in the communication device. Also, the factory 884 may be connected to the factories 885 and 886 via the Internet line.

[0358] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to the cloud 883 and exchanging information. Also, the master device 831 is connected to a plurality of industrial robots 842 included in the IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet (registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0359] The factory manager can connect to the factory 884 via the cloud 883 from the home 881 or the office 882 and know the operating status and the like. Also, defective product / missing product checks, location instructions, tact time measurement, etc. can be performed.

[0360] In recent years, factories branded as "smart factories" have been globally promoting the introduction of IoT into factories. In cases of smart factories, it has been reported that not only simple inspections and audits by endpoint microcontrollers but also fault detection, anomaly prediction, etc. are carried out.

[0361] Small-scale systems such as endpoint microcontrollers often have low overall system power consumption during operation, so the power reduction effect during the standby operation by the Noff-CPU becomes significant. Also, although immediacy may be required in the field of IoT integration, the use of the Noff-CPU enables high-speed recovery from the standby operation.

[0362] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments, etc.

Explanation of Signs

[0363] 10: Communication device, 11: Antenna, 12: Amplifier, 13: Amplifier, 14: Phase shifter, 15: Amplifier, 16: Inductor, 17: Inductor, 18: Wiring, 19: Wiring, 20: Amplification circuit, 21: Transistor, 21a: Transistor, 21b: Transistor, 22: Transistor, 22a: Transistor, 22b: Transistor, 23: Load, 23a: Load, 23b: Load, 24: Switch, 25: Operational amplifier, 25a: Operational amplifier, 25b: Operational amplifier, 26: Switch, 26a: Switch, 26b: Switch, 27: Switch, 27a: Switch, 27b: Switch, 28: Transistor, 31: Transistor, 31a: Transistor, 31b: Transistor, 32: Transistor, 32a: Transistor, 32b: Transistor, 33: Load, 33a: Load, 33b: Load, 34: Switch, 35a: Operational amplifier, 35b: Operational amplifier, 36a: Switch, 36b: Switch, 37a: Switch, 37b: Switch, 38: Transistor, 40: Terminal, 40a: Terminal, 40b: Terminal, 41: Wiring, 42: Wiring, 42a: Wiring, 42b: Wiring, 43: Wiring, 44: Potential generation circuit, 44a: Potential generation circuit, 44b: Potential generation circuit, 46a: Wiring, 46b: Wiring, 50: Terminal, 50a: Terminal, 50b: Terminal, 51: Wiring, 52: Wiring, 52a: Wiring, 52b: Wiring, 53: Wiring, 54: Potential generation circuit, 54a: Potential generation circuit, 54b: Potential generation circuit, 56a: Wiring, 56b: Wiring, 61: Phase shifter, 62: Capacitance, 63: Switch, 64: Phase shifter, 65: Inductor, 66: Inductor, 73: Wiring, 75: Wiring, 80: Memory circuit, 81: Transistor, 82: Capacitance, 84: Wiring, 85: Wiring, 90: Memory circuit, 91: Transistor, 92: Capacitance, 94: Wiring, 95: Wiring, 101: Inductor, 102: Capacitance, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 404: Insulator, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 513: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator,522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 540a: Conductor, 540b: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 550: Transistor, 552: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600A: Transistor, 600B: Transistor, 610: Conductor, 612: Conductor, 640: Insulator, 711: Substrate, 712: Circuit Region, 713: Isolation Region, 714: Isolation Line, 715: Chip, 750: Electronic Component, 752: Printed Circuit Board, 753: Semiconductor Device, 754: Mounting Substrate, 755: Lead, 801: Cloud Field, 802: Field, 803: IoT End Device, 804: Power Consumption, 805: Processing Performance, 831: Master Device, 832: Interface, 841: IoT End Device, 842: Industrial Robot, 881: Home, 882: Office, 883: Cloud, 884: Factory, 885: Factory, 886: Factory, 6100: Mobile Information Terminal, 6101: Housing, 6102: Display Unit, 6103: Band, 6105: Operation Button, 6200: Mobile Information Terminal, 6201: Housing, 6202: Display Unit, 6203: Operation Button, 6204: Speaker, 6205: Microphone, 6209: Fingerprint Sensor, 6300: Cleaning Robot, 6301: Housing, 6302: Display Unit, 6303: Camera, 6304: Brush, 6305: Operation Button, 6310: Dust, 6400: Robot, 6401: Illuminance Sensor, 6402: Microphone, 6403: Upper Camera, 6404: Speaker, 6405: Display Unit, 6406: Lower Camera, 6407: Obstacle Sensor, 6408: Moving Mechanism, 6409: Arithmetic Unit, 6500: Aircraft, 6501: Propeller, 6502: Camera, 6503: Battery, 6504: Electronic Component, 7160: Automobile, 8000: Display Device, 8001: Housing, 8002: Display Unit, 8003: Speaker Unit, 8004: Semiconductor Device, 8005: Power Storage Device, 8100: Lighting Device, 8101: Housing, 8102: Light Source, 8103: Semiconductor Device, 8104: Ceiling, 8105: Power Storage Device, 8200: Indoor Unit, 8201: Housing, 8202: Air Outlet, 8203: Semiconductor Device, 8204: Outdoor Unit,8205: Power storage device, 8300: Electric refrigerator-freezer, 8301: Cabinet, 8302: Refrigerator door, 8303: Freezer door, 8304: Semiconductor device, 8305: Power storage device, 8405: Side wall, 8406: Floor, 8407: Window

Claims

【Claim 1】 having an amplifier circuit, wherein the amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first load, a second load, a third load, a fourth load, a first terminal, a second terminal, a third terminal, and a fourth terminal; one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor; one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor; one of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor; one of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor; the other of the source or drain of the first transistor and the other of the source or drain of the third transistor are electrically connected to a first power supply line; the other of the source or drain of the fifth transistor and the other of the source or drain of the seventh transistor are electrically connected to a second power supply line; the gates of the second transistor and the fourth transistor are electrically connected to a first wiring; the gates of the sixth transistor and the eighth transistor are electrically connected to a second wiring; the first terminal is electrically connected to the gate of the first transistor, the other of the source or drain of the sixth transistor, and the first load; the second terminal is electrically connected to the gate of the third transistor, the other of the source or drain of the eighth transistor, and the second load; the third terminal is electrically connected to the gate of the fifth transistor, the other of the source or drain of the second transistor, and the third load; the fourth terminal is electrically connected to the gate of the seventh transistor, the other of the source or drain of the fourth transistor, and the fourth load. When a first signal wave is input to the first terminal, the amplification circuit has a function of outputting a signal wave corresponding to the first signal wave from the third terminal. When a second signal wave is input to the second terminal, the amplification circuit has a function of outputting a signal wave corresponding to the second signal wave from the fourth terminal. When a third signal wave is input to the third terminal, the amplification circuit has a function of outputting a signal wave corresponding to the third signal wave from the first terminal. When a fourth signal wave is input to the fourth terminal, the amplification circuit has a function of outputting a signal wave corresponding to the fourth signal wave from the second terminal. When the first signal wave is input to the first terminal and the second signal wave is input to the second terminal, the potential of the first wiring is set to a potential at which the second and fourth transistors operate in the saturation region, and the potential of the second wiring is set to a potential at which the sixth and eighth transistors are in the off state. When the third signal wave is input to the third terminal and the fourth signal wave is input to the fourth terminal, the potential of the first wiring is set to a potential at which the second and fourth transistors are in the off state. And the potential of the second wiring is set to a potential at which the sixth and eighth transistors operate in the saturation region. The first signal wave and the second signal wave are in a relationship of opposite phases to each other. The third signal wave and the fourth signal wave are in a relationship of opposite phases to each other. The second transistor, the fourth transistor, the sixth transistor, and the eighth transistor have back gates. The back gate of the second transistor is electrically connected to the first terminal. The back gate of the fourth transistor is electrically connected to the second terminal. The back gate of the sixth transistor is electrically connected to the third terminal. The back gate of the eighth transistor is electrically connected to the fourth terminal. The ratio of the channel width to the channel length of the second transistor is equal to or greater than the ratio of the channel width to the channel length of the first transistor. The ratio of the channel width to the channel length of the fourth transistor is equal to or greater than the ratio of the channel width to the channel length of the third transistor. The ratio of the channel width to the channel length of the sixth transistor is greater than or equal to the ratio of the channel width to the channel length of the fifth transistor. The ratio of the channel width to the channel length of the eighth transistor is greater than or equal to the ratio of the channel width to the channel length of the seventh transistor. The product of the channel width and the channel length of the second transistor is greater than or equal to the product of the channel width and the channel length of the first transistor. The product of the channel width and the channel length of the fourth transistor is greater than or equal to the product of the channel width and the channel length of the third transistor. The product of the channel width and the channel length of the sixth transistor is greater than or equal to the product of the channel width and the channel length of the fifth transistor. The product of the channel width and the channel length of the eighth transistor is greater than or equal to the product of the channel width and the channel length of the seventh transistor. The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor. The threshold voltage of the third transistor is greater than the threshold voltage of the fourth transistor. The threshold voltage of the fifth transistor is greater than the threshold voltage of the sixth transistor. A communication device in which the threshold voltage of the seventh transistor is greater than the threshold voltage of the eighth transistor. However, the ratio of the channel width to the channel length is defined as channel width / channel length.

Images