Memory Controller and Flash Memory System

Abstract

A memory controller according to an embodiment of the present invention is provided with a microprocessor that executes each of a data access process and an update process that updates area management information in accordance with the access process. The microprocessor determines the virtual addresses to be accessed on the basis of area management information that defines a correspondence between logical addresses of logical pages and virtual addresses of virtual pages included in a virtual block that comprises a plurality of physical blocks. When executing data writing processes as access processes on the basis of the determined virtual addresses, the microprocessor edits the area management information in a cache area each time the microprocessor executes a writing process, and writes and saves the edited area management information in a flash memory at a frequency lower than the frequency at which each writing process is executed, thus executing a process for updating the area management information.

Description

Technical Field

[0001] The present invention relates to a memory controller and a flash memory system.

Background Art

[0002] A memory controller that controls a flash memory or the like as a non-volatile memory, and a memory system (such as a flash memory system) including such a memory controller and a non-volatile memory have been proposed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] By the way, in such a memory controller or the like, generally, it is required to improve the data writing efficiency. It is desirable to provide a memory controller and a flash memory system capable of improving the data writing efficiency.

[0005] A memory controller according to an embodiment of the present invention is a memory controller that controls a flash memory, and includes a microprocessor that respectively executes data access processing for the flash memory and update processing for updating predetermined area management information in response to this access processing. This microprocessor determines a virtual address to be an access target during the access processing based on the area management information that defines the correspondence between the logical address of a logical page and the virtual address of a virtual page included in a virtual block composed of a plurality of physical blocks belonging to a plurality of channels in the flash memory. When executing a data write process as the access process based on the determined virtual address, each time this write process is executed, the area management information is edited on the cache area, and the edited area management information is written and stored on the flash memory at the frequency thinned out for each write process, thereby executing the above-described update process for the area management information. In addition, each of the plurality of virtual pages included in the virtual block is provided with a spare area for each physical page, and when the microprocessor executes a write process in units of virtual pages, the microprocessor also writes logical address information indicating the corresponding logical address to the spare area within the virtual page to be written. Further, when the power supply of the flash memory and the memory controller transitions from the on state to the off state before the area management information is written and stored on the flash memory, in the startup process when the power supply then returns from the off state to the on state, the microprocessor reads out the logical address information from the spare areas included in the virtual block being written, and on the cache area, edits the area management information for the unupdated part using the read logical address information.

[0006] A flash memory system according to an embodiment of the present invention includes the memory controller according to an embodiment of the present invention and the flash memory.

[0007] According to the memory controller and the flash memory system according to an embodiment of the present invention, it is possible to improve the data write efficiency.

Brief Description of Drawings

[0008]

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Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The description will be made in the following order. 1. Embodiment (Example of writing and storing at a frequency of thinning out the logical virtual conversion table) 2. Modification Example

[0010] <1. Embodiment> [Schematic Configuration] FIG. 1 shows a schematic configuration example of a flash memory system (flash memory system 3) according to an embodiment of the present invention, together with an external host system 4, represented by a block diagram. This flash memory system 3 is a system corresponding to, for example, an SSD (Solid State Drive) or an eMMC (embedded Multi Media Card).

[0011] As shown in FIG. 1, the flash memory system 3 includes a flash memory 1, a memory controller 2, and an external RAM (Random Access Memory) 30. Note that the host system 4 and the memory controller 2 (host interface 26 described later) are interconnected via an external bus 82, and the memory controller 2 (memory interface 21 described later) and the flash memory 1 are interconnected via an internal bus 81. Also, the memory controller 2 (RAM interface 22 described later) and the external RAM 30 are interconnected via an internal bus 80.

[0012] (A. Host System 4) The host system 4 is a host system that uses the flash memory system 3 as a secondary storage device. The host system 4 includes a CPU (Central Processing Unit) for controlling the operation of the entire host system 4 and a companion chip that is responsible for the exchange of various information with the flash memory system 3. Such a host system 4 is, for example, an information processing device such as a personal computer (PC) or a digital still camera.

[0013] The host system 4 also supplies a predetermined command to the flash memory system 3 to instruct the flash memory system 3 to execute various processes. Specifically, this command is a command for the memory controller 2 in the flash memory system 3 to instruct the flash memory 1 to execute various processes. That is, the flash memory 1 performs various operations according to the commands given from the memory controller 2.

[0014] (B. Flash Memory 1) The flash memory 1 is a non-volatile memory and is configured using one or two or more flash memory chips (chips). In the example of FIG. 1, a plurality (four) of chips (flash memories 10, 11, 12, 13) are provided as the entire flash memory 1. Hereinafter, for the sake of generality, the flash memories 10 to 13 will basically be described as the flash memory 1. This flash memory 1 is, for example, a NAND type flash memory. In this NAND type flash memory, data access processing (writing processing or reading processing) is performed in page units, and data erasure processing (bulk erasure) is performed in block units composed of a plurality of pages.

[0015] Incidentally, the pages and blocks in the flash memory 1 are generally also called physical pages and physical blocks, respectively. This is to distinguish them from the logical pages and logical blocks, which are the units when the host system 4 handles data.

[0016] Details of these logical pages, logical blocks, physical pages, physical blocks, etc. will be described later (FIGS. 2 to 5, etc.).

[0017] Such a flash memory 1 includes a register and a memory cell array in which a plurality of memory cells are arranged. The memory cell array has a plurality of memory cell groups and word lines. Each memory cell group is formed by connecting a plurality of memory cells in series. The word lines are for selecting specific memory cells from among the memory cell groups. Data writing processing (write processing) from the register to the selected memory cells or data reading processing (read processing) from the selected memory cells to the register is performed between the memory cells selected via the word lines and the register.

[0018] (C. Memory controller 2) The memory controller 2 controls the flash memory 1 according to commands (the above-described commands) from the host system 4. Specifically, for example, when there is a write request from the host system 4, the memory controller 2 writes the data received from the host system 4 into the flash memory 1. Also, for example, when there is a read request from the host system 4, the memory controller 2 reads data from the flash memory 1 and transmits it to the host system 4.

[0019] Also, in the present embodiment, although details will be described later, parallel data transfer using a plurality of channels is performed between the memory controller 2 and the flash memory 1 and between the memory controller 2 and the host system 4, respectively.

[0020] Such a memory controller 2 has, for example, as shown in FIG. 1, a memory interface 21, a RAM interface 22, an ECC (Error Correcting Code) block 23, a buffer 24, a table RAM 25, a host interface 26, and a microprocessor 27. Further, these memory interface 21, RAM interface 22, ECC block 23, buffer 24, table RAM 25, host interface 26 and microprocessor 27 are interconnected via a system bus 20, respectively.

[0021] The memory interface 21 is an interface for communicating with the flash memory 1. This memory interface 21 is, for example, a memory interface compliant with the ONFI (Open NAND Flash Interface) standard.

[0022] The RAM interface 22 is an interface for communicating with the external RAM 30. Note that this external RAM 30 is configured by a volatile memory such as a DRAM (Dynamic Random Access Memory), for example, and various data are temporarily stored therein. However, such an external RAM 30 may not be provided in the flash memory system 3.

[0023] The ECC block 23 is a block that generates an ECC (error correcting code) added to the data written to the flash memory 1. Further, the ECC block 23 is configured to detect and correct errors included in the read data based on the error correcting code added to the data read from the flash memory 1.

[0024] Buffer 24 is a part that temporarily holds the data read from Flash Memory 1 and the data to be written to Flash Memory 1 respectively. Specifically, the data read from Flash Memory 1 is held on Buffer 24 until it becomes in a state that can be received by Host System 4. Also, the data to be written to Flash Memory 1 is held on Buffer 24 until this Flash Memory 1 becomes in a writable state.

[0025] Table RAM 25 is a part that temporarily stores the information necessary for the control of Flash Memory 1, and is constituted by a volatile memory such as SRAM (Static Random Access Memory) for example. Specifically, various tables (Logical Virtual Conversion Table 51 and Management Table 52: see FIG. 6) described later are temporarily stored in Table RAM 25, and on this Table RAM 25, these various tables are appropriately updated.

[0026] Note that such Table RAM 25 corresponds to a specific example of the "cache area" in the present invention.

[0027] Host Interface 26 is an interface for communicating with Host System 4. This Host Interface 26 is, for example, an interface compliant with the SATA (Serial Advanced Technology Attachment) standard, or an interface compliant with the PCIe (Peripheral Component Interconnect-Express) standard, etc.

[0028] Microprocessor 27 is a circuit that controls the overall operation of Memory Controller 2. Specifically, Microprocessor 27 executes the data access process (write process or read process) to Flash Memory 1 and the update process of updating the various tables described above according to such access process respectively.

[0029] Details such as the access processing of such data and the update processing of various tables will be described later (Figs. 9A to 14).

[0030] [Address Space of Flash Memory 1] Subsequently, with reference to FIGS. 2 and 3, the address space (logical address space and physical address space) of flash memory 1 will be described in detail.

[0031] FIG. 2 schematically shows a schematic configuration example of the address space in flash memory 1.

[0032] As shown in FIG. 2, flash memory 1 is composed of the aforementioned "chip", "block (physical block)", "page (physical page)", and "sector (physical sector)". Flash memory 1 includes at least one chip (in the example of FIG. 1, a plurality of chips), and each chip includes a plurality of physical blocks.

[0033] The physical block is a processing unit in the data erasure processing performed in flash memory 1. In this data erasure processing, the data stored in a plurality of physical pages belonging to the same physical block is erased all at once. Each physical block includes, for example, 64, 128, or 256 physical pages.

[0034] The physical page is a processing unit in the data writing processing and reading processing performed in flash memory 1. In such data writing processing and reading processing, generally, memory cells are selected in units of physical pages, and the writing of data from a register to a memory cell and the reading of data from a memory cell to a register are each performed in units of physical pages.

[0035] A physical page contains, for example, 4, 8, or 16 physical sectors. Each physical sector is an area allocated to store 512 bytes of data (one-sector data). Also, the one-sector data stored in each physical sector is stored together with the ECC (Error Correcting Code) of that data.

[0036] Note that in the physical page, an area for storing one-sector data and an area for storing the ECC corresponding to that one-sector data may be alternately allocated. Also, in the physical page, an area for storing data of 4 sectors may be continuously allocated, and then an area for storing the ECC corresponding to the data of those 4 sectors may be continuously allocated. That is, areas may be allocated so that data of multiple sectors and the ECC of that data are alternately stored in units of several sectors.

[0037] Here, as shown in, for example, Figure 2, each chip, each physical block, each physical page, and each physical sector is assigned a sequential number as follows. That is, chip numbers CHIP#0, CHIP#1, CHIP#2,..., physical block numbers PB#0, PB#1, PB#2,..., physical page numbers PP#0, PP#1, PP#2,..., and physical sector numbers PS#0, PS#1, PS#2,... are each assigned as sequential numbers. Such chip numbers, physical block numbers, physical page numbers, and physical sector numbers are each used as a physical address, which is information indicating the storage location of the data stored in the flash memory 1.

[0038] More specifically, chip numbers CHIP#0, CHIP#1, CHIP#2, … are numbers for identifying each chip in the flash memory 1, and physical block numbers PB#0, PB#1, PB#2, … are numbers for identifying each physical block within a chip. Also, physical page numbers PP#0, PP#1, PP#2, … are numbers for identifying each physical page within a physical block, and physical sector numbers PS#0, PS#1, PS#2, … are numbers for identifying each physical sector within a physical page.

[0039] Furthermore, by combining the chip number and the physical block number, a physical block within the flash memory 1 can be identified. For example, the number “CHIP#0, PB#1,” which is a combination of the chip number and the physical block number, corresponds to the physical block PB#1 among the multiple physical blocks included in the chip CHIP#0. Similarly, by combining the chip number, the physical block number, and the physical page number, a physical page within the flash memory 1 can be identified. Also, by combining the chip number, the physical block number, the physical page number, and the physical sector number, a physical sector within the flash memory 1 can be identified.

[0040] Next, with reference to FIG. 3, the correspondence between the logical address defined in the address space (logical address space) on the host system 4 side and the physical address defined in the address space (physical address space) on the flash memory 1 side will be described in detail. FIG. 3 schematically shows an example of such a correspondence between the logical address and the physical address. Here, the logical address is an address managed in the host system 4 as information for identifying data stored in the flash memory 1.

[0041] As shown in FIG. 3, in the address space on the host system 4 side, the logical address is defined using the LBA (Logical Block Address). The LBA is an address assigned to a logical sector having a capacity of 512 bytes. To each LBA, LBA numbers LBA#0, LBA#1, LBA#2,... are assigned as sequential numbers. The host system 4 designates the data access area using such an LBA. Also, the memory controller 2 identifies the access area in the flash memory 1 based on the access area designated by the LBA.

[0042] Here, the memory controller 2 defines a group of a plurality of LBAs as a logical page. This logical page corresponds to a physical page on the flash memory 1 side and is the processing unit for the data writing process and reading process on the host system 4 side. To each logical page, for example, as shown in FIG. 3, logical page numbers LP#0, LP#1, LP#2,... are assigned as sequential numbers. Such logical page numbers LP#0, LP#1, LP#2,... correspond to the addresses of the logical pages.

[0043] The number of LBAs assigned to one logical page is set as follows, for example. That is, as an example in FIG. 3, the LBAs of LBA#0 to #7 are assigned to the logical page of LP#0, the LBAs of LBA#8 to #15 are assigned to the logical page of LP#1, and so on. One logical page is assigned for every 8 LBAs. Since the LBA and the logical page are assigned in sequential order like this, the correspondence relationship between the LBA and the logical page can be mutually converted by simple calculation.

[0044] The memory controller 2 performs address conversion for associating such a logical address with a physical address in units of logical pages. In other words, the memory controller 2 manages the addresses of the flash memory 1 using a page mapping method. This page mapping method is a method in which the memory controller 2 groups a plurality of LBAs in units of logical pages and manages the addresses.

[0045] Each logical page is assigned to any one of the virtual sub-pages included in the flash memory 1. This virtual sub-page is a sub-page divided by the logical page size within a virtual page described later, and is arranged across a plurality of physical pages (for example, refer to the virtual sub-page VSP shown in FIG. 5 described later). Details of these virtual pages and virtual sub-pages will be described later (FIGS. 4 and 5).

[0046] [Virtual Addresses, etc. in Flash Memory 1] Subsequently, with reference to FIGS. 4 and 5, virtual addresses and the like in the flash memory 1 will be described in detail.

[0047] FIG. 4 schematically shows a configuration example of virtual blocks, virtual pages, and the like according to the present embodiment. FIG. 5 schematically shows a detailed configuration example of the virtual page shown in FIG. 4.

[0048] First, in the present embodiment, the memory controller 2 performs data writing processing in units of virtual pages composed of a plurality of physical pages described below, rather than in units of the general physical pages described above. Also, the memory controller 2 performs data reading processing in units of virtual sectors described below.

[0049] Here, for example, as shown in FIG. 4, a virtual block is constituted by a plurality of physical blocks belonging to the plurality of channels CH0 to CH3 described above. In the example of FIG. 4, a virtual block number VB#M (M: an integer of 0 or more) is assigned to this virtual block. Also, in the example of FIG. 4, each of the channels CH0 to CH3 is provided with two physical blocks belonging to two planes (plane #0, #1), respectively. And each of the two physical blocks in each of the channels CH0 to CH3 contains a plurality of physical pages (256 physical pages consisting of physical page numbers PP#0 to PP#255).

[0050] Here, for example, as shown in FIG. 4, in such a virtual block, a virtual page is constituted by a plurality of physical pages belonging to the plurality of channels CH0 to CH3. In the example of FIG. 4, a virtual page number VP#N (N: an integer from 0 to 255) is assigned to this virtual page. Specifically, the virtual page VP#N is constituted by the physical pages belonging to channel CH0 (two physical pages of PP#N belonging to plane #0 and #1 respectively), the physical pages belonging to channel CH1 (two physical pages of PP#N), the physical pages belonging to channel CH2 (two physical pages of PP#N), and the physical pages belonging to channel CH3 (two physical pages of PP#N).

[0051] Also, for example, as shown in FIG. 5, in this virtual page of VP#N, each physical page contains a plurality of virtual sectors. In the example of FIG. 5, the entire virtual page contains 256 virtual sectors consisting of virtual sector numbers VS#0 to VS#255. And these virtual sectors VS#0 to VS#255 are assigned to a plurality of physical pages (8 physical pages in the example of FIG. 5) within the virtual block in the order of the virtual sector numbers. Also, in the example of FIG. 5, a logical page is assigned to each of the plurality of physical pages within the virtual page. Specifically, the aforementioned virtual sub - pages VSP, which are divided into logical page sizes in the order of the virtual sector numbers (in the example shown in FIG. 5, in the order of 8 virtual sector numbers VS#0 to VS#7), are assigned. Furthermore, in the example of FIG. 5, a spare area As is provided for each of the plurality of physical pages within the virtual page, into which logical address information to be described later is written.

[0052] [Configuration of Various Tables] Subsequently, with reference to FIGS. 6 to 8, the configuration of various tables (logical - virtual conversion table 51 and management table 52), which are temporarily stored and updated on the aforementioned table RAM25, will be described in detail.

[0053] FIG. 6 schematically shows configuration examples of the logical - virtual conversion table 51 (FIG. 6(A)) and the management table 52 (FIG. 6(B)) according to the present embodiment, respectively.

[0054] First, as described above in the present embodiment, a virtual page composed of a plurality of physical pages serves as a processing unit for data access processing (writing processing and reading processing). Therefore, the memory controller 2 writes data corresponding to each logical page to the virtual page corresponding to that logical page. Also, the correspondence relationship between addresses such as logical pages (logical addresses) and addresses such as virtual pages (virtual addresses) is not fixed and changes dynamically according to the data access processing.

[0055] Here, the memory controller 2 of the present embodiment manages the correspondence relationship between the dynamically changing logical address and virtual address by using the following logical virtual conversion table 51 and management table 52. Then, the memory controller 2 refers to each table defining these correspondence relationships, converts the logical address given from the host system 4 into a virtual address, and specifies the storage location of the data to be accessed in the flash memory 1 based on the converted virtual address.

[0056] The logical virtual conversion table 51 shown in FIG. 6(A) defines the correspondence relationship between the above-described logical address and virtual address for each of the plurality of data stored in the flash memory 1. As described above, since the memory controller 2 manages addresses using the page mapping method, the correspondence relationship in this logical virtual conversion table 51 is also defined in units of pages. That is, the memory controller 2 manages the correspondence relationship between the logical address and the virtual address by the correspondence relationship between the logical page address (the above-described logical page number) and the virtual page address (the above-described virtual page number).

[0057] More specifically, as shown in FIG. 6(A) for example, the logical virtual conversion table 51 defines the correspondence relationship between the logical page number and the virtual block number, virtual page number, and virtual sector number for each of the plurality of data stored in the flash memory 1. Also, as shown in FIG. 6(A) for example, a plurality of such logical virtual conversion tables 51 are provided for the entire flash memory 1, and each logical virtual conversion table 51 is assigned a unique number (logical virtual conversion table number: for example, LVTBL#0, etc.). In the example of FIG. 6(A), the correspondence relationship with the virtual address for 1024 logical addresses (logical page numbers) is described in each logical virtual conversion table 51.

[0058] Here, such a logical virtual conversion table 51 corresponds to a specific example of the "area management information" in the present invention.

[0059] On the other hand, the management table 52 shown in FIG. 6(B) defines the correspondence between the logical virtual conversion table number unique to each such logical virtual conversion table 51 and the address of the logical virtual conversion table 51 (the virtual address of the final storage destination on the flash memory 1). That is, although details will be described later, the logical virtual conversion table 51 is temporarily stored and updated on the table RAM 25 and finally written and stored on the flash memory 1.

[0060] More specifically, this management table 52, as shown in FIG. 6(B) for example, defines the correspondence between the logical virtual conversion table number in each logical virtual conversion table 51 and the virtual address of the storage destination of the logical virtual conversion table 51 (virtual block number, virtual page number, and virtual sector number). Also, as shown in FIG. 6(B) for example, a plurality of such management tables 52 are provided for the entire flash memory 1, and each management table 52 is assigned a unique number (management table number: for example, MNTBL#0, etc.). In the example of FIG. 6(B), the correspondence between the virtual addresses of the storage destinations for 1024 logical virtual conversion table numbers is described in each management table 52.

[0061] Here, FIG. 7 schematically shows an example of the arrangement of each table (logical virtual conversion table 51 and management table 52) in the table full expansion mode according to the present embodiment. Also, FIG. 8 schematically shows an example of the arrangement of each table in the table cache mode according to the present embodiment.

[0062] First, in the table full expansion mode shown in FIG. 7, on the table RAM 25, for example, various management data 50, 131,072 logical virtual conversion tables 51 (LVTBL#0 to LVTBL#131,071), and 128 management tables 52 (MNTBL#0 to MNTBL#127) are temporarily stored. As shown in FIG. 6(B), since the number of logical virtual conversion tables 51 (logical virtual conversion table numbers) included in each management table 52 is 1,024, in the example of FIG. 7, the number of logical virtual conversion tables 51 is (the number of management tables 52 (128) × 1,024 = 131,072).

[0063] Therefore, when the data size of each table (logical virtual conversion table 51 and management table 52) is 4 KB as an example, the total data size of the logical virtual conversion tables 51 in this table full expansion mode is as follows. That is, as shown in FIG. 7, it is (4 KB × 131,072 = 512 MB). Also, the total data size of the management tables 52 in the table full expansion mode is, as shown in FIG. 7, (4 KB × 128 = 512 KB).

[0064] On the other hand, in the table cache mode shown in FIG. 8, on the table RAM 25, for example, various management data 50, 256 caches of logical virtual conversion tables 51 (LVTBL#0 (cache) to LVTBL#255 (cache)), and 128 management tables 52 (MNTBL#0 to MNTBL#127) are temporarily stored. That is, in this table cache mode, compared with the above table full expansion mode, the number corresponding to the logical virtual conversion table 51 is (256 / 131,072) = (1 / 512) times.

[0065] Therefore, when the data size of each table (the logical virtual conversion table 51 and the management table 52) is 4 KB as an example, the data size of the entire logical virtual conversion table 51 in this table cache mode is as follows. That is, different from the above-described full table expansion mode, as shown in FIG. 8, it becomes (4 KB × 256 = 1 MB). On the other hand, the data size of the entire management table 52 in the table cache mode is, as in the above-described full table expansion mode, as shown in FIG. 8, (4 KB × 128 = 512 KB).

[0066] Here, such a logical virtual conversion table 51 and management table 52 are each read from the flash memory 1 to the table RAM 25 during the startup process of the flash memory system 3 or during the data access process. Further, the memory controller 2 appropriately updates the logical virtual conversion table 51 and the management table 52 on the table RAM 25. Then, the thus updated logical virtual conversion table 51 and management table 52 are each finally written and stored on the flash memory 1 at a predetermined time point described later. Note that the writing of each table onto the flash memory 1 is performed, for example, for each of the plurality of divided tables (for each table to which the above-described logical virtual conversion table number and management table number are assigned) shown in FIGS. 6(A) and 6(B).

[0067] [Operations, Actions, and Effects] Subsequently, an operation example in the flash memory system 3 of the present embodiment will be described.

[0068] First, in the present embodiment, the microprocessor 27 determines a virtual address that is the access target during data access processing based on the logical virtual conversion table 51 (and the management table 52) that defines the correspondence between the above-described logical address and the virtual address. Further, the microprocessor 27 executes an update process of updating various tables (the logical virtual conversion table 51 and the management table 52) according to the access process in response to such access processing (write processing or read processing).

[0069] Hereinafter, operation examples during such data write processing (write processing) and read processing (read processing) will be described in detail separately for each of the above-described full table expansion mode and table cache mode. Also, operation examples in the startup process when the power of the flash memory system 3 (the flash memory 1 and the memory controller 2) returns from the off state to the on state will be described in detail separately for each of these modes.

[0070] (A-1. Operation example during write processing: in full table expansion mode) FIGs. 9A and 9B each show an example of write processing (in full table expansion mode) according to the present embodiment in the form of a flowchart.

[0071] In the series of processes shown in FIGS. 9A and 9B, first, the microprocessor 27 receives user data (write data) supplied from the host system 4 via the host interface 26 (step S101 in FIG. 9A). Next, the microprocessor 27 registers the received user data (received complete data) in the write cache data in the buffer 24 (step S102). Subsequently, the microprocessor 27 determines whether the data amount of the write cache data in this buffer 24 (write cache data amount) is equal to or greater than the virtual page size in the flash memory 1 (step S103). Here, if it is determined that the write cache data amount is less than the virtual page size amount (step S103: N), the process proceeds to step S112 (FIG. 9B) described later.

[0072] On the other hand, if it is determined that the write cache data amount is equal to or greater than the virtual page size amount (step S103: Y), then next, the microprocessor 27 refers to the logical virtual conversion table 51 and the management table 52 to determine the virtual address on the flash memory 1 where the user data is to be written (step S104). Subsequently, the microprocessor 27 writes the user data (write cache data in the buffer 24) onto the flash memory 1 based on the virtual address thus determined (step S105). Also, at this time, the microprocessor 27 also writes the logical address information indicating the corresponding logical address to the spare area As (see FIG. 5) in the virtual page to be written.

[0073] Next, the microprocessor 27 edits the logical virtual conversion table 51 on the table RAM 25 in accordance with such writing process of user data (step S106 in FIG. 9B). Next, the microprocessor 27 releases the above-described written completion data from the write cache data in the buffer 24 (step S107). Then, the microprocessor 27 determines whether or not the virtual block to be written on the flash memory 1 has been written up to the last page among a plurality of virtual pages included in the virtual block (step S108). Here, if it is determined that the virtual block to be written is not written up to the last page (step S108: N), the process proceeds to step S112 (FIG. 9B) described later.

[0074] On the other hand, if it is determined that the virtual block to be written is written up to the last page (step S108: Y), the following occurs. That is, next, the microprocessor 27 executes an update process for the logical virtual conversion table 51 by writing and storing the logical virtual conversion table 51 edited in step S106 on the flash memory 1 (step S109). Also, at this time, the microprocessor 27 makes the virtual block on which user data is written during the writing process and the virtual block on which the edited logical virtual conversion table 51 is written and stored different from each other on the flash memory 1.

[0075] Subsequently, the microprocessor 27 edits the management table 52 on the table RAM 25 in accordance with the writing and storing of the logical virtual conversion table 51 on the flash memory 1 (step S110). Then, the microprocessor 27 executes an update process for the management table 52 by writing and storing the edited management table 52 on the flash memory 1 in this manner (step S111).

[0076] Next, the microprocessor 27 determines whether the commands for the entire write process have been completed (step S112). Here, if it is determined that the commands for the entire write process have not been completed yet (step S112: N), the process returns to the aforementioned step S101 (Fig. 9A). On the other hand, if it is determined that the commands for the entire write process have been completed (step S112: Y), the series of processes shown in Figs. 9A and 9B ends.

[0077] (A-2. Example of operation during write process: in table cache mode) Also, Figs. 10A and 10B each show an example of the write process (in table cache mode) according to the present embodiment represented as a flowchart.

[0078] The series of processes shown in Figs. 10A and 10B corresponds to the series of processes shown in Figs. 9A and 9B described above with steps S113 to S115 further added. Therefore, below, steps S113 to S115 will be briefly described.

[0079] First, steps S113 and S114 are processes added between the aforementioned steps S105 and S106. Specifically, after the aforementioned step S105 (writing user data), next, the microprocessor 27 determines whether the target (editing target) logical virtual conversion table 51 has been expanded (step S113 in Fig. 10A). Here, if it is determined that the target logical virtual conversion table 51 has already been expanded (step S113: Y), the process proceeds to the aforementioned step S106 (editing of the logical virtual conversion table 51: see Fig. 10B). On the other hand, if it is determined that the target logical virtual conversion table 51 has not yet been expanded (step S113: N), next, the microprocessor 27 expands the target logical virtual conversion table 51 (step S114 in Fig. 10A). And then, also in this case, the process proceeds to step S106 (editing of the logical virtual conversion table 51: see Fig. 10B).

[0080] Also, step S115 is a process performed when it is determined in step S108 described above that the virtual block to be written is not yet written up to the final page (step S108: N). Specifically, in this case, next, the microprocessor 27 determines whether the free space in the table cache in the table RAM 25 is equal to or less than a predetermined threshold (step S115 in FIG. 10B). Here, if it is determined that the free space in the table cache exceeds the predetermined threshold (step S115: N), the process proceeds to step S112 described above (determination of whether the command is completed). On the other hand, if it is determined that the free space in the table cache is equal to or less than the predetermined threshold (step S115: Y), the process proceeds to step S109 described above (writing and saving of the logical virtual conversion table 51).

[0081] This concludes the description of the series of processes shown in FIGS. 10A and 10B.

[0082] In this way, in the write process of the present embodiment, the microprocessor 27 writes and saves the edited logical virtual conversion table 51 on the flash memory at an interval frequency for each write process of user data (step S105) (step S109), thereby executing an update process for the logical virtual conversion table 51. Specifically, when the write process is completed up to the final virtual page in the virtual block (step S108: Y), or when the free space in the table cache becomes equal to or less than a predetermined threshold (step S115: Y), the microprocessor 27 writes and saves the edited logical virtual conversion table 51 on the flash memory 1.

[0083] (B-1. Operation example during read process: in table full expansion mode) Next, FIG. 11 is a flowchart showing an example of the read process (in table full expansion mode) according to the present embodiment.

[0084] In the series of processes shown in FIG. 11, first, the microprocessor 27 determines whether the target (read target) user data is already registered in the write cache data in the buffer 24 (step S201). Here, if it is determined that the user data to be read is already registered in the write cache data (step S201: Y), the process proceeds to step S205 (transmission of user data) described later.

[0085] On the other hand, if it is determined that the user data to be read is not already registered in the write cache data (step S201: N), next, the microprocessor 27 refers to the logical virtual conversion table 51 (step S202). Then, based on the referred logical virtual conversion table 51, the microprocessor 27 determines the virtual address that is the read source on the flash memory 1 (step S203).

[0086] Subsequently, the microprocessor 27 reads the user data from the flash memory 1 using the thus determined virtual address (step S204). Then, the microprocessor 27 transmits the user data read in this way to the host system 4 via the host interface 26 (step S205).

[0087] Next, the microprocessor 27 determines whether the command for the entire read process has been completed (step S206). Here, if it is determined that the command for the entire read process has not yet been completed (step S206: N), the process returns to step S201 described above. On the other hand, if it is determined that the command for the entire read process has been completed (step S206: Y), the series of processes shown in FIG. 11 ends.

[0088] (B-2. Example of operation during read process: in table cache mode) Also, FIG. 12 shows an example of the read process (in table cache mode) according to the present embodiment in the form of a flowchart.

[0089] The series of processes shown in this Figure 12 corresponds to the series of processes shown in the above-mentioned Figure 11, with steps S207 to S209 further added between steps S201 and S202. Therefore, hereinafter, these steps S207 to S209 will be briefly described.

[0090] First, step S207 is a process that is performed when it is determined in the aforementioned step S201 that the user data to be read is not registered in the write cache data (step S201: N). Specifically, in this case, next, the microprocessor 27 determines whether the target logical virtual conversion table 51 has been expanded (step S207). Here, if it is determined that the target logical virtual conversion table 51 has already been expanded (step S207: Y), the process proceeds to the aforementioned step S202 (reference of the logical virtual conversion table 51).

[0091] On the other hand, if it is determined that the target logical virtual conversion table 51 has not yet been expanded (step S207: N), next, the microprocessor 27 refers to the corresponding management table 52 (step S208) and expands the target logical virtual conversion table 51 (step S209). Then, afterwards, the process proceeds to the aforementioned step S202 (reference of the logical virtual conversion table 51).

[0092] This concludes the description of the series of processes shown in Figure 12.

[0093] (C-1. Example of operation during startup processing: in the case of the full table expansion mode) Next, Figure 13 shows an example of the aforementioned startup processing (in the full table expansion mode) according to the present embodiment, represented as a flowchart.

[0094] Here, this startup process assumes a case where the power supply of the flash memory system 3 (the flash memory 1 and the memory controller 2) transitions from the on state to the off state before the logical virtual conversion table 51 is written and stored on the flash memory 1. And this startup process is the process to be executed when the power supply of the flash memory system 3 returns from the off state to the on state after such a precondition state.

[0095] In the series of processes shown in FIG. 13, first, the microprocessor 27 determines the virtual block that was being written before the above-mentioned power supply recovery (step S301). Next, the microprocessor 27 initializes (page = "0") the virtual page to be read within the corresponding virtual block (step S302). Then, the microprocessor 27 reads the above-mentioned spare area As (see FIG. 5) in the virtual page to be read (step S303).

[0096] Next, the microprocessor 27 determines whether the above-mentioned logical address information (see step S105 in FIGS. 9A and 10A) has been written to the read spare area As (step S304). Here, if it is determined that the logical address information has not been written to the spare area As (step S304: N), since there is no more valid data in the target virtual block, the series of processes shown in FIG. 13 ends.

[0097] On the other hand, if it is determined that the logical address information has been written to the spare area As (step S304: Y), next, the microprocessor 27 performs the following processes. That is, in this case, the microprocessor 27 reads the written logical address information from the spare area As and uses the read logical address information to edit the unupdated part of the logical virtual conversion table 51 on the table RAM 25 (step S305).

[0098] Subsequently, the microprocessor 27 determines whether the current virtual page to be read is the last page within the corresponding virtual block (step S306). Here, if it is determined that the virtual page to be read is not the last page (step S306: N), then the microprocessor 27 updates the virtual page to be read (page: +1) (step S307). Thereafter, the process returns to step S303 described above.

[0099] On the other hand, if it is determined that the virtual page to be read is the last page (step S306: Y), the series of processes shown in FIG. 13 ends.

[0100] (C-2. Example of operation during startup processing: in table cache mode) Further, FIG. 14 shows an example of the above-described startup processing (in table cache mode) according to the present embodiment in a flowchart.

[0101] The series of processes shown in this FIG. 14 corresponds to the series of processes shown in FIG. 13 described above, with steps S308 and S309 further added between steps S304 and S305. Therefore, below, steps S308 and S309 will be briefly described.

[0102] First, step S308 is a process performed when it is determined in step S304 described above that logical address information has already been written to the spare area As to be read (step S304: Y). Specifically, in this case, the microprocessor 27 then determines whether the target (editing target) logical virtual conversion table 51 has been expanded (step S308). Here, if it is determined that the target logical virtual conversion table 51 has already been expanded (step S308: Y), the process proceeds to step S305 (editing of the logical virtual conversion table 51) described above.

[0103] On the other hand, when it is determined that the target logical virtual conversion table 51 has not been expanded yet (step S308: N), next, the microprocessor 27 expands the target logical virtual conversion table 51 (step S309). After that, the process proceeds to step S305 (editing of the logical virtual conversion table 51) described above.

[0104] Thus, the description of the series of processes shown in FIG. 14 is completed.

[0105] (D. Operation and Effect) In this way, in the present embodiment, every time the writing process of data (user data) is executed, the logical virtual conversion table 51 is edited on the table RAM 25. Then, the edited logical virtual conversion table 51 is written and stored on the flash memory 1 at the decimated frequency for each writing process, thereby executing the update process for the logical virtual conversion table 51.

[0106] Accordingly, in the present embodiment, for example, every time the writing process using the page mapping method is executed, the logical conversion table (a table that defines the correspondence between the logical address and the physical address) is edited and written and stored on the flash memory. Compared with the case (comparative example) of doing so, the following occurs. That is, first, in the method of this comparative example, for example, in the case of a writing process by random access, since the writing frequency of the logical conversion table onto the flash memory increases, there is a risk that the writing efficiency of the data deteriorates. On the other hand, in the present embodiment, for example, even in the case of such a writing process by random access, since the update frequency of the logical virtual conversion table 51 is low, it is possible to improve the writing efficiency of the data compared with the case of the comparative example.

[0107] Also, in this embodiment, on the flash memory 1, the virtual block into which data is written during the write process and the virtual block into which the edited logical virtual conversion table 51 is written and stored are made different from each other, so the following occurs. That is, for example, if these virtual blocks are made to match each other, in this embodiment, since the update frequencies of the user data and the logical virtual conversion table 51 are different from each other, there is a risk of being disadvantaged during garbage collection. Therefore, by making these virtual blocks different from each other, the risk of being disadvantaged during garbage collection can be avoided, and it becomes possible to further improve the data write efficiency.

[0108] Furthermore, in this embodiment, during the above-described startup process, the logical address information written together during the data write process is read from the spare area As included in the virtual block being written. Then, using the read logical address information, the unupdated part of the logical virtual conversion table 51 is edited on the table RAM 25. As a result, in this embodiment, for example, even if the power of the flash memory system 3 shifts from the on state to the off state before the logical virtual conversion table 51 is written and stored on the flash memory 1, the following occurs. That is, even in such a case, during the subsequent startup process, the update process (editing) of the unupdated part of the logical virtual conversion table 51 can be ensured. As a result, in this embodiment, it becomes possible to improve the reliability of the flash memory system 3.

[0109] <2. Variation> The present invention has been described above with reference to embodiments, but the present invention is not limited to these embodiments, and various modifications are possible.

[0110] For example, in the above-described embodiment, the configurations of the host system, the flash memory, and the memory controller, and the configuration of the control circuit have been specifically described. However, each of these configurations is not limited to those described in the above-described embodiment. Specifically, for example, in the above-described embodiment, an example in which the flash memory 1 is a NAND-type flash memory has been described. However, this is not the only example, and for example, a NOR-type flash memory may be used as the flash memory 1.

[0111] Also, in the above-described embodiment, an example has been described in which the logical virtual conversion table 51 and the management table 52 are respectively created and updated (edited) on the table RAM 25 in the memory controller 2 and written and stored on the flash memory 1. However, this is not the only example. For example, the logical virtual conversion table 51 and the management table 52 may be created and updated on another non-volatile memory (e.g., external RAM 30) outside the memory controller 2 or outside the flash memory system 3. Furthermore, the correspondence relationships of the respective pieces of information in these logical virtual conversion table 51 and management table 52 are not limited to the format described in the above-described embodiment and may be defined in other formats. In addition, the correspondence relationships of these respective pieces of information (such as the correspondence relationship between the logical address and the virtual address) are not limited to the form of a table and may be defined in other formats.

[0112] Also, the number of physical blocks included in each chip, the number of physical pages included in each physical block, the number of physical sectors included in each physical page, the number of physical blocks included in each virtual block, the number of physical pages included in each virtual page, the number of LBAs included in each logical page, etc., described in the above-described embodiment are merely examples, and other numerical values may be used.

[0113] Furthermore, in the above embodiment, the access processing (read processing and write processing) of data by the microprocessor 27, the update processing of each table, and each operation example at the time of startup processing have been specifically described. However, these various processing examples are not limited to those described in the above embodiment, and other methods may be used to perform these various processing examples.

[0114] In addition, the respective configuration examples and operation examples described so far may be applied in any combination.

Claims

1. A memory controller for controlling a flash memory, comprising: a microprocessor that respectively executes data access processing for the flash memory and update processing for updating predetermined area management information according to the access processing; The microprocessor: Based on the area management information that defines the correspondence between the logical address of the logical page and the virtual address of the virtual page included in the virtual block composed of a plurality of physical blocks belonging to a plurality of channels in the flash memory, determine the virtual address to be accessed during the access processing; When executing the data writing process as the access process based on the determined virtual address, Each time the writing process is executed, edit the area management information on the cache area, and At the frequency thinned out for each writing process, write and save the edited area management information on the flash memory, thereby Execute the update process for the area management information; Each of the plurality of virtual pages included in the virtual block is provided with a spare area for each physical page, and The microprocessor: When executing the writing process in units of the virtual page, Write logical address information indicating the corresponding logical address to the spare area in the virtual page to be written; The microprocessor: When the power supply of the flash memory and the memory controller shifts from the on state to the off state before the area management information is written and saved on the flash memory, In the startup process when the power supply then returns from the off state to the on state, Read out the logical address information from the spare areas included in the virtual block in the middle of writing, and On the cache area, use the read logical address information to edit the unupdated area management information Memory controller.

2. The microprocessor: When the writing process is completed up to the last page among the plurality of virtual pages included in the virtual block, or When the free area on the cache area becomes equal to or less than the threshold value, Write and save the edited area management information on the flash memory. The memory controller according to claim 1.

3. The microprocessor On the flash memory, The virtual block where the data is written during the writing process and the virtual block where the edited area management information is written and saved Make them different from each other The memory controller according to claim 1 or claim 2.

4. The memory controller according to any one of claims 1 to 3, The flash memory A flash memory system comprising.

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