ΔΣ modulation type A / D conversion device

Abstract

To provide an A / D conversion circuit capable of performing AD conversion in high accuracy while reducing an offset.SOLUTION: An A / D conversion circuit includes a capacitance coupled amplifier 11 for amplifying an analog input signal configured by providing capacitors C1a, C1b, C3a, C3b, and amplifier OP1. A first integrator 12 in correlated double sampling type as a first stage integrator is provided following the stage of the capacitance coupled amplifier 11. The output of the capacitance coupled amplifier 11 and the input of capacitors C4a, C4b of the first integrator 12 are directly connected without through a switch. A second integrator 13 is provided following the first integrator 12. A quantizer T1 for quantizing an output value of the second integrator 13 is provided following the second integrator 13. D / A converters 20a, 20b, 220a, 220b for performing D / A conversion for the output of the quantizer T1 and feeding it back to either the capacitance coupled amplifier 11, the first integrator 12, or the second integrator 13 are provided.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a ΔΣ modulation type A / D conversion device.

Background Art

[0002] For example, according to the device described in Patent Document 1, it includes a capacitive differential amplifier circuit that amplifies an analog differential signal in proportion to the ratio of the first and second capacitances of a capacitive differential circuit to provide an analog differential signal, and provides a technique of integrating the analog differential signal amplified by the capacitive differential amplifier circuit with an integrator. Further, Patent Document 2 exemplifies an A / D conversion device that generates a digital output signal based on an analog differential signal amplified by a capacitive differential amplifier circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, according to the description in Patent Document 1, it is not explicitly stated that it incorporates a ΔΣ modulator, and it is not a configuration capable of performing high-precision A / D conversion. Even if the configuration of Patent Document 2 is adopted, there is still room for improvement in reducing the offset.

[0005] An object of the present disclosure is to provide a ΔΣ modulation type A / D conversion device capable of performing A / D conversion with high precision while reducing the offset.

Means for Solving the Problems

[0006] The present disclosure is a ΔΣ modulation type A / D converter that digitally converts an analog input signal. It includes a sampling capacitor, a feedback capacitor, and a capacitive coupling amplifier that amplifies the analog input signal. A first integrator of a correlated double sampling type is provided as the first-stage integrator after the capacitive coupling amplifier, and the output of the capacitive coupling amplifier and the input of the sampling capacitor of the first integrator are directly connected without passing through a switch. A second integrator is provided after the first integrator. A quantizer that quantizes the output value of the second integrator is provided after the second integrator. The D / A converter performs D / A conversion on the output of the quantizer Either feedback to the capacitive coupling amplifier or the first integrator, or Any one of the capacitive coupling amplifier, the first integrator, and the second integrator two and feeds it back.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, several embodiments of the A / D conversion device will be described with reference to the drawings. In each embodiment, substantially the same or similar parts are denoted by the same reference numerals or similar reference numerals (for example, the same digit in the units and tens places and a different digit in the hundreds place), and the description thereof will be omitted as necessary. Each embodiment will be described centering on the characteristic parts. Also, in the following embodiments, a differential circuit is used for the description, and circuit components having a symmetric differential configuration are illustrated and described with suffixes a and b attached thereto.

[0009] (First Embodiment) The first embodiment will be described with reference to FIGS. 1 and 6. FIG. 1 shows a schematic configuration of a ΔΣ type A / D converter 10. In the first embodiment, a form in which the A / D converter 10 has a CIFF configuration will be described.

[0010] The A / D converter 1 includes a capacitive coupling amplifier 11, a first integrator 12, a second integrator 13, and a control circuit 14. Further, a quantizer T1 is configured at the output stage of the second integrator 13. The ΔΣ modulator 15 has a feedback configuration including the first integrator 12, the second integrator 13, the quantizer T1, and D / A converters 20a and 20b. The D / A converters 20a and 20b correspond to the second D / A converter according to the present disclosure. The control circuit 14 is constituted by a microcomputer or a logic circuit or the like, and outputs control signals to the respective configurations of the capacitive coupling amplifier 11, the first integrator 12, the second integrator 13, the quantizer T1, and the D / A converters 20a and 20b.

[0011] Differential analog input signals Vinp and Vinm are input to the capacitive coupling amplifier 11 through input terminals Ina and Inb. At this time, a voltage of about Vinp - Vinm = ±100 mV is applied. Since an offset voltage Vcm of about ±100 mV is also input to each of the input terminals Ina and Inb, voltages of Vinp = +Vdiff / 2 + Vcm and Vinm = -Vdiff / 2 + Vcm are input to the input terminals Ina and Inb.

[0012] The capacitive coupling amplifier 11 is mainly constituted by a fully differential operational amplifier OP1, and a parallel connection circuit of resistors R1a and R1b and capacitors C3a and C3b serving as feedback capacitors is connected between the input and output of the operational amplifier OP1. The resistors R1a and R1b are provided to determine the input voltage. Further, sampling capacitors C1a and C1b are respectively connected between the input terminals Ina and Inb and the inverting input terminal and the non-inverting input terminal of the operational amplifier OP1.

[0013] Also, switches S1a and S2b are respectively interposed and connected between the input terminal Ina and the inverting input terminal and non-inverting input terminal of the operational amplifier OP1. Switches S2a and S1b are respectively interposed and connected between the input terminal Inb and the inverting input terminal and non-inverting input terminal of the operational amplifier OP1. By the control circuit 14 performing on / off control of the switches S1a, S1b, S2a, and S2b, the analog input signals Vinp and Vinm can be inverted in polarity and input to the operational amplifier OP1. The output of the operational amplifier OP1 is directly connected to the inputs of the capacitors C1a and C1b of the first integrator 12 without passing through a switch, and no switch is interposed between the input and output of the operational amplifier OP1.

[0014] The output of the capacitive coupling amplifier 11 is input to the first integrator 12. In other words, a capacitive coupling amplifier 11 that amplifies the analog input signals Vinp and Vinm is connected in front of the first integrator 12. The first integrator 12 constitutes the first-stage integrator and is a so-called correlated double sampling (CDS) type integrator. The first integrator 12 is also mainly composed of a fully differential operational amplifier OP2. The output of the operational amplifier OP1 is input to the input of the operational amplifier OP2 via the capacitors C4a and C4b.

[0015] A short-circuit switching path and a current conduction path of the capacitors C5a and C5b are connected in parallel between the input and output of the operational amplifier OP2. Switches S7a and S7b are configured between the input and output of the operational amplifier OP2 in the short-circuit switching path. In the current conduction path of the capacitors C5a and C5b, the capacitors C5a and C5b and the switches S8a and S8b are connected in series, and the charging and discharging of the capacitors C5a and C5b can be switched using the switches S8a and S8b.

[0016] The output of the first integrator 12 is input to the second integrator 13. The second integrator 13 is also mainly composed of a fully differential operational amplifier OP3. The output of the operational amplifier OP2 is connected to the input of the operational amplifier OP3 via capacitors C6a and C6b. Also, between the output of the operational amplifier OP2 and the input of the operational amplifier OP3, switches S9a, S9b, S10a, S10b, S11a, S11b, S12a, and S12b are connected in the illustrated form. These switches S9a, S9b, S10a, S10b, S11a, S11b indicate switches that are switched during charging from capacitors C5a, C5b to capacitors C6a, C6b or during discharging of capacitors C6a, C6b.

[0017] Capacitors C7a and C7b are connected as feedback capacitances between the input and output of the operational amplifier OP3. The switches S12a and S12b indicate switches that are switched during charging from capacitors C6a, C6b to capacitors C7a, C7b. The output of the operational amplifier OP3 is connected to the input of the quantizer T1 via capacitors C9a and C9b. Also, between the output of the operational amplifier OP3 and the input of the quantizer T1, switches S13a, S13b, S14a, S14b, S15a, and S15b are connected in the illustrated form. These switches S13a and S13b indicate switches that are switched during charging from capacitors C7a, C7b to capacitors C9a, C9b, and the switches S14a, S14b, S15a, and S15b indicate switches that are switched during discharging of capacitors C9a, C9b.

[0018] The quantizer T1 converts the level of the output of the second integrator 13 into a binary digital signal Dout of "1" or "0". Also, the digital signal Dout of the quantizer T1 is input to the D / A converters 20a and 20b. The D / A converters 20a and 20b of this embodiment feed back to the first integrator 12 based on the binary values of the digital signal Dout. The D / A converters 20a and 20b are circuits that output two levels of a high potential, for example, +5V, or a low potential, for example, 0V, based on the digital signal Dout.

[0019] Between the D / A converters 20a and 20b and the input of the operational amplifier OP2 that constitutes the first integrator 12, switches S4a and S4b and capacitors C2a and C2b are connected in series. When the control circuit 14 turns on the switches S4a and S4b, the D / A converters 20a and 20b feed back to the first integrator 12.

[0020] The operation and effect of the above configuration will be described. As shown in the time chart of FIG. 2, the control circuit 14 outputs on / off control signals Φ1, Φ2, Φ1d, and Φ2d to the target switches S1a, S1b~S15a, S15b to turn on and off the switches S1a, S1b~S15a, S15b. For the detailed on / off control content of the switches S1a, S1b~S15a, S15b, refer to FIGS. 2 to 5. FIG. 3 shows the on / off control signals Φ1, Φ2, Φ1d, and Φ2d applied to each switch. Also, the control circuit 14 outputs the control signal ΦEVAL to the quantizer T1 to sample the input signal at the timing ta of the rising edge of the control signal ΦEVAL, and then digitally convert the sampled voltage at the timing tb of the falling edge of the subsequent control signal ΦEVAL and output it as a digital signal Dout.

[0021] Note that the on / off control signals Φ1 and Φ2 are control signals that turn on and off complementarily, and the on / off control signals Φ1d and Φ2d are also control signals that turn on and off complementarily. Also, the on / off control signals Φ1d and Φ2d are control signals output so as to be slightly delayed compared to the on / off control signals Φ1 and Φ2. FIG. 4 shows the connection state when the on / off control signals Φ1 = ON, Φ1d = ON, Φ2 = OFF, and Φ2d = OFF, and FIG. 5 shows the connection state when the on / off control signals Φ1 = OFF, Φ1d = OFF, Φ2 = ON, and Φ2d = ON.

[0022] The following will briefly explain the signal processing flow and operation. <Explanation of the on / off operation of each switch and the signal processing flow> First, at timings t1 and t1d shown in FIG. 2, when the on-off control signals Φ1, Φ2, Φ1d, Φ2d become Φ1 = ON, Φ1d = ON, Φ2 = OFF, Φ2d = OFF, since Φ1d = ON turns on switches S2a and S2b, as shown in FIG. 4, the analog input signals Vinp and Vinm are input to capacitors C1b and C1a of the capacitive coupling amplifier 11. Also, since switches S8a and S8b turn off, the charges of capacitors C4a and C5b are retained as they are.

[0023] Thereafter, at timings t2 and t2d, when the on-off control signals Φ1, Φ2, Φ1d, Φ2d become Φ1 = OFF, Φ1d = OFF, Φ2 = ON, Φ2d = ON, they are connected as shown in FIG. 5. At this time, since the stored charges of the input capacitors C1a and C1b of the capacitive coupling amplifier 11 are discharged, the input voltage decreases, the voltage at the output terminal also decreases, and the input voltage of the first integrator 12 also decreases.

[0024] When the input voltage is changed from Vinp to Vinm, the capacitive coupling amplifier 11 inputs and amplifies the input voltage Vinp - Vinm. Subsequently, it is sampled by capacitors C4a and C4b which are the sampling capacitors of the first integrator 12. As the input voltage of the first integrator 12 decreases, the output values of capacitors C5a and C5b increase, and as a result, the current change amount is added to the previous output value and integrated and output.

[0025] On the other hand, since Φ2d = ON turns on switches S9a and S9b, the stored charges of capacitors C5a and C5b are charge-distributed to capacitors C6a and C6b. Further, since switches S12a and S12b turn on, the second integrator 13 inputs the integration output of the first integrator 12 and further outputs an integration output, and accumulates charges from the output of the operational amplifier OP3 to capacitors C7a and C7b.

[0026] Thereafter, at timings t3 and t3d, when the on-off control signals Φ1, Φ2, Φ1d, and Φ2d become Φ1 = ON, Φ1d = ON, Φ2 = OFF, and Φ2d = OFF, switches S13a and S13b turn on. Therefore, as shown in FIG. 4, the integration output of the second integrator 13 is sampled by capacitors C9a and C9b.

[0027] On the other hand, when the on-off control signals Φ1 = ON and Φ1d = ON, the stored charges in capacitors C6a and C6b are discharged. In the capacitive coupling amplifier 11 and the first integrator 12, due to the same operation as described above, the capacitive coupling amplifier 11 amplifies the analog input signal.

[0028] Thereafter, at timings t4 and t4d in FIG. 2, when the on-off control signals Φ1, Φ2, Φ1d, and Φ2d become Φ1 = OFF, Φ1d = OFF, Φ2 = ON, and Φ2d = ON, after switches S15a and S15b turn off and then switches S14a and S14b turn on, a voltage based on the stored voltages of capacitors C9a and C9b is input to the quantizer T1 with respect to the ground potential. The quantizer T1 inputs the voltages of these capacitors C9a and C9b at timing ta2 in FIG. 2 and generates a digital signal Dout based on this voltage.

[0029] Thereafter, at timings t5 and t5d in FIG. 2, after the on-off control signals Φ1, Φ2, Φ1d, and Φ2d become Φ1 = ON, Φ1d = ON, Φ2 = OFF, and Φ2d = OFF, the quantizer T1 outputs to the D / A converters 20a and 20b at timing tb2. The D / A converters 20a and 20b feedback-output a high potential or a low potential to the first integrator 12 based on the digital signal Dout. Subsequently, the first integrator 12 adds the outputs of the D / A converters 20a and 20b and outputs an integration output.

[0030] Summarizing these operations, it is as follows. Repeated charging and discharging due to the action of the switched capacitor, hold the previous output at the timing of the on-off control signals Φ1 and Φ1d = ON shown in FIG. 4, and then, at the timing of the on-off control signals Φ2 and Φ2d = ON shown in FIG. 5, transfer the charge to the capacitors C5a and C5b that become the feedback capacitance of the first integrator 12, and at the same time transfer the charge to the capacitors C7a and C7b of the second integrator 13. Furthermore, at the timing of the on-off control signals Φ1 and Φ1d = ON shown in FIG. 4 that follow, the charge can be transferred to the capacitors C9a and C9b.

[0031] Furthermore, it can be input to the quantizer T1 at the timing ta2 during the on-off control signals Φ2 and Φ2d = ON shown in FIG. 5 that follow, and then the quantizer T1 outputs the digital signal Dout at the timing tb2. This digital signal Dout is fed back to the first integrator 12 through the capacitors C2a and C2b which are the DAC capacitances from the D / A converters 20a and 20b.

[0032] According to this operation, since the input side of the operational amplifier OP2 has high impedance and the output side has low impedance, the output value of the first integrator 12 is determined by the charge transfer amount between the capacitors C4a, C4b → C5a, C5b when the on-off control signal changes from Φ1 = OFF to Φ2 = ON. Before the on-timing of the on-off control signal φ1d, the charges of the capacitors C4a and C4b are determined at the on-timing of the on-off control signal φ1. Therefore, the ON timing of the on-off control signal Φ1d does not participate in the output of the first integrator 12. Assuming the capacitance values of the capacitors C1a and C1b are Csc and the capacitance values of the capacitors C3a and C3b are Cfc, when observing the stage before the input of the first integrator 12, the capacitive coupling amplifier 11 can be regarded as a continuous amplifier that simply amplifies by Csc / Cfc times.

[0033] Explain the offset reduction effect, which is the technical significance of the above configuration. Fig. 6 shows an explanatory diagram of the offset cancellation effect. Let Voscca be the offset generated at the input terminal of the operational amplifier OP1, and Voscds be the offset generated at the input terminal of the operational amplifier OP2.

[0034] At this time, the output voltage Voutp - Voutm of the capacitive coupling amplifier 11 is Voutp - Voutm = Csc(Vinp - Vinm) / Cfc and can be expressed as such. Also, the output voltage Vout of the first integrator 12 is Vout = Cs1{(Voutp + Voscca) - (Voutm + Voscca)} / Cf1 = Cs1(Voutp - Voutm) / Cf1 = Cs1·Csc(Vinp - Vinm) / Cf1·Cfc and can be expressed as such.

[0035] Since the output voltage of the first integrator 12 becomes Vout + Voscds, Vout + Voscds = Cs1·Csc(Vinp - Vinm) / Cf1·Cfc + Voscds and can be expressed as such.

[0036] In the configuration of this embodiment, the offset Voscca input to the capacitive coupling amplifier 11 is canceled by the first integrator 12. Therefore, as a whole, the offset can be improved by the gain of the capacitive coupling amplifier 11.

[0037] <Summary> According to this embodiment, a capacitive coupling amplifier 11 is configured in front of the first integrator 12. Compared with the case where the first integrator 12 is a simple correlated double sampling (CDS) second-order ΔΣ modulator, the capacitive coupling amplifier 11 can amplify the analog input signal Vinp - Vinm. The output value is determined at the sampling and holding timing of the first integrator 12, and from the perspective of the first integrator 12, since the capacitive coupling amplifier 11 can be regarded as a continuous amplifier, it is no longer affected by sampling noise.

[0038] The first integrator 12 is configured in a correlated double sampling type and can perform double sampling, so it is no longer affected by the offset of the capacitive coupling amplifier 11. Therefore, overall, the influence of the offset can be suppressed and improved by the gain of the capacitive coupling amplifier 11. As a result, it becomes possible to perform high-precision A / D conversion while reducing the offset.

[0039] Instead of using the configurations of the capacitive coupling amplifier 11 and the first integrator 12 as a simple integrator, by using them as a ΔΣ modulator in which the output of the quantizer T1 is fed back by the D / A converters 20a and 20b, it is possible to continuously integrate the analog input signal Vinp - Vinm without saturating the output of the first integrator 12, and high-precision A / D conversion can be performed. According to this embodiment, there is no need to provide a switch or the like between the capacitive coupling amplifier 11 and the first integrator 12, and they can be directly connected. Since the switch is not required, it becomes possible to control without being affected by the on-resistance of the switch and injection, etc., and high-precision A / D conversion can be performed.

[0040] In this embodiment, since the CIFF configuration is adopted, it is not necessary to feed back the feedback outputs of the D / A converters 20a and 20b to the second integrator 13, and the feedback path can be reduced, so the configuration can be simplified.

[0041] (Second Embodiment) The second embodiment will be described with reference to FIGS. 7 and 8. The A / D conversion device 210 shown in FIG. 7 is different from that of the first embodiment in that the D / A converters 220a and 220b are configured to feed back the output to the capacitive coupling amplifier 11, and the capacitive coupling amplifier 11 is configured within the feedback loop of the ΔΣ modulator 215. The D / A converters 220a and 220b correspond to a first D / A converter.

[0042] The ΔΣ modulator 215 is composed of a capacitive coupling amplifier 11, a first integrator 12, a second integrator 13, a quantizer T1, and D / A converters 220a and 220b. The outputs of the D / A converters 220a and 220b are fed back to the input terminal of the operational amplifier OP1 of the capacitive coupling amplifier 11 through the switches S24a and S24b and the capacitors C22a and C22b, respectively, with the high potential being, for example, +5V and the low potential being, for example, 0V. The on / off control signal Φ2d shown in the above-described embodiment is applied to the switches S24a and S24b. Other configurations are the same as those of the first embodiment. Then, as shown in FIG. 8, when the on / off control signals Φ2 and Φ2d = ON, the capacitive coupling amplifier 11 amplifies both the feedback output by the D / A converters 220a and 220b and the analog input signal Vinp - Vinm.

[0043] In this case, the influence of the variation in the feedback capacitors C3a and C3b of the capacitive coupling amplifier 11 and the influence of the variation in the capacitors C4a, C4b, C5a, C5b, etc. configured in the subsequent first integrator 12, etc. are reduced, so that the gain error can be reduced.

[0044] When the D / A converters 20a and 20b output a relatively small absolute value of the digital signal Dout of the quantizer T1 after D / A conversion, if fed back to the first integrator 12 as shown in the first embodiment, the DAC capacitance value constituting the first integrator 12 has to be designed to be increased. However, by feeding back the output of the quantizer T1 to the capacitive coupling amplifier 11 as in this embodiment, it becomes possible to achieve the same result even with a small DAC capacitance due to the amplification by the capacitive coupling amplifier 11.

[0045] (Embodiment 3) Embodiment 3 will be described with reference to FIGS. 9 and 10. The ΔΣ modulator 315 shown in FIG. 9 is different from the ΔΣ modulator 15 of the first embodiment in that D / A converters 220a, 220b and 20a, 20b are provided corresponding to both the capacitive coupling amplifier 11 and the first integrator 12, and the output is configured to be fed back to both the capacitive coupling amplifier 11 and the first integrator 12. Another feature is that the capacitive coupling amplifier 11 is configured within the feedback loop of the ΔΣ modulator 315.

[0046] The switches S4a, S4b, S24a, S24b are given the on / off control signal Φ2d shown in the above-described embodiments. As shown in FIG. 10, when the on / off control signals Φ2, Φ2d = ON, the capacitive coupling amplifier 11 amplifies both the feedback output by the D / A converters 220a, 220b and the analog input signals Vinp - Vinm, and the first integrator 12 also amplifies the feedback output by the D / A converters 20a, 20b. Thus, according to this embodiment, the same operation as that of the first embodiment is achieved and the same operational effects as those of the second embodiment are achieved.

[0047] Also, it becomes easier to handle even when there is a difference in the feedback output values between the D / A converters 20a, 20b and the D / A converters 220a, 220b. For example, when the output value of the D / A converters 20a, 20b is V1 and the output value of the D / A converters 220a, 220b is V2, and V1 > V2, if both the output value V1 and the output value V2 are to be fed back and output to the first integrator 12, it is necessary to increase the DAC capacitance in order to increase the amplification degree on the output value V2 side. However, by feeding back the output value V2 to the capacitive coupling amplifier 11, it is not necessary to increase the DAC capacitance by the amount amplified by the capacitive coupling amplifier 11.

[0048] (Embodiment 4) The fourth embodiment will be described with reference to FIG. 11. The difference between the fourth embodiment and the first embodiment is that the plurality of sets of D / A converters 220a, 220b, 20a, 20b compensate for the temperature dependence by outputting either a PTAT signal VPTAT that increases with temperature or a CTAT signal VCTAT that decreases with temperature based on the temperature characteristics of the analog input signals Vinp, Vinm. The D / A converters 220a, 220b, 20a, 20b compensate for the temperature dependence by outputting the PTAT signal VPTAT and the CTAT signal VCTAT and adjusting the feedback amount.

[0049] When the analog input signals Vinp, Vinm change depending on the temperature, for example, increase or decrease, it may be desirable to correct this temperature dependence. In such a case, it is advisable to provide a temperature acquisition unit 30 that acquires a signal (such as a voltage or current) depending on the ambient temperature for the source of the analog input signals Vinp, Vinm. For example, when the source of the analog input signals Vinp, Vinm is a signal sensing unit 31 such as a pressure sensor or a current sensor using a shunt resistor, the analog input signals Vinp, Vinm change depending on the ambient temperature. In such a case, it is advisable to provide the temperature acquisition unit 30 so as to acquire the temperature of the signal sensing unit 31.

[0050] The D / A converters 220a, 220b, 20a, 20b multiply the output of the digital signal Dout of the quantizer T1 by the PTAT signal VPTAT or the CTAT signal VCTAT and output the result as feedback. For example, a CTAT signal VCTAT depending on the temperature characteristics of the first diode may be generated by applying a constant current to the first diode and using the obtained voltage as a value, and a different constant current may be passed through the second diode, and the voltage difference between the first diode and the second diode may be calculated to generate the PTAT signal VPTAT.

[0051] When it is understood that the analog input signals Vinp and Vinm depend on the temperature T acquired by the temperature acquisition unit 30, the D / A converters 220a and 220b multiply the PTAT signal VPTAT depending on the temperature by the digital signal Dout of the quantizer T1 and output the result, and the D / A converters 20a and 20b multiply the CTAT signal VCTAT by the digital signal Dout of the quantizer T1 and output the result.

[0052] By feeding back the D / A converters 220a, 220b, 20a, and 20b with the same temperature dependence as the analog input signals Vinp and Vinm, the temperature component can be canceled out. When there is a relationship of Vinp - Vinm = kT, where k is the temperature-dependent coefficient and T is the temperature, Vref = VPTAT + VCTAT / α = k’T - k’’T / α = kT If it can be set to this, the influence of the change in temperature T can be compensated.

[0053] Here, the coefficients k’ and k’’ respectively indicate the temperature-dependent coefficients of the PTAT signal VPTAT and the CTAT signal VCTAT, that is, the coefficients of the slopes with respect to the increase and decrease of temperature. Also, the coefficient α indicates a coefficient based on the input capacitance and feedback capacitance ratio of the capacitive coupling amplifier 11, and the DAC capacitance of the D / A converters 20a and 20b and the feedback capacitance ratio of the first integrator 12.

[0054] Let the capacitance values of the capacitors C1a and C1b that are the input capacitances of the capacitive coupling amplifier 11 be Cin, and the capacitance values of the capacitors C3a and C3b that are the feedback capacitances be Cfb. Also, when the capacitance values of the capacitors C2a and C2b that are the output DAC capacitances of the D / A converters 20a and 20b are Cdac, and the capacitance values of the capacitors C4a and C4b that are the input capacitances of the first integrator 12 are Cin2, the coefficient α can be expressed as α = (Cin / Cfb) × (Cin2 / Cdac). By setting it in this way, the influence of the change in the environmental temperature T can be compensated.

[0055] (Fifth Embodiment) The fifth embodiment will be described with reference to FIG. 12. As shown in FIG. 12, a series connection circuit of a D / A converter 20a, a switch S4a, and a capacitor C2a is connected in parallel with a series connection circuit of a D / A converter 620a, a switch S64a, and a capacitor C62a. Further, a switch Sf64a is connected between the output of the quantizer 5 and the input of the D / A converter 20a. The switches S4a and S64a are controlled to turn on and off synchronously.

[0056] On the other hand, a series connection circuit of a D / A converter 20b, a switch S4b, and a capacitor C2b is connected in parallel with a series connection circuit of a D / A converter 620b, a switch S64b, and a capacitor C62b. Further, a switch Sf64b is connected between the output of the quantizer 5 and the input of the D / A converter 20b. The switches S4b and S64b are controlled to turn on and off synchronously. The D / A converters 620a and 620b correspond to the third D / A converter according to the present disclosure.

[0057] When the analog input signal Vinp-Vinm has temperature dependence on a plurality of parameters, it is desirable to perform temperature correction by switching a plurality of feedback paths for the dependence coefficients k1 and k2 of the respective parameters.

[0058] When the relationship Vinp-Vinm = k1·T holds for the dependence coefficient k1, if Vref = VPTAT + VCTAT / α = (k’·T)-(k’’·T / α) = k1·T can be achieved, the dependence on the temperature T can be compensated. However, assuming that the capacitance values of the capacitors C2a and C2b, which are the DAC capacitances connected in series to the D / A converters 20a and 20b, are Cdac1, then, as in the fifth embodiment, α = (Cin / Cfb)×(Cin2 / Cdac1).

[0059] On the other hand, when the relationship Vinp-Vinm = k2·T holds for the dependence coefficient k2, the temperature component can be canceled if Vref = VPTAT + VCTAT / λ = (k’T)-(k’’T / λ) = k2·T can be achieved.

[0060] Assuming that the capacitance values of capacitors C62a and C62b, which are DAC capacitances connected in series to D / A converters 620a and 620b, are Cdac2, then λ = (Cin / Cfb) × (Cin2 / Cdac2). Therefore, even if the analog input signal Vinp - Vinm changes in a temperature-dependent manner depending on a plurality of parameters, by determining the aforementioned α and λ and adjusting the respective capacitor capacitances, and determining the feedback amount for each feedback path, the compensation amount for the dependency on temperature T can be adjusted. As a result, the dependency on temperature T based on a plurality of parameters can be decomposed into elements, and by determining the circuit constants of independent feedback paths, the compensation amount for the dependency on temperature T can be adjusted for each individual element.

[0061] For example, by setting so as to roughly adjust the temperature compensation of the analog input signal Vinp - Vinm by the feedback of D / A converters 620a and 620b, and setting so as to finely adjust the temperature compensation of the analog input signal Vinp - Vinm by the feedback of D / A converters 20a and 20b, the range in which temperature compensation can be performed can be further extended compared to the fifth embodiment. Also, if the capacitance can be made variable, it is possible to perform even finer adjustment.

[0062] <Modification Example> Hereinafter, modification examples of the fourth and fifth embodiments will be described. The D / A converters 20a, 20b, 220a, 220b, 620a, and 620b described in the fourth and fifth embodiments can be combined in any manner. For example, the relationship of the output voltage based on the PTAT signal VPTAT and the CTAT signal VCTAT by the D / A converters 20a, 20b, 220a, and 220b described in the fourth embodiment may be interchanged.

[0063] If the direction of the dependency of the analog input signals Vinp and Vinm on temperature T is known in advance, the D / A converters 20a, 20b, 220a, 220b, 620a, and 620b may all be configured to output a voltage obtained by multiplying the output of the quantizer T1 by the PTAT signal VPTAT, or may all be configured to output a voltage obtained by multiplying the output of the quantizer T1 by the CTAT signal VCTAT.

[0064] In the case where both of the D / A converters 20a, 20b, 620a, and 620b described in the fifth embodiment output a voltage using, for example, a PTAT signal VPTAT, either one of the D / A converters (for example, 20a, 20b) may coarsely adjust and stepwise change the voltage based on this PTAT signal VPTAT, and the other D / A converter (for example, 620a, 620b) may finely adjust the voltage based on the PTAT signal VPTAT. The same applies to the case where a voltage is output using a CTAT signal VCTAT.

[0065] Although a configuration in which two D / A converters 20a, 20b, 620a, and 620b are provided in parallel has been described, three or more D / A converters may be configured in parallel, and the degree of change in the output of the D / A converters may be adjusted stepwise.

[0066] Similarly, in the case where both of the D / A converters 20a, 20b, 620a, and 620b described in the fifth embodiment are outputting a voltage using, for example, a PTAT signal VPTAT, only one of them may be switched to output a voltage using a CTAT signal VCTAT.

[0067] Also, in the case where both of the D / A converters 20a, 20b, 220a, and 220b described in the fourth embodiment are outputting a voltage using, for example, a PTAT signal VPTAT, only one of the D / A converters 20a, 20b, 220a, and 220b may be switched to output the voltage using a CTAT signal VCTAT, or both of them may be configured to output a voltage using a CTAT signal VCTAT.

[0068] (Sixth Embodiment) The sixth embodiment will be described with reference to FIGS. 13A and 13B. In the sixth embodiment, the D / A converters 20a, 20b, 220a, and 220b include feedback amount adjustment circuits 30a, 30b, 630a, and 630b that adjust the feedback amount for each quantization result by the quantizer T1 in a bit stream controlled method, that is, and the outputs of the D / A converters 20a and 20b are determined according to the feedback amount adjustment circuits 30a, 30b, 630a, and 630b.

[0069] In the first to fifth embodiments, the D / A converters 20a and 20b output one output, for example, a high potential or a low potential, for example, +5V or -5V, corresponding to one output value "1" or "0" of the digital signal Dout. That is, each time the digital signal Dout is output once, the D / A converters 20a and 20b output once.

[0070] In the present embodiment, as shown in FIG. 13A, there are feedback amount adjustment circuits 30a, 30b, 630a, and 630b for adjusting the feedback amount at the output destination of the quantizer T1, and the D / A converters 20a, 20b, 630a, and 630b output corresponding to the respective outputs of the feedback amount adjustment circuits 30a, 30b, 630a, and 630b. The feedback amount adjustment circuits 30a, 30b, 630a, and 630b are provided for each quantization result of the quantizer T1. For example, when the digital signal Dout of the output of the quantizer T1 is a 2-bit output of 0 or 1, it is input to the first feedback amount adjustment circuits 30a and 30b when Dout = 0 is output, and is input to the second feedback amount adjustment circuits 630a and 630b when Dout = 1 is output. Digital processing is performed in separate feedback amount adjustment circuits for each digital signal Dout. Thereafter, the outputs of the D / A converters 20a, 20b, 630a, and 630b are determined according to the outputs of the feedback amount adjustment circuits 30a, 30b, 630a, and 630b.

[0071] As a specific example of FIG. 13A, for example, the feedback amount adjustment circuits 30a, 30b, 630a, and 630b are configured to determine the DAC output by ΔΣ modulating the output of the quantizer T1. FIG. 13B shows an example when the feedback amount adjustment circuits 30a, 30b, 630a, and 630b perform ΔΣ modulation. As illustrated in the upper part of FIG. 13B, when the amplification factor of the feedback amount is 1 and bitstream control is not performed, when the digital signal Dout is "1", the D / A converters 20a and 20b output a high potential, for example, +5V, as one analog signal. When the digital signal Dout is "0", the D / A converters 20a and 20b output a low potential, for example, -5V, as one analog signal.

[0072] On the other hand, as illustrated in the middle part of FIG. 13B, when the amplification factor of the feedback amount is 1 / 2, while the previous past digital signal Dout "1" is output twice, the D / A converters 20a and 20b output a middle potential, for example, 0V, once and a high potential of 5V once as an analog signal. Conversely, while the previous past digital signal Dout "0" is output twice, the D / A converters 20a and 20b output a middle potential of 0V once and a low potential of -5V once as an analog signal.

[0073] Similarly, as illustrated in the lower part of FIG. 13B, when the amplification factor of the feedback amount is 1 / 3, while the previous past digital signal Dout "1" is output three times, the D / A converters 20a and 20b output a middle potential of 0V twice and a high potential of 5V once as an analog signal. Conversely, while the previous past digital signal Dout "0" is output three times, the D / A converters 20a and 20b output a middle potential of 0V twice and a low potential of -5V once as an analog signal.

[0074] According to this embodiment, without changing the analog circuit configuration, the feedback amount can be freely adjusted only by changing the digital processing. By simply changing the amplification factor of the feedback amount shown above, the feedback amount can be roughly adjusted or finely adjusted. Utilizing this property, for example, when correcting the feedback amount based on the acquired temperature, rough adjustment or fine adjustment can be switched and implemented.

[0075] (Embodiment 7) Embodiment 7 will be described with reference to FIG. 14. In the first embodiment, the CIFF configuration was used as the feedback configuration, but as shown in the A / D conversion device 710 in FIG. 14, a CIFB configuration can also be used. The difference between the A / D conversion device 710 and the A / D conversion device 10 lies in the configuration of the second integrator 713 and the fact that the D / A converter 720a feeds back to the second integrator 713.

[0076] In the A / D conversion device 710 shown in FIG. 14, the capacitors C9a, C9b and the configuration of the switches S13a to S15a, which were configured at the output of the operational amplifier OP3 of the A / D conversion device 10, are deleted, and the capacitors C8a, C8b, which are the feedback capacitances of the second integrator 13 as the second integrator 713, are deleted, and it is configured by directly connecting between the output of the operational amplifier OP3 and the input of the quantizer T1.

[0077] Also, the D / A converters 720a, 720b feed back the digital signal Dout output from the quantizer T1 to the second integrator 713 through the switch S74a 、S74b and the capacitor C72a 、C72b . As a result, the capacitors C9a, C9b and the switches S13a to S15a used in the CIFF configuration can be reduced. Thereby, the configuration area of the capacitors and switches can be reduced and the overall size can be reduced.

[0078] (Embodiment 8) The eighth embodiment will be described with reference to FIGS. 15 to 19. The ΔΣ modulator 815 shown in FIG. 15 includes polarity inversion circuits X1 (X1a, X1b), X2 (X2a, X2b), X3 (X3a, X3b), X4 (X4a, X4b) for chopping before and after input and output, and also includes a polarity inversion circuit X5 with a control terminal.

[0079] The polarity inversion circuits X1 (X1a, X1b), X2 (X2a, X2b), X3 (X3a, X3b), X4 (X4a, X4b) shown in FIG. 15 are circuits equivalent to the polarity inversion circuits X1 to X4 shown in FIGS. 16 to 19, respectively. The polarity inversion circuit X1 shown in FIG. 16 is configured immediately after the input terminals Ina and Inb using switches X1a and X1b for switching the straight / cross connection of the wiring, and the input of the analog input signals Vinp and Vinm can be switched by inputting the polarity inversion signal flf. Thus, the input section for inputting the analog input signals Vinp and Vinm is configured to perform a chopping operation.

[0080] The polarity inversion circuit X2 shown in FIG. 17 is a circuit that switches the series connection between the capacitors C5a and C5b and the switches S8a and S8b using switches (not labeled) for switching the straight / cross connection of the wiring, and the connection can be switched by inputting the polarity inversion signal flf. Thus, the front and rear of the feedback capacitance of the first integrator 12 are configured to perform a chopping operation.

[0081] The polarity inversion circuit X3 shown in FIG. 18 is a circuit that switches the feedback path from the output of the quantizer T1 to the inputs of the D / A converters 20a and 20b using switches for switching the straight / cross connection of the wiring, and the connection can be switched by inputting the polarity inversion signal flf. Thus, the input sections of the D / A converters 20a and 20b for feeding back the output of the digital signal Dout are configured to perform a chopping operation.

[0082] The polarity inversion circuit X4 shown in FIG. 19 is a circuit that switches the connection of capacitors C7a and C7b using a switch (not numbered) that switches between straight / cross connections of the wiring, and can switch the connection by inputting a polarity inversion signal flf. Thereby, it is configured to chop the front and back of the feedback capacitance of the second integrator 13.

[0083] Also, the inversion circuit X5 with a control terminal shown in FIG. 15 is a circuit that can switch between forward / backward outputs by inputting a polarity inversion signal flfd.

[0084] The control circuit 14 can switch the connection by sequentially switching the straight / cross connections of switches X1a, X1b, X2, X3, and X4 using the polarity inversion signals flf and flfd. Also, the control circuit 14 is configured to switch between forward output / backward output by switching the enable / disable of the inversion circuit X5 using the polarity inversion signal flfd. It is configured to chop the subsequent stage of the output section of the quantizer T1.

[0085] The control circuit 14 performs polarity inversion control by changing the polarity inversion signals flf and flfd as shown in FIG. 20 to switch the straight / cross connections of the polarity inversion circuits X1 to X4 and to switch the forward / backward outputs of the inversion circuit X5.

[0086] At this time, only the chopping of the subsequent stage of the output section of the quantizer T1 by the inversion circuit X5 is configured to operate by the polarity inversion signal flfd. This chopping operation is controlled to be delayed by one AD conversion timing compared to the chopping at the input section of the analog input signals Vinp and Vinm by the other polarity inversion circuits X1 to X4, before and after the feedback capacitances of the first integrator 12 and the second integrator 13, and at the input sections of the D / A converters 20a and 20b for feeding back the output of the digital signal DOUT.

[0087] When the control circuit 14 gives an instruction to directly connect the polarity inversion signal flf, it repeats the operation 2^n times, for example, 4 times, 8 times, …, 128 times, 256 times, and then, as an instruction to perform cross connection, it inverts the polarity and repeats the operation 2^n times further. These processes are sequentially repeated.

[0088] As described above, by repeating the charge and discharge of the capacitor, the capacitive coupling amplifier 11 amplifies the analog input signals Vinp and Vinm, and the first integrator 12 integrates and outputs the output charge. After that, by inverting the connection using the polarity inversion circuits X1 to X4, it becomes possible to discharge the charge based on the offset input in the forward direction to the capacitor in the reverse direction. Then, the offsets sequentially accumulated by repeating the operation 2^n times can be canceled by repeating the operation 2^n times in the reverse direction, and the influence of the offset can be further reduced as compared with the configuration of the foregoing embodiment. In addition, according to the present embodiment, the degree of freedom of the sampling timing by the quantizer T1 (comparator) can be increased, and the setting time at this time can be ensured.

[0089] (Other Embodiments) The present invention is not limited to the foregoing embodiment, and for example, the following modifications or extensions are possible.

[0090] The configurations and functions of the foregoing plurality of embodiments may be combined. An aspect in which a part of the foregoing embodiment is omitted as long as the problem can be solved can also be regarded as an embodiment. In addition, any aspect conceivable within the scope not departing from the essence of the invention specified by the language described in the claims can also be regarded as an embodiment.

[0091] Although the present disclosure has been described in accordance with the foregoing embodiments, it is understood that the present disclosure is not limited to such embodiments and structures. The present disclosure includes various modification examples and modifications within an equivalent range. In addition, various combinations and forms, and further, other combinations and forms including one element, more than one element, or less than one element thereof, are also within the scope and spirit of the present disclosure.

Description of Reference Numerals

[0092] In the drawings, 11 is a capacitive coupling amplifier, 12 is a first integrator, 13 is a second integrator, 20a and 20b are D / A converters (second D / A converters), 220a and 220b are D / A converters (first D / A converters), 620a and 620b are D / A converters (third D / A converters), 30 is a temperature acquisition unit, T1 is a quantizer, and OP1 to OP3 indicate operational amplifiers (amplifiers).

Claims

1. A ΔΣ modulation type A / D converter for digitally converting an analog input signal, comprising: a capacitive coupling amplifier (11) configured to amplify the analog input signal, including sampling capacitors (C1a, C1b), feedback capacitors (C3a, C3b), and an amplifier (OP1); a first integrator (12) of a correlated double sampling type as a first-stage integrator provided after the capacitive coupling amplifier; the output of the capacitive coupling amplifier and the input of the sampling capacitors (C4a, C4b) of the first integrator are directly connected without passing through a switch; a second integrator (13) provided after the first integrator; a quantizer (T1) for quantizing the output value of the second integrator provided after the second integrator; a D / A converter (20a, 20b; 220a, 220b) for D / A converting the output of the quantizer and feeding back to either the capacitive coupling amplifier or the first integrator, or feeding back to any two of the capacitive coupling amplifier, the first integrator, and the second integrator.

2. The ΔΣ modulation type A / D converter according to claim 1, wherein the D / A converter (220a, 220b) is configured to feed back the output to the capacitive coupling amplifier.

3. The ΔΣ modulation type A / D converter according to claim 1, wherein the D / A converter includes a first D / A converter (220a, 220b) for feeding back the output of the quantizer to the capacitive coupling amplifier, and a second D / A converter (20a, 20b) for feeding back the output of the quantizer to the first integrator.

4. comprising a temperature acquisition unit (30) for acquiring temperature; the first D / A converter is configured to output a voltage (VPTAT) that increases with the temperature and feed back to the capacitive coupling amplifier, and the second D / A converter is configured to output a voltage (VCTAT) that decreases with the temperature and feed back to the first integrator; The ΔΣ modulation type A / D converter according to claim 3, wherein the temperature compensation amount is adjusted by adjusting the feedback amount by the second D / A converter.

5. The D / A converter includes the first D / A converter (220a, 220b), the second D / A converter (20a, 20b), and a third D / A converter (620a, 620b) for feeding back the output of the quantizer to the first integrator. The third D / A converter is configured to output a voltage (VCTAT) that decreases with the temperature and feedback it to the first integrator. The ΔΣ modulation type A / D conversion device according to claim 4, wherein the temperature compensation amount of the input signal is roughly adjusted by adjusting the feedback amount by the third D / A converter. **Claim 6** A feedback amount adjustment circuit (30a, 30b, 630a, 630b) that adjusts the feedback amount by the second D / A converter for each quantization result by the quantizer is provided. The ΔΣ modulation type A / D conversion device according to any one of claims 3 to 5, having a mechanism in which the output voltage of the second D / A converter is determined according to the feedback amount adjustment circuit. **Claim 7** The ΔΣ modulation type A / D conversion device according to any one of claims 1 to 6, which is constituted by CIF F or CIF B. **Claim 8** The ΔΣ modulation type A / D conversion device according to any one of claims 1 to 7, wherein an input unit for inputting the analog input signal and a stage subsequent to the output unit of the quantizer are configured to perform a chopping operation. **Claim 9** An input unit for inputting the analog input signal, before and after the feedback capacitances of the first integrator and the second integrator, an input unit of the D / A converter for feedbacking the output of the digital signal, and a stage subsequent to the output unit of the quantizer are configured to perform a chopping operation. The ΔΣ modulation type A / D conversion device according to claim 8. **Claim 10** Only the chopping of the stage subsequent to the output unit of the quantizer The ΔΣ modulation type A / D conversion device according to claim 9, which is configured to perform a chopping operation with a delay of one A / D conversion timing compared to the chopping in the input unit, before and after the feedback capacitances of the first integrator and the second integrator, and the input unit of the D / A converter.

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