Analog-to-digital conversion device and optical sensor

Abstract

To provide a Δ Σ type analog-digital converter and an optical sensor capable of suppressing an increase in sampling frequency, suppressing an increase in measurement time, and having high sensitivity.SOLUTION: An analog-to-digital conversion device includes a Δ Σ analog-to-digital converter that converts an analog signal into a digital signal having a pulse width corresponding to a magnitude of the analog signal, first to n-th delay circuits in which a first delay circuit delays the digital signal to generate a first delay signal, an i-th delay circuit delays an (i- 1) - th delay signal to generate an i-th delay signal, I is an integer of 2 or more and n or less, and n is an integer of 2 or more, and a signal processing circuit that acquires a signal value corresponding to the magnitude from the digital signal and the first to n-th delay signals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an analog-to-digital conversion device and an optical sensor. [Background technology]

[0002] Patent Document 1 discloses an analog-to-digital converter. In this analog-to-digital converter, a charging circuit is charged by an input current to increase an output signal. A comparison circuit sets a comparison signal to a high voltage when the output signal exceeds a reference voltage. A flip-flop samples the comparison signal, and sets a charge signal to a high voltage when the comparison signal is set to a high voltage. When the charge signal is set to a high voltage, a discharge circuit discharges the charging circuit to decrease the output signal. A counter counts the number of times the discharge circuit discharges. As a result, the counter outputs a digital value corresponding to the input current (paragraphs 0003-0010). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-75782 Summary of the Invention [Problem to be solved by the invention]

[0004] In most optical sensors, a current corresponding to the intensity of light received by a photodiode flows through the photodiode, and a ΔΣ analog-to-digital converter such as the analog-to-digital converter disclosed in Patent Document 1 generates a signal value corresponding to the current that flows.

[0005] Increasing the size of the photodiode is an effective way to increase the sensitivity of the optical sensor. However, the size of the photodiode has a large effect on the size of the optical sensor, so if the size of the photodiode is increased, the size of the optical sensor will increase significantly. For this reason, it is hoped that the sensitivity of a ΔΣ analog-to-digital converter can be increased without increasing the size of the photodiode.

[0006] Delta-sigma analog-to-digital converters perform oversampling, which contributes to increasing the sensitivity of the delta-sigma analog-to-digital converter. However, when the light sensor is placed on the back side of an organic light-emitting diode (OLED) display panel and used as an illuminance sensor, the need to shorten the measurement time negates the effect of oversampling.

[0007] Increasing the sampling frequency of a delta-sigma analog-digital converter is an effective way to increase its sensitivity. However, increasing the sampling frequency requires a large-scale circuit such as a phase-locked loop (PLL) circuit, which increases the current consumption of the delta-sigma analog-digital converter.

[0008] In addition, to increase the sensitivity of a ΔΣ analog-to-digital converter, it is also effective to calculate the arithmetic average of multiple signal values ​​to obtain the final signal value. However, if the arithmetic average of multiple signal values ​​is calculated to obtain the final signal value, the measurement time becomes longer and the obtained final signal value is limited to a multiple of the number of additions, which may result in large quantization errors.

[0009] One aspect of the present disclosure has been made in view of these problems, and aims to provide a ΔΣ analog-to-digital converter and an optical sensor that can, for example, prevent the sampling frequency from increasing and prevent the measurement time from becoming long, and have high sensitivity. [Means for solving the problem]

[0010] An analog-to-digital conversion device according to a first aspect of the present disclosure includes: a ΔΣ analog-to-digital converter that converts an analog signal into a digital signal having a pulse width corresponding to the magnitude of the analog signal; first to nth delay circuits that delay the digital signal to generate a first delayed signal and an i-th delay circuit that delays the (i-1)th delayed signal to generate the i-th delayed signal, where i is an integer greater than or equal to 2 and less than or equal to n, and n is an integer greater than or equal to 2; and a signal processing circuit that obtains signal values ​​corresponding to the magnitude from the digital signal and the first to nth delayed signals.

[0011] An optical sensor according to a second aspect of the present disclosure includes the analog-to-digital conversion device according to the first aspect of the present disclosure and a light detection element that converts light into the analog signal. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a circuit diagram of the optical sensor according to the first embodiment. [Figure 2] 1 is a diagram illustrating an example of the relationship between the magnitude of an analog signal input to a ΔΣ analog-digital converter provided in the optical sensor of the first embodiment and the waveform of a digital signal output from the Σ analog-digital converter. [Figure 3] 10 is a timing chart showing an example of waveforms of a clock signal and a digital signal input to a sampling circuit provided in the optical sensor of the reference example. [Figure 4] 4 is a timing chart showing an example of waveforms of a clock signal, a digital signal, and first to third delayed signals input to a sampling circuit provided in the photosensor of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same or equivalent elements are designated by the same reference numerals, and redundant description will be omitted.

[0014] 1. First embodiment 1.1 Optical sensor FIG. 1 is a circuit diagram of the optical sensor according to the first embodiment.

[0015] The optical sensor 1 of the first embodiment shown in FIG. 1 receives light L and generates a signal value SUM according to the intensity of the received light L.

[0016] 1, the optical sensor 1 includes a photodiode 11, an analog-to-digital converter 12, and a ground 13. The photodiode 11 includes an anode 11A and a cathode 11B. The analog-to-digital converter 12 includes an input terminal 12A.

[0017] The cathode 11B of the photodiode 11 is electrically connected to an input terminal 12A of the analog-to-digital conversion device 12. The anode 11A of the photodiode 11 is electrically connected to the ground 13.

[0018] The photodiode 11 receives light L. A current I1 corresponding to the intensity of the light L received by the photodiode 11 flows through the photodiode 11. The current I1 flows from the cathode 11B of the photodiode 11 to the anode 11A of the photodiode 11. As a result, the current I1 flows out from the input terminal 12A of the analog-to-digital conversion device 12. The current I1 flowing out from the input terminal 12A of the analog-to-digital conversion device 12 flows into the cathode 11B of the photodiode 11. The current I1 flowing into the cathode 11B of the photodiode 11 flows out from the anode 11A of the photodiode 11. The current flowing out from the anode 11A of the photodiode 11 flows into ground 13.

[0019] As a result, the photodiode 11 converts the received light L into an analog signal consisting of a current I1. The analog signal is input to an input terminal 12A of the analog-to-digital converter 12. The analog-to-digital converter 12 generates a signal value SUM according to the magnitude of the input analog signal.

[0020] The photodiode 11 is an example of a photodetector element. The photodiode 11 may be replaced with a photodetector element other than the photodiode 11.

[0021] 1.2 Analog-to-Digital Conversion Device As shown in FIG. 1, the analog-to-digital conversion device 12 includes a ΔΣ analog-to-digital converter 21, first to n-th delay circuits 221, 222, . . . , 22 n-1 ,twenty two n and a signal processing circuit 23. The ΔΣ analog-to-digital converter 21 has an input terminal 21A and an output terminal 21B. The first to n-th delay circuits 221, 222, . . . , 22 n-1 ,twenty two n are input terminals 22A1, 22A2, . . . , 22A n-1 ,22A n and output terminals 22B1, 22B2, . . . , 22B n-1 ,22B n The signal processing circuit 23 has an input terminal 23A and input terminals 23A1, 23A2, . . . , 23A. n-1 ,23A n n is an integer equal to or greater than 2. The first to n-th delay circuits 221, 222, . . . , 22 n-1 ,twenty two n is also called a delay line.

[0022] The input terminal 21A of the ΔΣ analog-to-digital converter 21 is electrically connected to the input terminal 12A of the analog-to-digital conversion device 12. The input terminal 22A1 of the first delay circuit 221 is electrically connected to the output terminal 21B of the ΔΣ analog-to-digital converter 21. i Input terminal 22A iis the (i-1)th delay circuit 22 i-1 Output terminal 22B i-1 The number i is an integer between 2 and n. That is, the second to n-th delay circuits 222,...,22 n-1 ,twenty two n Input terminals 22A2, , 22A n-1 ,22A n are the first to (n-1)th delay circuits 221, 222, . . . , 22 n-1 Output terminals 22B1, 22B2, . . ., 22B n-1 As a result, the first to n-th delay circuits 221, 222, . . . , 22 n-1 ,twenty two n are electrically connected in series. An input terminal 23A of the signal processing circuit 23 is electrically connected to an output terminal 21B of the ΔΣ analog-to-digital converter 21. The input terminals 23A1, 23A2, . . . , 23A of the signal processing circuit 23 are n-1 ,23A n are the first to n-th delay circuits 221, 222, . . . , 22 n-1 ,twenty two n Output terminals 22B1, 22B2, . . ., 22B n-1 ,22B n is electrically connected to

[0023] An analog signal input to the input terminal 12A of the analog-to-digital conversion device 12 is input to an input terminal 21A of the delta-sigma analog-to-digital converter 21. The delta-sigma analog-to-digital converter 21 converts the input analog signal into a digital signal SD. The digital signal SD obtained by conversion is output from an output terminal 21B of the delta-sigma analog-to-digital converter 21.

[0024] 2 is a diagram showing an example of the relationship between the magnitude of an analog signal input to a ΔΣ analog-digital converter provided in the optical sensor of Embodiment 1 and the waveform of a digital signal output from the Σ analog-digital converter. The waveform is shown as a graph with time on the horizontal axis and the voltage of the digital signal on the vertical axis.

[0025] As shown in FIG. 2, the voltage of the digital signal SD output from the ΔΣ analog-to-digital converter 21 changes over time and becomes either a first voltage VH or a second voltage VL. The digital signal SD has a pulse width that corresponds to the magnitude of the analog signal. The pulse width of the digital signal SD increases as the magnitude of the analog signal increases. In other words, the ratio of the time during which the voltage of the digital signal SD is at the first voltage VH to the measurement time increases as the magnitude of the analog signal increases.

[0026] 1 receives the digital signal SD output from the output terminal 12B of the analog-to-digital conversion device 12. The first delay circuit 221 delays the input digital signal SD by a delay amount D to generate a first delay signal SDL1. The generated first delay signal SDL1 is output from the output terminal 22B1 of the first delay circuit 221.

[0027] i-th delay circuit 22 i Input terminal 22A i The (i-1)th delay circuit 22 i-1 Output terminal 22B i-1 The (i-1)th delayed signal SDL output from i-1 is input to the i-th delay circuit 22 i is the input (i-1)th delayed signal SDL i-1 is delayed by a delay amount D to obtain the i-th delayed signal SDL i The i-th delay circuit 22 i Output terminal 22B i The generated ith delayed signal SDL i is output, where i is an integer between 2 and n. That is, the second to nth delay circuits 222,...,22 n-1 ,twenty two n Input terminals 22A2, , 22A n-1 ,22A n , 221, 222, . . . , 22 n-1 Output terminals 22B1, 22B2, . . ., 22B n-1The first to n-1th delayed signals SDL1, SDL2, . . . , SDL n-1 are input to the second to n-th delay circuits 222, . . . , 22 n-1 ,twenty two n are the input delayed signals SDL1, SDL2, . . . , SDL n-1 are delayed by a delay amount D to obtain the second to nth delayed signals SDL2, . . . , SDL n-1 ,SDL n The second to n-th delay circuits 222, . . . , 22 n-1 ,twenty two n Output terminals 22B2, 22B n-1 ,22B n The generated second to n-th delayed signals SDL2,...,SDL n-1 ,SDL n are output respectively.

[0028] The digital signal SD output from the output terminal 21B of the ΔΣ analog-to-digital converter 21 is input to the input terminal 23A of the signal processing circuit 23. n-1 ,23A n , 221, 222, . . . , 22 n-1 ,twenty two n Output terminals 22B1, 22B2, . . ., 22B n-1 ,22B n The first to nth delayed signals SDL1, SDL2, . . . , SDL n-1 ,SDL n The signal processing circuit 23 receives the input digital signal SD and the first to n-th delayed signals SDL1, SDL2, . . . , SDL n-1 ,SDL n A signal value SUM is generated according to the magnitude of the analog signal from the signal, and the generated signal value SUM is stored.

[0029] 1.3 Signal processing circuit As shown in FIG. 1, the signal processing circuit 23 includes a sampling circuit 31, an arithmetic circuit 32, and a generation circuit 33.

[0030] The sampling circuit 31 has an input terminal 31A, input terminals 31A1, 31A2, . . . , 31A n-1 ,31A n , output terminal 31B, output terminals 31B1, 31B2, . . . , 31B n-1 ,31B n and a clock terminal 31C.

[0031] The input terminal 31A of the sampling circuit 31 is electrically connected to the input terminal 23A of the signal processing circuit 23. The input terminals 31A1, 31A2, . . . , 31A of the sampling circuit 31 n-1 ,31A n are the input terminals 23A1, 23A2, . . . , 23A of the signal processing circuit 23, respectively. n-1 ,23A n The arithmetic circuit 32 is electrically connected to the output terminal 31B of the sampling circuit 31 and the output terminals 31B1, 31B2, . . . , 31B n-1 ,31B n is electrically connected to

[0032] The digital signal SD input to the input terminal 23A of the signal processing circuit 23 is input to the input terminal 31A of the sampling circuit 31. n-1 ,31A n , 23A1, 23A2, . . . , 23A3 of the signal processing circuit 23. n-1 ,23A n The first to nth delayed signals SDL1, SDL2,...,SDL n-1 ,SDL n are input to the sampling circuit 31. A clock signal SCLK is input to a clock terminal 31C of the sampling circuit 31. The sampling circuit 31 samples the voltage of the input digital signal SD and outputs the sampled voltage VS. The sampling circuit 31 samples the voltage of the input first to n-th delayed signals SDL1, SDL2, ..., SDLn-1 ,SDL n The voltages are sampled to obtain the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n The sampling circuit 31 outputs a sampled voltage VS from the output terminal 31B. The sampling circuit 31 outputs the sampled voltage VS from the output terminals 31B1, 31B2, . . . , 31B. n-1 ,31B n The first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n The sampling circuit 31 outputs the voltage of the digital signal SD and the first to n-th delay signals SDL1, SDL2, . . . , SDL n-1 ,SDL n The voltages of the first to n-th delayed signals SDL1, SDL2, . . . , SDL are sampled simultaneously in synchronization. The edge may be either a rising edge or a falling edge. n-1 ,SDL n are delayed from the digital signal SD by delays of 1×D, 2×D, . . . , (n-1)×D, and n×D, respectively. Therefore, the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n is equivalent to the voltage that would be output if the voltage of the digital signal SD were sampled at a timing delayed by 1×D, 2×D, . . . , (n-1)×D, or n×D from the timing at which the voltage of the digital signal SD was sampled.

[0033] The arithmetic circuit 32 receives the sampled voltage VS and the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n The arithmetic circuit 32 receives the sampled voltage VS and the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS nAt this time, the arithmetic circuit 32 generates a signal value SUM from the sampled voltage VS and the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n When each voltage included in the count is the first voltage VH, the count number is increased by 1, and when each voltage is the second voltage VL, the count number is maintained.

[0034] 3 is a timing chart showing an example of the waveforms of a clock signal and a digital signal input to a sampling circuit provided in the optical sensor of the reference example. In the timing chart of FIG. 3, time is plotted on the horizontal axis and voltage is plotted on the vertical axis.

[0035] 3, in the optical sensor of the reference example, the voltage of the digital signal SD is sampled at rising edges of the clock signal SCLK at times T1, T2, T3, T4, T5, and T6 within the measurement time. At times T1, T2, and T3, the voltage of the digital signal SD is a first voltage VH, and at times T4, T5, and T6, the voltage of the digital signal SD is a second voltage VL. Therefore, the count increases by 1 at each of the times T1, T2, and T3, and remains the same at each of the times T4, T5, and T6. Therefore, a count of 3 is obtained after the end of the measurement time.

[0036] 4 is a timing chart showing example waveforms of a clock signal, a digital signal, and first to third delayed signals input to a sampling circuit provided in the optical sensor of Embodiment 1. In the timing chart of FIG. 4, the horizontal axis represents time and the vertical axis represents voltage.

[0037] 4, in the optical sensor 1 of the first embodiment, the voltage of the digital signal SD and the voltages of the first to third delay signals SDL1, SDL2, and SDL3 are sampled at rising edges of the clock signal SCLK at times T1, T2, T3, T4, T5, and T6 within the measurement time. At times T1, T2, and T3, the voltage of the digital signal SD is the first voltage VH, and at times T4, T5, and T6, the voltage of the digital signal SD is the second voltage VL. Also, at times T2 and T3, the voltages of the first and second delay signals SDL1 and SDL2 are the first voltage VH, and at times T1, T4, T5, and T6, the voltages of the first and second delay signals SDL1 and SDL2 are the second voltage VL. Furthermore, at times T2, T3, and T4, the voltage of the third delay signal SDL3 is the first voltage VH, and at times T1, T5, and T6, the voltage of the third delay signal SDL3 is the second voltage VL. Therefore, at time T1, the count increases by 1, at times T2 and T3, the count increases by 4, at time T4, the count increases by 1, and at times T5 and T6, the count remains the same. Therefore, a count of 10 is obtained after the end of the measurement time.

[0038] The count number 10 obtained by the optical sensor 1 of the first embodiment is greater than the count number 3 obtained by the optical sensor of the reference example. This means that the sensitivity of the optical sensor 1 of the first embodiment is greater than the sensitivity of the optical sensor of the reference example. The count number 10 obtained by the optical sensor 1 of the first embodiment is not four times the count number 3 obtained by the optical sensor of the reference example. This means that a missing code that limits the count number obtained by the optical sensor 1 of the first embodiment to a multiple of four does not occur, and the quantization error of the optical sensor 1 of the first embodiment does not increase. This effect is obtained when the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS nis equivalent to the voltage sampled when the digital signal SD is sampled using a clock signal having a frequency n times the frequency of the clock signal SCLK. These effects can be obtained without increasing the sampling frequency or lengthening the measurement time.

[0039] The generation circuit 33 generates a clock signal SCLK. The delay D is 1 / n of the period of the clock signal SCLK. As a result, the sampled voltage VS and the first to n-th sampled voltages VS1, VS2, . . . , VS n-1 ,VS n can be made equivalent to the voltage sampled when the digital signal SD is sampled using a clock signal having a frequency n times the frequency of the clock signal SCLK, and can be made equivalent to the voltage sampled when the digital signal SD is sampled at a uniform period.

[0040] 1.4 Sampling circuit As shown in FIG. 1, the sampling circuit 31 includes a flip-flop 41 and first to n-th flip-flops 411, 412, . . . , 41 n-1 ,41 n The flip-flop 41 has an input terminal 41A, an output terminal 41B, and a clock terminal 41C. The first to n-th flip-flops 411, 412, . . . , 41 n-1 ,41 n are input terminals 41A1, 41A2, . . . , 41A n-1 ,41A n and output terminals 41B1, 41B2, . . . , 41B n-1 ,41B n and clock terminals 41C1, 41C2, . . . , 41C n-1 ,41C n Each is equipped with:

[0041] The input terminal 41A of the flip-flop 41 is electrically connected to the input terminal 31A of the sampling circuit 31. The first to n-th flip-flops 411, 412, . . . , 41 n-1 ,41 n Input terminals 41A1, 41A2, . . ., 41A n-1 ,41A n are the input terminals 31A1, 31A2, . . . , 31A of the sampling circuit 31, respectively. n-1 ,31A n The clock terminal 41C of the flip-flop 41 and the first to n-th flip-flops 411, 412, . . . , 41 n-1 ,41 n Clock terminals 41C1, 41C2, . . ., 41C n-1 ,41C n is connected to the clock terminal 31C of the sampling circuit 31. The output terminal 41B of the flip-flop 41 is electrically connected to the output terminal 31B of the sampling circuit 31. The first to n-th flip-flops 411, 412, . . . , 41 n-1 ,41 n Output terminals 41B1, 41B2, . . ., 41B n-1 ,41B n are the output terminals 31B1, 31B2, . . . , 31B of the sampling circuit 31, respectively. n-1 ,31B n is electrically connected to

[0042] The digital signal SD input to the input terminal 31A of the sampling circuit 31 is input to the input terminal 41A of the flip-flop 41. n-1 ,41 n Input terminals 41A1, 41A2, . . ., 41A n-1 ,41A n , 31A1, 31A2, . . . , 31A n-1 ,31A n The first to nth delayed signals SDL1, SDL2,...,SDL n-1 ,SDL nare input to the clock terminal 41C of the flip-flop 41 and the first to n-th flip-flops 411, 412, . . . , 41 n-1 ,41 n Clock terminals 41C1, 41C2, . . ., 41C n-1 ,41C n The clock signal SCLK input to the clock terminal 31C of the sampling circuit 31 is input to the flip-flop 41. The flip-flop 41 samples the voltage of the input digital signal SD at the timing of the edge of the input clock signal SCLK, and outputs the sampled voltage VS. The first to n-th flip-flops 411, 412, ..., 41 n-1 ,41 n are the first to n-th input delay signals SDL1, SDL2, . . . , SDL n-1 ,SDL n The voltages VS1, VS2, VS n-1 ,VS n The first to n-th flip-flops 411, 412, . . . , 41 output a sampled voltage VS from the output terminal 41B of the flip-flop 41. n-1 ,41 n Output terminals 41B1, 41B2, . . ., 41B n-1 ,41B n The first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n are output respectively.

[0043] Flip-flop 41 and first to n-th flip-flops 411, 412, . . . , 41 n-1 ,41 n are D-type flip-flops, etc.

[0044] 1.5 Arithmetic circuit The arithmetic circuit 32 includes a count circuit 51 , an accumulator circuit 52 , and a register 53 .

[0045] The count circuit 51 is connected to the output terminal 31B of the sampling circuit 31 and the output terminals 31B1, 31B2, . . . , 31B n-1 ,31B n is electrically connected to

[0046] The count circuit 51 receives the sampled voltage VS output from the output terminal 31B of the sampling circuit 31 and the voltages V1, V2, . . . , V3 of the sampling circuit 31. n-1 ,31B n The first to nth sampled voltages VS1, VS2, . . . , VS are output from n-1 ,VS n The count circuit 51 receives the value indicated by the sampled voltage VS and the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n The sum of the first to nth values ​​is counted. The sampled voltage VS and the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n The value indicated by each voltage included in is 1 when each voltage is the first voltage VH, and is 0 when each voltage is the second voltage VL. As a result, the sampled voltage VS and the first to nth sampled voltages VS1, VS2, . . . , VS n-1 ,VS n It is possible to count the number of voltages included in the voltage VH that are the first voltage VH.

[0047] The integrating circuit 52 integrates the total value TV over the measurement time to obtain a signal value SUM, and writes the obtained signal value SUM to the register 53. The written register 53 is read by other circuits.

[0048] 1.6 Delta-Sigma Analog-Digital Converter As shown in FIG. 1, the ΔΣ analog-to-digital converter 21 includes a subtractor 61, an integrator 62, a comparator 63, and a feedback circuit 64.

[0049] The subtractor 61 generates a residual signal SR by subtracting a subtraction signal formed by the current I2 from an analog signal formed by the current I1 by combining the current I2, which cancels out the current I1, with the current I1.

[0050] The integrator 62 integrates the generated residual signal SR to generate an integrated signal SI. The current I1 is a current that charges the integrator 62. The current I2 is a current that discharges the integrator 62.

[0051] The comparator 63 compares the voltage of the generated integrated signal SI with a reference voltage VREF to generate a digital signal SD. If the voltage of the integrated signal SI is higher than the reference voltage VREF, the comparator 63 sets the voltage of the digital signal SD to a first voltage VH. If the voltage of the integrated signal SI is lower than the reference voltage VREF, the comparator 63 sets the voltage of the digital signal SD to a second voltage VL. The first voltage VH is, for example, higher than the second voltage VL and greater than 0V. The second voltage VL is, for example, 0V.

[0052] The feedback circuit 64 samples the voltage of the digital signal SD to generate a sampled voltage VS, and generates a current I2 according to the generated voltage VS.

[0053] As shown in FIG. 1, the feedback circuit 64 includes a flip-flop 41, a pulse width modulation (PWM) circuit 72, a reference current source 73, and a switch 74.

[0054] The flip-flop 41 is shared by the sampling circuit 31 and the feedback circuit 64. The flip-flop 41 samples the voltage of the digital signal SD and outputs the sampled voltage VS.

[0055] The PWM circuit 72 PWM-modulates the generated voltage VS to generate a PWM-modulated voltage VPWM.

[0056] The reference current source 73 generates a reference current.

[0057] When the PWM-modulated voltage VPWM is the first voltage VH, the switch 74 closes the line from the reference current source 73 to the integrator 62, uses the current I2 as the reference current, and reduces the residual signal SR. When the PWM-modulated voltage VPWM is the second voltage VL, the switch 74 opens the line from the reference current source 73 to the integrator 62, makes the current I2 non-current, and does not reduce the residual signal SR. The PWM circuit 72 may be omitted, and the sampled voltage VS may be used as is instead of the PWM-modulated voltage VPWM.

[0058] As a result, the larger the magnitude of the analog signal, the longer the time that the voltage of the digital signal SD is at the first voltage VH, the shorter the time that the voltage of the digital signal SD is at the second voltage VL, and the larger the pulse width of the digital signal SD.

[0059] The clock signal SCLK is not input to the comparator 63. Therefore, the comparator 63 receives the voltage of the digital signal SD from the sampling circuit 31 and the first to n-th delay signals SDL1, SDL2, . . . , SDL n-1 ,SDL n The voltage of the integrated signal SI is compared with the reference voltage VREF without synchronizing with the sampling of the integrated signal SI, thereby generating the digital signal SD. This allows the timing of the rise of the voltage of the digital signal SD from the second voltage VL to the first voltage VH and the fall of the voltage of the digital signal SD from the first voltage VH to the second voltage VL to be offset from the timing of the edges of the clock signal SCLK, thereby preventing an increase in quantization error. [Explanation of symbols]

[0060] 1 light sensor 11 Photodiode 11A anode 11B cathode 12 Analog-to-digital conversion device 12A input terminal 12B output terminal 13 Grand 21 Delta-Sigma Analog-Digital Converter 21A input terminal 21B output terminal 221,222,···,22 n-1 ,twenty two n Delay Circuit 22A1, 22A2, , 22A n-1 ,22A n Input terminal 22B1, 22B2, , 22B n-1 ,22B n Output terminal 23 Signal processing circuit 23A input terminal 23A1, 23A2, , 23A n-1 ,23A n Input terminal 31 Sampling circuit 31A, 31A1, 31A2, , 31A n-1 ,31A n Input terminal 31B, 31B1, 31B2, 31B n-1 ,31B n Output terminal 31C Clock terminal 32 Arithmetic circuit 41,411,412,···,41 n-1 ,41 n flip flop 41A, 41A1, 41A2, , 41A n-1 ,41A n Input terminal 41B, 41B1, 41B2, , 41B n-1 ,41B n Output terminal 41C, 41C1, 41C2, , 41C n-1 ,41C n Clock terminal 51 Counting circuit 52 integrating circuit 53 Registers 61 Subtractor 62 Integrator 63 Comparator 72 Pulse Width Modulation (PWM) Circuit 73 Reference current source 74 Switch L light

Claims

1. a ΔΣ analog-to-digital converter for converting an analog signal into a digital signal having a pulse width corresponding to the magnitude of the analog signal; a first delay circuit delaying the digital signal to generate a first delayed signal, an i-th delay circuit delaying the (i-1)th delayed signal to generate an i-th delayed signal, first to n-th delay circuits, i being an integer between 2 and n, and n being an integer greater than or equal to 2; a signal processing circuit that acquires signal values ​​according to the magnitudes from the digital signal and the first to n-th delayed signals; An analog-to-digital conversion device comprising:

2. The signal processing circuit a sampling circuit that samples a voltage of the digital signal and outputs the sampled voltage, and samples voltages of the first to n-th delayed signals and outputs first to n-th sampled voltages, respectively; an arithmetic circuit that acquires the signal value from the sampled voltage and the first to nth sampled voltages; Equipped with 2. The analog-to-digital conversion device according to claim 1.

3. The sampling circuit a flip-flop that receives the digital signal and outputs the sampled voltage; first to n-th flip-flops each receiving the first to n-th delayed signals and outputting the first to n-th sampled voltages; Equipped with 3. The analog-to-digital conversion device according to claim 2.

4. the signal processing circuit includes a generation circuit that generates a clock signal; The sampling circuit samples the voltage of the digital signal and the voltages of the first to n-th delayed signals in synchronization with the timing of an edge of the clock signal.

3. The analog-to-digital conversion device according to claim 2.

5. the first delay circuit delays the digital signal by a delay amount that is 1 / n of the period of the clock signal; The i-th delay circuit delays the i-1th delay signal by the delay amount.

5. The analog-to-digital conversion device according to claim 4.

6. The arithmetic circuit comprises: a counting circuit that counts the sum of the value indicated by the sampled voltage and the first to nth values ​​indicated by the first to nth sampled voltages, respectively; an integrating circuit that integrates the sum over an integration measurement time to obtain the signal value; Equipped with 3. The analog-to-digital conversion device according to claim 2.

7. The ΔΣ analog-to-digital converter comprises: a subtractor that subtracts a subtraction signal from the analog signal to generate a residual signal; an integrator that integrates the residual signal to generate an integrated signal; a comparator that compares the voltage of the integrated signal with a reference voltage to generate the digital signal; a feedback circuit that samples a voltage of the digital signal to generate a sampled voltage and generates the subtraction signal according to the sampled voltage; Equipped with 7. An analog-to-digital conversion device according to claim 1.

8. the signal processing circuit includes a sampling circuit that samples a voltage of the digital signal to generate a sampled voltage, and samples voltages of the first to n-th delayed signals to generate first to n-th sampled voltages; The comparator generates the digital signal by comparing the voltage of the integrated signal with the reference voltage asynchronously with the sampling circuit sampling the voltage of the digital signal and the voltages of the first to n-th delayed signals.

8. An analog-to-digital conversion device according to claim 7.

9. An analog-to-digital conversion device according to any one of claims 1 to 6; a photodetector element that converts light into the analog signal; An optical sensor comprising:

Images