Dynamic-biased ring amplifier, biasing module and pipelined SAR ADC, chip
By introducing a dynamic bias circuit with a capacitor base into the ring amplifier, the bias circuit design is simplified, noise and power consumption are reduced, the problem of difficulty in balancing noise performance and power consumption in the prior art is solved, and the stability and robustness of the amplifier are improved.
CN121173235BActive Publication Date: 2026-03-24ANHUI UNIV
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Patent Information
- Application Number
- CN202511267877.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-05
- Publication Date
- 2026-03-24
- Estimated Expiration
- 2045-09-05
AI Technical Summary
Technical Problem
Existing dynamic bias ring amplifiers struggle to balance noise performance and power consumption, and their complex external bias control circuitry affects amplifier stability and PVT characteristics.
Method used
The ring amplifier employing dynamic bias includes the amplifier body, feedback loop, and bias unit. It utilizes capacitors to generate dynamic bias signals, and reduces the design difficulty and noise impact of the bias circuit through charge sharing, thus simplifying the circuit structure.
Benefits of technology
This improves the noise performance and stability of the ring amplifier, reduces power consumption, and decreases sensitivity to PVT variations, thereby enhancing the overall circuit robustness and signal-to-noise ratio.
✦ Generated by Eureka AI based on patent content.
Abstract
The application belongs to the field of integrated circuits, and particularly relates to a dynamic biasing ring amplifier, a biasing module, a pipeline SAR ADC and a chip. The circuit comprises an amplifier main body, a feedback loop and a biasing unit. The output end of the second stage of the amplifier main body comprises CMOS resistors P3 and N3. The biasing unit is used for synchronously generating a dynamic biasing signal V BL and V BH output to the gate of P3 and N3 according to the reset signal RST and the amplification signal AMP input in the feedback loop. The biasing unit comprises one PMOS tube P5, two NMOS tubes N5 and N6 and one capacitor C0. The source of P5 is connected to a power supply, the gate of P5 and N6 is connected to AMP; the drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as the output port of V BH . The source of N5 is connected to the ground, the gate of N5 is connected to RST, and the drain of N5 and N6 is connected to the lower plate of C0 and serves as the output port of V BL . The application solves the problems of the existing dynamic biasing ring amplifier, such as the difficulty in balancing the noise resistance performance and the circuit power consumption.
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