Dynamic-biased ring amplifier, biasing module and pipelined SAR ADC, chip

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a dynamic biasing ring amplifier, a biasing module, a pipeline SAR ADC and a chip. The circuit comprises an amplifier main body, a feedback loop and a biasing unit. The output end of the second stage of the amplifier main body comprises CMOS resistors P3 and N3. The biasing unit is used for synchronously generating a dynamic biasing signal V BL and V BH output to the gate of P3 and N3 according to the reset signal RST and the amplification signal AMP input in the feedback loop. The biasing unit comprises one PMOS tube P5, two NMOS tubes N5 and N6 and one capacitor C0. The source of P5 is connected to a power supply, the gate of P5 and N6 is connected to AMP; the drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as the output port of V BH . The source of N5 is connected to the ground, the gate of N5 is connected to RST, and the drain of N5 and N6 is connected to the lower plate of C0 and serves as the output port of V BL . The application solves the problems of the existing dynamic biasing ring amplifier, such as the difficulty in balancing the noise resistance performance and the circuit power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, specifically relating to a dynamically biased ring amplifier, a bias module for the ring amplifier, a pipelined SAR ADC, and a chip with computational functions. Background Technology

[0002] In recent years, with the development of 5G communication, optical communication, and high-speed interface circuits, the speed requirements for ADCs have become increasingly stringent, reaching tens of Gsps in some fields. However, the quantization accuracy requirements are generally below 10 bits. At the same time, according to Moore's Law, chip integration density is increasing year by year, costs are decreasing year by year, and product power consumption is decreasing year by year, gradually revealing the upper limit of traditional ADCs.

[0003] For chips used in the medical field, precision requirements are constantly increasing, along with demands for higher spurious-free dynamic range, higher linearity, and lower power consumption to meet the requirements of wearable devices. In the high-speed field, not only are higher speeds required, but also higher precision and improved matching between channels. Against this backdrop, hybrid ADC structures have been proposed. Among them, SAR ADCs, due to their low power consumption and good process compatibility, have led to numerous hybrid architectures based on SAR ADCs. The combination of pipelined ADCs and SAR ADCs, in particular, significantly reduces power consumption while increasing the conversion rate of SAR ADCs, thus becoming a focus of research in both academia and industry.

[0004] Amplifiers, as a crucial component of pipelined SAR ADCs, play a vital role in the overall pipelined SAR ADC design. However, commonly used amplifiers are increasingly failing to meet the design requirements of pipelined SAR ADCs. For example, while open-loop amplifiers offer fast response speeds, they exhibit significant nonlinearity, resulting in poor signal accuracy. Closed-loop OTA amplifiers, despite their strong stability, suffer from slow response speeds and high design complexity. These issues are the main reasons for the poor performance of pipelined SAR ADCs in high-speed, high-precision applications. Therefore, researchers have proposed various novel amplifiers, among which ring amplifiers are a representative solution. The performance of ring amplifiers is heavily influenced by external bias circuitry. For instance, dynamically biased ring amplifiers introduce additional noise when dynamically adjusting the bias current, potentially leading to a decrease in signal-to-noise ratio. Furthermore, dynamically biased ring amplifiers require additional bias control circuitry, increasing circuit design complexity and overall power consumption. Moreover, with the addition of external control circuitry, the amplifier's PVT characteristics deteriorate further. Summary of the Invention

[0005] To address the challenges of balancing noise immunity and power consumption in existing dynamic bias ring amplifiers, this invention provides a dynamically biased ring amplifier, a bias module for the ring amplifier, a pipelined SAR ADC, and a chip with logic operation functionality.

[0006] The technical solution provided by this invention is as follows:

[0007] A dynamically biased ring amplifier includes an amplifier body, a feedback loop, and a bias unit. The amplifier body comprises a first stage, a second stage, and a third stage connected in series; the output of the second stage includes CMOS resistors P3 and N3. The feedback loop adjusts the input signals and circuit topology at each port of the amplifier body according to the input reset signal RST and the amplified signal AMP, thereby switching the operating mode of the amplifier body.

[0008] The bias unit is used to synchronously generate a dynamic bias signal V output to the gates of P3 and N3 based on the input RST and AMP. BL and V BH The bias unit includes one PMOS transistor P5, two NMOS transistors N5 and N6, and a capacitor C0. The source of P5 is connected to the power supply, and the gates of P5 and N6 are connected to the AMP. The drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as V. BH The output port of N5. The source of N5 is grounded, the gate of N5 is connected to RST, and the drains of N5 and N6 are connected to the lower plate of C0 and serve as V. BL The output port.

[0009] As a further improvement of the present invention, the control logic of the bias unit is as follows:

[0010] (1) When RST is high and AMP is low, the bias unit is in a reset state. At this time, P5 and N5 are turned on and N6 is turned off, and the upper and lower plates of C0 begin to charge and discharge, thereby causing the V input to the amplifier body to be discharged. BL Reduced to GND, V BH Rise to VDD.

[0011] (2) When RST is low and AMP is high, the bias unit is in a balanced state. At this time, P5 and N5 are off, and N6 is on; charge transfer occurs between the upper and lower plates of C0, causing V input to the amplifier body to be reduced. BL Increase V BH The levels decrease, and eventually reach a state of equilibrium.

[0012] As a further improvement of the present invention, the first, second and third stages of the amplifier body are three inverters connected in series.

[0013] Specifically, the amplifier body consists of four PMOS transistors P1-P4 and four NMOS transistors N1-N4. The sources of P1, P2, and P4 are connected to the power supply; the sources of N1, N2, and N4 are grounded. The gates of P1 and N1 are connected and serve as the input terminal VIN of the amplifier body. The drains of P1 and N1 are connected to the gates of P2 and N2. The drains of P2 and N3 are connected to the source of P3 and the gate of P4; the drains of N2 and P3 are connected to the source of N3 and the gate of N4. The gates of P4 and N4 are connected and serve as the output terminal VOUT of the amplifier body. The gates of P3 and N3 serve as the output terminals VOUT and VOUT, respectively. BL and V BH The input port.

[0014] As a further improvement of the present invention, the bias unit outputs an adaptively adjusted dynamic bias signal V under different states. BL and V BH By matching the operating mode of the amplifier body and biasing P3 and N3, the dead zone voltage inside the ring amplifier is dynamically adjusted, thereby improving the noise of the overall ring amplifier structure.

[0015] As a further improvement of this invention, the feedback loop includes three capacitors C1-C3 and three transmission gates TG1-TG3. TG3 is connected between the input and output terminals of the amplifier body. The input terminal of the amplifier body is connected to one end of C1, the other end of C1 is connected to one end of C3, and the other end of C3 is connected to an external input. One end of TG2 is connected between C1 and C3, and the other end is connected to the common-mode voltage VCM. One end of C2 is connected between C1 and C3; the other end is connected to the output terminal of the amplifier body. One end of TG1 is connected to VCM, and the other end is connected to the output terminal of the amplifier body. The control terminals of TG1-TG3 are all connected to RST.

[0016] The present invention also includes a dynamically biased ring amplifier, comprising one biasing unit and two sets of amplifier bodies and feedback loops as described above. The two sets of amplifier bodies and feedback loops are arranged in a mirror image and serve as the in-phase and out-of-phase sides of the ring amplifier, respectively, thereby forming a differential two-port device.

[0017] The dynamic bias signal V output by the bias circuit BL and V BH Simultaneously connected to the CMOS resistors P3 and N3 of the corresponding amplifier bodies on the non-inverting and inverting sides.

[0018] This invention also includes a bias module for a ring amplifier, applied to a ring amplifier whose second-stage output includes CMOS resistors P3 and N3. The bias module for the ring amplifier is used to synchronously generate a dynamic bias signal V output to the gates of P3 and N3 based on a set of input inverting control signals. BL and VBH .

[0019] The bias module for the ring amplifier includes one PMOS transistor P5, two NMOS transistors N5 and N6, and a capacitor C0. The source of P5 is connected to the power supply, and the gates of P5 and N6 are connected to one of the input signals. The drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as V. BH The output port of N5; the source of N5 is grounded, the gate of N5 is connected to another input signal, and the drains of N5 and N6 are connected to the lower plate of C0 and serve as V. BL The output port.

[0020] As a further improvement of the present invention, in the bias module for the ring amplifier, the inverting control signals are denoted as RST and AMP. Then, when RST is high and AMP is low, V... BL From the equilibrium voltage decreasing to GND, V BH The voltage rises from the equilibrium voltage to VDD. When RST is low and AMP is high, V BL From GND, rise to the equilibrium voltage; V BH Reduce from VDD to the equilibrium voltage.

[0021] The present invention also includes a pipelined SAR ADC comprising a dynamically biased ring amplifier as described above. The common-mode input of the dynamically biased ring amplifier is connected to the output port of the preceding SAR ADC; the common-mode output of the dynamically biased ring amplifier is connected to the input port of the following SAR ADC.

[0022] As a further improvement of the present invention, the capacitance value of capacitor C2 in the feedback loop of the dynamically biased ring amplifier is equal to twice the base capacitance in the DAC array of the SAR ADC.

[0023] The present invention also includes a chip with logic operation function, which uses a pipelined SAR ADC as described above to quantize the results of logic operations.

[0024] The technical solution provided by this invention has the following beneficial effects:

[0025] This invention provides a dynamically biased ring amplifier that introduces a novel bias circuit, resulting in significant improvements in multiple aspects, including basic circuit performance, noise performance, power consumption, and stability. Compared to existing current biasing methods that use multiple MOSFETs to form a current mirror, this invention employs a capacitor-based dynamic biasing method through charge sharing, reducing the design complexity of the bias circuit. Existing current mirror-based biasing schemes are inherently more susceptible to PVT (Power Transmission Voltage), thus significantly impacting the overall PVT robustness of the ring amplifier. The capacitor-based voltage design of this invention effectively reduces the influence of the bias circuit on the overall amplifier's PVT robustness, achieving more stable gain despite changes in parameters such as temperature and process angle.

[0026] Furthermore, existing biasing schemes based on current mirrors are relatively complex and generate significant input noise during dynamic biasing, which affects the performance of the amplifier. In contrast, the scheme of this invention has a simpler circuit and does not generate significant noise during dynamic biasing, thus effectively reducing the degree to which the amplifier is affected by noise. Attached Figure Description

[0027] Figure 1 This is a circuit diagram of the dynamically biased ring amplifier provided in Embodiment 1 of the present invention.

[0028] Figure 2 This is a circuit diagram of a typical scheme of the amplifier body used in the dynamically biased ring amplifier in Embodiment 1 of the invention.

[0029] Figure 3 This is a circuit diagram of the bias unit in the dynamically biased ring amplifier of Embodiment 1 of the present invention.

[0030] Figure 4 This is a circuit diagram of the feedback loop in the dynamically biased ring amplifier of Embodiment 1 of the present invention.

[0031] Figure 5 This is a circuit diagram of a dynamically biased ring amplifier with differential dual ports provided in Embodiment 1 of the present invention.

[0032] Figure 6 This is a schematic diagram of the pipelined SAR ADC provided in Embodiment 3 of the present invention.

[0033] Figure 7 This is a test of the circuit invented in the experiment, showing the change curve of the output noise level as the input noise frequency gradually increases.

[0034] Figure 8 The simulation results were used to test the gain of the circuit of the present invention under different temperature conditions and process angles under the same input conditions in the experiment. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0036] Example 1

[0037] This embodiment provides a dynamically biased ring amplifier, such as... Figure 1 As shown, it includes: an amplifier body, a feedback loop, and a bias unit. The amplifier body and feedback loop can employ existing circuit designs. The amplifier body comprises a first stage, a second stage, and a third stage connected in series; the first, second, and third stages of the amplifier body are three inverters connected in series. The feedback loop is used to adjust the input signals and circuit topology at each port of the amplifier body according to the input reset signal RST and the amplified signal AMP, thereby switching the operating mode of the amplifier body. In practical applications, this ring amplifier can amplify the quantization margin of the first-stage SAR ADC output in a pipelined SRR ADC.

[0038] Specifically, in the amplifier body of the dynamically biased ring amplifier provided in this embodiment, the output terminal of the second stage needs to include CMOS resistors, which are denoted as P3 and N3 in this embodiment. For example, in a typical scheme of this embodiment, the amplifier body can adopt the following... Figure 2 The circuit shown consists of four PMOS transistors P1-P4 and four NMOS transistors N1-N4. The sources of P1, P2, and P4 are connected to the power supply; the sources of N1, N2, and N4 are grounded. The gates of P1 and N1 are connected and serve as the input terminal VIN of the amplifier. The drains of P1 and N1 are connected to the gates of P2 and N2. The drains of P2 and N3 are connected to the source of P3 and the gate of P4; the drains of N2 and P3 are connected to the source of N3 and the gate of N4. The gates of P4 and N4 are connected and serve as the output terminal VOUT of the amplifier. The gates of P3 and N3 serve as the output terminals VOUT and VOUT, respectively. BL and V BH The input ports are as follows: P1 and N1 form the inverter in the first stage; P2 and N2 form the inverter in the second stage; P3 and N3 serve as two CMOS resistors at the output of the second stage; and P4 and N4 form the inverter in the third stage.

[0039] It should be noted that, Figure 2 The circuit shown is only a basic example of the amplifier body in this embodiment. In other embodiments, the amplifier body may also use other types of three-stage ring amplifiers with CMOS resistors at the output of the second stage.

[0040] Based on this, the bias circuit introduced in this embodiment, consisting of only three MOS transistors, can generate a dynamically changing bias signal V using the existing two-phase non-overlapping clocks (AMP and RST clock signals, respectively) in the amplifier body. BL and V BH During the dynamic change of the output bias signal, the bias voltage biases the CMOS resistors inside the amplifier body, namely P3 and N3, thereby dynamically adjusting the dead zone voltage inside the ring amplifier to improve the noise of the overall ring amplifier structure.

[0041] Specifically, this embodiment provides a simple and efficient dynamic bias signal V that can synchronously generate outputs to the gates of P3 and N3 based on the input RST and AMP. BL and V BH The bias unit consists of one PMOS transistor P5, two NMOS transistors N5 and N6, and a capacitor C0. For example... Figure 3 As shown, the source of P5 is connected to the power supply, and the gates of P5 and N6 are connected to the AMP; the drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as V. BH The output port of N5. The source of N5 is grounded, the gate of N5 is connected to RST, and the drains of N5 and N6 are connected to the lower plate of C0 and serve as V. BL The output port.

[0042] Analysis of the circuit's working principle reveals that the control logic of the bias unit in the dynamically biased ring amplifier of this embodiment is as follows:

[0043] (1) When the reset signal RST is high and the amplification signal AMP is low, the bias unit is in the reset state. At this time, P5 and N5, which act as reset transistors, are turned on, and N6, which acts as a balance transistor, is turned off. The upper and lower plates of C0 begin to charge and discharge. The upper plate of capacitor C0 is connected to the power supply VDD for charging, which causes the voltage of the upper plate to rise rapidly to VDD and serve as the bias signal V. BH Meanwhile, the upper plate of capacitor C0 discharges at the ground terminal VSS, causing the voltage of the lower plate to drop rapidly to GND, which then serves as the bias signal V. BL .

[0044] (2) When RST is low and AMP is high, the bias unit is in a balanced state. At this time, P5 and N5 are off and N6 is on; therefore, the charging and discharging channels corresponding to the upper and lower plates of capacitor C0 are closed, while the charge transfer channel between the upper and lower plates is opened. Therefore, charge transfer occurs between the upper and lower plates of C0, and the V input to the amplifier body is reduced. BL Increase V BH The voltage decreases, and the two eventually reach an equilibrium. In practical applications, considering the charge loss caused by the device itself, VBL and V BH The voltage will reach a stable voltage slightly below 1 / 2 VDD.

[0045] Further integration Figure 2 and Figure 3 Circuit principle analysis shows that the bias unit in this embodiment outputs an adaptively adjusted dynamic bias signal V under different states. BL and V BH It can match the operating mode of the amplifier body and adaptively bias P3 and N3 to dynamically adjust the dead-time voltage inside the ring amplifier. For example, when the dynamically changing V BH and V BL When applied to the gates of P3 and N3, the drain voltage Vbp of transistor P3 increases and the drain voltage Vbn of transistor Mn3 decreases, thereby increasing the dead zone voltage Vdz inside the amplifier (where Vdz = Vbp - Vbn). Therefore, the bias circuit introduced in the amplifier body in this embodiment can reduce the impact of noise in the input signal on the overall output of the circuit while ensuring output accuracy.

[0046] Furthermore, considering that the bias circuit provided in this embodiment can achieve the aforementioned precise biasing effect using only three CMOS transistors and one capacitor, the power consumption of the circuit can be significantly reduced. Moreover, the noise generated by variations in the bias circuit is also less than the noise generated by existing structures based on external bias current modules, thus further reducing the noise impact on the ring amplifier.

[0047] In the dynamically biased ring amplifier provided in this embodiment, the feedback loop can adopt a scheme including three capacitors C1~C3 and three transmission gates TG1~TG3. Specifically, as shown... Figure 4 As shown, transmission gate TG3 is connected between the input and output terminals of the amplifier body. The input terminal of the amplifier body is connected to one end of C1, the other end of C1 is connected to one end of C3, and the other end of C3 is connected to an external input. One end of TG2 is connected between C1 and C3, and the other end is connected to the common-mode voltage VCM. One end of C2 is connected between C1 and C3; the other end is connected to the output terminal of the amplifier body. One end of TG1 is connected to VCM, and the other end is connected to the output terminal of the amplifier body. The control terminals of TG1 to TG3 are all connected to RST.

[0048] Therefore, in reset mode, RST=1; at this time, the input and output terminals of the amplifier main body (RAMP), as well as the two ends of C1 and C2, are all connected to the common-mode voltage VCM. In amplification mode, RST=0; at this time, the input terminal of the amplifier main body is connected to an external input, and C1 and C2 are connected in series between the input and output terminals of the amplifier main body.

[0049] In a further improved version of this embodiment, a method such as... is also provided. Figure 5 The dynamically biased ring amplifier is shown. The circuit includes a bias unit as described above, and two sets of amplifier bodies and feedback loops as described above. The two sets of amplifier bodies and feedback loops are arranged in a mirror image and serve as the non-inverting and inverting sides of the ring amplifier, respectively, thus forming a differential two-port device.

[0050] The dynamic bias signal V output by the bias circuit BL and V BH Simultaneously connected to the CMOS resistors P3 and N3 of the corresponding amplifier bodies on the non-inverting and inverting sides.

[0051] Example 2

[0052] Building upon the technology of Embodiment 1, this embodiment further provides a bias module for a ring amplifier, which is applied in a ring amplifier whose output terminals include CMOS resistors P3 and N3 in the second stage. This bias module is used to synchronously generate a dynamic bias signal V output to the gates of P3 and N3 based on the input RST and AMP. BL and V BH .

[0053] The bias module for the ring amplifier provided in this embodiment is the bias unit in the dynamically biased ring amplifier in Embodiment 1. This embodiment can be designed and manufactured as an independent circuit module. This circuit module includes a power supply terminal VDD, a ground terminal VSS, two control signal input terminals RST and AMP, and two output terminals V... BL and V BH .

[0054] The signal modulation logic of the bias module for this ring amplifier is as follows: when RST is high and AMP is low, V BL From the equilibrium voltage decreasing to GND, V BH The voltage rises from the equilibrium voltage to VDD. When RST is low and AMP is high, V BL From GND, rise to the equilibrium voltage; V BH The voltage is reduced from VDD to the balancing voltage. It should be noted that when the ring amplifier uses the bias module as a separate functional module, RST and AMP here are simply two inverted input control signals of the circuit, not the narrowly defined reset and amplification signals as in Example 1.

[0055] Specifically, in the bias module for the ring amplifier provided in this embodiment, the circuit includes one PMOS transistor P5, two NMOS transistors N5 and N6, and a capacitor C0. The source of P5 is connected to the power supply, and the gates of P5 and N6 are connected to the AMP. The drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as V. BH The output port of N5; the source of N5 is grounded, the gate of N5 is connected to RST, and the drains of N5 and N6 are connected to the lower plate of C0 and serve as V. BL The output port.

[0056] Example 3

[0057] Based on the excellent performance of the dynamically biased ring amplifier provided in Embodiment 1, this embodiment further provides a pipelined SAR ADC, such as... Figure 6 As shown, it employs a dynamically biased ring amplifier with differential ports, as in Embodiment 1. The common-mode input of the dynamically biased ring amplifier is connected to the output port of the preceding SAR ADC; while the common-mode output is connected to the input port of the following SAR ADC. The capacitance value of capacitor C2 in the feedback loop of the dynamically biased ring amplifier is equal to twice the base capacitance in the SAR ADC's DAC array.

[0058] The pipelined SAR ADC provided in this embodiment can further improve the noise immunity and reduce the power consumption of the circuit while ensuring the quantization rate. Its performance is excellent. Furthermore, this embodiment also includes a chip with computational functions, which uses the aforementioned pipelined SAR ADC to quantize the results of logical operations. This chip can include various in-memory computing chips (CIMs) or other types of arithmetic logic units (ALUs).

[0059] Performance testing

[0060] To verify the performance of the dynamically biased ring amplifier provided by this invention, technicians simulated and tested the circuit scheme.

[0061] 1. Noise reduction performance

[0062] This experiment first tested the change in the output noise level of the dynamically biased ring amplifier of this invention under the condition of continuously increasing input noise frequency, and obtained the following results: Figure 7 The results of the noise simulation experiment are shown.

[0063] analyze Figure 7 The experimental results show that when the input noise frequency changes from low to high, the output noise level decreases from below 9nV. 2 The level gradually decreases, and compared to commonly used self-biased ring amplifiers, it is generally higher than 10nV.2 The noise level of this invention is low throughout the entire working process, thus this invention has good noise reduction performance.

[0064] The reason why this invention can achieve the above performance is that the solution abandons the original complex bias circuit scheme of dynamic bias ring amplifier, thus introducing less noise during dynamic biasing.

[0065] 2. PVT simulation

[0066] This experiment further simulates and tests the circuit scheme provided by this invention under different temperatures and process angles. This includes testing the change in gain as a function of response time under three process angles (SS, FF, and TT) and three temperature conditions (-40℃, 27℃, and 120℃), yielding the following results: Figure 8 The curve shown

[0067] analyze Figure 8 The data reveals that because the ring amplifier provided by this invention employs a capacitor-dominated bias unit, the gain provided by the closed-loop circuit can quickly stabilize near the expected value under different process angles and temperatures, demonstrating excellent circuit stability. This circuit overcomes the problem of significant PVT influence in existing solutions.

[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dynamically biased ring amplifier, characterized in that, It includes: The amplifier body comprises a first stage, a second stage, and a third stage connected in series; the output terminal of the second stage includes CMOS resistors P3 and N3. The feedback loop is used to adjust the input signals and circuit topology of each port of the amplifier body according to the input reset signal RST and amplification signal AMP, thereby switching the operating mode of the amplifier body. The biasing unit is used to synchronously generate a dynamic bias signal V output to the gates of P3 and N3 based on the input RST and AMP. BL and V BH The bias unit includes one PMOS transistor P5, two NMOS transistors N5 and N6, and a capacitor C0; the source of P5 is connected to the power supply, and the gates of P5 and N6 are connected to the AMP; the drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as V. BH The output port of N5; the source of N5 is grounded, the gate of N5 is connected to RST, and the drains of N5 and N6 are connected to the lower plate of C0 and serve as V. BL The output port.

2. The dynamically biased ring amplifier as described in claim 1, characterized in that, The control logic of the bias unit is as follows: When RST is high and AMP is low, the bias unit is in a reset state; at this time, P5 and N5 are turned on and N6 is turned off, and the upper and lower plates of C0 begin to charge and discharge, thereby causing V input to the amplifier body to... BL Reduced to GND, V BH Rise to VDD; When RST is low and AMP is high, the bias unit is in a balanced state. At this time, P5 and N5 are off, and N6 is on; charge transfer occurs between the upper and lower plates of C0, causing V input to the amplifier body to... BL Increase V BH The levels decrease, and eventually reach a state of equilibrium.

3. The dynamically biased ring amplifier as described in claim 2, characterized in that: The amplifier body consists of three inverters connected in series, forming the first, second, and third stages. The amplifier body consists of four PMOS transistors P1-P4 and four NMOS transistors N1-N4. The sources of P1, P2, and P4 are connected to the power supply; the sources of N1, N2, and N4 are grounded; the gates of P1 and N1 are connected and serve as the input terminal VIN of the amplifier body; the drains of P1 and N1 are connected to the gates of P2 and N2; the drains of P2 and N3 are connected to the source of P3 and the gate of P4; the drains of N2 and P3 are connected to the source of N3 and the gate of N4; the gates of P4 and N4 are connected and serve as the output terminal VOUT of the amplifier body; the gates of P3 and N3 serve as the output terminals VOUT and VOUT, respectively. BL and V BH The input port.

4. The dynamically biased ring amplifier as described in claim 3, characterized in that: The bias unit outputs an adaptively adjusted dynamic bias signal V under different states. BL and V BH By matching the operating mode of the amplifier body and biasing P3 and N3, the dead zone voltage inside the ring amplifier is dynamically adjusted, thereby improving the noise of the overall ring amplifier structure.

5. The dynamically biased ring amplifier as described in claim 1, characterized in that: The feedback loop includes three capacitors C1 to C3 and three transmission gates TG1 to TG3. TG3 is connected between the input and output terminals of the amplifier body. The input terminal of the amplifier body is connected to one end of C1, the other end of C1 is connected to one end of C3, and the other end of C3 is connected to an external input. One end of TG2 is connected between C1 and C3, and the other end is connected to the common-mode voltage VCM. One end of C2 is connected between C1 and C3, and the other end is connected to the output terminal of the amplifier body. One end of TG1 is connected to VCM, and the other end is connected to the output terminal of the amplifier body. The control terminals of TG1 to TG3 are all connected to RST.

6. A dynamically biased ring amplifier, characterized in that: It includes a bias unit in a dynamically biased ring amplifier as described in any one of claims 1-5, and two sets of amplifier bodies and feedback loops in a dynamically biased ring amplifier as described in any one of claims 1-5; the two sets of amplifier bodies and feedback loops are arranged in a mirror image and serve as the in-phase side and out-of-phase side of the ring amplifier, respectively, thereby forming a differential two-port device. The dynamic bias signal V output by the bias circuit BL and V BH Simultaneously connected to the CMOS resistors P3 and N3 of the corresponding amplifier bodies on the non-inverting and inverting sides.

7. A bias module for a ring amplifier, characterized in that: It is applied to a ring amplifier whose output terminal includes CMOS resistors P3 and N3; the ring amplifier uses a bias module to synchronously generate a set of dynamic bias signals V based on the input inverting control signal. BL and V BH ; The bias module for the ring amplifier includes one PMOS transistor P5, two NMOS transistors N5 and N6, and a capacitor C0; the source of P5 is connected to the power supply, and the gates of P5 and N6 are connected to one of the input signals; the drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as V. BH The output port of N5; the source of N5 is grounded, the gate of N5 is connected to another input signal, and the drains of N5 and N6 are connected to the lower plate of C0 and serve as V. BL The output port.

8. The bias module for a ring amplifier as described in claim 7, characterized in that: Let the inverting control signals be RST and AMP. Then, when RST is high and AMP is low, V BL From the equilibrium voltage decreasing to GND, V BH The voltage rises from the equilibrium voltage to VDD; when RST is low and AMP is high, V BL From GND, rise to the equilibrium voltage; V BH Reduce from VDD to the equilibrium voltage.

9. A pipelined SAR ADC, characterized in that: It includes a dynamically biased ring amplifier as described in claim 7; the common-mode input of the dynamically biased ring amplifier is connected to the output port of the preceding SAR ADC; and the common-mode output of the dynamically biased ring amplifier is connected to the input port of the following SAR ADC.

10. A chip with computing function, characterized in that, It uses the pipelined SAR ADC as described in claim 9 to quantize the calculation results.

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