Cmos cascode radio frequency amplifier with temperature and process variation compensation

Abstract

The application belongs to the technical field of radio frequency amplifiers, and specifically discloses a CMOS common-source common-gate radio frequency amplifier with temperature and process deviation compensation, which comprises a bias circuit and an amplification stage circuit; the bias circuit adopts a temperature and process deviation compensation bias circuit; when the ambient temperature changes, the bias circuit can collect the real-time temperature of an amplifying tube and generate a new bias voltage, so that the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the temperature change is reduced; similarly, when the process parameter distribution deviation occurs in different regions of a wafer during the chip manufacturing process, the same chip bias circuit and the amplifying tube region of the amplification stage circuit are the same, the same process deviation is generated, the bias circuit can generate a new bias voltage according to the process deviation, the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the process deviation is reduced. The application is suitable for a low-noise amplifier in a WiFi radio frequency front-end module.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency amplifier technology and relates to a CMOS common-source cascode radio frequency amplifier with temperature and process deviation compensation. Background Technology

[0002] The WiFi RF front-end module is one of the important modules in a WiFi transceiver system. It mainly consists of a power amplifier, a low-noise amplifier, and a switching circuit. To reduce costs and improve integration, the low-noise amplifier and switching circuit are generally fabricated using CMOS technology, which offers low cost, high integration, and good compatibility. The CMOS common-source cascode RF amplifier, with its high gain, wide bandwidth, low noise, and small area, has become a common structure for low-noise amplifiers in WiFi RF front-end modules.

[0003] Improving the stability and reliability of WiFi transceiver systems is a current research hotspot, which requires WiFi RF front-end modules to have stable power consumption and gain characteristics.

[0004] Traditional WiFi RF front-end low-noise amplifiers (LNAs) often use resistor dividers for bias circuits. When temperature changes or process parameters deviate, the bias voltage cannot be modulated, causing large fluctuations in amplifier gain and power consumption with temperature. The bias voltage's inability to adapt to process deviations leads to poor chip gain consistency. Some WiFi RF front-end LNAs possess gain temperature compensation features, but their temperature compensation coefficient is fixed, making it impossible to dynamically acquire the real-time temperature of the LNA's transistors. Furthermore, traditional temperature-compensated bias circuits mostly lack process parameter deviation compensation features.

[0005] Chinese invention patent CN 109716648 B discloses a common-source cascode amplifier bias circuit, which utilizes a common-source cascode reference circuit to bias the final stage of the amplifier under the control of a closed-loop bias control circuit. The closed-loop bias control circuit ensures that the current in the common-source cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage of the final stage of the amplifier. However, this bias voltage cannot vary with temperature and process parameters, thus failing to compensate for the amplifier's power consumption and current, making it unsuitable for applications requiring high stability and reliability. Summary of the Invention

[0006] The purpose of this invention is to provide a CMOS common-source cascode RF amplifier with temperature and process deviation compensation, which can sense the temperature characteristics of the amplifier tube in real time and dynamically adjust the bias voltage to reduce amplifier gain and power consumption fluctuations; at the same time, it can dynamically adjust the bias voltage according to process parameter deviations to reduce amplifier gain and power consumption fluctuations caused by process deviations.

[0007] To achieve the above objectives, the technical solution adopted by this invention is as follows:

[0008] A CMOS common-source cascode RF amplifier with temperature and process deviation compensation includes a bias circuit and an amplification stage circuit.

[0009] The amplifier stage circuit includes a common-source transistor, a common-gate transistor, a choke inductor, an input matching network, and an output matching network;

[0010] The drain of the common source transistor is connected to the source of the common gate transistor, the source of the common source transistor is grounded, and the gate of the common source transistor is connected to the input matching network on one hand and to the first bias voltage output terminal of the bias circuit on the other hand.

[0011] The drain of the common-gate transistor is connected to the power supply voltage on one hand through a choke inductor, and on the other hand to the output matching network; the gate of the common-gate transistor is connected to the second bias voltage output terminal of the bias circuit.

[0012] The bias circuit consists of a first bias branch and a second bias branch;

[0013] The first bias branch includes a first current source, a first resistor, and a second resistor connected in series, with one end of the second resistor grounded; it also includes a first bias transistor and a second bias transistor.

[0014] Both the first bias transistor and the second bias transistor are MOSFETs; one end of the first resistor is connected to the output terminal of the first current source and the drain of the second bias transistor on the other side; the source of the second bias transistor is connected to the drain of the first bias transistor; and the source of the first bias transistor is grounded; the gate of the first bias transistor is connected to the common terminal of the first resistor and the second resistor on one side, and serves as the first bias voltage output terminal of the bias circuit on the other side.

[0015] The second bias branch includes a second current source, a third resistor, a fourth resistor, and a MOS transistor unit connected in series in the form of diodes; the MOS transistor unit is composed of the first to nth MOS transistors connected in series, the drain of the first MOS transistor is connected to the fourth resistor, the source of the (m-1)th MOS transistor is connected to the drain of the mth MOS transistor, and the source of the nth MOS transistor is grounded; where n≥2, m∈[2,n];

[0016] The gate of the second bias transistor is connected to the common terminal of the third and fourth resistors on one hand, and serves as the second bias voltage output terminal of the bias circuit on the other hand.

[0017] The first current source is a temperature-independent current source, and the second current source is a positive temperature coefficient current source.

[0018] As a limitation, the first bias transistor and the second bias transistor are arranged around the common source transistor and the common gate transistor with the minimum process spacing during layout.

[0019] As a second limitation, the current in the amplifier stage circuit is expressed as:

[0020]

[0021] Where, μ n C ox Indicates the process parameters of the common source tube. V represents the width-to-length ratio of a common-source transistor. G1 This represents the first bias voltage, V. TH V represents the threshold voltage of the common-source transistor; λ represents the channel modulation coefficient of the common-source transistor. DS This represents the drain-source voltage of a common-source transistor;

[0022] The gain of the amplifier stage circuit is expressed as:

[0023]

[0024] Among them, g m R represents the transconductance of the amplifier stage circuit; out V represents the output equivalent resistance of the amplifier stage circuit; GS This represents the gate-source voltage of a common-source transistor;

[0025] The current in the first bias branch is expressed as:

[0026]

[0027] Where R2 represents the resistance value of the second resistor; I MB1 This represents the current flowing through the first bias transistor; V DS1 This represents the drain-source voltage of the first bias transistor.

[0028] The present invention, by adopting the above-described technical solution, achieves the following technical advancements compared to existing technologies:

[0029] (1) In this invention, the bias circuit adopts a temperature and process deviation compensation bias circuit. When the ambient temperature changes, the bias circuit can collect the real-time temperature of the common source transistor M1 and the common gate transistor M2 and generate a new bias voltage to realize the dynamic adjustment of the bias state of the amplifier stage circuit and reduce the fluctuation of its gain and power consumption with temperature changes. Similarly, when the process parameter distribution deviation occurs in different areas of the wafer during chip manufacturing, the bias circuit of the same chip and the amplifier stage circuit have the same amplification transistor area and the same process deviation. The bias circuit can generate a new bias voltage according to the process deviation to realize the dynamic adjustment of the bias state of the amplifier stage circuit and reduce the fluctuation of amplifier gain and power consumption with process deviation.

[0030] (2) The second bias voltage V in this invention G2The voltage is temperature-independent and does not change with temperature. The first bias voltage is V. G1 It can change with the amplifier's operating temperature and process parameter bias; when the amplifier's operating temperature changes or the process parameters deviate, the first bias voltage V generated by the first bias branch X1 will change. G1 It will change accordingly, compensating for the gain and power consumption of the amplifier stage circuit in the opposite direction, forming a negative feedback effect, thereby reducing the fluctuation range of the gain and power consumption of the amplifier stage circuit with temperature or process parameters.

[0031] (3) In the first bias branch of the present invention, the first bias tube and the second bias tube are arranged close to the common source tube and the common grid tube of the amplification stage in the layout to ensure the accuracy of temperature acquisition in the amplification area.

[0032] (4) When applied to a WiFi transceiver system, this invention can improve the stability and reliability of the system.

[0033] This invention belongs to the field of radio frequency amplifier technology. It can simultaneously compensate for temperature and process deviations, reduce amplifier gain and power consumption fluctuations, and reduce the fluctuations in amplifier gain and power consumption due to process deviations. Attached Figure Description

[0034] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0035] In the attached diagram:

[0036] Figure 1 This is a circuit schematic diagram of an embodiment of the present invention;

[0037] Figure 2 This is a circuit schematic diagram of the amplification stage circuit according to an embodiment of the present invention;

[0038] Figure 3 This is a circuit diagram of the bias circuit according to an embodiment of the present invention;

[0039] Figure 4 This is a block diagram illustrating the working principle of the bias circuit temperature compensation in an embodiment of the present invention.

[0040] Figure 5 This is a block diagram illustrating the working principle of bias circuit process parameter compensation in an embodiment of the present invention.

[0041] Figure 6 The first bias voltage V in this embodiment of the invention G1 A graph showing how temperature changes the temperature.

[0042] Figure 7 This is a comparison curve of the current change of the amplifier stage circuit with and without the bias circuit in an embodiment of the present invention.

[0043] Figure 8 This is a graph showing the gain of the amplifier stage circuit versus temperature in an embodiment of the present invention without a bias circuit.

[0044] Figure 9 This is a graph showing the gain of the amplifier stage circuit versus temperature when a bias circuit is present in an embodiment of the present invention.

[0045] Figure 10 The first bias voltage V in the embodiment of the present invention G1 A graph showing how process parameters change;

[0046] Figure 11 This is a comparison curve of the current of the amplifier stage circuit with and without bias circuit and the process parameters in the embodiments of the present invention.

[0047] Figure 12 This is a graph showing the gain of the amplifier stage circuit as a function of process parameters when there is no bias circuit in this embodiment of the invention.

[0048] Figure 13 This is a graph showing the gain of the amplifier stage circuit as a function of process parameters when a bias circuit is present in an embodiment of the present invention. Detailed Implementation

[0049] The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0050] The embodiment features a CMOS cascode RF amplifier with temperature and process deviation compensation.

[0051] like Figure 1 As shown, this embodiment includes a bias circuit and an amplifier stage circuit; the amplifier stage circuit adopts a CMOS common-source common-gate amplifier stage circuit.

[0052] like Figure 1 and Figure 2 As shown, the amplifier stage circuit includes a common-source transistor M1, a common-gate transistor M2, a choke inductor L1, an input matching network, and an output matching network. The drain of the common-source transistor M1 is connected to the source of the common-gate transistor M2, and the source of the common-source transistor M1 is grounded. The gate of the common-source transistor M1 is connected to the input matching network on one hand, and to the first bias voltage V of the bias circuit on the other hand through the fifth resistor R5. G1 The output terminals are connected; the drain of the common-gate transistor M2 is connected to the power supply voltage VCC through the choke inductor L1 and to the output matching network on the other hand; the gate of the common-gate transistor M2 is connected to the second bias voltage V through the sixth resistor R6. G2 The output terminal is connected, and on the other hand, it is grounded through the first capacitor.

[0053] like Figure 1 and Figure 3 As shown, the bias circuit consists of a first bias branch X1 and a second bias branch X2. The first bias branch X1 includes a first current source, a first resistor R1, and a second resistor R2 connected in series, with one end of the second resistor R2 grounded. It also includes a first bias transistor MB1 and a second bias transistor MB2. Both the first bias transistor MB1 and the second bias transistor MB2 are MOSFETs.

[0054] One end of the first resistor R1 is connected to the output terminal of the first current source and the drain of the second bias transistor MB2 on the other side. The source of the second bias transistor MB2 is connected to the drain of the first bias transistor MB1, and the source of the first bias transistor MB1 is grounded. The gate of the first bias transistor MB1 is connected to the common terminal of the first resistor R1 and the second resistor R2 on one side, and serves as the first bias voltage V of the bias circuit on the other side. G1 Output terminal.

[0055] The second bias branch X2 includes a second current source, a third resistor R3, a fourth resistor R4, and a MOS transistor unit connected in series in the form of diodes. The MOS transistor unit consists of a series-connected first to nth MOS transistors. The drain of the first MOS transistor is connected to the fourth resistor R4, the source of the (m-1)th MOS transistor is connected to the drain of the mth MOS transistor, and the source of the nth MOS transistor is grounded. Where n ≥ 2, m ∈ [2, n]. In actual design, n can be determined based on the second bias voltage V. G2 The actual required value is adjusted. In the MOS transistor unit, the drain of each MOS transistor is connected to its own gate.

[0056] The gate of the second bias transistor MB2 is connected to the common terminal of the third resistor R3 and the fourth resistor R4 on one hand, and serves as the second bias voltage V of the bias circuit on the other hand. G2 Output terminal.

[0057] In this embodiment, the first current source is a temperature-independent current source, and the second current source is a positive temperature coefficient current source.

[0058] When laying out the first bias transistor MB1 and the second bias transistor MB2, they need to be close to the common source transistor M1 and the common gate transistor M2. In this embodiment, the first bias transistor MB1 and the second bias transistor MB2 are laid out around the common source transistor M1 and the common gate transistor M2 with the minimum process spacing.

[0059] As described above, the current I in the second bias branch X2 is... X2 Since the current has a positive temperature coefficient, the gate-source voltage of the MOSFET cell has a negative temperature coefficient. Therefore, by adjusting the temperature coefficient relationship, a second bias voltage V that is independent of temperature can be obtained. G2 This is used for gate biasing of the common-gate transistor M2. The current I in the first bias branch X1 is...X1 For temperature-independent current, I X1 The current is shunted by the paths of the first bias transistor MB1 and the second bias transistor MB2, and the remaining current acts on the second resistor R2 to generate the first bias voltage V. G1 It is used for gate biasing of common source transistor M1.

[0060] The current in the amplifier stage circuit is expressed as:

[0061]

[0062] Where, μ n C ox This indicates the process parameters of common source tube M1. V represents the aspect ratio of the common-source transistor M1. G1 This represents the first bias voltage, V. TH V represents the threshold voltage of the common-source transistor M1; λ represents the channel modulation coefficient of the common-source transistor M1. DS This represents the drain-source voltage of the common-source transistor M1;

[0063] The gain of the amplifier stage circuit is expressed as:

[0064]

[0065] Among them, g m R represents the transconductance of the amplifier stage circuit; out V represents the output equivalent resistance of the amplifier stage circuit; GS This represents the gate-source voltage of the common-source transistor M1;

[0066] The current in the first bias branch is expressed as:

[0067]

[0068] Where R2 represents the resistance value of the second resistor R2; I MB1 This represents the current flowing through the first bias transistor MB1; V DS1 This represents the drain-source voltage of the first bias transistor MB1.

[0069] In formula ①, V TH It decreases with increasing temperature and increases with decreasing temperature, exhibiting a negative temperature coefficient. The gain Av of the amplifier stage circuit is given by formula ②, since V TH Due to its negative temperature characteristic, the gain Av of the amplifier stage circuit increases with increasing temperature and decreases with decreasing temperature. When the temperature rises while other parameters remain constant, the current I of the amplifier stage circuit... D As the temperature increases, the gain Av of the amplifier stage increases; as the temperature decreases, other parameters remain unchanged, and the current I of the amplifier stage increases. D As the process parameters deviate, the gain Av of the amplifier stage circuit decreases. THThe most obvious change occurs when the process parameters deviate positively, becoming V. TH +ΔV TH Amplifier stage circuit current I D As the process parameters decrease, the gain Av decreases; when the process parameters have a negative deviation, it becomes V. TH -ΔV TH Amplifier stage circuit current I D As the temperature increases, the gain Av increases. Therefore, the gain and power consumption of the amplifier stage fluctuate significantly when the temperature changes or when the process parameters change.

[0070] Figure 4 The principle of temperature compensation during the operation of the bias circuit is explained. The first bias transistor MB1 and the second bias transistor MB2 are laid out close to the common-source transistor M1 and the common-gate transistor M2 in the amplification stage to ensure the accuracy of temperature acquisition in the amplification region. As the temperature rises, as described above, the gain Av and current I of the amplification stage circuit will... D This will increase. At this time, in temperature-compensated bias, the threshold voltage V of the first bias transistor MB1 will increase. THMB1 Lowering the threshold voltage V of the second bias transistor MB2 THMB2 Reduced. Simultaneously, the second bias voltage V G2 Regardless of temperature, this causes the drain-source voltage V of the first bias transistor MB1 to be independent. DSMB1 Increase. From formula ①, it can be seen that the current in the first bias transistor MB1 branch increases to I. MB1 +ΔI H Due to the current I in the first bias branch X1 X1 Since the current is temperature-independent and remains constant, the current flowing through the second resistor R2 decreases, resulting in a decrease in the first bias voltage V. G1 Reduce, first bias voltage V G1 The decrease in voltage further reduces the current in the first bias transistor MB1 branch, thus creating negative feedback at temperature T. H A bias voltage V is generated at the location. G1H This voltage is lower than the first bias voltage V at the initial temperature. G1 From formulas ① and ②, it can be concluded that the temperature compensation voltage generated by the bias circuit reduces the fluctuations in gain Av and power consumption of the amplifier stage circuit with temperature. The principle remains the same when the temperature decreases.

[0071] Figure 6 The first bias voltage V is given. G1 Simulation curves showing temperature variation. Figure 7 The current I of the amplifier stage circuit with and without bias circuit is given. D Simulation comparison curves showing temperature variation. Figure 8 and Figure 9Simulation comparison curves of the gain Av of the amplifier stage with and without bias circuit as a function of temperature are presented. Table 1 summarizes and compares the data.

[0072] Table 1

[0073]

[0074] It can be seen that after introducing the bias circuit, the changes in power consumption and gain with temperature are significantly improved. The power consumption changes from 72.7% to 33.8%, and the gain changes from 12.4% to 3.4%.

[0075] Figure 5 The principle of process parameter deviation compensation during bias circuit operation is explained. The first bias transistor MB1 and the second bias transistor MB2 are placed close to the common-source transistor M1 and the common-gate transistor M2 in the amplifier stage circuit during layout to ensure consistency with the process parameters of the amplifier transistors in the amplification region. When the process parameters shift towards a positive standard deviation, the threshold voltage V of the first bias transistor MB1... THMB1 As shown in formula ①, the current in the first bias transistor MB1 branch decreases to I. MB1 -ΔI P Due to the current I in the first bias branch X1 X1 Since the current remains constant, the current flowing through the second resistor R2 increases, causing the bias voltage V to remain constant. G1 Increase the first bias voltage V G1 The increase in voltage further increases the current in the first bias transistor MB1 branch, thus creating negative feedback and generating a bias voltage V. G1P This voltage is higher than the first bias voltage V under typical process parameters. G1 From formulas ① and ②, it can be concluded that the process parameter compensation voltage generated by this bias circuit reduces the fluctuation of the amplifier stage circuit gain Av and power consumption with process parameters.

[0076] Figure 10 The first bias voltage V is given. G1 Simulation curves showing changes in process parameters. Figure 11 The current I of the amplifier stage circuit with and without bias circuit is given. D Simulation comparison curves showing changes in process parameters. Figure 12 and Figure 13 Simulation comparison curves of the gain Av of the amplifier stage with and without bias circuit as a function of process parameters are presented. Table 2 summarizes and compares the data.

[0077] Table 2

[0078]

[0079] It can be seen that after introducing the bias circuit, the changes in power consumption and gain with process parameters are significantly improved. The power consumption changes from 86.1% to 6.1%, and the gain changes from 26.9% to 9.6%.

Claims

1. A CMOS cascode RF amplifier with temperature and process deviation compensation, characterized in that, Includes bias circuitry and amplifier stage circuitry; The amplifier stage circuit includes a common-source transistor, a common-gate transistor, a choke inductor, an input matching network, and an output matching network; The drain of the common source transistor is connected to the source of the common gate transistor. The source of the common source transistor is grounded. The gate of the common source transistor is connected to the input matching network on one hand and to the first bias voltage output terminal of the bias circuit on the other hand. The drain of the common-gate transistor is connected to the power supply voltage on one hand through a choke inductor, and on the other hand to the output matching network. The gate of the common-gate transistor is connected to the second bias voltage output terminal of the bias circuit; The bias circuit consists of a first bias branch and a second bias branch; The first bias branch includes a first current source, a first resistor, and a second resistor connected in series, with one end of the second resistor grounded; it also includes a first bias transistor and a second bias transistor. Both the first bias transistor and the second bias transistor are MOSFETs; one end of the first resistor is connected to the output terminal of the first current source on one side and to the drain of the second bias transistor on the other side, the source of the second bias transistor is connected to the drain of the first bias transistor, and the source of the first bias transistor is grounded. The gate of the first bias transistor is connected to the common terminal of the first resistor and the second resistor on one hand, and serves as the first bias voltage output terminal of the bias circuit on the other hand. The second bias branch includes a second current source, a third resistor, a fourth resistor, and a MOS transistor unit connected in series in the form of diodes; the MOS transistor unit is composed of the first to nth MOS transistors connected in series, the drain of the first MOS transistor is connected to the fourth resistor, the source of the (m-1)th MOS transistor is connected to the drain of the mth MOS transistor, and the source of the nth MOS transistor is grounded; where n≥2, m∈[2,n]; The gate of the second bias transistor is connected to the common terminal of the third and fourth resistors on one hand, and serves as the second bias voltage output terminal of the bias circuit on the other hand. The first current source is a temperature-independent current source, and the second current source is a positive temperature coefficient current source.

2. The CMOS cascode RF amplifier with temperature and process deviation compensation according to claim 1, characterized in that, In the layout, the first and second bias transistors are placed around the common source and common gate transistors with the minimum process spacing.

3. The CMOS cascode RF amplifier with temperature and process deviation compensation according to claim 1 or 2, characterized in that, The current in the amplifier stage circuit is expressed as: Where, μ n C ox Indicates the process parameters of the common source tube. V represents the aspect ratio of a common-source transistor. G1 This represents the first bias voltage, V. TH V represents the threshold voltage of the common-source transistor; λ represents the channel modulation coefficient of the common-source transistor. DS This represents the drain-source voltage of a common-source transistor; The gain of the amplifier stage circuit is expressed as: Among them, g m R represents the transconductance of the amplifier stage circuit; out V represents the output equivalent resistance of the amplifier stage circuit; GS This represents the gate-source voltage of a common-source transistor; The current in the first bias branch is expressed as: Where R2 represents the resistance value of the second resistor; I MB1 This represents the current flowing through the first bias transistor; V DS1 This represents the drain-source voltage of the first bias transistor.

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