An adaptive slew rate enhancement circuit and control method for CMOS operational amplifiers

Abstract

This invention provides an adaptive slew rate enhancement circuit for CMOS operational amplifiers, used for adaptively increasing the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output. The circuit is characterized by including at least a positive slew rate enhancement circuit and a negative slew rate enhancement circuit connected to the rail-to-rail input floating Class AB operational amplifier. The positive slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to rise with the input voltage VIP, and the negative slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to fall with the input voltage VIP. A corresponding control method is also provided. Under the action of the positive and negative slew rate enhancement circuits provided by this invention, the speed at which the output voltage VOUT builds up to 99% is increased by approximately 60% and 40%, respectively, when the input voltage VIP changes. This patent proposes an enhancement circuit that is simple, low-cost, and can significantly improve the driving speed of the operational amplifier.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, particularly semiconductor chip technology, and is especially applicable to fields such as video and display driver ICs, high-speed analog signal processing systems, and communication systems. Specifically, it relates to an adaptive slew rate enhancement circuit for CMOS operational amplifiers. Background Technology

[0002] To balance low power consumption, low cost, and high stability, traditional CMOS operational amplifiers employ a constant current source and fixed internal frequency compensation. This results in a speed bottleneck in large-signal dynamic response, especially when the output stage drives a large load capacitor, where the large-signal dynamic response is even worse. The low slew rate of traditional CMOS operational amplifiers is mainly due to the inherent design limitations of their internal circuit structure, specifically, at least the following two technical defects: 1. Limitations of the constant current source in the input stage: The input differential pair of a CMOS op-amp is typically biased by a constant current source. When a large input signal changes, one MOSFET in the differential pair turns on while the other turns off, and the entire current source is used to charge and discharge the compensation capacitor. The current in this constant current source is the maximum value of the charging and discharging current; therefore, the slew rate is fixed at constant current / compensation capacitor value, making it impossible to dynamically increase the slew rate while considering low power consumption.

[0003] 2. Limitations of Internal Compensation Capacitors: To ensure stability, traditional CMOS operational amplifiers typically integrate internal compensation capacitors. When large input signals change, the available current in the input stage is limited, requiring time for this capacitor to charge and discharge. The slew rate is directly limited by the charging current divided by the compensation capacitor value. Therefore, the presence of the compensation capacitor fundamentally limits the maximum slew rate of the voltage.

[0004] For example, Figure 1 This diagram illustrates a traditional two-stage operational amplifier topology. The first stage is a single-stage op-amp with rail-to-rail fully differential input and a common-source, common-gate load. The second stage is a Class AB common-source stage with a floating current source output. Cmp and Cmn are Miller compensation capacitors. When the two-stage operational amplifier operates in a unity-gain negative feedback system driving a capacitive load CL, Cmp and Cmn, as Miller compensation capacitors, provide phase compensation, increasing system stability and ensuring that the output voltage VOUT completely follows the input voltage VIP. Figure 2 The schematic diagram is shown. The non-inverting input is connected to the input reference voltage VIP, and the inverting input is shorted to the output voltage VOUT, forming a unity-gain operational amplifier. The "virtual short" characteristic of negative feedback is used to achieve VOUT=VIP.

[0005] If the input voltage VIP undergoes a positive step change, the tail current Itail_p flows entirely through the second PMOS transistor MP2, and is mirrored at NG through dynamic current mirrors MN3 and MN4, discharging NG. Simultaneously, the tail current Itail_n flows entirely through MN1, discharging at point PG. This causes the ninth PMOS transistor MP9 to quickly turn on, charging the load and raising the output voltage VOUT until VOUT = VIP, at which point the op-amp is in steady state. Similarly, if the input voltage VIP undergoes a negative step change, the tail currents Itail_p and Itail_n quickly charge points NG and PG respectively, causing the ninth NMOS transistor MN9 to quickly turn on, discharging the load and lowering the output voltage VOUT until VOUT = VIP. Therefore, the slew rate of the op-amp is determined by the charge and discharge speeds of the PG and NG points, i.e., slew rate = Itail_p / Cmn or Itail_n / Cmp. In other words, the slew rate is determined by the tail current of the differential amplifier and the compensation capacitor. Although increasing the tail current can increase the slew rate, the power consumption will also increase accordingly. That is, the traditional op-amps used in the existing technology are not suitable for low-power systems.

[0006] Therefore, there is a need for an enhancement circuit that can more quickly improve the slew rate of CMOS operational amplifiers. Summary of the Invention

[0007] To address the technical deficiencies of existing technologies, the present invention aims to provide an adaptive slew rate enhancement circuit for CMOS operational amplifiers. This circuit adaptively enhances the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output. The circuit is characterized by including at least a positive slew rate enhancement circuit and a negative slew rate enhancement circuit connected to the rail-to-rail input floating Class AB operational amplifier. The positive slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to rise in tandem with the input voltage VIP, and the negative slew rate enhancement circuit accelerates the time it takes for the output voltage VOUT to fall in tandem with the input voltage VIP.

[0008] Preferably, the positive slew rate enhancement circuit includes at least a tenth PMOS transistor MP10, a tenth NMOS transistor MN10, an eleventh PMOS transistor MP11, and an eleventh NMOS transistor MN11. The drain of the tenth PMOS transistor MP10 is grounded, its gate is connected to the input voltage VIP, and its source is connected to the source of the tenth NMOS transistor MN10. The gate and drain of the tenth NMOS transistor MN10 are connected together and connected to the drain of the eleventh PMOS transistor MP11. The gate of the eleventh PMOS transistor MP11 is connected to a fixed bias voltage, and its source is connected to a power supply. The drain of the eleventh NMOS transistor MN11 is connected to a power supply, and its gate is connected to the drain of the tenth NMOS transistor MN10.

[0009] Preferably, the negative slew rate enhancement circuit includes at least a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a twelfth NMOS transistor MN12, and a thirteenth NMOS transistor MN13. The drain of the twelfth NMOS transistor MN12 is connected to the power supply, its gate is connected to the input voltage VIP, and its source is connected to the source of the twelfth PMOS transistor MP12. The gate and drain of the twelfth PMOS transistor MP12 are connected together and connected to the drain of the thirteenth NMOS transistor MN13. The gate of the thirteenth NMOS transistor MN13 is connected to a fixed bias voltage, and its source is connected to ground. The drain of the thirteenth PMOS transistor MP13 is grounded, and its gate is connected to the drain of the twelfth PMOS transistor MP12.

[0010] According to another aspect of the present invention, a control method for the above-described adaptive slew rate enhancement circuit applied to a CMOS operational amplifier is also provided, which is used for adaptively increasing the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output, characterized by comprising the following steps: a. When the input voltage VIP experiences a positive step voltage, current I1 is injected into point P, the connection point between the positive slew rate enhancement circuit and the rail-to-rail input floating Class AB output two-stage operational amplifier, through the positive slew rate enhancement circuit, to increase the slew rate of the operational amplifier and accelerate the rise of the output voltage VOUT. b. Continuously inject the current I1 until the output voltage VOUT rises to the input voltage VIP, at which point the slew rate enhancement circuit automatically shuts down and stops injecting the current I1 into the connection point P.

[0011] Preferably, in step a, when the output voltage VOUT << the input voltage VIP, the source voltage of the tenth PMOS transistor MP10 immediately follows the input voltage VIP and undergoes a positive step, causing the VGS voltage of the eleventh NMOS transistor MN11 to increase, thus injecting the current I1 into the connection point P.

[0012] Preferably, the above control method further includes the following steps: c. When the input voltage VIP experiences a negative step voltage, the negative slew rate enhancement circuit draws current I2 from point N, the connection point between the negative slew rate enhancement circuit and the rail-to-rail input floating Class AB output two-stage operational amplifier, to increase the slew rate of the operational amplifier and accelerate the decrease of the output voltage VOUT. d. When the current I2 is continuously drawn until the output voltage VOUT drops to the input voltage VIP, the negative slew rate enhancement circuit automatically shuts down and stops drawing the current I2 from the connection point N.

[0013] Preferably, in step c, when the output voltage VOUT >> the input voltage VIP, the source voltage of the twelfth NMOS transistor MN12 immediately follows the input voltage VIP and undergoes a negative step, causing the VGS voltage of the thirteenth PMOS transistor MP13 to increase, and drawing current I2 from the connection point N.

[0014] This patent proposes an adaptive slew rate enhancement circuit for CMOS operational amplifiers. In addition to traditional CMOS operational amplifiers, positive and negative slew rate enhancement circuits are added. By detecting changes in the reference voltage VIP through a source follower, the slew rate of the operational amplifier is increased, accelerating the speed at which the output voltage drives the load. After completing the slew rate enhancement, the circuit automatically shuts down without affecting the operation of the main operational amplifier. Under the action of the positive and negative slew rate enhancement circuits, the speed at which the output voltage VOUT builds up to 99% is increased by approximately 60% and 40%, respectively, when the input voltage VIP changes. This is perfectly suitable for low-cost, low-power integrated circuit applications. The enhancement circuit proposed in this patent is simple, low-cost, and can significantly improve the driving speed of the operational amplifier. Attached Figure Description

[0015] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of the topology of a rail-to-rail input, floating Class AB operational amplifier in the prior art is shown; Figure 2 It shows the use of Figure 1 The diagram shows the structure of a unity-gain negative feedback operational amplifier. Figure 3 A schematic diagram of the circuit structure of an adaptive slew rate enhancement circuit applied to a CMOS operational amplifier according to a first embodiment of the present invention is shown. Figure 4 This diagram illustrates a comparison of the operational performance of the adaptive slew rate enhancement circuit for CMOS operational amplifiers provided by the present invention with that of prior art rail-to-rail input, floating Class AB operational amplifiers. Specifically, it shows a comparison of the output voltage settling time under the action of the positive slew rate enhancement circuit; and Figure 5 The diagram illustrates a comparison of the operating effects of the adaptive slew rate enhancement circuit for CMOS operational amplifiers provided according to the present invention with those of existing rail-to-rail input, floating Class AB operational amplifiers. Specifically, it is a comparison of the output voltage settling time under the action of the negative slew rate enhancement circuit. Detailed Implementation

[0016] To better illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings. Figure 3 This patent presents an innovative structure for a two-stage operational amplifier with rail-to-rail input and floating Class AB output, specifically a schematic diagram of the adaptive slew rate enhancement circuit for a CMOS operational amplifier according to the first embodiment of the present invention. As analyzed above, the slew rate of a traditional operational amplifier is affected by the sizes of the Miller compensation capacitors Cmp and Cmn, and the tail current limits its charging and discharging time. The ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 are difficult to turn on quickly, slowing down the settling time of VOUT and limiting the slew rate. To address this problem, this patent adds a positive slew rate enhancement circuit composed of the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the tenth NMOS transistor MN10, and the eleventh NMOS transistor MN11 to the traditional two-stage operational amplifier, accelerating the rise time of the output voltage VOUT following the input voltage VIP, and a negative slew rate enhancement circuit composed of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the twelfth NMOS transistor MN12, and the thirteenth NMOS transistor MN13, accelerating the fall time of the output voltage VOUT following the input voltage VIP.

[0017] In the positive slew rate enhancement circuit, the tenth PMOS transistor MP10 is connected as a source follower. Its drain is grounded, its gate is connected to the input voltage VIP, and its source is connected to the source of the tenth NMOS transistor MN10. The gate and drain of the tenth NMOS transistor MN10 are connected together and connected to the drain of the eleventh PMOS transistor MP11. The gate of the eleventh PMOS transistor MP11 is connected to a fixed bias voltage, and its source is connected to the power supply, which serves as a current limiter. The drain of the eleventh NMOS transistor MN11 is connected to the power supply, and its gate is connected to the drain of the tenth NMOS transistor MN10. Its gate voltage M follows the output voltage VIP. The source of the eleventh NMOS transistor MN11 is connected to point P, forming a charging path between the power supply and point P. Under the control of VIP, the eleventh NMOS transistor MN11 injects current I1 into point P.

[0018] When a positive step voltage occurs in VIP, when VOUT << VIP, the tail current Itail_p all flows through the second PMOS transistor MP2, the voltage at point P is VOUT + VTH, and the source voltage of the tenth PMOS transistor MP10 immediately follows the positive step of the input voltage VIP. After passing through the voltage difference of the source-drain voltage VDS of the tenth NMOS transistor MN10, it further increases the gate voltage of the eleventh NMOS transistor MN11, making the VGS voltage of the eleventh NMOS transistor MN11 increase, injecting current I1 into point P. The tail current Itail_p all flows through the second PMOS transistor MP2, and is all mirrored at NG through the dynamic current mirrors MN3 and MN4, discharging NG, increasing the slew rate of the operational amplifier, that is, slewrate=(Itail_p + I1) / Cmn, and accelerating the rise of VOUT.

[0019] When VOUT rises to a threshold voltage VTH lower than VIP, the voltage at point P gradually rises. However, at this time, the VGS voltage of the eleventh NMOS transistor MN11 is still greater than a threshold voltage VTH, and the eleventh NMOS transistor MN11 is in a critical off state and still injects current I1 into point P, playing a role in enhancing the slew rate and accelerating the rise of the output voltage VOUT following the input voltage VIP.

[0020] When VOUT rises to VIP, due to the existence of the VDS voltage difference of the tenth NMOS transistor MN10, the VGS of the eleventh NMOS transistor MN11 is only the VDS voltage difference of the tenth NMOS transistor MN10, which is less than VTH and is not sufficient to turn on the eleventh NMOS transistor MN11. The positive slew rate enhancement circuit is turned off, which will not affect the static operating point of the operational amplifier in the stable state, and there is no additional power consumption. In the negative slew rate enhancement circuit, the twelfth NMOS transistor MN12 is connected in the source follower configuration. Its drain is connected to the power supply, its gate is connected to the input voltage VIP, and its source is connected to the source of the twelfth PMOS transistor MP12. The gate and drain of the twelfth PMOS transistor MP12 are connected together and connected to the drain of the thirteenth NMOS transistor MN13. The gate of the thirteenth NMOS transistor MN13 is connected to a fixed bias voltage, and its source is connected to the ground, playing a current limiting role. The drain of the thirteenth PMOS transistor MP13 is grounded, and its gate is connected to the drain of the twelfth PMOS transistor MP12. Its gate voltage Y follows the change of the output voltage VIP. The source of the thirteenth PMOS transistor MP13 is connected to point N, forming a discharge path between point N and the ground, and extracting current I2 at point N through the thirteenth PMOS transistor MP13 under the control of VIP.

[0021] When a negative step voltage occurs at VIP, when VOUT >> VIP, the tail current Itial_n all flows through the second NMOS transistor MN2, the voltage at point P is VOUT - VTH, and the source voltage of the twelfth NMOS transistor MN12 immediately follows the negative step of the input voltage VIP. After passing through the source-drain voltage difference VDS of the twelfth PMOS transistor MP12, it further reduces the gate voltage of the eleventh NMOS transistor MN11, increasing the VGS voltage of the thirteenth PMOS transistor MP13, drawing current I2 at point N. The tail current Itial_n all flows through the second NMOS transistor MN2, and is all mirrored at PG through the dynamic current mirrors MP3 and MP4, charging PG, increasing the slew rate of the operational amplifier, that is slew rate=(Itail_n+I2) / Cmp, accelerating the decline of VOUT.

[0022] When VOUT drops to a threshold voltage VTH higher than VIP, the voltage at point N gradually decreases. However, at this time, the VGS voltage of the thirteenth PMOS transistor MP13 is still greater than a threshold voltage VTH, and the thirteenth PMOS transistor MP13 is in a critical off state, still drawing current I2 at point N, playing a role in enhancing the slew rate, accelerating the output voltage VOUT to follow the input voltage VIP down.

[0023] When VOUT drops to VIP, due to the existence of the VDS voltage difference of the twelfth PMOS transistor MP12, the VGS of the thirteenth PMOS transistor MP13 is only the VDS voltage difference of the twelfth PMOS transistor MP12, which is less than VTH and is not sufficient to turn on the thirteenth PMOS transistor MP13. The negative slew rate enhancement circuit is turned off, which will not affect the static operating point of the operational amplifier in the stable state, and there is no additional power consumption.

[0024] Under the action of the positive slew rate enhancement circuit, when the VIP voltage undergoes a positive step, VOUT will quickly follow and rise to the voltage of VIP - VTH. Under the action of the negative slew rate enhancement circuit, when the VIP voltage undergoes a negative step, VOUT will quickly follow and drop to the voltage of VIP + VTH. As the operational amplifier enters the small-signal state and starts to be in a stable operating state, VOUT approaches the reference voltage VIP infinitely, and the positive and negative slew rate enhancement circuits automatically turn off, which will not affect the operating state of the operational amplifier in the stable state and there is no additional power consumption. In addition, when the operational amplifier switches the load, when the load draws current resulting in VOUT < VIP - VTH or the load sinks current resulting in VOUT > VIP + VTH, the positive and negative slew rate enhancement circuits of this patent will automatically turn on, increasing the slew rate of the operational amplifier and accelerating the settling time of the operational amplifier.

[0025] Figure 4This patent compares the settling time of the output voltage VOUT (red curve) under the action of the slew rate enhancement circuit with that of the traditional op-amp output voltage VOUT (green curve) when the input voltage VIP experiences a positive step voltage. It can be found that the slew rate enhancement circuit proposed in this patent increases the speed at which the output voltage rises to 99% of the target voltage by 60%. Figure 5 The comparison of the settling time of the output voltage VOUT (red curve) under the action of the negative slew rate enhancement circuit and the traditional op-amp output voltage VOUT (green curve) when the input voltage VIP of this patent has a negative step voltage shows that the negative slew rate enhancement circuit proposed in this patent increases the speed at which the output voltage drops to 99% of the target voltage by 40%.

[0026] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. An adaptive slew rate enhancement circuit for CMOS operational amplifiers, used for adaptively increasing the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output, characterized in that... It includes at least a positive slew rate enhancement circuit and a negative slew rate enhancement circuit connected to the rail-to-rail input floating Class AB operational amplifier. The positive slew rate enhancement circuit is used to accelerate the time for the output voltage VOUT to rise with the input voltage VIP, and the negative slew rate enhancement circuit accelerates the time for the output voltage VOUT to fall with the input voltage VIP.

2. The enhancement circuit according to claim 1, characterized in that, The positive slew rate enhancement circuit includes at least a tenth PMOS transistor (MP10), a tenth NMOS transistor (MN10), an eleventh PMOS transistor (MP11), and an eleventh NMOS transistor (MN11). The drain of the tenth PMOS transistor (MP10) is grounded, its gate is connected to the input voltage VIP, and its source is connected to the source of the tenth NMOS transistor (MN10). The gate and drain of the tenth NMOS transistor (MN10) are connected together and connected to the drain of the eleventh PMOS transistor (MP11). The gate of the eleventh PMOS transistor (MP11) is connected to a fixed bias voltage, and its source is connected to the power supply. The drain of the eleventh NMOS transistor (MN11) is connected to the power supply, and its gate is connected to the drain of the tenth NMOS transistor (MN10).

3. The enhancement circuit according to claim 1, characterized in that, The negative slew rate enhancement circuit includes at least a twelfth PMOS transistor (MP12), a thirteenth PMOS transistor (MP13), a twelfth NMOS transistor (MN12), and a thirteenth NMOS transistor (MN13). The drain of the twelfth NMOS transistor (MN12) is connected to the power supply, the gate is connected to the input voltage VIP, and the source is connected to the source of the twelfth PMOS transistor (MP12). The gate and drain of the twelfth PMOS transistor (MP12) are connected together and connected to the drain of the thirteenth NMOS transistor (MN13). The gate of the thirteenth NMOS transistor (MN13) is connected to a fixed bias voltage, and the source is connected to ground. The drain of the thirteenth PMOS transistor (MP13) is grounded, and the gate is connected to the drain of the twelfth PMOS transistor (MP12).

4. A control method for the enhancement circuit according to any one of claims 1 to 3, characterized in that it is used for adaptively increasing the slew rate of a two-stage operational amplifier with rail-to-rail input and floating Class AB output, wherein... Includes the following steps: a. When the input voltage VIP experiences a positive step voltage, current I1 is injected into point P, the connection point between the positive slew rate enhancement circuit and the rail-to-rail input floating Class AB output two-stage operational amplifier, through the positive slew rate enhancement circuit, to increase the slew rate of the operational amplifier and accelerate the rise of the output voltage VOUT. b. Continue injecting the current I1 until the output voltage VOUT rises to the input voltage VIP, at which point the slew rate enhancement circuit automatically shuts down and stops injecting the current I1 into the connection point P.

5. The control method according to claim 4, characterized in that, In step a, when the output voltage VOUT << the input voltage VIP, the source voltage of the tenth PMOS transistor (MP10) immediately follows the input voltage VIP and undergoes a positive step, causing the VGS voltage of the eleventh NMOS transistor (MN11) to increase, thus injecting the current I1 into the connection point P.

6. A control method for the enhancement circuit of claim 4 or 5, characterized in that, It also includes the following steps: c. When the input voltage VIP experiences a negative step voltage, the negative slew rate enhancement circuit draws current I2 from point N, the connection point between the negative slew rate enhancement circuit and the rail-to-rail input floating Class AB output two-stage operational amplifier, to increase the slew rate of the operational amplifier and accelerate the decrease of the output voltage VOUT. d. When the current I2 is continuously drawn until the output voltage VOUT drops to the input voltage VIP, the negative slew rate enhancement circuit automatically shuts down and stops drawing the current I2 from the connection point N.

7. A control method for the enhancement circuit of claim 6, characterized in that, In step c, when the output voltage VOUT >> the input voltage VIP, the source voltage of the twelfth NMOS transistor (MN12) immediately follows the input voltage VIP and undergoes a negative step, causing the VGS voltage of the thirteenth PMOS transistor (MP13) to increase, and drawing current I2 from the connection point N.

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