Master Clock Generation Device

Abstract

A reference signal generation unit (104) that generates a master clock, a multiplier (105) that generates a signal with a frequency multiplied by the frequency of the master clock based on the master clock generated by the reference signal generation unit (104), a first difference detection unit (101a) provided for each of one or more systems, that detects a phase difference or a frequency difference between the signal generated by the multiplier (105) and the signal of the corresponding system's atomic clock (2), a second difference detection unit (101b) that detects a phase difference or a frequency difference between the signal generated by the multiplier (105) and the master clock generated by the reference signal generation unit (104), a digital signal processing unit (102) that generates frequency phase control data which is data for controlling the frequency and phase of the master clock based on the detection result by the first difference detection unit (101a) and the detection result by the second difference detection unit (101b), and a signal synthesis unit (103) that controls the frequency and phase of the output signal to the reference signal generation unit (104) based on the frequency phase control data generated by the digital signal processing unit (102). The reference signal generation unit (104) generates a master clock according to the output signal from the signal synthesis unit (103).

Description

Technical Field

[0001] The present disclosure relates to a master clock generation device that generates a master clock.

Background Art

[0002] A master clock generation device is a device that generates a 10.23 MHz master clock based on the signal of an atomic clock mounted on a positioning satellite. The master clock generation device is also called a timekeeping system. By controlling a VCXO (Voltage Controlled Crystal Oscillator) having good short-term stability characteristics to follow an atomic clock having excellent long-term stability characteristics, a stable master clock is generated in a wide time domain.

[0003] Patent Document 1 discloses a master clock generation device capable of detecting abnormal behavior by constructing a redundant system using signals of a plurality of atomic clocks and measuring the phase difference between a main clock and a sub-clock. In the master clock generation device disclosed in this Patent Document 1, a reference frequency signal (10.23 MHz), which is the output signal of the master clock generation device, is generated by selecting a normal main clock or sub-clock and inputting it to a frequency signal generator.

[0004] Non-Patent Document 1 also discloses a high-stability time generation system using an ensemble clock method that generates an ensemble time system by weighted-averaging signals of a plurality of atomic clocks. In the high-stability time generation system disclosed in this Non-Patent Document 1, an ensemble time system is generated by detecting the phase difference between a plurality of atomic clocks and performing signal processing, and based on this, the frequency and phase of the VCXO are controlled to synthesize a reference signal (10.23 MHz). At this time, in the circuit that synthesizes the reference signal, a quadrupled reference signal is used as a drive clock.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Non-Patent Document

[0006]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the master clock generation device disclosed in Patent Document 1, a main clock or a sub-clock obtained by frequency-converting the signal of an atomic clock is selected and input to a frequency signal generator. Therefore, in this master clock generation device, when a phase jump occurs in the atomic clock, its influence appears in the output reference frequency signal. That is, it is known that in a rubidium atomic clock mounted on a positioning satellite, a phase jump of the output signal occurs irregularly due to the optical shift effect caused by the optical system. Therefore, the master clock generation device disclosed in Patent Document 1 has a problem that the frequency stability of the reference frequency signal deteriorates due to this influence.

[0008] On the other hand, in the highly stable time generation system disclosed in Non-Patent Document 1, an ensemble time system obtained by weighted-averaging the signals of a plurality of atomic clocks is used. Therefore, in this highly stable time generation system, when a phase jump is detected in the signal processing unit, the influence on the output signal can be avoided by setting the weight of the atomic clock to zero. In addition, in this high-stability time generation system, as a signal for driving the signal synthesis unit that synthesizes the reference signal, a signal obtained by quadrupling the reference signal, which is the output of the high-stability time generation system, is used. Therefore, in this high-stability time generation system, the reference signal can avoid the influence of the phase jump of the atomic clock and maintain a stable reference signal.

[0009] However, since the quadrupler that quadruples the frequency of the reference signal is composed of analog components, the temperature characteristic of the phase delay is large. That is, in this high-stability time generation system, when the ambient temperature changes, there is a problem that the stability of the reference signal deteriorates due to the fluctuation of the output phase of the signal synthesis unit caused by the phase fluctuation of the quadrupler.

[0010] The present disclosure has been made to solve the above problems, and an object thereof is to provide a master clock generation device capable of generating a stable master clock even when the temperature changes.

Means for Solving the Problems

[0011] The master clock generation device according to the present disclosure includes a reference signal generation unit that generates a master clock, a multiplier that generates a signal with a frequency multiplied by the master clock based on the master clock generated by the reference signal generation unit, a first difference detection unit that is provided for each of one or more systems and detects a phase difference or a frequency difference between the signal generated by the multiplier and the signal of the atomic clock of the corresponding system, a second difference detection unit that detects a phase difference or a frequency difference between the signal generated by the multiplier and the master clock generated by the reference signal generation unit, a digital signal processing unit that generates frequency and phase control data, which is data for controlling the frequency and phase of the master clock, based on the detection result by the first difference detection unit and the detection result by the second difference detection unit, and a signal synthesis unit that controls the frequency and phase of the output signal to the reference signal generation unit based on the frequency and phase control data generated by the digital signal processing unit, and the reference signal generation unit generates a master clock according to the output signal from the signal synthesis unit.

Advantages of the Invention

[0012] According to the present disclosure, since it is configured as described above, it is possible to generate a stable master clock even when the temperature changes.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. Embodiment 1. FIG. 1 is a block diagram showing a configuration example of the master clock generation device 1 according to Embodiment 1. In FIG. 1, in addition to the master clock generation device 1, one or more systems of atomic clocks 2 are also shown. The master clock generation device 1 is a circuit that generates a master clock based on the signals of one or more systems of atomic clocks 2. That is, the atomic clock 2 constantly outputs a clock signal to the master clock generation device 1, and the master clock generation device 1 generates a master clock based on this signal. The master clock is a stable 10.23 MHz master clock, that is, a master clock with high frequency stability.

[0015] As the atomic clock 2, for example, a rubidium atomic clock or a passive hydrogen maser atomic clock can be used.

[0016] Also, in FIG. 1, the case where the master clock generation device 1 inputs the signals of M systems of atomic clocks 2 (atomic clocks 2-1 to 2-M) is shown. M is an integer of 2 or more.

[0017] That is, in the example of FIG. 1, the signal of the atomic clock 2-1 is output to the first phase difference detection unit 101a-1 (to be described later) of the master clock generation device 1. Also, the signal of the atomic clock 2-2 is output to the first phase difference detection unit 101a-2 (to be described later) of the master clock generation device 1. In addition, the signal of the atomic clock 2-M is output to a first phase difference detection unit 101a-M (to be described later) of the master clock generation device 1.

[0018] As shown in FIG. 1, for example, the master clock generation device 1 includes one or more first phase difference detection units (first difference detection units) 101a, a second phase difference detection unit (second difference detection unit) 101b, a digital signal processing unit 102, a signal synthesis unit 103, a reference signal generation unit 104, and a multiplier 105.

[0019] The first phase difference detection unit 101a detects the phase difference between the signal multiplied by the multiplier 105 for the master clock and the signal of the atomic clock 2 of the corresponding system. A signal indicating the phase difference detected by the first phase difference detection unit 101a is output to the digital signal processing unit 102.

[0020] As the first phase difference detection unit 101a, for example, an ADC (Analog to Digital Converter) can be used. When the first phase difference detection unit 101a is an ADC, this ADC converts the signal of the atomic clock 2 of the corresponding system from an analog signal to a digital signal and outputs it to the digital signal processing unit 102. At this time, by using the signal multiplied by the multiplier 105 for the master clock as the sampling clock of the ADC, the output phase of the first phase difference detection unit 101a becomes a value corresponding to the phase difference between the signal of the atomic clock 2 of the corresponding system and the master clock.

[0021] Also, FIG. 1 shows a case where the master clock generation device 1 includes M first phase difference detection units 101a (first phase difference detection units 101a-1 to 101a-M).

[0022] That is, in the example of FIG. 1, the first phase difference detection unit 101a-1 detects the phase difference between the signal obtained by multiplying the master clock by the multiplier 105 and the signal of the atomic clock 2-1. The signal indicating the phase difference detected by the first phase difference detection unit 101a-1 is output to the digital signal processing unit 102. Also, the first phase difference detection unit 101a-2 detects the phase difference between the signal obtained by multiplying the master clock by the multiplier 105 and the signal of the atomic clock 2-2. The signal indicating the phase difference detected by the first phase difference detection unit 101a-2 is output to the digital signal processing unit 102. Also, the first phase difference detection unit 101a-M detects the phase difference between the signal obtained by multiplying the master clock by the multiplier 105 and the signal of the atomic clock 2-M. The signal indicating the phase difference detected by the first phase difference detection unit 101a-M is output to the digital signal processing unit 102.

[0023] The second phase difference detection unit 101b detects the phase difference between the signal generated by the multiplier 105 and the master clock generated by the reference signal generation unit 104. The signal indicating the phase difference detected by the second phase difference detection unit 101b is output to the digital signal processing unit 102.

[0024] Note that, for example, an ADC can be used as the second phase difference detection unit 101b. When the second phase difference detection unit 101b is an ADC, this ADC converts the master clock from an analog signal to a digital signal and outputs it to the digital signal processing unit 102. At this time, by using the signal obtained by multiplying the master clock by the multiplier 105 as the sampling clock of the ADC, the output phase of the second phase difference detection unit 101b becomes a value depending on the passing characteristics of the multiplier 105.

[0025] The digital signal processing unit 102 generates frequency phase control data based on the phase difference detected by the first phase difference detection unit 101a and the phase difference detected by the second phase difference detection unit 101b. The frequency phase control data is data for controlling the frequency and phase of the master clock output from the master clock generation device 1. The frequency phase control data generated by this digital signal processing unit 102 is output to the signal synthesis unit 103.

[0026] More specifically, first, the digital signal processing unit 102 calculates the phase difference by performing FFT (Fast Fourier Transform) analysis on the signal indicating the phase difference detected by the first phase difference detection unit 101a and the signal indicating the phase difference detected by the second phase difference detection unit 101b. Then, the digital signal processing unit 102 generates frequency phase control data based on the detected phase difference. At this time, the digital signal processing unit 102 generates, as the frequency phase control data, data for reducing the phase difference detected by the first phase difference detection unit 101a and reducing the change associated with the temperature characteristics in the multiplier 105 based on the phase difference detected by the second phase difference detection unit 101b.

[0027] Also, the digital signal processing unit 102 may have a function of improving the short-term and long-term frequency stability of the master clock by adjusting the control period of the master clock with the frequency phase control data. That is, the digital signal processing unit 102 may generate, as the frequency phase control data, data for reducing the control timing deviation in the signal synthesis unit 103 based on the phase difference detected by the second phase difference detection unit 101b.

[0028] Also, when signals of a plurality of atomic clocks 2 are input to the master clock generation device 1, the digital signal processing unit 102 may have a function of generating an ensemble time scale based on the phase information of the plurality of atomic clocks 2. That is, the digital signal processing unit 102 may generate frequency phase control data based on the ensemble time scale based on the phase information, which is the phase difference detected by the first phase difference detection unit 101a of each system. Regarding the method for generating the ensemble time scale by this digital signal processing unit 102, for example, the method disclosed in Non-Patent Document 1 can be used, and a detailed description thereof is omitted.

[0029] Furthermore, the digital signal processing unit 102 may have a function of detecting the stop, phase jump, frequency jump, and deterioration of frequency stability of the atomic clock signal due to the abnormality of the atomic clock 2 based on the phase information detected by the first phase difference detection unit 101a of each system. Regarding the various abnormality detection methods by this digital signal processing unit 102, for example, the method disclosed in Non-Patent Document 1 can be used, and a detailed description thereof is omitted. When the digital signal processing unit 102 detects an abnormality of the atomic clock 2, it avoids the influence on the master clock by setting the weight of the atomic clock 2 to zero in the weighted average process.

[0030] The signal synthesis unit 103 controls the frequency and phase of the output signal to the reference signal generation unit 104 based on the frequency phase control data generated by the digital signal processing unit 102.

[0031] Note that, for example, a DDS (Direct Digital Synthesizer) or an NCO (Numerically Controlled Oscillator) can be used as the signal synthesis unit 103. When the signal synthesizer 103 is a DDS, this DDS uses, for example, as shown in FIG. 1, the signal obtained by multiplying the master clock by the multiplier 105 as the drive clock, and controls the frequency and phase of the output signal at the control timing depending on the frequency stability of the master clock, and outputs it to the reference signal generator 104.

[0032] The reference signal generator 104 generates a master clock according to the output signal from the signal synthesizer 103. This master clock is a master clock of 10.23 MHz with high frequency stability as described above. The master clock generated by this reference signal generator 104 is output to the outside of the master clock generation device 1, the second phase difference detector 101b, and the multiplier 105.

[0033] As the reference signal generator 104, for example, a PLL (Phase Locked Loop) circuit that phase-locks a VCXO (Voltage Controlled crystal Oscillator) to the output signal from the signal synthesizer 103 can be used. When the reference signal generator 104 is a PLL circuit, this PLL circuit detects an error signal corresponding to the phase difference between the output signal from the signal synthesizer 103 and the VCXO by a phase comparator, integrates the error signal with a loop filter to obtain a control voltage for the VCXO, and performs feedback control so that the output frequency of the VCXO follows the output frequency of the signal synthesizer 103.

[0034] Also, f0 in FIG. 1 indicates the frequency of the master clock generated by the reference signal generator 104.

[0035] The multiplier 105 generates a signal with a frequency that is a multiple of the master clock based on the master clock generated by the reference signal generation unit 104. In FIG. 1, a case is shown where the multiplier 105 generates a signal with a frequency that is N times the frequency of the master clock. That is, in FIG. 1, the frequency of the signal generated by the multiplier 105 is N×f0. Note that N is an integer of 2 or more. The signal generated by this multiplier 105 is output to the first phase difference detection unit 101a, the second phase difference detection unit 101b, and the signal synthesis unit 103. Then, the signals output to the first phase difference detection unit 101a and the second phase difference detection unit 101b are used as sampling clocks, and the signal output to the signal synthesis unit 103 is used as a drive clock.

[0036] Next, an operation example of the master clock generation device 1 according to Embodiment 1 shown in FIG. 1 will be described. Here, it is assumed that the first phase difference detection unit 101a and the second phase difference detection unit 101b are ADCs, and the reference signal generation unit 104 is a PLL circuit.

[0037] First, signals with good long-term frequency stability generated by a plurality of atomic clocks 2 of each system are respectively input to the corresponding first phase difference detection unit 101a of each system in the master clock generation device 1. Note that the frequency of the signal of each atomic clock 2 of each system is, for example, 10 MHz.

[0038] The signals of each atomic clock 2 of each system are converted into digital signals in the first phase difference detection unit 101a of each system to detect the phase difference from the master clock. Here, since the first phase difference detection unit 101a of each system samples the signal of each atomic clock 2 (for example, a signal with a frequency of 10 MHz), a signal obtained by multiplying the master clock (a signal with a frequency of 10.23 MHz) by N by the multiplier 105 is used as a sampling clock. As a result, the digital signal output from the first phase difference detection unit 101a includes information on the phase difference between the atomic clock 2 and the master clock.

[0039] Then, FFT analysis is performed on the digital signals output from the first phase difference detection units 101a of each system in the digital signal processing unit 102. Here, the digital signal processing unit 102 can detect a value corresponding to the phase difference between the atomic clock 2 of each system and the master clock by calculating the phase value at the frequency (for example, 10 MHz) of the signal of the atomic clock 2 of each system through FFT analysis. Then, based on the above detection result, the digital signal processing unit 102 generates frequency-phase control data for the master clock and outputs it to the signal synthesis unit 103.

[0040] When there are a plurality of atomic clocks 2, by taking the weighted average of the respective phase differences between the plurality of atomic clocks 2 and the master clock, a phase value reflecting the frequency stability of each of the plurality of atomic clocks 2 can be detected. Therefore, the digital signal processing unit 102 may generate frequency-phase control data based on the ensemble time system.

[0041] Then, the signal synthesis unit 103 generates a signal with its frequency and phase adjusted based on the frequency-phase control data. At this time, it is desirable that the master clock generation device 1 drives the signal synthesis unit 103 with a signal obtained by multiplying the master clock by N, thereby controlling the frequency and phase at a timing depending on the frequency stability of the master clock and outputting it to the reference signal generation unit 104.

[0042] That is, in this case, in the master clock generation device 1 according to the first embodiment, the signals of the respective atomic clocks 2 are not used as the clocks for driving the signal synthesis unit 103. Therefore, in this case, the master clock generation device 1 according to the first embodiment can obtain the effect of avoiding the phase fluctuation of the master clock caused by the phase jump of the atomic clock 2.

[0043] Also, in the master clock generation device 1 according to Embodiment 1, by setting the frequency of the output signal from the signal synthesizing unit 103 to 10.23 MHz, in the PLL circuit which is the reference signal generation unit 104 in the subsequent stage, phase comparison can be directly performed with the output signal of the master clock. Therefore, in this case, in the master clock generation device 1 according to Embodiment 1, a feedback frequency divider is not required in the PLL circuit, and a master clock with low phase noise can be obtained. Furthermore, in this case, in the master clock generation device 1 according to Embodiment 1, by using a signal that is N times the master clock (a signal with a frequency of 10.23 MHz) as the drive clock of the signal synthesizing unit 103, the influence of the folding spur of the drive clock at the output frequency (10.23 MHz) of the signal synthesizing unit 103 can also be suppressed.

[0044] The 10.23 MHz signal whose frequency and phase are adjusted by this signal synthesizing unit 103 is input to the reference signal generation unit 104 and becomes the reference signal of the PLL circuit. Then, in the PLL circuit, phase comparison is performed between the reference signal and the master clock output from the VCXO, and based on the result, frequency control of the VCXO is performed, thereby performing PLL control in which the frequency of the master clock follows the frequency of the reference signal.

[0045] FIG. 2 is a diagram showing an example of the frequency stability of the atomic clock 2, VCXO, and master clock in Embodiment 1. In FIG. 2, the horizontal axis represents the average time, and the vertical axis represents the Allan standard deviation. Also, in FIG. 2, reference numeral 21 indicates the frequency stability of the atomic clock 2, reference numeral 22 indicates the frequency stability of the VCXO, and reference numeral 23 indicates the frequency stability of the master clock.

[0046] Frequency stability is represented by the characteristics of the Allan standard deviation with respect to the average time. And generally, the atomic clock 2 has characteristics of good long-term stability, and the VCXO has characteristics of good short-term stability. Then, as shown in FIG. 2, by setting the control period of the signal synthesizer 103 by the frequency-phase control data generated in the digital signal processing unit 102 to the time (time constant) at which the Allan standard deviations of the atomic clock 2 and the VCXO intersect, the short-term stability of the master clock follows the VCXO, and the long-term stability of the master clock follows the atomic clock 2. As a result, in the master clock generation device 1 according to the first embodiment, a master clock having good frequency stability can be obtained both in the short term and in the long term.

[0047] Next, the operation when there is a phase fluctuation of the master clock due to the temperature characteristics of the multiplier 105 will be described. When the ambient temperature of the master clock generation device 1 changes, the output phase changes in the multiplier 105 having a large temperature characteristic of the passing phase. Since the output signal of the multiplier 105 serves as the driving clock of the signal synthesizer 103, if the output phase changes in the multiplier 105, the control timing of the frequency and phase in the signal synthesizer 103 will fluctuate.

[0048] FIG. 3 is a diagram showing an example of the phase change of the atomic clock 2 and the master clock (before correction) in the first embodiment. In FIG. 3, the horizontal axis represents time, and the vertical axis represents phase. Also, in FIG. 3, reference numeral 31 indicates the phase of the atomic clock 2, and reference numeral 32 indicates the phase of the master clock (before correction).

[0049] As shown in this FIG. 3, due to the fluctuation of the output phase of the multiplier 105 during temperature change, the frequency (the slope of the phase change with respect to time) and phase (the offset of the vertical axis) of the master clock (before correction) deviate from the characteristics of the ideal time system of the atomic clock 2. Also, due to the phase fluctuation of the driving clock in the signal synthesizer 103 during temperature change, the control timing of the frequency and phase of the master clock (before correction) also deviates from the ideal control timing depending on the atomic clock 2.

[0050] On the other hand, the second phase difference detection unit 101b detects the phase difference before and after passing through the multiplier 105. Therefore, in the master clock generation device 1 according to the first embodiment, the temperature characteristics of the passing phase of the multiplier 105 can be measured. Therefore, the digital signal processing unit 102 generates frequency phase control data for reducing the change associated with the temperature characteristics of the passing phase of the multiplier 105, and outputs it to the signal synthesis unit 103. As a result, in the master clock generation device 1 according to the first embodiment, even if the ambient temperature of the master clock generation device 1 changes, a stable master clock can be generated.

[0051] Furthermore, the digital signal processing unit 102 generates frequency phase control data for reducing the change associated with the temperature characteristics of the passing phase of the multiplier 105 and reducing the deviation caused by the error in the control timing of the frequency and phase, so that, as shown in FIG. 3, the master clock can be made to match the characteristics of the ideal time system of the atomic clock 2.

[0052] As described above, the master clock generation device 1 according to the first embodiment controls the master clock so as to reduce the phase fluctuation caused by the temperature characteristics of the multiplier 105, thereby obtaining the effect of suppressing the deterioration of the frequency stability of the master clock when the temperature changes.

[0053] In the above, the case where the first difference detection unit 101a is the first phase difference detection unit 101a and the second difference detection unit 101b is the second phase difference detection unit 101b is shown. However, the present invention is not limited to this, and the first difference detection unit 101a may be the first frequency difference detection unit 101a and the second difference detection unit 101b may be the second frequency difference detection unit 101b.

[0054] The first frequency difference detection unit 101a detects the frequency difference between the signal obtained by multiplying the master clock by the multiplier 105 and the signal of the corresponding system atomic clock 2 based on these signals. The signal indicating the frequency difference detected by the first frequency difference detection unit 101a is output to the digital signal processing unit 102.

[0055] Note that, as the first frequency difference detection unit 101a, for example, a TIC (Time Interval Counter) can be used. When the first frequency difference detection unit 101a is a TIC, this TIC calculates the frequency difference by measuring the time interval between two input signals, and outputs the result as a digital signal to the digital signal processing unit 102.

[0056] The second frequency difference detection unit 101b detects the frequency difference between the signal generated by the multiplier 105 and the master clock generated by the reference signal generation unit 104. The signal indicating the phase difference detected by the second frequency difference detection unit 101b is output to the digital signal processing unit 102.

[0057] Note that, as the second frequency difference detection unit 101b, for example, a TIC can be used. When the second frequency difference detection unit 101b is a TIC, this TIC calculates the frequency difference by measuring the time interval between two input signals, and outputs the result as a digital signal to the digital signal processing unit 102.

[0058] And, in this case, the digital signal processing unit 102 generates frequency phase control data based on the frequency difference detected by the first frequency difference detection unit 101a and the frequency difference detected by the second frequency difference detection unit 101b, in the same manner as above.

[0059] As described above, according to the first embodiment, the master clock generation device 1 includes a reference signal generation unit 104 that generates a master clock, a multiplier 105 that generates a signal with a frequency multiplied by the master clock based on the master clock generated by the reference signal generation unit 104, a first differential detection unit 101a provided for each of one or more systems, that detects a phase difference or a frequency difference between the signal generated by the multiplier 105 and the signal of the atomic clock 2 of the corresponding system, a second differential detection unit 101b that detects a phase difference or a frequency difference between the signal generated by the multiplier 105 and the master clock generated by the reference signal generation unit 104, a digital signal processing unit 102 that generates frequency and phase control data which is data for controlling the frequency and phase of the master clock based on the detection result of the first differential detection unit 101a and the detection result of the second differential detection unit 101b, and a signal synthesizing unit 103 that controls the frequency and phase of the output signal to the reference signal generation unit 104 based on the frequency and phase control data generated by the digital signal processing unit 102. The reference signal generation unit 104 generates a master clock according to the output signal from the signal synthesizing unit 103. Thereby, the master clock generation device 1 according to the first embodiment can generate a stable master clock even when the temperature changes.

[0060] Second Embodiment. FIG. 4 is a block diagram showing a configuration example of the master clock generation device 1 according to the second embodiment. The master clock generation device 1 according to the second embodiment shown in FIG. 4 has, in addition to the master clock generation device 1 according to the first embodiment shown in FIG. 1, a first frequency conversion unit 106a and a second frequency conversion unit 106b for one or more systems. Regarding other configuration examples of the master clock generation device 1 according to the second embodiment shown in FIG. 4, they are the same as the configuration example of the master clock generation device 1 according to the first embodiment shown in FIG. 1, and only the different parts will be described with the same reference numerals.

[0061] The first frequency conversion unit 106a frequency-converts the signal into a signal with a lower frequency based on the master clock generated by the reference signal generation unit 104 and the signal of the corresponding system atomic clock 2. The signal after frequency conversion by this first frequency conversion unit 106a is output to the first phase difference detection unit 101a of the corresponding system.

[0062] Also, in FIG. 4, the case where the master clock generation device 1 includes the first frequency conversion units 106a (first frequency conversion units 106a-1 to 106a-M) of M systems is shown.

[0063] That is, in the example of FIG. 4, the first frequency conversion unit 106a-1 frequency-converts the signal into a signal with a lower frequency based on the master clock generated by the reference signal generation unit 104 and the signal of the atomic clock 2-1. The signal after frequency conversion by this first frequency conversion unit 106a-1 is output to the first phase difference detection unit 101a-1. Also, the first frequency conversion unit 106a-2 frequency-converts the signal into a signal with a lower frequency based on the master clock generated by the reference signal generation unit 104 and the signal of the atomic clock 2-2. The signal after frequency conversion by this first frequency conversion unit 106a-2 is output to the first phase difference detection unit 101a-2. Also, the first frequency conversion unit 106a-M frequency-converts the signal into a signal with a lower frequency based on the master clock generated by the reference signal generation unit 104 and the signal of the atomic clock 2-M. The signal after frequency conversion by this first frequency conversion unit 106a-M is output to the first phase difference detection unit 101a-M.

[0064] The second frequency conversion unit 106b frequency-converts the master clock into a signal with a lower frequency based on the master clock generated by the reference signal generation unit 104. The signal after frequency conversion by this second frequency conversion unit 106b is output to the second phase difference detection unit 101b.

[0065] The first phase difference detection unit 101a detects the phase difference between the signal generated by the multiplier 105 and the signal after frequency conversion by the first frequency conversion unit 106a of the corresponding system.

[0066] That is, in the example of FIG. 4, the first phase difference detection unit 101a-1 detects the phase difference between the signal generated by the multiplier 105 and the signal after frequency conversion by the first frequency conversion unit 106a-1. Also, the first phase difference detection unit 101a-2 detects the phase difference between the signal generated by the multiplier 105 and the signal after frequency conversion by the first frequency conversion unit 106a-2. Also, the first phase difference detection unit 101a-M detects the phase difference between the signal generated by the multiplier 105 and the signal after frequency conversion by the first frequency conversion unit 106a-M.

[0067] Also, the second phase difference detection unit 101b detects the phase difference between the signal generated by the multiplier 105 and the signal after frequency conversion by the second frequency conversion unit 106b.

[0068] Next, a configuration example of the first frequency conversion unit 106a and the second frequency conversion unit 106b will be described with reference to FIG. 5. FIG. 5 is a block diagram showing a configuration example of the first frequency conversion units 106a-1 to 106a-M and the second frequency conversion unit 106b shown in FIG. 4. In FIG. 5, the frequency of the master clock is f0, the frequency of the signal of the atomic clock 2-1 is f1, the frequency of the signal of the atomic clock 2-2 is f2, and the frequency of the signal of the atomic clock 2-M is f M is.

[0069] As shown in FIG. 5, the first frequency conversion unit 106a includes a PLL circuit 1061a and a mixer 1062a.

[0070] The PLL circuit 1061a generates an LO signal based on the master clock generated by the reference signal generation unit 104. The LO signal generated by this PLL circuit 1061a is output to the mixer 1062a of the corresponding system.

[0071] In the example of FIG. 5, the PLL circuit 1061a-1 generates an LO signal based on the master clock generated by the reference signal generation unit 104. In FIG. 5, the frequency of the LO signal generated by the PLL circuit 1061a-1 is f1 + f b and is. The LO signal generated by this PLL circuit 1061a-1 is output to the mixer 1062a-1. Also, the PLL circuit 1061a-2 generates an LO signal based on the master clock generated by the reference signal generation unit 104. In FIG. 5, the frequency of the LO signal generated by the PLL circuit 1061a-2 is f2 + f b and is. The LO signal generated by this PLL circuit 1061a-2 is output to the mixer 1062a-2. Also, the PLL circuit 1061a-M generates an LO signal based on the master clock generated by the reference signal generation unit 104. In FIG. 5, the frequency of the LO signal generated by the PLL circuit 1061a-M is f M + f b and is. The LO signal generated by this PLL circuit 1061a-M is output to the mixer 1062a-M.

[0072] The mixer 1062a is driven by the LO signal generated by the PLL circuit 1061a of the corresponding system, and converts the signal of the atomic clock 2 of the corresponding system into a signal with a lower frequency (beat signal). The signal obtained by this mixer 1062a is output to the first phase difference detection unit 101a of the corresponding system.

[0073] In the example of Fig. 5, mixer 1062a-1 is driven by the LO signal generated by PLL circuit 1061a-1 to convert the signal of atomic clock 2-1 into a signal with a lower frequency (beat signal). In Fig. 5, the frequency of the signal obtained by mixer 1062a-1 is f b This is the case. The signal obtained by this mixer 1062a-1 is output to the first phase difference detection unit 101a-1. Also, mixer 1062a-2 is driven by the LO signal generated by PLL circuit 1061a-2 to convert the signal of atomic clock 2-2 into a signal with a lower frequency (beat signal). In Fig. 5, the frequency of the signal obtained by mixer 1062a-2 is f b This is the case. The signal obtained by this mixer 1062a-2 is output to the first phase difference detection unit 101a-2. Also, mixer 1062a-M is driven by the LO signal generated by PLL circuit 1061a-M to convert the signal of atomic clock 2-M into a signal with a lower frequency (beat signal). In Fig. 5, the frequency of the signal obtained by mixer 1062a-M is f b This is the case. The signal obtained by this mixer 1062a-M is output to the first phase difference detection unit 101a-M.

[0074] As shown in Fig. 5, the second frequency conversion unit 106b includes a PLL circuit 1061b and a mixer 1062b.

[0075] Based on the master clock generated by the reference signal generation unit 104, PLL circuit 1061b generates an LO signal. In Fig. 5, the frequency of the LO signal generated by PLL circuit 1061b is f0 + f b This is the case. The LO signal generated by this PLL circuit 1061b is output to mixer 1062b.

[0076] Driven by the LO signal generated by PLL circuit 1061b, mixer 1062b converts the master clock generated by the reference signal generation unit 104 into a signal with a lower frequency (beat signal). In Fig. 5, the frequency of the signal obtained by mixer 1062b is fb It is. The signal obtained by this mixer 1062b is output to the second phase difference detector 101b.

[0077] As shown in FIG. 5, in the first frequency conversion unit 106a, the frequency of the signal of the atomic clock 2 (for example, 10 MHz) is converted into a beat signal of a lower frequency (for example, 1 kHz) via a mixer 1062a driven by an LO signal (for example, a signal of 10.001 MHz) generated by the PLL circuit 1061a. The beat signal obtained by this first frequency conversion unit 106a is input to the first phase difference detector 101a and converted into a digital signal. Similarly, in the second frequency conversion unit 106b, the frequency of the master clock (10.23 MHz) is converted into a beat signal of a lower frequency (for example, 1 kHz) via a mixer 1062b driven by an LO signal (for example, a signal of 10.231 MHz) generated by the PLL circuit 1061b. The beat signal obtained by this second frequency conversion unit 106b is input to the second phase difference detector 101b and converted into a digital signal. Thus, in the master clock generation device 1 according to the second embodiment, the frequencies of the input signals to the first phase difference detector 101a and the second phase difference detector 101b are converted to lower frequencies. Thereby, in the master clock generation device 1 according to the second embodiment, the detection accuracy of the phase difference can be improved by the frequency conversion ratio (10,000 times in the above example).

[0078] Note that, in the operation example of the master clock generation device 1 according to the second embodiment, the operation examples after the phase difference detection operation in the first phase difference detector 101a and the second phase difference detector 101b are the same as those in the first embodiment, and the description thereof is omitted.

[0079] In the above description, the case where the first difference detection unit 101a is the first phase difference detection unit 101a and the second difference detection unit 101b is the second phase difference detection unit 101b has been shown. However, the present invention is not limited to this, and the same applies to the case where the first difference detection unit 101a is the first frequency difference detection unit 101a and the second difference detection unit 101b is the second frequency difference detection unit 101b as in Embodiment 1.

[0080] As described above, according to this Embodiment 2, the master clock generation device 1 includes a reference signal generation unit 104 that generates a master clock, a multiplier 105 that generates a signal obtained by multiplying the frequency of the master clock based on the master clock generated by the reference signal generation unit 104, one or more first frequency conversion units 106a provided for each of one or more systems, and based on the master clock generated by the reference signal generation unit 104 and a signal from the corresponding system's atomic clock 2, frequency-converts the signal to a lower-frequency signal, a second frequency conversion unit 106b that frequency-converts the master clock to a lower-frequency signal based on the master clock generated by the reference signal generation unit 104, a first difference detection unit 101a provided for each system that detects a phase difference or a frequency difference between the signal generated by the multiplier 105 and the signal after frequency conversion by the corresponding system's first frequency conversion unit 106a, a second difference detection unit 101b that detects a phase difference or a frequency difference between the signal generated by the multiplier 105 and the signal after frequency conversion by the second frequency conversion unit 106b, a digital signal processing unit 102 that generates frequency phase control data, which is data for controlling the frequency and phase of the master clock, based on the detection result by the first difference detection unit 101a and a signal indicating the detection result by the second difference detection unit 101b, and a signal synthesizing unit 103 that controls the frequency and phase of the output signal to the reference signal generation unit 104 based on the frequency phase control data generated by the digital signal processing unit 102. The reference signal generation unit 104 generates a master clock in response to the output signal from the signal synthesizing unit 103. That is, in the master clock generation device 1 according to Embodiment 2, the frequency of the signal of the atomic clock 2 is frequency-converted to a lower frequency by the first frequency conversion unit 106a, and the frequency of the master clock is frequency-converted to a lower frequency by the second frequency conversion unit 106b, and then the DMTD (Dual Mixer Time Difference) method for detecting the phase difference or the frequency difference is used. As a result, in addition to the effects of the master clock generation device 1 according to Embodiment 1, the master clock generation device 1 according to Embodiment 2 can improve the detection accuracy of the phase difference or the frequency difference, and can further suppress the deterioration of the frequency stability of the master clock.

[0081] Finally, with reference to FIG. 6, a hardware configuration example of the master clock generation device 1 according to Embodiments 1 and 2 will be described. Hereinafter, a hardware configuration example of the master clock generation device 1 according to Embodiment 1 will be described, but the same applies to the hardware configuration example of the master clock generation device 1 according to Embodiment 2. The function of the digital signal processing unit 102 in the master clock generation device 1 is realized by the processing circuit 51. As shown in FIG. 6A, the processing circuit 51 may be dedicated hardware, or as shown in FIG. 6B, it may be a CPU (Central Processing Unit, also referred to as a central processing unit, a processing device, an arithmetic device, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor)) 52 that executes a program stored in the memory 53.

[0082] When the processing circuit 51 is dedicated hardware, the processing circuit 51 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof.

[0083] When the processing circuit 51 is the CPU 52, the functions of the digital signal processing unit 102 are realized by software, firmware, or a combination of software and firmware. The software and firmware are described as programs and stored in the memory 53. The processing circuit 51 realizes the functions of each part by reading and executing the programs stored in the memory 53. That is, the master clock generation device 1 includes a memory 53 for storing a program that, when executed by the processing circuit 51, will result in the execution of the processing of the digital signal processing unit 102. Also, these programs can be said to cause a computer to execute the procedures and methods of the digital signal processing unit 102. Here, examples of the memory 53 include non-volatile or volatile semiconductor memories such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), and EEPROM (Electrically EPROM), magnetic disks, flexible disks, optical disks, compact disks, mini disks, or DVDs (Digital Versatile Discs).

[0084] Note that free combinations of the embodiments, modifications of any components of the embodiments, or omissions of any components in the embodiments are possible.

Industrial Applicability

[0085] The master clock generation device according to the present disclosure can generate a stable master clock even when the temperature changes, and is suitable for use in a master clock generation device that generates a master clock and the like.

Explanation of Reference Numerals

[0086] 1 Master clock generation device, 2,2-1 to 2-M atomic clocks, 51 Processing circuit, 52 CPU, 53 Memory, 101a, 101a-1 to 101a-M First phase difference detection unit (first difference detection unit), 101b Second phase difference detection unit (second difference detection unit), 102 Digital signal processing unit, 103 Signal synthesis unit, 104 Reference signal generation unit, 105 Multiplier, 106a, 106a-1 to 106a-M First frequency conversion unit, 106b Second frequency conversion unit, 1061a, 1061a-1 to 1061a-M PLL circuits, 1061b PLL circuit, 1062a, 1062a-1 to 1062a-M Mixers, 1062b Mixer.

Claims

1. A reference signal generation unit that generates a master clock; A multiplier that generates a signal with a frequency multiplied by the frequency of the master clock based on the master clock generated by the reference signal generation unit; A first difference detection unit provided for each of one or more systems, which detects a phase difference or a frequency difference between the signal generated by the multiplier and the signal of the corresponding system's atomic clock based on the signal generated by the multiplier and the signal of the corresponding system's atomic clock; A second difference detection unit that detects a phase difference or a frequency difference between the signal generated by the multiplier and the master clock generated by the reference signal generation unit based on the signal generated by the multiplier and the master clock generated by the reference signal generation unit; A digital signal processing unit that generates frequency and phase control data, which is data for controlling the frequency and phase of the master clock, based on the detection result by the first difference detection unit and the detection result by the second difference detection unit; A signal synthesis unit that controls the frequency and phase of the output signal to the reference signal generation unit based on the frequency and phase control data generated by the digital signal processing unit, and the reference signal generation unit generates a master clock according to the output signal from the signal synthesis unit. A master clock generation device characterized by the above.

2. A reference signal generation unit that generates a master clock; A multiplier that generates a signal with a frequency multiplied by the frequency of the master clock based on the master clock generated by the reference signal generation unit; One or more first frequency conversion units provided for each of one or more systems, which frequency-convert the signal based on the master clock generated by the reference signal generation unit and the signal from the corresponding system's atomic clock into a signal with a lower frequency; A second frequency conversion unit that frequency-converts the master clock into a signal with a lower frequency based on the master clock generated by the reference signal generation unit; A first difference detection unit provided for each system, which detects a phase difference or a frequency difference between the signal generated by the multiplier and the signal after frequency conversion by the corresponding system's first frequency conversion unit based on the signal generated by the multiplier and the signal after frequency conversion by the corresponding system's first frequency conversion unit; A second difference detection unit that detects a phase difference or a frequency difference between the signal generated by the multiplier and the signal after frequency conversion by the second frequency conversion unit based on the signal generated by the multiplier and the signal after frequency conversion by the second frequency conversion unit; A digital signal processing unit that generates frequency and phase control data, which is data for controlling the frequency and phase of a master clock, based on the detection result by the first difference detection unit and the detection result by the second difference detection unit; A signal synthesizing unit that controls the frequency and phase of the output signal to the reference signal generating unit based on the frequency and phase control data generated by the digital signal processing unit; The reference signal generating unit generates a master clock in response to the output signal from the signal synthesizing unit A master clock generation device characterized by the above.

3. The digital signal processing unit generates, as the frequency and phase control data, data for reducing changes associated with the temperature characteristics in the multiplier. The master clock generation device according to claim 1 or claim 2, characterized by the above.

4. The digital signal processing unit generates, as the frequency and phase control data, data for reducing the deviation of the control timing in the signal synthesizing unit. The master clock generation device according to claim 3, characterized by the above.

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