Improvement of the Lifetime and Coherence of Superconducting Quantum Bits by Backside Etching

Abstract

A method for improving the lifetime and coherence time of a qubit in a quantum mechanical device is provided. The method includes providing a substrate having a front surface and a back surface, the front surface having at least one qubit formed thereon, the at least one qubit having a capacitor pad. The method further includes at least one of removing a predetermined amount of substrate material from an area of ​​the back surface of the substrate opposite the at least one qubit, or depositing a superconducting metal layer on the back surface of the substrate opposite the at least one qubit, to reduce high frequency current losses through at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, to increase the lifetime (T1) and coherence time (T2) of the at least one qubit.

Description

Technical Field

[0001] Embodiments of the present invention currently claimed relate to superconducting quantum mechanical devices, and more particularly, to methods for improving the lifetime and coherence time of qubits in quantum mechanical devices, and to quantum mechanical devices having one or more qubits with improved lifetime and coherence time.

Background Art

[0002] In superconducting quantum computing systems, the lifetime (T1) and coherence time (T2) of qubits are fundamental metrics for system performance, and a common goal is to create a system where T1 and T2 are as long as possible while maintaining appropriate interactions between the relevant qubits and quanta. Longer temporal metrics in quantum computers enable more complex calculations, so the longer the T1 and T2 times, the more advanced problems can be solved using a quantum computer. The T1 and T2 times have been improved by using front-side etching to reduce surface states present at the interfaces between various materials. Surface states cause high-frequency (RF: radiofrequency) losses that degrade both T1 and T2. Currently, front-side etching of qubits is used to reduce existing surface states proximate to the shunt capacitors of the qubits that interact with RF energy to produce losses. Such surface states that cause these losses can exist at the silicon-air (SA), silicon-metal (SM), and metal-air (MA) interfaces. The mechanism of RF loss can include contributions not only from the SA, SM, and MA surface states, but also from the loss tangent of bulk Si.

[0003] Conventionally, the performance specifications of qubits have been modified by front-side etching. However, front-side etching is undesirable because (i) it significantly perturbs the qubits when the intensity of the electromagnetic (e.g., microwave or high-frequency) field is very strong, (ii) the chip cannot perform front-side etching without debonding the chip and performing further processing when flip-chip bumps are bonded, and (iii) the bump bonding process itself may affect the final qubit performance evaluation criteria.

Summary of the Invention

[0004] Aspects of the present invention provide a method for improving the lifetime and coherence time of qubits in a quantum mechanical device. The method includes providing a substrate having a front surface and a back surface, where the front surface has at least one qubit formed thereon, and the at least one qubit has a capacitor pad, and removing a predetermined amount of substrate material from an area on the back surface of the substrate opposite the at least one qubit or depositing a superconducting metal layer on an area on the back surface of the substrate opposite the at least one qubit, at least one of which is to reduce high-frequency current loss by at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface to increase the lifetime (T1) and coherence time (T2) of the at least one qubit.

[0005] In one embodiment, reducing high-frequency current loss includes reducing current loss by increasing the high-frequency overlap with lower-loss geometric features of the quantum mechanical device and decreasing the high-frequency overlap with higher-loss geometric features of the quantum mechanical device.

[0006] In one embodiment, removing the substrate material from an area on the back surface of the substrate, on the opposite side of at least one qubit, includes selectively chemically etching the back surface of the substrate using a chemical etching solution selected according to the substrate material. In one embodiment, before chemically etching the back surface of the substrate, an initial recess is formed near at least one qubit on the back surface of the substrate by mechanically removing material from the back surface of the substrate, and then the initially formed recess on the back surface of the substrate is chemically etched. In one embodiment, forming an initial recess on the back surface of the substrate includes defining a surface of the initial recess having one or more first crystal planes and one or more second crystal planes, whereby the chemical etching solution preferentially etches the substrate material from the one or more first crystal planes but does not substantially etch the substrate material from the one or more second crystal planes, forming a final recess etched near at least one qubit.

[0007] In one embodiment, removing a predetermined amount of substrate material from the back surface of the substrate includes removing a predetermined amount of substrate material within an area on the back surface of the substrate and forming a trench near a gap between capacitor pads of at least one qubit. In one embodiment, removing a predetermined amount of substrate material within an area on the back surface of the substrate and forming a trench near a gap between capacitor pads of at least one qubit includes removing a predetermined amount of substrate material such that the trench is located substantially centered around the gap between capacitor pads of at least one qubit.

[0008] In one embodiment, removing a predetermined amount of substrate material such that the trench is located substantially centered around the gap between the capacitor pads of at least one qubit includes forming a trench to reduce the participation rate of surface states having an RF energy density at the silicon-metal (SM) interface and increasing the participation rate of surface states having an RF energy density at the silicon-air (SA) interface. In one embodiment, as the depth of the trench increases, the overlap of the RF energy density with the surface states at the silicon-metal (SM) interface decreases, and the overlap of the RF energy density of the surface states at the silicon-air (SA) interface increases.

[0009] In one embodiment, removing a predetermined amount of substrate material from the back surface of the substrate includes removing a predetermined amount of substrate material within the area of the back surface of the substrate and forming a trench in the vicinity of the gap between the capacitor pads of at least one qubit, and depositing a superconducting metal layer in the trench to reduce the high-frequency current loss due to the metal-air (MA) interface. In one embodiment, forming a trench in the vicinity of the gap between the capacitor pads of at least one qubit includes forming a trench that is centered under and around one of the capacitor pads of at least one qubit. In one embodiment, the high-frequency current loss due to the metal-air (MA) interface decreases based on the back surface width of the trench.

[0010] In one embodiment, removing substrate material from an area on the back surface of the substrate opposite at least one qubit includes attaching an etching mask film to the back surface of the substrate and etching a selected area on the back surface of the substrate opposite at least one qubit. In one embodiment, the method further includes forming one or more openings in a selected area of the etching mask film after attaching the etching mask film to the back surface of the substrate and before etching the selected area on the back surface of the substrate. In one embodiment, etching a selected area on the back surface of the substrate opposite at least one qubit includes chemically etching a desired thickness of the substrate in the selected area to form a trench in the selected area. In one embodiment, the method also includes depositing a superconducting metal layer in the trench.

[0011] In one embodiment, removing substrate material from an area on the back surface of the substrate opposite at least one qubit includes attaching a mask film to the back surface of the substrate and depositing a metal superconductor on the masked area of the back surface of the substrate.

[0012] Another aspect of the present invention is to provide a quantum mechanical device. The quantum mechanical device includes a substrate having a front surface and a back surface, and a plurality of qubits formed on the front surface of the substrate, the plurality of qubits having a plurality of capacitor pads. The substrate includes at least one trench formed on the back surface of the substrate opposite at least one of the plurality of qubits, and at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, or any combination thereof, to reduce high-frequency current loss in order to increase the lifetime (T1) and coherence time (T2) of at least one qubit. At least one of the size, shape, or position of at least one trench or the superconducting material deposited in the trench is selected.

[0013] In one embodiment, the substrate is selected from the group consisting of silicon, high-resistivity silicon, and sapphire. In one embodiment, the plurality of capacitor pads are made of a superconducting material. In one embodiment, the superconducting material can be one of aluminum (Al) and niobium (Nb).

[0014] In one embodiment, the trench is provided in the vicinity of the gap between two of the plurality of capacitor pads. In one embodiment, the trench is located approximately at the center around the gap so as to reduce the energy density of the surface state of the silicon-metal (SM) interface and increase the energy density of the surface state of the silicon-air (SA) interface.

[0015] In one embodiment, the superconducting metal layer is provided in the trench to reduce the high-frequency current loss due to the metal-air (MA) interface. In one embodiment, the trench is formed to be located under and around the center of one or more of the plurality of capacitor pads.

[0016] The patent or application file includes at least one drawing created in color. Upon request and payment of the required fee, a copy of this patent or patent application publication including the color drawing will be provided by the Office(R).

[0017] Not only this disclosure, but also the operating methods and functions of the related elements of the structure, the combinations of components, and the manufacturing economy, all of which form part of this specification, will become clearer when considering the following description and the appended claims with reference to the accompanying drawings, in which the same reference numerals represent corresponding parts in the various figures. However, it should be clearly understood that the drawings are for illustrative and explanatory purposes only and are not intended as a definition limiting the present invention.

Brief Description of the Drawings

[0018]

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Embodiments for Carrying Out the Invention

[0019] In embodiments of the present invention, the RF overlap with the interfaces of bulk silicon, air, and various materials can be modified by backside etching or a metal coating on the grounded backside, or both. The severity of various loss mechanisms (i.e., the loss tangent of bulk silicon, the surface states of SA, MA, and SM) varies, and the total RF loss of the qubit is basically a weighted average of the RF overlap with various loss mechanisms related to specific geometric features of the qubit.

[0020] By increasing the RF overlap with low-loss geometric features and decreasing the overlap with more lossy features, there is an opportunity to increase (e.g., maximize) the lifetime (T1) and coherence time (T2) by reducing (e.g., minimizing) the overall loss.

[0021] To realize the same physical structure, different process flows may be implemented. Also, different processing protocols may be used if the manufacturing lines are different. Both of these issues can change which material interfaces contribute the most to RF loss. Thus, the most concerning material interfaces can vary depending on the choice of specific processes performed during manufacturing.

[0022] Therefore, to reduce (e.g., minimize) RF loss, it can be beneficial to have a flexible strategy that manipulates the amount of RF overlap with various geometric features within the qubit to adapt to the various potential loss mechanisms that can occur with different process flows, with the goal of minimizing the overall loss.

[0023] As further explained in the following paragraphs, an increase or enhancement (e.g., maximization) of T1 and T2 in a superconducting qubit system can be achieved by using two device modification techniques. The first technique involves etching the substrate from the backside of the qubit or the qubit chip. The second technique involves metallizing and grounding the backside of the qubit or the qubit chip. These two techniques can be implemented separately or individually, or together if needed, depending on the specific situation.

[0024] As shown in the following paragraphs, simulations have shown that, similar to bulk silicon, fully back-etched qubits can also reduce the RF overlap (or RF participation factor) with silicon-air (SA) and silicon-metal (SM) surface states. However, due to the geometry of the fully back-etched device, the metal-air (MA) overlap increases. By appropriately etching the back surface of the chip adjacent to the qubit, coating the back surface of the chip with a metal film, and optionally grounding the back surface of the chip, the MA overlap can be reduced (minimized). Therefore, if the contribution of RF interference due to the MA interface to losses is smaller than that of, for example, bulk Si, as well as the contributions of SA and SM, overall improvements in T1 and T2 can be achieved when the back surface of the qubit is fully etched. If the RF losses due to the MA interface contribute more significantly to the RF losses compared to the contributions of bulk Si, as well as SA and SM, the back surface of the chip can be appropriately etched, coated with a metal film made of a superconductor, and optionally grounded to minimize the overall RF losses. In the previous paragraph, the substrate is often referred to as silicon (Si) or bulk Si as an example. However, as will be understood and further explained in the following paragraphs, other materials such as high-resistivity silicon and sapphire can also be used.

[0025] Figure 1(A) is a schematic cross-sectional view of a qubit device 100 according to an embodiment of the present invention. As shown in Figure 1(A), the qubit device 100 includes a Josephson junction 102 and capacitor pads 104A and 104B. The Josephson junction 102 is connected to the capacitor pads 104A and 104B. The capacitor pads 104A and 104B can be further capacitively coupled to electromagnetic (e.g., microwave or high-frequency) signal lines 106A, 106B, and 106C via, for example, capacitors 108A, 108B, and 108C.

[0026] Figure 1(B) is an electron microscope (EM) image of a Josephson junction according to an embodiment of the present invention. In one embodiment, the Josephson junction can have a size of about 100×100 nm 2 .

[0027] Figure 1(C) is an electrical diagram of a qubit device 100 coupled to an electromagnetic signal line via capacitors 108A, 108B, and 108C according to an embodiment of the present invention. The Josephson junction 102 has an internal capacitance C j and an internal inductance L j (e.g., L j is about 20 nH and C j is about 1 fF). However, it should be understood that the internal inductance L j and internal capacitance C j of the Josephson junction may have other values depending on the structure of the Josephson junction 102. The qubit 100 also has a coupling capacitance or signal capacitance C j due to capacitor pads 104A and 104B in addition to the internal capacitance C s of the Josephson junction. In one embodiment, the capacitance C s (due to capacitor pads 104A and 104B) can be about 60 fF. However, the capacitance C s may also have other values depending on the size, geometry, or shape of capacitor pads 104A and 104B.

[0028] In one embodiment, the resonance frequency is determined by the capacitive and resistive contributions from both the Josephson junction (including internal capacitance C j and internal inductance L j ) and the associated capacitor C s due to capacitor pads 104A and 104B. Thus, for example, the first resonance frequency f 01It depends on the capacitance of the device and can be mathematically expressed by the following formula (1). For example, the subscript "0" indicates the ground state of the Josephson junction 102, and the subscript "1" indicates the first excited state of the Josephson junction 102.

Number

Number

Number

Number

[0029] Therefore, by changing the high - frequency field distribution related to the capacitance C s including the contribution of the capacitance C Σ the resonance frequency of the qubit (for example, the first resonance frequency f 01) can be changed or varied to alter the overlap (or participation rate) with a loss source associated with at least one of the silicon-air (SA) interface, metal-air (MA) interface, or silicon-metal (SM) interface of the high-frequency current, thereby reducing the overall amount of high-frequency loss to increase the lifetime (T1) and coherence time (T2) in at least one qubit.

[0030] FIG. 2 is a contour plot of a simulated two-dimensional electric field generated by capacitor pads 104A and 104B connected to Josephson junction 102, according to one embodiment of the present invention. The two capacitor pads 104A and 104B of qubit 100 are represented by bars in FIG. 2. The Josephson junction 102 (not shown) is located between the two bars 104A and 104B. For example, the left bar corresponding to capacitor pad 104A can be connected to zero potential, while the right bar corresponding to capacitor pad 104B can be connected to a higher potential of 1 V (as a result, for example, an electric field strength of about 7×10 3 V / m could be obtained). In FIG. 2, an electrical contour plot is superimposed on the representation of capacitor pads 104A, 104B, which are part of the quantum mechanical device 200. Qubit 100 is also part of the quantum mechanical device 200, which includes a substrate 202. The substrate 202 has a front surface 202A and a back surface 202B. The capacitor pads 104A and 104B represented by bars in FIG. 2, and the Josephson junction 102 located between the two capacitor pads 104A and 104B of qubit 100, are located on the front surface 200A of the substrate 202 of the quantum mechanical device 200.

[0031] The change in the electric field distribution indicates the change in the effective dielectric constant of the substrate 202. The capacitance of the quantum mechanical device 200 is related to the effective dielectric constant of the substrate 202. The change in the electric field distribution can be implemented by changing the thickness of the substrate 202 at a specific location of the substrate 202. This can be carried out, for example, by etching the substrate 202 from the back surface 202B, that is, by removing the substrate material from the back surface 202B. The change in the electric field distribution due to the etching at the back surface 202B of the substrate 202 indicates the change in the capacitance of the quantum mechanical device.

[0032] FIG. 3 is a schematic top view of a qubit device 100 showing the relative positions of capacitor pads 104A and 104B and Josephson junctions (JJs) 102 according to an embodiment of the present invention. The qubit device 100 is surrounded by a ground plane 300, which is part of the quantum mechanical device 200.

[0033] Figures 4A - 4C are contour diagrams of the potential distribution around capacitor pads 104A and 104B according to an embodiment of the present invention. Figure 4A is a contour diagram of a simulated two - dimensional electric field generated by capacitor pads 104A and 104B connected to Josephson junction 102 along cross - section line 4 - 4 shown in Figure 3. Using electrostatic calculations, the overlap of the RF energy density with various surface states can be estimated. Since the RF wavelength is much larger than the geometric dimensions of the device, this is a reasonable approach. Equipotential lines 400 are drawn around the ends of capacitor pads 104A and 104B. Figure 4A shows the potential distribution around Josephson junction 102 with the back surface 202B of the substrate 202 of the quantum mechanical device 200 not etched. The ends of capacitor pads 104A, 104B can be recognized by the higher concentration of potential 400. Josephson junction 102 is located between the end of capacitor pad 104A and the end of capacitor pad 104B. Figure 4B shows the potential distribution around Josephson junction 102. Josephson junction 102 is still located between the end of capacitor pad 104A and the end of capacitor pad 104B. However, as shown in Figure 4B, the back surface 202B of the substrate 202 is etched in the vicinity of Josephson junction 102. The profile of the etched material of the substrate 202 is shown by a trapezoidal shape 402, and more material is removed in the vicinity of Josephson junction 102 than away from it. The removal of material on the back surface 202B of the substrate 202 modifies the shape of the equipotential lines 400, thereby modifying the potential distribution around or in the vicinity of Josephson junction 102. Thus, this shows that the capacitance of the qubit 100 around Josephson junction 102 as well as capacitor pads 104A and 104B is changed. Figure 4C shows the potential distribution around Josephson junction 102. Josephson junction 102 is still located between the end of capacitor pad 104A and the end of capacitor pad 104B.As shown in FIG. 4C, the back surface 202B of the substrate 202 is etched even more in the vicinity of the Josephson junction 102 as compared with the etching profile shown in FIG. 4B. The profile of the etched material of the substrate 202 is shown in a trapezoidal shape 404, and more material is removed in the vicinity of the Josephson junction 102 as compared with the trapezoidal profile 402 shown in FIG. 4B. The removal of the material at the back surface 202B of the substrate 202 modifies the shape of the equipotential line 400, thereby modifying the distribution of the potential in the vicinity or around the Josephson junction 102. Therefore, this indicates that the capacitance of the qubit around the Josephson junction 102 and the capacitor pads 104A and 104B is changed even more as compared with FIG. 4B.

[0034] FIG. 5A shows a graph of the surface state energy density versus the etching depth (μm) corresponding to the amount of substrate material removed at the back surface 202B of the substrate 202 according to an embodiment of the present invention. The curve 502 in FIG. 5A shows the change in the surface state energy density of the silicon-air (SA) interface as a function of the etching depth. The curve 504 in FIG. 5A shows the change in the surface state energy density of the silicon-metal (SM) interface as a function of the etching depth. The curve 506 in FIG. 5A shows the change in the surface state energy density of the metal-air (MA) interface as a function of the etching depth.

[0035] As shown in FIG. 5A, when more material is removed from the back surface of the qubit 100 to form trenches 402, 404, as shown in FIGS. 4A - 4C, as the depth increases, the participation rate of the surface state having the RF energy density at the silicon - air (SA) interface increases (curve 502). As shown in FIG. 5A, when more material is removed from the back surface of the qubit to form trenches, as shown in FIGS. 4A - 4C, as the depth increases, the participation rate of the surface state having the RF energy density at the silicon - metal (SM) interface decreases (curve 504). As shown in FIG. 5A, when more material is removed from the back surface of the qubit to form trenches, as shown in FIGS. 4A - 4C, as the depth increases, the participation rate of the surface state having the RF energy density at the metal - air (MA) interface remains substantially flat or constant (curve 506). The point "PA" in FIG. 5A corresponds to the configuration shown in FIG. 4A where no material has been removed from the back surface 202B of the substrate 202. The point "PB" in FIG. 5A corresponds to the configuration shown in FIG. 4B where relatively little material has been removed from the back surface 202B of the substrate 202. The point "PC" in FIG. 5A corresponds to the configuration shown in FIG. 4C where relatively more material has been removed from the back surface 202B of the substrate 202. The point "PC" corresponds to the configuration shown in FIG. 4C where substantially no material remains in the area directly under the Josephson junction. At the point "PC", the curve 502 drops sharply.

[0036] As shown in FIG. 5A, the RF overlap with the SA surface state decreases by more than about 90%, the RF overlap with the SM surface state decreases by more than about 90%, and the RF overlap with the MA surface state increases by more than about 2 - fold.

[0037] Figure 5B shows the bulk energy density versus the etching depth (μm) corresponding to the amount of substrate material removed from the back surface 202B of the substrate 202 according to an embodiment of the present invention. The curve 508 in Figure 5B shows the variation of the bulk energy density of silicon as a function of the etching depth. The curve 509 in Figure 5B shows the variation of the bulk energy density of air as a function of the etching depth. As shown in Figure 5B, as more material is removed from the back surface of the qubit 100 to form the trenches 402, 404, as shown in Figures 4A - 4C, the contribution rate of the bulk energy density of silicon decreases as the depth increases (curve 508). As shown in Figure 5B, as more material is removed from the back surfaces of the qubits 100, 200 to form the trenches 402, 404, as shown in Figures 4A - 4C, the contribution rate of the bulk energy density of air increases as the depth increases (curve 509). As shown in Figure 5B, at the point "PC", the RF overlap with silicon decreases from about 85% to about 15%, and the RF overlap with air increases by more than about 8 times to about 85%.

[0038] Figure 6 shows a graph of the percentage of MA versus the backside etching width according to an embodiment of the present invention. The term "backside etching width" as used herein refers to the width of the trapezoidal trench at the apex of the trapezoidal trench (i.e., the thinnest part of the substrate). The various curves in the graph of Figure 6 correspond to an increasing etching depth from the upper curve to the bottom curve as shown in the graph. For example, the upper curve corresponds to a substrate thickness (e.g., Si) of 25 μm at the apex of the trapezoidal trench, while the bottom curve corresponds to a substrate (e.g., Si) thickness of 2 μm at the apex of the trapezoidal trench. The variation in the percentage of MA as a function of the backside etching width is more pronounced at the deepest trench, i.e., the thinnest part of the substrate closest to the qubit, as shown by the bottom curve in Figure 6.

[0039] Figures 7A and 7B are contour diagrams of the potential distribution around capacitor pads 104A and 104B when a trench is formed under one of the capacitor pads according to an embodiment of the present invention. In one embodiment, as shown in Figures 7A and 7B, one of the capacitor pads is biased and the other capacitor pad is grounded. In one embodiment, the trench is disposed directly under the biased capacitor pad to change the electric field of the potential generated around a particular capacitor pad. In one embodiment, a metal layer can be deposited in the trench. The metal layer can be grounded. It should be noted that when the substrate is etched in this way, the capacitance increases, and accordingly, the operating frequency of the quantum bit changes. In order to maintain an appropriate operating frequency, the geometric features of the shunt capacitor can be modified to reduce the overall capacitance of the shunt capacitor and bring it closer to the operating frequency of an example of a non-etched device, which will have a further impact on the overlap factor with various surface state regions of the RF energy density.

[0040] Figure 7A shows a device profile that realizes the ratio of MA corresponding to the point "PL" in Figure 6. This device profile reduces the overlap with MA of the RF energy density by approximately 40% compared to a design that is not etched and has no metal on the back surface. This device profile is an exemplary representation of the concept that by appropriately modifying the geometry of the device profile, the overlap of the energy density with various types of surface states can be minimized. The RF overlap with silicon increases to approximately 95%. The RF overlap with air decreases to approximately 5%. The RF overlap with the SA surface state decreases by approximately 40%. The RF overlap with the SM surface state increases by approximately 40%. The RF overlap with the MA surface state decreases by approximately 40%.

[0041] Figure 7B shows a device profile that realizes the ratio of MA corresponding to the point "PM" in Figure 6. This device profile reduces the overlap of the RF energy density with MA by approximately 85% compared to a design that is not etched and has no metal on the back surface. This device profile is an exemplary representation of the concept that by appropriately modifying the geometry of the device profile, the overlap of the energy density with various types of surface conditions can be minimized. The RF overlap with silicon increases to approximately 99%. The RF overlap with air decreases to approximately 1%. The RF overlap with the SA surface condition decreases by approximately 85%. The RF overlap with the SM surface condition increases by approximately 14 times. The RF overlap with the MA surface condition decreases by approximately 85%.

[0042] FIG. 8 shows a schematic diagram of a plurality of qubits, each having a trench geometrically etched according to an embodiment of the present invention. As shown in FIG. 8, the geometric shape of the backside etching can be changed by changing the process flow used to perform the substrate backside etching, for example, in combination with dry etching using a chemical etchant such as KOH or TMAH. Additionally, various geometric profiles can be realized in the backside etching due to anisotropic etching and the resulting features of self-limiting etching. For example, the substrate material can be removed from the backside of the substrate in an area opposite at least one qubit by using selective chemical etching. The chemical etchant can be selected according to the substrate material. In one embodiment, one or more initial recesses can be formed in the vicinity of at least one qubit on the backside of the substrate, for example, by mechanically removing material from the backside of the substrate before chemically etching the backside. Following the mechanical removal, chemical etching can be performed, for example, in the initially formed recess on the backside of the substrate. By forming an initial recess on the backside of the substrate, a surface of the initial recess having one or more first crystal planes and one or more second crystal planes can be defined, whereby the chemical etchant preferentially etches the substrate material from the one or more first crystal planes but does not substantially etch the substrate material from the one or more second crystal planes, forming an etched final recess or trench in the vicinity of at least one qubit.

[0043] FIG. 8 further shows the back surface 202B of the substrate 202 having a plurality of trenches 800 according to an embodiment of the present invention. The size and / or shape of the trenches can be controlled, for example, by selecting an appropriate shape of the initial recess. In this way, the etching of the substrate material stops such that the size is self-limited to form the final trenches 800 that are etched when one or more first crystal planes (e.g., (111) plane) are substantially removed. In one embodiment, controlling the amount of material to be etched includes controlling the etching depth of the final trenches from the back surface to the front surface of the substrate 202.

[0044] FIGS. 9(A) - 9(D) show the steps of a process for removing substrate material from an area on the back surface 202B of the substrate 202 opposite at least one qubit 100 (qubit 1, qubit 2, qubit 3) according to an embodiment of the present invention. An etching mask film 900 (shown in FIG. 9(B)) can be attached to the back surface 202B of the substrate 202 (shown in FIG. 9(A)), and a selected area 902 (shown in FIG. 9(C)) on the back surface 202B of the substrate 202 opposite at least one qubit 100 (not shown in FIG. 9(C)) can be etched. In one embodiment, attaching the etching mask film 900 to the back surface 202B of the substrate 202 includes depositing niobium (Nb) on the back surface 202B of the substrate 202. In another embodiment, attaching the etching mask film 900 to the back surface 202B of the substrate 202 includes depositing an oxide or silicon nitride (SiN) on the back surface 202B of the substrate 202. FIG. 9(D) shows a patterned back surface mask film on the etched qubit wafer showing a plurality of trenches 904 formed in the wafer.

[0045] In one embodiment, after attaching or creating an etching mask 900 on the substrate 202, the substrate 202 is processed by performing aluminum evaporation on the front surface of the substrate 202 to create capacitor pads, Josephson junctions, etc. The processed substrate with a back coating is then diced to create a plurality of chips having one or more qubits.

[0046] FIG. 10 is a flowchart of a method for improving the qubit lifetime and coherence time in a quantum mechanical device according to an embodiment of the present invention. The method includes, at 1002, preparing a substrate having a front surface and a back surface, the front surface having at least one qubit formed thereon, and the at least one qubit including a capacitor pad. The method further includes, at 1004, removing a predetermined amount of substrate material from an area on the back surface of the substrate opposite the at least one qubit, or depositing a superconducting metal layer on an area on the back surface of the substrate opposite the at least one qubit, to reduce high-frequency current loss by at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface in order to increase the qubit lifetime (T1) and coherence time (T2). In one embodiment, the superconducting metal layer can be grounded.

[0047] In one embodiment, reducing high-frequency current loss includes reducing current loss by increasing the high-frequency overlap of the quantum mechanical device with lower-loss geometric features and decreasing the high-frequency overlap of the quantum mechanical device with higher-loss geometric features.

[0048] In one embodiment, removing the substrate material from an area on the back surface of the substrate, on the opposite side of at least one qubit, includes selectively chemically etching the back surface of the substrate using a chemical etchant selected according to the substrate material. In one embodiment, prior to chemically etching the back surface of the substrate, an initial recess is formed near at least one qubit on the back surface of the substrate by mechanically removing material from the back surface of the substrate, and then the initially formed recess on the back surface of the substrate is chemically etched. In one embodiment, forming an initial recess on the back surface of the substrate includes defining a surface of the initial recess having one or more first crystal planes and one or more second crystal planes, whereby the chemical etchant preferentially etches the substrate material from the one or more first crystal planes but does not substantially etch the substrate material from the one or more second crystal planes, forming a final etched recess near at least one qubit.

[0049] In one embodiment, removing a predetermined amount of substrate material from the back surface of the substrate includes removing a predetermined amount of substrate material within an area of the back surface of the substrate and forming a trench near a gap between capacitor pads of at least one qubit. In one embodiment, to form a trench near a gap between capacitor pads of at least one qubit, removing a predetermined amount of substrate material within an area of the back surface of the substrate includes removing a predetermined amount of substrate material such that the trench is located substantially centered around the gap between capacitor pads of at least one qubit. In one embodiment, removing a predetermined amount of substrate such that the trench is located substantially centered around the gap between capacitor pads of at least one qubit includes forming the trench to reduce the participation rate of surface states having an RF energy density at the silicon-metal (SM) interface and increasing the participation rate of surface states having an RF energy density at the silicon-air (SA) interface. In one embodiment, as the depth of the trench increases, the overlap of the RF energy density with the surface states at the silicon-metal (SM) interface decreases, and the overlap of the RF energy density with the surface states at the silicon-air (SA) interface increases.

[0050] In one embodiment, removing a predetermined amount of substrate material from the back surface of the substrate includes removing a predetermined amount of substrate material within an area of the back surface of the substrate and forming a trench near a gap between capacitor pads of at least one qubit, and depositing a superconducting metal layer in the trench to reduce high-frequency current loss due to a metal-air (MA) interface. In one embodiment, forming a trench near a gap between capacitor pads of at least one qubit includes forming a trench under and centered around one of the capacitor pads of at least one qubit. In one embodiment, the high-frequency current loss due to the metal-air (MA) interface decreases based on the back surface width of the trench.

[0051] In one embodiment, removing substrate material from an area on the back surface of the substrate opposite at least one qubit includes attaching an etching mask film to the back surface of the substrate and etching a selected area on the back surface of the substrate opposite at least one qubit. In one embodiment, after attaching an etching mask film to the back surface of the substrate and before etching a selected area on the back surface of the substrate, one or more openings are formed in the selected area of the etching mask film. In one embodiment, etching a selected area on the back surface of the substrate opposite at least one qubit includes chemically etching a desired thickness of the substrate in the selected area to form a trench in the selected area. In one embodiment, the method further includes depositing a superconducting metal layer in the trench.

[0052] In one embodiment, removing substrate material from an area on the back surface of the substrate opposite at least one qubit includes attaching a mask film to the back surface of the substrate and depositing a metal superconductor on the masked area of the back surface of the substrate.

[0053] As can be understood from the above paragraphs, a quantum mechanical device is further provided. The quantum mechanical device includes 1) a substrate having a front surface and a back surface, and 2) a plurality of qubits formed on the front surface of the substrate, and the plurality of qubits includes a plurality of capacitor pads. The substrate includes at least one trench formed on the back surface of the substrate on the opposite side of at least one of the plurality of qubits. To increase the lifetime (T1) and coherence time (T2) of at least one qubit, at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, or any combination thereof, is selected to reduce high-frequency current loss, and at least one of the size, shape, or position of the at least one trench or the superconducting material deposited in the trench is selected.

[0054] In one embodiment, the substrate can be any one of silicon, high-resistivity silicon, and sapphire. In one embodiment, the plurality of capacitor pads are made of a superconducting material. In one embodiment, the superconducting material can be either aluminum (Al) or niobium (Nb).

[0055] In one embodiment, the trench is provided near the gap between two of the plurality of capacitor pads. In one embodiment, the trench is located approximately at the center around the gap so as to reduce the energy density of the surface state of the silicon-metal (SM) interface and increase the energy density of the surface state of the silicon-air (SA) interface.

[0056] In one embodiment, a superconducting metal layer is provided in the trench to reduce high-frequency current loss due to the metal-air (MA) interface. In one embodiment, the trench is formed to be located under and centered around one or more of the plurality of capacitor pads.

[0057] The above backside etching method has many advantages. The severity of various loss mechanisms (i.e., the loss tangent of bulk silicon, and the surface states of SA, MA, and SM) varies, and the total RF loss of the qubit is basically the weighted linear sum of all loss factors such that the weighting is determined by the overlap of the RF field strength with the various loss mechanisms. These loss mechanisms are incidentally related to specific geometric features within the qubit. The RF overlap with bulk silicon, air, and the surface states at the interfaces of SA, MA, and SM is corrected using backside etching of the wafer. Note that reducing the overlap of the energy density with a given device's geometric surface generally increases the overlap of the energy density with other surfaces of the device's geometry, unless the overall size of the device electrodes is significantly changed. Thus, the above method can be used when a certain surface creates a higher likelihood of increasing RF loss compared to other surface types. By using the change in the amount of RF overlap with various interfaces and the bulk substrate (whether a silicon substrate or another substrate material), the overall RF loss can be minimized by backside etching of the wafer, metallizing the backside, or both. Thus, by increasing the RF overlap with low-loss geometric features and decreasing the RF overlap with more lossy features, the overall loss can be reduced (e.g., minimized), thereby increasing (e.g., maximizing) T1 and T2. Also note that the various manufacturing facilities and process flows can affect which material interfaces contribute most to RF loss, so the most concerning interfaces depend on the process flow or manufacturing line, or both. Thus, having a flexible strategy for minimizing RF loss may be beneficial as it may be necessary to balance the RF overlap strengths in various ways using the geometric features of various qubits to minimize the state in which various RF loss mechanisms contribute to the overall loss across various manufacturing lines.

[0058] The descriptions of various embodiments of the present invention have been presented for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements in technologies seen in the market, or to enable other skilled artisans in the art to understand the embodiments described herein.

Claims

1. A method for improving the lifetime and coherence time of qubits in a quantum mechanical device, comprising: providing a substrate having a front surface and a back surface, the front surface having at least one qubit formed thereon, the at least one qubit comprising a first capacitor pad and a second capacitor pad, the first capacitor pad and the second capacitor pad having a gap therebetween; removing a predetermined amount of substrate material from an area of the back surface of the substrate, near at least the gap and on the opposite side of the at least one qubit, so as to reduce high-frequency current loss caused by at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, in order to increase the lifetime (T1) and coherence time (T2) of the at least one qubit; A method as described above.

2. The method according to claim 1, wherein reducing the high-frequency current loss includes reducing the current loss by increasing the high-frequency overlap of the quantum mechanical device with a lower-loss geometric feature other than at least one of the silicon-air (SA) interface, the metal-air (MA) interface, or the silicon-metal (SM) interface, and reducing the high-frequency overlap of the quantum mechanical device with a higher-loss geometric feature related to at least one of the silicon-air (SA) interface, the metal-air (MA) interface, or the silicon-metal (SM) interface.

3. The method according to claim 1 or 2, wherein removing the substrate material from the area of the back surface of the substrate, on the opposite side of the at least one qubit, includes selectively chemically etching the back surface of the substrate using a chemical etching solution selected according to the substrate material.

4. The method according to claim 3, further comprising forming an initial recess near the at least one qubit on the back surface of the substrate by mechanically removing material from the back surface of the substrate before chemically etching the back surface of the substrate, and then chemically etching the formed initial recess on the back surface of the substrate.

5. Forming the initial recess on the back surface of the substrate includes defining a surface of the initial recess having one or more first crystal planes and one or more second crystal planes, whereby the chemical etchant preferentially etches the substrate material from the one or more first crystal planes but does not substantially etch the substrate material from the one or more second crystal planes, and forming an etched final recess in the vicinity of the at least one qubit. The method according to claim 4.

6. Removing the predetermined amount of substrate material from the back surface of the substrate includes removing the predetermined amount of substrate material within an area of the back surface of the substrate and forming a trench in the vicinity of a gap between the first capacitor pad and the second capacitor pad of the at least one qubit. The method according to any one of claims 1 to 5.

7. Removing the predetermined amount of substrate material within the area of the back surface of the substrate and forming the trench in the vicinity of the gap between the first capacitor pad and the second capacitor pad of the at least one qubit includes removing the predetermined amount of substrate material such that the trench is located substantially at the center around the gap between the first capacitor pad and the second capacitor pad of the at least one qubit. The method according to claim 6.

8. Removing the predetermined amount of substrate such that the trench is located substantially at the center around the gap between the first capacitor pad and the second capacitor pad of the at least one qubit includes forming the trench to reduce the participation rate of surface states having an RF energy density at the silicon-metal (SM) interface and increasing the participation rate of surface states having the RF energy density at the silicon-air (SA) interface. The method according to claim 7.

9. As the depth of the trench increases, the overlap of the RF energy density with the surface states at the silicon-metal (SM) interface decreases, and the overlap of the surface states at the silicon-air (SA) interface with the RF energy density increases. The method according to claim 6.

10. Removing the predetermined amount of substrate material from the back surface of the substrate includes removing the predetermined amount of substrate material within an area of the back surface of the substrate, forming a trench in the vicinity of a gap between the first capacitor pad and the second capacitor pad of the at least one qubit, and depositing a superconducting metal layer in the trench to reduce the high-frequency current loss due to a metal-air (MA) interface. The method according to any one of claims 1 to 5.

11. Forming the trench in the vicinity of the gap between the first capacitor pad and the second capacitor pad of the at least one qubit includes forming the trench that is centered around one of the first capacitor pad and the second capacitor pad and is located under one of the first capacitor pad and the second capacitor pad. The method according to claim 10.

12. The method according to claim 10 or 11, wherein the high-frequency current loss due to a metal-air (MA) interface decreases based on the back surface width of the trench.

13. Removing the substrate material from an area of the back surface of the substrate on the opposite side of the at least one qubit includes attaching an etching mask film to the back surface of the substrate and etching a selected area of the back surface of the substrate on the opposite side of the at least one qubit. The method according to any one of claims 1 to 12.

14. After attaching the etching mask film to the back surface of the substrate and before etching the selected area of the back surface of the substrate, the method according to claim 13 further includes forming one or more openings in the selected area of the etching mask film.

15. Etching the selected area of the back surface of the substrate on the opposite side of the at least one qubit includes chemically etching a desired thickness of the substrate in the selected area to form a trench in the selected area. The method according to claim 13 or 14.

16. The method according to claim 15 further includes depositing a superconducting metal layer in the trench.

17. Removing the substrate material from the area on the back surface of the substrate opposite the at least one qubit includes attaching a mask film to the back surface of the substrate and depositing a metallic superconductor on the masked area of the back surface of the substrate, the method according to any of claims 1 to 16.

18. A quantum mechanical device comprising a substrate having a front surface and a back surface, and a plurality of qubits formed on the front surface of the substrate, wherein the plurality of qubits include a first capacitor pad and a second capacitor pad, and have a gap therebetween, the substrate includes at least one trench formed in an area near at least the gap on the back surface of the substrate opposite at least one of the plurality of qubits, a quantum mechanical device, wherein at least one of the size, shape, or position of the at least one trench is selected to reduce high-frequency current loss by at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, or any combination thereof, to increase the lifetime (T1) and coherence time (T2) of the at least one qubit.

19. The quantum mechanical device according to claim 18, wherein the substrate is selected from the group consisting of silicon, high-resistivity silicon, and sapphire.

20. The quantum mechanical device according to claim 19, wherein the first capacitor pad and the second capacitor pad are made of a superconducting material.

21. The quantum mechanical device according to claim 20, wherein the superconducting material is selected from the group consisting of aluminum (Al) and niobium (Nb).

22. The quantum mechanical device according to any of claims 18 to 21, wherein the trench is provided near the gap between the first capacitor pad and the second capacitor pad.

23. The quantum mechanical device according to claim 22, wherein the trench is located approximately at the center around the gap so as to reduce the energy density of the surface state of the silicon-metal (SM) interface and increase the energy density of the surface state of the silicon-air (SA) interface.

24. The quantum mechanical device according to any one of claims 18 to 23, wherein the superconducting metal layer is provided in the trench in order to reduce the high-frequency current loss due to the metal-air (MA) interface.

25. The quantum mechanical device according to claim 24, wherein the trench is formed under the first capacitor pad or the second capacitor pad and centered around the first capacitor pad or the second capacitor pad.

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