Method for the efficient implementation of unitary operations in Clifford algebra as a quantum circuit

Abstract

This disclosure relates to methods for building efficient quantum circuits for Clifford Loaders, and to variations of these methods that follow a similar paradigm.

Description

Technical Field

[0001] This disclosure is in the fields of quantum algorithms and quantum linear algebra. In particular, it provides a logarithmic-depth construction of a quantum circuit called a Clifford loader. This disclosure is also in the field of quantum machine learning. In particular, it provides an application of the Clifford loader circuit to quantum machine learning.

Background Art

[0002] Deterministic sampling by classical computers is computationally expensive as the complexity of computing the determinant of a single d-dimensional matrix scale is O(d 3 ). Theoretically, there are complex theoretical constructs that can achieve O(d 2.37 ) for computing a single determinant factor, but these can only outperform the standard methods for very large d due to their large factor overhead. Furthermore, most classical determinant sampling algorithms require computing several determinants which brings even higher computational requirements.

Summary of the Invention

[0003] This disclosure provides a logarithmic-depth construction of a quantum circuit called a Clifford loader. This circuit performs specific unitary operations in Clifford algebra and has applications to quantum linear algebra and quantum machine learning. The constructed circuit is optimized with respect to the number of qubits, the depth of the quantum circuit, and the types of gates in the circuit.

[0004] Quantum machine learning and linear algebra algorithms may rely on the ability to represent classical data as quantum states in order to use quantum procedures for linear algebra tasks. This disclosure provides a procedure for efficiently representing the subspace spanned by k-vectors as a quantum state using a Clifford loader. Embodiments of the disclosure have applications to, for example, quantum machine learning for tasks such as determinant sampling and phase geometric data analysis, and to, for example, quantum linear algebra for the convex hull and solution of low-dimensional linear systems.

[0005] Some embodiments relate to a quantum circuit for implementation by a quantum computer, the quantum computer including at least N qubits q n The quantum circuit includes first and second branch circuits and a gadget circuit. The first branch circuit, subsequent to the implementation of the first branch circuit, includes quantum gates applied to N / 2 qubits q1 - q N / 2 where the numerical value of qubit q2 represents the parity of qubits q2 - q N / 2 The second branch circuit is arranged to be executed simultaneously with the first branch circuit and includes quantum gates applied to N / 2 qubits q (N / 2+1) - q N The gadget circuit is arranged to be executed after the first and second branch circuits. The gadget circuit includes quantum gates applied to qubits q1, q2, q (N / 2+1) One of the quantum gates of the gadget circuit is a BS(θ) gate. The BS(θ) gate is a two - qubit quantum gate represented by a single parameter. When the numerical value of qubit q2 is 0, the gadget circuit applies the BS(θ) gate to qubits q1 and q (N / 2+1) When the value of qubit q2 is 1, the gadget circuit instead applies the conjugate of the BS(θ) gate to qubits q1 and q (N / 2+1)

[0006] In some embodiments, the first branch circuit includes a third branch circuit, a fourth branch circuit, and a second gadget circuit. The third branch circuit, subsequent to the execution of the third branch circuit, includes quantum gates applied to N / 4 qubits q1 - q N / 4 where the value of qubit q2 represents the parity of qubits q2 - q N / 4 The fourth branch circuit is configured to be executed simultaneously with the third branch circuit and includes quantum gates applied to N / 4 qubits q (N / 4+1) - q N / 2 The second gadget circuit is after the third and fourth branch circuits. The second gadget circuit includes qubits q1, q2, and q (N / 4+1) ​includes quantum gates applied to, where one of the quantum gates of the second gadget circuit is a second BS(θ) gate. When the value of qubit q2 is 0, the second BS(θ) gate is applied to qubits q1 and q (N / 4+1) is applied, and when the value of qubit q2 is 1, the conjugate of the second BS(θ) gate is applied to qubits q1 and q (N / 4+1) is applied.

[0007] In some embodiments, the quantum circuit further includes an X gate applied to qubit q1 after the gadget circuit. In some embodiments, the quantum circuit further includes a second gadget circuit after the X gate. The second gadget circuit includes quantum gates applied to qubits q1, q2, and q (N / 2+1) where one of the quantum gates of the second gadget circuit is a second BS(θ) gate. When the value of qubit q2 is 0, the conjugate BS(θ) gate is applied to qubits q1 and q (N / 2+1) and when the value of qubit q2 is 1, the BS(θ) gate is applied to qubits q1 and q (N / 2+1) In some embodiments, the quantum circuit further includes a third branch circuit after the second gadget circuit. The third branch circuit includes quantum gates applied to N / 2 qubits q1-q N / 2 where the quantum gates of the third branch circuit that match are the quantum gates of the first branch circuit excluding the quantum gates of the third branch circuit arranged in reverse order, and the BS(θ) gates are combined. In some embodiments, the present quantum circuit further includes a fourth branch circuit configured to be executed simultaneously with respect to the third branch circuit. The fourth branch circuit includes quantum gates applied to N / 2 qubits q (N / 2+1) -q N where the quantum gates of the fourth branch circuit that match are the quantum gates of the second branch circuit excluding the quantum gates of the fourth branch circuit arranged in reverse order, and the BS(θ) gates are combined.

[0008] In some embodiments, the quantum circuit includes a first layer that applies a second BS(θ) gate to qubits q1 and q2 and a third BS(θ) gate to qubits q3 and q4, a second layer that applies a first CZ gate to qubits q1 and q2, where the CZ gate is a controlled Z gate, a third layer that applies a fourth BS(θ) gate to qubits q1 and q3, a fourth layer that applies a second CZ gate to qubits q1 and q2 and a first CX gate to qubits q3 and q4, where the CX gate is a controlled X gate, and a fifth layer that applies a second CX gate to qubits q2 and q3.

[0009] In some embodiments, the gadget branching circuit includes a first layer that applies a first CZ gate to qubits q1 and q2, where the CZ gate is a controlled Z gate, and a second layer that applies a BS(θ) gate to qubits q1 and q (N / 2+1) and a third layer that applies a second CZ gate to qubits q1 and q2.

[0010] Some embodiments relate to a method of executing a quantum circuit by a quantum computer. Note that the following circuit includes a nested branching circuit. The quantum circuit includes at least N qubits q n where N = 2 K and N qubits q with K ≧ 2 n and a recursive circuit level K from K = 1 to K. Each circuit level k includes a level k circuit of (N / 2 k ), and each level k circuit includes one or more quantum gates applied to qubits q n of 2 k . The 2 k qubits for each level k circuit include a first qubit and a second qubit for that level K circuit. Each level 1 circuit includes qubits q nincludes a BS gate applied to two of them, where one of the two qubits is the first qubit of the level 1 circuit and the other of the two qubits is the second qubit of the level 1 circuit. Each level k circuit for K≧2 includes a first branch circuit, which is one of the level (k - 1) circuits, and a second branch circuit, which is the other of the level (k - 1) circuits, and a gadget circuit including a BS gate. When the value of the second qubit of the first branch circuit is 0, the BS gate is applied to the first qubit of the first branch circuit and the first qubit of the second branch circuit. When the value of the second qubit of the first branch circuit is 1, the conjugate of the BS gate is applied to the first qubit of the first branch circuit and the first qubit of the second branch circuit.

[0011] Some embodiments relate to quantum circuits for implementation by a quantum computer, the quantum computer including at least N qubits q n This circuit includes a set of N - 1 layers and an additional layer. The set of N - 1 layers sequentially applies N - 1 BS gates to N qubits q n Each BS gate is a two - qubit gate represented by a single parameter. Each layer applies a BS gate to two qubits, and each subsequent layer applies a BS gate to one of the two qubits of the layer and a new qubit. The additional layer follows the set of N - 1 layers and applies an X gate to one of the qubits.

[0012] In some embodiments, the new qubit in each subsequent layer is a qubit to which the previous layer has not applied a BS gate.

[0013] In some embodiments, the X gate is applied to the new qubit of the N - 1th layer.

[0014] In some embodiments, the quantum circuit further includes a second set of N - 1 layers after the additional layer. The second set of N - 1 layers that apply N - 1 BS gates to N qubits has each layer applying the BS gate to two qubits, and each subsequent layer applying the BS gate to one of the two qubits of the layer and a new qubit. In some embodiments, the BS gate is a conjugate gate corresponding to the BS gate within the second N - 1 layers of the N - 1 set.

[0015] As other aspects, components, devices, systems, improvements, methods, processes, applications, computer - readable storage media, and other technologies related to any of the above are included.

Brief Description of the Drawings

[0016] The disclosed embodiments designated as Clifford loaders have other advantages and features that will become more readily apparent from the following detailed description and claims, and when taken in conjunction with the accompanying exemplary drawings, are as follows.

[0017] For each vector x=(x1,x2,...,x N ) having Euclidean norm 1, the Clifford loader is parameterized by an N - dimensional single vector such that there exists a corresponding Clifford loader designated as C(x).

[0018]

Figure 1

Figure 2

Figure 3A

Figure 3B

[0019] The figures show various embodiments for illustrative purposes only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods shown herein can be employed without departing from the principles described herein. For example, changing certain ones of the BS gates or using different / less - optimized ways to perform parity calculations using the control of the Z gate.

Mode for Carrying Out the Invention

[0020] The figures and the following description relate to preferred embodiments for illustrative purposes only. Note that from the following description, alternative embodiments of the structures and methods disclosed herein are readily recognized as viable alternatives that can be employed without departing from the disclosed principles.

[0021] [Part 1: Clifford Loader] Classical vectors are represented in N - dimensional coordinates (x1, x2, ..., x N ). Here, x i is a real number and the Euclidean norm of the vector is 1. For the sake of clarity in representing this particular aspect, assume that N is a power of 2, but our method can be extended to the general case.

[0022] For the classical vector x = (x1, x2, ..., x N ), a certain single operator in Clifford algebra is described, and the Clifford loader corresponds to the implementation of this single operator.

[0023] The Pauli matrices X and Z correspond to single qubit bit-flip and phase-flip operators, and they are two-dimensional anti-commuting matrices. P i = Z i-1 XI N-i Let it be. Here, the string represents the tensor product of N Pauli operators, and the X operator is at position i. The single-term operator implemented by the Clifford loader for the vector x acts on N qubits and is given as follows.

Number

[0024] The operator C(x) is unitary for all vectors x with Euclidean norm 1 that square to the identity. R N Since it is a linear combination of the generators P i of the Clifford algebra for R, it belongs to the Clifford algebra. As a matrix, C(x) has dimension 2 N x 2 N and thus there is no a priori reason to expect it to be implementable as a quantum circuit using polynomials of 2-qubit gates (within the input size N). The disclosure provides such an implementation for these circuits, and furthermore, the depth of the circuits for our implementation is logarithmic in N, which makes these circuits extremely efficient.

[0025] One type of 2-qubit gate parameterized is denoted as BS(θ) and the following description is in the standard basis.

Number

[0026] Also, controlled-Z and controlled-X gates are used. These have the following descriptions in the standard basis.

Number

Number

[0027] Two matrix identities were introduced that can be verified by direct calculation on the 4D matrix given above. These identities describe the effect of conjugating the strings XI and ZZ with the gate \(BS(\theta)\) and were later used to establish the correctness of the authors' construction.

Number

Number

[0028] To construct a Clifford loader circuit, the following three quantum bits (e.g., for convenience, like 1, 2, and 3) are required to act on a gadget (a term used for a branched circuit that performs a specific function in circuit complexity theory). When quantum bit 2 is 0 (e.g., based on a standard), it applies the operation BS(θ) to quantum bits 1 and 3. When quantum bit 2 is 1 (e.g., based on a standard), instead, it applies the operation BS(θ) * is applied. This gadget is denoted as G 123 (θ), and for example, a sequence of three gates CZ 21 BS 13 (θ)CZ 21 can be used for implementation, where the CZ gate controls quantum bit 2 and the BS(θ) gate acts on quantum bits 1 and 3. The operation of this gadget as described above can be verified by calculating the product of three matrices. In another case, this gadget circuit is implemented by treating the BS(θ) gate not as a single gate but as a sequence of three rotations

[0029] In addition to the gadget, the Clifford loader includes a series of angles used as inputs to the BS gate. This sequence of angles is calculated from the vector x. The sequences of angles for two embodiments are described below. Note that the sequence of angles of the first embodiment is the same as the sequence described in U.S. Patent Application No. 16 / 986,553 incorporated by reference in its entirety. The sequence of angles of the second embodiment is specific to this disclosure

[0030] The sequence of angles of the first embodiment is the same as the sequence described in U.S. Patent Application No. 16 / 986,553, but is briefly described here for completeness. First, an auxiliary series (r1, r2, ..., r N ) of the intermediate squared amplitudes of the vector x is defined. The last N / 2 values (r N / 2 , r N / 2+1 , ..., r N-1 ) have indices

Number

Number

Number

Number

Number

Number

[0031] The angle sequence of the second embodiment is defined as follows. The first angle is as follows.

Number

Number

[0032] There can be a similar way to define the numerical value of the angle, and both examples will be classified in the same way as this book. For example, the sign of the angle can be inverted, or a multiple of π can be added to the angle.

[0033] For any vector x = (x1, x2, ..., x N ), two quantum circuits can be defined to implement the Clifford loader.

Number

[0034] The first embodiment for constructing the Clifford loader will be described here. This embodiment is illustrated for the 8-dimensional vector in FIG. 1 and the 16-dimensional vectors in FIGS. 3A and 3B (FIG. 3B shows the level of the C(x) circuit). The Clifford loader circuit of the first embodiment includes an X gate on the first qubit sandwiched between the quantum circuit C(x) on the left and the adjacent (C(x) * ) on the right, where C(x) and C(x) * each have a logarithmic depth, that is, C(x) = C(x)(X N-1 )C(x) * . The recursive description of C(x) is shown below using gadgets. Also, it is explicitly shown that the total circuit depth is logarithmic in N. For C(x) * , the gates are inverse to C(x) and are conjugated (note that CX and CZ are self-conjugate).

[0035] Some notations used to construct two different quantum circuits S1 and S2 are introduced. In these descriptions, the notation (S1||S2) is used. The quantum circuits and S1 and S2 are executed in parallel for separate sets of qubits, and (S1, S2) indicates the sequential configuration of the circuits on the same set of qubits. Note that a circuit is an ordered set of one or more gates. For example, a circuit can contain only a single gate. A branch circuit may refer to a circuit that is part of a larger circuit. Also included are auxiliary circuits that make up a Clifford loader with CX gates. Define C'(x) after a sequence of CX gates such that qubit 2 includes the parity of qubits from 2 to N at the end of the calculation (e.g., refer to circuit C'(x

Number

[0036] Here, a recursive construction example of circuit C(x) in Figure 1 is shown. As described above, the Clifford loader can be obtained by applying circuits C(x) and C(x) * with an X gate between them. Assume that the dimension of vector x (i.e., N) is a power of 2. This assumption can be made without loss of generality because vector x can be padded with some 0s to make the dimension a power of 2. For a two-dimensional unit vector

Number

Number

Number

[0037] The circuit depth for C(x) can be obtained from the recurrence relation. Let d(N) be the circuit depth as a function of the dimension. Next, let d(2)=1, and from the recurrence, let d(N) = d'(N / 2)+3 and d'(N) = d'(N / 2)+4. The gadget G ijk has a depth of 3, and note that CX(N / 2+2, N / 2+1) can be executed in parallel with the third layer of the gadget G ijk when implementing the circuit using these recurrence relations. Therefore, the explicit solution of these recurrences is d(N) = 4(log2N - 1) for powers of 2 greater than 2.

[0038] Expand the recurrence and give an explicit description of C(x) for 4-dimensional and 8-dimensional vectors x. The 4-dimensional C(x) circuit has a depth of 4*(2 - 1)=4. It uses the angles (θ1, θ2, θ3) (described above) for the vector x calculated according to the first embodiment as inputs to the BS gates. Give a gate-level description of the four layers in the circuit C(x). Layer 1: (BS 12 (θ2)||BS34 (θ3) Layer 2: CZ 21 Layer 3: BS 13 (θ1) Layer 4: CZ 21 The 8 - dimensional C(x) circuit will have a depth of 4*(3 - 1)=8 as described above. The angles (θ1, θ2, ...,θ7) for the vector x are calculated according to the first embodiment (above) and are inputs to the BS gates in C(x). In C(x) shown in FIG. 1, all 8 - layer gate - level descriptions are given. Layer 1: (BS 12 (θ4)||BS 34 (θ5)||BS 56 (θ6)||BS 78 (θ7)) Layer 2: (CZ 21 ||CZ 65 ) Layer 3: ((BS 13 (θ2))||BS 57 (θ3)) Layer 4: (CZ 21 ||CZ 65 ||CX 43 ||CX 78 ) Layer 5: (CZ 32 ||CZ 76 ) Layer 6: CZ 21 Layer 7: BS 15 (θ1) Layer 8: CZ 21 Note that in layers 2 - 4 and 6 - 8, the gadget G ijk is implemented along with some parity calculations that are executed in parallel in layer 4. Specifically, the parity calculations are represented by CX gates and the CZ gates are part of the gadget G ijk . Note that when traversing C(x) from bottom - to - top and left - to - right in FIG. 1, the calculated sequence of angles is used in reverse order.

[0039] The second embodiment of the Clifford loader uses the sequence of angles described with reference to equations 10 and 11. Here, (θ1, θ2, …, θ n-1 ) is the sequence of angles, and then the Clifford loader according to Example 2 can be realized as follows. [Number] In contrast to the first embodiment, in order to implement the Clifford loader C(x) for an n-dimensional vector x, (n - 1) BS gates are used sequentially and have a line width. An example of a circuit Clifford loader circuit according to the second embodiment is shown in FIG. 2.

[0040] [Part 2: Application of Clifford Loader] Here, a method of using the Clifford loader for applications in quantum machine learning related to determinant sampling is shown. In particular, a method of using the Clifford loader to solve the basic problem of sampling according to a deterministic distribution and its application to typical feature selection are shown.

[0041] Deterministic sample extraction by a classical computer is computationally expensive as the complexity of calculating the determinant of a single d-dimensional matrix scale is O(d 3 ). Theoretically, there are complex theoretical constructs that can achieve O(d 2.37 ) for calculating a single determinant, but these can only outperform the standard method for very large d due to their large constant factor overhead. Furthermore, most classical determinant sampling algorithms require calculating several determinants, which results in even higher computational requirements. In contrast, the quantum algorithms described in this disclosure have a complexity of O(d log N).

[0042] The input to the deterministic sampling problem is the matrix [Number] and this is a matrix containing n - row vectors each having dimension d. The output is a subset [Number] (|S| = d) such that the probability of selecting S is proportional to the squared volume of the parallelepiped spanned by the vectors in S. More formally, [Number] A S denotes the d x d matrix obtained by selecting the rows of A that belong to S. It is clear that all probabilities are positive and the sum of the probabilities for all possible S's is 1 by the Cauchy - Binet identity.

[0043] The output of the determinant sampler is a set S of d 'nearly orthogonal' vectors because the determinant is maximized when the vectors are orthogonal and small when any of the vectors is a linear combination of the others. The row vectors are guaranteed to be linearly independent of the output of the determinant sampler so that det(X S ) = 0. If there is linear dependence, S will not be displayed in the output of the sampler. The output of the determinant sampler is a diverse and representative set of vectors. This can be useful in machine - learning applications where the goal is to sample a representative set of features.

[0044] As a use - case of the example, consider a large dataset of users and features associated with the user. The goal here is to select a set of users with representative and diverse features. Deterministic sampling selects a diverse and representative group of users from the dataset. It is a technique for obtaining a concise summary of a large dataset that holds all the different groups of users that exist there.

[0045] The output of the determinant sampler can also be used as an input to a low - rank approximation by row selection or to a clustering algorithm. This has been found to be improved over standard methods.

[0046] Hereinafter, a method for performing deterministic sampling using a combination of Clifford loaders will be described. From Part 1, the Clifford loader [Number] is recalled to be a unitary operator defined for each N-dimensional vector x. Furthermore, regarding the first embodiment, an example of a Clifford loader using O(NlogN) 2-qubit gates and having a circuit depth of O(JogN) was provided.

[0047] The determinant sampling algorithm using the Clifford loader is as follows. (a 1 , a 2 ,..., a d ) are the columns of the matrix [Number] . Apply the quantum circuit [Number] and measure the resulting state in the standard basis. The result of these operations is a quantum superposition on a bit string whose amplitude of a bit string having d 1s and (N - d) 0s is the determinant det(A s ). Therefore, measurement in the standard basis samples the determinant prime distribution and [Number] . The quantum algorithm measures in the standard basis to obtain an N-bit output string. Let S be the set of 1s in the output string. If |S| = d, output S.

[0048] The above procedure uses N qubits and has a circuit depth of O(d log N) using the first embodiment of the first part, and sequentially applies Clifford loader circuits continuously. This procedure succeeds with probability 1 if the columns of matrix A are orthogonal. More generally, the success probability is det(A T A).

[0049] If the procedure described above with reference to Equation 16 succeeds, the output S is a sample from a deterministic distribution. That is, this procedure is exact and exactly solves the deterministic sampling problem in time O(d log N).

[0050] The success probability of the determinant sampler can be improved by multiplying matrix A by a random unitary matrix or a Hadamard matrix and then running the determinant sampler on A' = AH. Using state-of-the-art procedures for multiplication by the Hadamard matrix, such preprocessing is executed linearly in time with respect to the number of non-zero entries of A.

[0051] When A is an orthogonal matrix, the quantum determinant sampling algorithm with running time O(d log N) provides a speedup over the best-known classical algorithm with running time O(d 3 ).

[0052] More generally, a sequence of Clifford loader operations

Number

[0053] The Clifford loader is also useful in quantum topology data analysis, where

Number

[0054] The second part is described with reference to the first embodiment of the Clifford loader, but instead, the second embodiment of the Clifford loader may be used. In this case, the running time is O(dN).

[0055] [Other Considerations] A quantum processing device (also called a quantum computer) utilizes the laws of quantum mechanics to perform calculations. Quantum processing devices generally use so-called qubits, i.e., quantum bits. While classical bits always have a value of either 0 or 1, qubits are quantum mechanical systems that can have values of 0, 1, or a superposition of both [Number] and here [Number] is the case. For example, physical implementations of qubits include superconducting qubits, electron traps, and photon systems (e.g., photons in a waveguide).

[0056] A quantum circuit is an ordered set of one or more gates. A branch circuit may refer to a circuit that is part of a larger circuit. A gate represents a single operation performed on one or more qubits. A quantum computer can use a universal set of one- and two-qubit gates. Universally, it means that any quantum circuit can be written as a combination of these gates. Quantum gates can be described using unitary matrices. The depth of a quantum circuit is the minimum number of steps required to execute the circuit on a quantum computer. A layer of a quantum circuit may refer to a step of the circuit.

[0057] Instructions for executing a quantum circuit on one or more quantum computers can be stored in a non-transitory computer-readable storage medium. The term "computer-readable storage medium" should be interpreted to mean a single medium or multiple media, a centralized or distributed database, or any associated cache and server that can store the instructions. Also, the term "computer-readable medium" shall include a medium that can store instructions for execution by a quantum computer and cause the quantum computer to execute any one or more of the methodologies disclosed herein. The term "computer-readable medium" includes, but is not limited to, data repositories in the form of solid-state memory, optical media, and magnetic media.

[0058] The above-described techniques may be suitable for a cloud quantum computing system where quantum computing is provided as a shared service that separates users. An example is described in Patent Application No. 15 / 446,973, "Quantum Computing as a Service," which is incorporated by reference herein.

[0059] Some portions of the above description explain embodiments from the perspective of algorithmic processes or operations. These algorithmic descriptions and representations are commonly used by those skilled in the computer art to effectively communicate the substance of their work to other skilled artisans. These operations, while described functionally, computationally, or logically, are understood to be implemented by a computer program having instructions for execution by a processor or equivalent electrical circuit, microcode, etc. Further, it has proven convenient at times, without sacrificing generality, to refer to these arrangements of functional operations as modules.

[0060] Any reference to "an embodiment" or "embodiments" used in this specification means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in an embodiment" in various places in the specification do not necessarily all refer to the same embodiment. Similarly, the use of "a" or "one" before an element or component is done merely for convenience. This description should be understood to mean that there is one or more of the element or component, unless it is clear from the context that it is intended otherwise.

[0061] When a value is described as "about" or "substantially" (or derivatives thereof), the value should be construed as being accurate to + / - 10% unless another meaning is clear from the context. For example, "about 10" should be understood to mean a range from 9 to 11.

[0062] As used herein, the terms "comprise," "comprising," "include," "including," "have," "having," "hold," "holding" or any other variation thereof are intended to cover non-exclusive inclusions. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to inclusive OR and not exclusive OR. For example, a condition A or B is satisfied if either A is true (or present) and B is false (or absent), or A is false (or absent) and B is true (or present), or both A and B are true (or present).

[0063] In the arrangement, operation, and details of the methods and apparatuses disclosed in this specification, various other modifications, changes, and variations that are obvious to those skilled in the art can be made without departing from the concept and scope as defined in the claims. Therefore, the scope of the present invention should be determined by the appended claims and their legal equivalents.

[0064] Alternative embodiments are implemented in computer hardware, firmware, software, and / or combinations thereof. Implementations may be implemented within a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor, and method steps may be performed by a programmable processor executing a program of instructions to operate on input data and generate output to perform functions. Embodiments may be advantageously implemented with one or more computer programs executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program may be implemented in a high-level procedural or object-oriented programming language, or, if desired, in assembly or machine language, and in any case, the language may be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. In general, a processor receives instructions and data from read-only memory and / or random access memory. In general, a computer will include one or more mass storage devices for storing data files. Such devices include magnetic disks, such as internal hard disks and removable disks, magneto-optical disks, and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks in any form of non-volatile memory. Any of the foregoing may be supplemented by, or incorporated in, ASICs (application specific integrated circuits) and other forms of hardware.

Claims

1. A non-transitory computer-readable storage medium including stored instructions for executing a quantum circuit by a quantum computer, the quantum computer including at least N quantum bits q n where n is an integer value from 1 to N, and the stored instructions, when executed by the quantum computer, cause the quantum computer to Quantum bit q of N / 2 1 -q N / 2 Executing a first branching circuit including a quantum gate applied to, and following the execution of the first branching circuit, quantum bit q 2 The value of is the parity of quantum bit q 2 -q N / 2 indicating, and To execute a second branching circuit simultaneously with the first branching circuit, the second branching circuit including quantum gates applied to N / 2 quantum bits q (N / 2+1) -q N and that is the case executing a gadget circuit after the first branching circuit and the second branching circuit, the gadget circuit being for qubits q 1 , q 2 and q (N / 2+1) and including quantum gates applied to, one of the quantum gates of the gadget circuit being a BS(θ) gate, the BS(θ) gate being a two-qubit quantum gate represented by a single parameter Quantum bit q 2 When the value of is 0, the BS(θ) gate is applied to the quantum bit q 1 and q (N / 2+1) and Quantum bit q 2 When the value of is 1, the conjugate of the BS(θ) gate is applied to the quantum bit q 1 and q (N / 2+1) and, A non - transitory computer - readable storage medium for causing an operation including

2. In the non - transitory computer - readable storage medium according to Claim 1, executing the first branch circuit Quantum bit q of N / 4 1 -q N / 4 Executing a third branching circuit including a quantum gate applied to, following the execution of the third branching circuit, quantum bit q 2 The value of is quantum bit q 2 -q N / 4 Indicating the parity of, and Simultaneously with the third branching circuit, execute a fourth branching circuit including a quantum gate applied to N / 4 quantum bits q (N / 4+1) -q N / 2 and, executing a second gadget circuit after the third and fourth branch circuits, the second gadget circuit including quantum gates applied to qubits q 1 , q 2 and q (N / 4+1) wherein one of the quantum gates of the second gadget circuit is a second BS(θ) gate Quantum bit q 2 When the value of is 0, the second BS(θ) gate is applied to the quantum bit q 1 and q (N / 4+1) and Quantum bit q 2 When the value of is 1, the conjugate of the second BS(θ) gate is applied to the quantum bit q 1 and q (N / 4+1) which is applied to, and A non - transitory computer - readable storage medium including

3. In the non-transitory computer-readable storage medium according to claim 1, the operation further includes executing an X gate applied to the quantum bit q after the gadget circuit 1 A non-transitory computer-readable storage medium.

4. In the non - transitory computer - readable storage medium according to Claim 3, the operation further executing a second gadget circuit after the X gate, the second gadget circuit being quantum bits q 1 ,q 2 and q (N / 2+1) including quantum gates applied to, one of the quantum gates of the second gadget circuit being a second BS(θ) gate qubit q 2 When the value of is 0, the conjugate of the BS(θ) gate is applied to qubit q 1 and q (N / 2+1) and Quantum bit q 2 When the value of is 1, the BS(θ) gate is applied to the quantum bit q 1 and q (N / 2+1) which is applied to, and A non - transitory computer - readable storage medium including

5. In the non - transitory computer - readable storage medium according to Claim 4, the operation further Executing a third branch circuit after the second gadget circuit, the third branch circuit including quantum gates applied to N / 2 quantum bits q 1 -q N / 2 wherein the quantum gates of the third branch circuit match the quantum gates of the first branch circuit, except that the quantum gates of the third branch circuit are arranged in reverse order and the BS(θ) gates of the third branch circuit are conjugated, A non - transitory computer - readable storage medium including

6. In the non - transitory computer - readable storage medium according to Claim 5, the operation further To execute a fourth branch circuit simultaneously with the third branch circuit, the fourth branch circuit including quantum bits q (N / 2+1) -q N to which a quantum gate is applied, the quantum gate of the fourth branch circuit being identical to the quantum gate of the second branch circuit except that the quantum gates of the fourth branch circuit are arranged in reverse order and the BS(θ) gates of the fourth branch circuit are conjugated, A non - transitory computer - readable storage medium including

7. In the non - transitory computer - readable storage medium according to Claim 1, executing the first branch circuit Apply the second BS(θ) gate to qubits q 1 and q 2 and apply the third BS(θ) gate to qubits q 3 and q 4 to execute the first layer Apply a second layer that performs a first controlled Z gate (CZ gate) to qubits q 1 and q 2 and execute. Execute the third layer that applies the fourth BS(θ) gate to qubits q 1 and q 3 and, Apply the second CZ gate to qubits q 1 and q 2 and apply the first controlled-X gate (CX gate) to qubits q 3 and q 4 Execute the fourth layer for application Execute the fifth layer that applies to the second CX gate to the qubits q 2 and q 3 and, A non - transitory computer - readable storage medium including

8. In the non - transitory computer - readable storage medium according to Claim 1, executing the gadget circuit Execute the first layer that applies the first controlled Z gate (CZ gate) to qubits q 1 and q 2 ; Apply the BS(θ) gate to the qubits q 1 and q (N / 2+1) and execute a second layer Apply the second CZ gate to qubits q 1 and q 2 and execute a third layer that applies to them A non - transitory computer - readable storage medium including

9. In the non - transitory computer - readable storage medium according to Claim 1, the conjugate of the BS(θ) gate is BS(-θ). A non - transitory computer - readable storage medium

10. In the non - transitory computer - readable storage medium according to Claim 1, the BS(θ) gate BS(θ) = [[1, 0, 0, 0], [0, cos(θ), sin(θ), 0], [0, -sin(θ), cos(θ), 0], [0, 0, 0, 1]] A non - transitory computer - readable storage medium having the form of

11. A method for executing a quantum circuit by a quantum computer, wherein the quantum computer includes at least N quantum bits q n where n is an integer value from 1 to N, and the method comprises Execute a first branching circuit including a quantum gate applied to N / 2 quantum bits q 1 -q N / 2 Subsequent to the execution of the first branching circuit, the value of the quantum bit q 2 is the parity of the quantum bit q 2 -q N / 2 indicating, and executing, by the quantum computer, a second branch circuit simultaneously with the first branch circuit, the second branch circuit including quantum gates applied to N / 2 quantum bits q (N / 2+1) -q N ; and The quantum computer executes a gadget circuit after the first branch circuit and the second branch circuit, and the gadget circuit includes quantum gates applied to quantum bits q 1 , q 2 , and q (N / 2+1) . One of the quantum gates of the gadget circuit is a BS(θ) gate, and the BS(θ) gate is a two-qubit quantum gate represented by a single parameter. Quantum bit q 2 When the value of is 0, the BS(θ) gate is applied to the quantum bit q 1 and q (N / 2+1) and the BS(θ) gate is a two-qubit gate represented by a single parameter, Quantum bit q 2 When the value of is 1, the conjugate of the BS(θ) gate is applied to the quantum bit q 1 and q (N / 2+1) which is applied to, and A method including

12. In the method according to Claim 11, executing the first branch circuit Quantum bit q of N / 4 1 -q N / 4 Executing a third branching circuit including a quantum gate applied to, and following the execution of the third branching circuit, quantum bit q 2 The value of is the parity of quantum bit q 2 -q N / 4 indicating, and Simultaneously with the third branching circuit, execute a fourth branching circuit including a quantum gate applied to N / 4 quantum bits q (N / 4+1) -q N / 2 ; and executing a second gadget circuit after the third branching circuit and the fourth branching circuit, the second gadget circuit being for qubits q 1 , q 2 and q (N / 4+1) and including quantum gates applied to them, one of the quantum gates of the second gadget circuit being a second BS(θ) gate Quantum bit q 2 When the value of is 0, the second BS(θ) gate is applied to the quantum bit q 1 and q (N / 4+1) and Quantum bit q 2 When the value of is 1, the conjugate of the second BS(θ) gate is applied to the quantum bit q 1 and q (N / 4+1) , and A method including

13. The method according to claim 11, further comprising performing an X gate applied to the quantum bit q 1 after the gadget circuit.

14. In the method according to Claim 13 To execute a second gadget circuit after the X gate, the second gadget circuit being quantum bits q 1 , q 2 , and q (N / 2+1) including quantum gates applied to, one of the quantum gates of the second gadget circuit being a second BS(θ) gate, Quantum bit q 2 When the value of is 0, the conjugate of the BS(θ) gate is applied to the quantum bit q 1 and q (N / 2+1) and Quantum bit q 2 When the value of is 1, the BS(θ) gate is applied to the quantum bit q 1 and q (N / 2+1) which is, A method further including

15. In the method according to Claim 14 Executing a third branch circuit after the second gadget circuit, wherein the third branch circuit includes quantum gates applied to N / 2 quantum bits q 1 -q N / 2 and the quantum gates of the third branch circuit match the quantum gates of the first branch circuit, except that the quantum gates of the third branch circuit are arranged in reverse order and the BS(θ) gates of the third branch circuit are conjugated, A method further including

16. In the method according to Claim 15 To execute a fourth branch circuit simultaneously with the third branch circuit, the fourth branch circuit including quantum bits q (N / 2+1) -q N and the quantum gates applied to the fourth branch circuit being identical to the quantum gates of the second branch circuit except that the quantum gates of the fourth branch circuit are arranged in reverse order and the BS(θ) gates of the fourth branch circuit are conjugated, A method further including

17. In the method according to Claim 11, executing the first branch circuit Apply the second BS(θ) gate to qubits q 1 and q 2 and apply the third BS(θ) gate to qubits q 3 and q 4 to execute the first layer Apply a first controlled Z gate (CZ gate) to qubits q 1 and q 2 and execute a second layer Execute a third layer that applies a fourth BS(θ) gate to qubits q 1 and q 3 and, Apply the second CZ gate to qubits q 1 and q 2 and apply the first controlled-X gate (CX gate) to qubits q 3 and q 4 to execute the fourth layer Execute the fifth layer that applies to the second CX gate on qubits q 2 and q 3 ; and A method including

18. In the method according to Claim 11, executing the gadget circuit Execute the first layer that applies the first controlled Z gate (CZ gate) to qubits q 1 and q 2 and Apply the BS(θ) gate to qubits q 1 and q (N / 2+1) and execute a second layer Apply the second CZ gate to qubits q 1 and q 2 and execute a third layer A method including

19. In the method according to Claim 11, the conjugate of the BS(θ) gate is BS(-θ). A method

20. A quantum circuit for execution by a quantum computer, the quantum circuit comprising: N = 2 K and K ≧ 2, and n is an integer value from 1 to N, and q is an N-qubit n and recursive circuit levels K from K = 1 to K, Each circuit level k includes the level k circuit of (N / 2 k ), and each level k circuit includes one or more quantum gates applied to the quantum bit q n of 2 ｋ . For each level k circuit, the 2 k quantum bits include a first quantum bit and a second quantum bit for that level K circuit. Each level 1 circuit includes a BS(θ) gate applied to two of the qubits q n The BS(θ) gate is a two-qubit quantum gate represented by a single parameter. One of the two qubits is the first qubit of the level 1 circuit, and the other of the two qubits is the second qubit of the level 1 circuit. for each level k circuit where K ≧ 2, one of the level (k - 1) circuits as a first branch circuit and the other of the level (k - 1) circuits as a second branch circuit, and a gadget circuit including a BS(θ) gate, wherein when the value of the second qubit of the first branch circuit is 0, the BS(θ) gate is applied to the first qubit of the first branch circuit and the first qubit of the second branch circuit, and when the value of the second qubit of the first branch circuit is 1, the conjugate of the BS(θ) gate is applied to the first qubit of the first branch circuit and the first qubit of the second branch circuit, a quantum circuit.

21. A quantum circuit executed by a quantum computer, the quantum computer including at least N quantum bits qn, where n is an integer value from 1 to N, the quantum circuit comprising: a first branch circuit including quantum gates applied to N / 2 quantum bits q1 - qN / 2, wherein following execution of the first branch circuit, the value of qubit q2 indicates the parity of qubits q2 - qN / 2, the first branch circuit; a second branch circuit configured to be executed simultaneously with the first branch circuit, the second branch circuit including quantum gates applied to N / 2 quantum bits q(N / 2 + 1) - qN, the second branch circuit; a gadget circuit configured to be executed after the first branch circuit and the second branch circuit, the gadget circuit including quantum gates applied to qubits q1, q2 and q(N / 2 + 1), one of the quantum gates of the gadget circuit being a BS(θ) gate, the BS(θ) gate being a two - qubit quantum gate represented by a single parameter, wherein when the value of qubit q2 is 0, the BS(θ) gate is applied to qubits q1 and q(N / 2 + 1), and when the value of qubit q2 is 1, the conjugate of the BS(θ) gate is applied to qubits q1 and q(N / 2 + 1), the gadget circuit; a quantum circuit including. A method comprising executing a quantum circuit by a quantum computer, wherein the quantum computer includes at least N quantum bits qn where N = 2K and K ≧ 2, and n is an integer value from 1 to N, and the quantum circuit includes recursive circuit levels from K = 1 to K of K, each circuit level k includes (N / 2k) level k circuits, each level k circuit includes one or more quantum gates applied to 2k of the quantum bits qn, and the 2k quantum bits for each level k circuit include a first quantum bit and a second quantum bit for that level K circuit, each level 1 circuit includes a BS(θ) gate applied to two of the quantum bits qn, the BS(θ) gate is a two-qubit quantum gate represented by a single parameter, one of the two quantum bits is the first quantum bit of the level 1 circuit, and the other of the two quantum bits is the second quantum bit of the level 1 circuit, for each level k circuit where K ≧ 2, one of the level (k - 1) circuits as a first branch circuit and the other of the level (k - 1) circuits as a second branch circuit, and a gadget circuit including a BS(θ) gate, wherein when the value of the second quantum bit of the first branch circuit is 0, the BS(θ) gate is applied to the first quantum bit of the first branch circuit and the first quantum bit of the second branch circuit, and when the value of the second quantum bit of the first branch circuit is 1, the conjugate of the BS(θ) gate is applied to the first quantum bit of the first branch circuit and the first quantum bit of the second branch circuit. A non-transitory computer-readable storage medium including stored instructions, wherein when the stored instructions are executed by a quantum computer, the quantum computer is caused to perform an operation including executing a quantum circuit by the quantum computer, the quantum computer includes at least N quantum bits qn where N = 2K and K ≧ 2, and n is an integer value from 1 to N, and the quantum circuit includes recursive circuit levels from K = 1 to K of K, Each circuit level k includes (N / 2^k) level-k circuits, each level-k circuit includes one or more quantum gates applied to 2^k of the quantum bits q_n, and the 2^k quantum bits for each level-k circuit include, for that level-k circuit, a first quantum bit and a second quantum bit. Each level-1 circuit includes a BS(θ) gate applied to two of the quantum bits q_n, the BS(θ) gate being a two-qubit quantum gate represented by a single parameter, one of the two quantum bits being the first quantum bit of the level-1 circuit and the other of the two quantum bits being the second quantum bit of the level-1 circuit. For each level k circuit where k≥2, includes, as a first branch circuit, one of the level-(k - 1) circuits, and, as a second branch circuit, the other of the level-(k - 1) circuits, and a gadget circuit including a BS(θ) gate. When the value of the second quantum bit of the first branch circuit is 0, the BS(θ) gate is applied to the first quantum bit of the first branch circuit and the first quantum bit of the second branch circuit. When the value of the second quantum bit of the first branch circuit is 1, the conjugate of the BS(θ) gate is applied to the first quantum bit of the first branch circuit and the first quantum bit of the second branch circuit, a non-transitory computer-readable storage medium.

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