Display driver and display device

Abstract

PURPOSE: To provide a display driver and a display device with which it is possible to detect a break in wiring that connects between a display panel and the display driver.CONSTITUTION: Each of a plurality of output circuits is provided, corresponding to each of a plurality of external terminals, and connected to one corresponding external terminal among the plurality of external terminals. Each of the plurality of the output circuits includes: an op-amp that outputs a current to one external terminal until an external terminal voltage becomes equal to a grayscale voltage that is received by an input terminal; and a disconnection detection circuit for detecting whether or not a wiring connected to the one external terminal is disconnected. The disconnection detection circuit supplies a test voltage, in place of the grayscale voltage, to the input terminal of the op-amp in the non-display period of each video signal frame, and measures the time taken until the voltage of the one external terminal exceeds a reference voltage from there, as a rise time. Then, on the basis of the rise time measured in one frame and a rise time measured in the other frame, a disconnection detection signal is outputted that represents whether or not the wiring connected to the one external terminal is disconnected.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a display driver and a display device that drive a display panel according to a video signal.

Background Art

[0002] In recent years, vehicles have emerged in which display panels such as liquid crystal display panels and organic EL (Electro Luminescence) display panels are used to display the scenery around the vehicle, the state of the vehicle, and driving information. Incidentally, if the display panel malfunctions during vehicle operation and incorrect display is made, there is a risk of hindering driving.

[0003] Therefore, a display device has been proposed that can detect whether or not display abnormalities or panel failures occur on the display driver side for the display panel in operation, and notify the controller side of the detection result, so as to cope with display panel failures (see, for example, Patent Document 1).

[0004] In the display device described in Patent Document 1, a loop-shaped disconnection detection wiring is wired along the outer edge on the glass substrate of a display panel in which a plurality of gate lines and source lines cross and are juxtaposed. Further, the display driver is provided with a disconnection detection circuit that detects whether or not the disconnection detection wiring is disconnected by applying a detection voltage to the disconnection detection wiring, and detects that it is disconnected. That is, in the display device, when a crack or other damage occurs in the outer contour or glass substrate of the display panel, the disconnection detection wiring is disconnected due to the damage. Therefore, when this disconnection is detected, it is determined that a failure has occurred in the display panel.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the display device described in Patent Document 1, although damage to the outer contour of the display panel or the glass substrate can be detected as a failure, disconnection of the wiring connecting between the display driver and the display panel cannot be detected.

[0007] Therefore, an object of the present invention is to provide a display driver and a display device capable of detecting disconnection of the wiring connecting between a display panel and a display driver.

Means for Solving the Problem

[0008] The display driver according to the present invention includes a plurality of external terminals, and a plurality of output circuits provided corresponding to the plurality of external terminals respectively and each connected to a corresponding one of the plurality of external terminals, and outputting a plurality of output voltages obtained by amplifying a plurality of gradation voltages based on a video signal from the plurality of external terminals, and supplying the plurality of output voltages to a plurality of source lines of a display panel via a plurality of wirings connected to the plurality of external terminals. Each of the plurality of output circuits includes an operational amplifier that receives the gradation voltage at an input terminal and outputs a current to the one external terminal until the voltage of the external terminal becomes equal to the voltage received at the input terminal, and a disconnection detection circuit that detects whether or not the wiring connected to the one external terminal is disconnected. The disconnection detection circuit includes a test voltage supply unit that supplies a test voltage to the input terminal of the operational amplifier during a non-display period of each frame in the video signal instead of the gradation voltage, a measurement unit that measures, as a rise time, the time taken until the voltage of the one external terminal exceeds a reference voltage after supplying the test voltage to the input terminal of the operational amplifier, and a disconnection determination unit that outputs a disconnection detection signal indicating whether or not the wiring connected to the one external terminal is disconnected based on the rise time measured in one frame of each of the frames and the rise time measured in other frames.

[0009] In addition, the display device according to the present invention includes a plurality of external terminals, and a plurality of output circuits provided corresponding to the plurality of external terminals respectively and each connected to a corresponding one of the plurality of external terminals, and outputs a plurality of output voltages obtained by amplifying a plurality of gradation voltages based on a video signal from the plurality of external terminals. A display driver, a display panel having a plurality of source lines, and a plurality of wirings connecting the plurality of external terminals and the plurality of source lines. Each of the plurality of output circuits receives the gradation voltage at an input terminal and outputs a current to the one external terminal until the voltage of the external terminal becomes equal to the voltage received at the input terminal. An operational amplifier, and a disconnection detection circuit that detects whether or not the wiring connected to the one external terminal is disconnected. The disconnection detection circuit includes a test voltage supply unit that supplies a test voltage to the input terminal of the operational amplifier instead of the gradation voltage during a non-display period of each frame in the video signal, and supplies the test voltage to the input terminal of the operational amplifier. A measurement unit that measures, as a rise time, the time taken until the voltage of the one external terminal exceeds a reference voltage after the test voltage is supplied, and the rise time measured in one frame of each of the frames and the rise time measured in other frames. When they do not match, a disconnection determination unit that determines that the wiring connected to the one external terminal is disconnected and outputs a disconnection detection signal indicating that the disconnection has occurred.

Advantages of the Invention

[0010] According to the present invention, during the normal display operation of the display device, it is possible to individually detect whether or not a disconnection has occurred in the plurality of wirings connecting the display driver and each of the plurality of source lines of the display panel.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0013] FIG. 1 is a block diagram showing the configuration of a display device 100 as a display device according to the present invention.

[0014] The display device 100 includes a drive control unit 11, a gate driver 12, a source driver 13, and a capacitive display panel 20.

[0015] In the display panel 20, gate lines G1 to Gm (m is an integer of 2 or more) each extending in the horizontal direction of the two-dimensional screen and source lines S1 to Sn (n is an integer of 2 or more) each extending in the vertical direction of the two-dimensional screen are arranged to intersect. At the intersection of the gate line and the source line, a display cell PC such as a liquid crystal element or an organic EL element is formed, for example.

[0016] The drive control unit 11 receives the video signal VS, generates a scanning signal according to the horizontal synchronization signal included in the video signal VS, and supplies this to the gate driver 12. Further, the drive control unit 11 generates a video data signal VPD including various control signals including a data load signal and a clock signal representing the data capture timing together with the horizontal synchronization signal and the vertical synchronization signal included in the video signal VS, and a series PD of display data pieces representing the luminance level of each pixel in, for example, 8 bits, and supplies this to the source driver 13.

[0017] Still, when the drive control unit 11 receives the disconnection information signal BK sent from the source driver 13 and the disconnection information signal BK indicates a wiring that is disconnected (also referred to as a disconnected wiring), for example, a warning message such as "Disconnection exists" and a series of display data pieces representing the disconnected wiring in character information or the like are included in the series of display data pieces based on the video signal VS.

[0018] The gate driver 12 generates scan pulses in response to the scan signals supplied from the drive control unit 11 and sequentially and selectively applies these to the gate lines G1 to Gn of the display panel 20.

[0019] The source driver 13 individually detects whether each of the wirings L1 to Ln connecting between the display panel 20 and the source driver 13 is disconnected. When there is a disconnected wiring, a signal indicating the wiring is supplied to the drive control unit 11 as the above-described disconnection information signal BK.

[0020] Furthermore, the source driver 13 takes in the above-described video data signal VPD and generates n output voltages GV1 to GVn for each horizontal scan period based on the video data signal VPD. Then, the source driver 13 supplies the output voltages GV1 to GVn to the source lines S1 to Sn of the display panel 20 via the wirings L1 to Ln connecting each of the source driver 13 and the source lines S1 to Sn of the display panel 20. Thereby, an image based on the video data signal VPD, or an image in which a warning message such as "Disconnection exists" and character information or the like representing the disconnected wiring as described above are superimposed on this image is displayed on the display panel 20.

[0021] FIG. 2 is a block diagram showing an example of the internal configuration of the source driver 13.

[0022] As shown in FIG. 2, the source driver 13 includes a signal extraction unit 130, a data latch unit 131, a decoder unit 132, and an output unit 133.

[0023] The signal extraction unit 130 extracts the series PD of display data pieces and the above-described various control signals from the video data signal VPD, and supplies them to the data latch unit 131 respectively. Further, the signal extraction unit 130 supplies the horizontal synchronization signal included in the video data signal VPD to the output unit 133 as the horizontal synchronization signal Hs. Furthermore, based on the vertical synchronization signal included in the video data signal VPD, the signal extraction unit 130 generates a binary signal representing the vertical blanking period as logic level 1 and the display operation period as logic level 0 as the vertical blanking signal Vblk, and supplies this to the output unit 133.

[0024] The data latch unit 131 captures the series PD of the above-described display data pieces at the timing of the data load signal. And each time the data latch unit 131 captures n display data pieces for one horizontal scanning period, it supplies them to the decoder unit 132 as display data J1 to Jn respectively.

[0025] For each of the display data J1 to Jn, the decoder unit 132 selects a gradation voltage corresponding to the luminance level indicated by the display data Jq (q is an integer from 1 to n) from, for example, 256 gradation voltages having different voltage values from each other. And the decoder unit 132 supplies the n gradation voltages selected as described above based on the display data J1 to Jn to the output unit 133 as gradation voltages V1 to Vn.

[0026] The output unit 133 includes output circuits AM1 to AMn provided corresponding to the source lines S1 to Sn of the display panel 20, respectively, and a disconnection information generation unit DIG.

[0027] The output circuits AM1 to AMn receive the gradation voltages V1 to Vn, and by individually amplifying each of them, generate output voltages GV1 to GVn having voltage values corresponding to the voltage pairs of the respective gradation voltages. The output circuits AM1 to AMn output the generated output voltages GV1 to GVn from the external terminals TM1 to TMn to the display panel 20. Note that the source lines S1 to Sn of the display panel 20 are respectively connected to the external terminals TM1 to TMn. Therefore, the output voltages GV1 to GVn output from the external terminals TM1 to TMn of the source driver 13 are respectively supplied to the source lines S1 to Sn of the display panel 20 via the wirings L1 to Ln.

[0028] Furthermore, the output circuits AM1 to AMn detect whether or not the wiring is broken for each of the wirings L1 to Ln, generate disconnection detection signals f1 to fn indicating the detection result for each wiring, and supply them to the disconnection information generation unit DIG. When there is a disconnection detection signal indicating that a disconnection has occurred among the disconnection detection signals f1 to fn, the disconnection information generation unit DIG generates information indicating the wiring (disconnected wiring) in which the disconnection has occurred as a disconnection information signal BK, and supplies this to the drive control unit 11.

[0029] Note that the above-described output circuits AM1 to AMn have the same internal configuration.

[0030] Hereinafter, the internal configuration of the output circuit AM1 will be described by extracting it from the output circuits AM1 to AMn.

[0031] FIG. 3 is a circuit diagram showing an example of the internal configuration of the output circuit AM1.

[0032] The output circuit AM1 includes a disconnection detection circuit 31 in addition to an operational amplifier 30 provided to generate, as an output voltage GV1, a voltage obtained by amplifying the gradation voltage V1.

[0033] The output terminal of the operational amplifier 30 is connected to the external terminal TM1. The operational amplifier 30 receives the gradation voltage V1 at its non-inverting input terminal, and outputs a current to the external terminal TM1 until the voltage on the external terminal TM1 becomes equal to the voltage received at the non-inverting input terminal.

[0034] The disconnection detection circuit 31 includes an AND gate AN1, a selector SEL, a switch SW1, comparators Q1 and Q2, a counter CTR, and latches LC1 and LC2.

[0035] The AND gate AN1 supplies a selection signal having a logic level of 1 to the selector SEL during a period in which both the horizontal synchronization signal Hs and the vertical blanking signal Vblk have a logic level of 1, and a selection signal having a logic level of 0 during a period in which either or both of them have a logic level of 0. That is, the AND gate AN1 supplies a selection signal having a logic level of 1 to the selector SEL only at the horizontal synchronization timing during the vertical blanking period, and supplies a selection signal having a logic level of 0 to the selector SEL during other periods.

[0036] The selector SEL receives a gradation voltage V1 and a test voltage VTST having a predetermined voltage value, and selects one of these gradation voltage V1 and test voltage VTST based on the above selection signal. That is, the selector SEL selects the test voltage VTST at the horizontal synchronization timing during the vertical blanking period, and selects the gradation voltage V1 during other periods. Then, the selector SEL supplies the selected one of the gradation voltage V1 and the test voltage VTST to the non-inverting input terminal of the operational amplifier 30.

[0037] The switch SW1 is turned on only during a period in which the vertical blanking signal Vblk has a logic level of 1, that is, only during the vertical blanking period, and supplies the voltage of the external terminal TM1 as a disconnection monitoring voltage FB to the comparator Q1.

[0038] The comparator Q1 compares the magnitudes of a predetermined reference voltage Vref and the disconnection monitoring voltage FB, and supplies a count stop signal CS having a logic level of 1 for prompting count stop to the counter CTR when the disconnection monitoring voltage FB is higher than the reference voltage Vref.

[0039] The counter CTR becomes enabled only during the period when the vertical blanking signal Vblk has a logic level of 1, that is, during the vertical blanking period, and performs the following operations. That is, the counter CTR starts counting the number of pulses of the clock signal CLK from a count value of zero in response to the horizontal synchronization signal Hs, and increments the count value by 1 for each pulse of the clock signal CLK. Here, when a count stop signal CS of logic level 1 is supplied from the comparator Q1, the counter CTR stops the counting operation and supplies a count signal Cout representing the count value after the count stop to the latch LC1.

[0040] That is, the counter CTR obtains the count value after the count stop as information representing the time (rise time) required from when the test voltage VTST is supplied to the non-inverting input terminal of the operational amplifier 30 until the voltage (FB) on the external terminal TM1 exceeds the reference voltage Vref. Note that the counter CTR is disabled during the period when the vertical blanking signal Vblk has a logic level of 0, that is, during the normal display operation period, and stops the above-described counting operation.

[0041] The latch LC1 captures the count signal Cout when the vertical blanking signal Vblk transitions from a logic level of 1 to a logic level of 0, that is, when transitioning from the vertical blanking period to the display operation period. Then, the latch LC1 supplies a signal representing the count value indicated by the captured count signal Cout to the latch LC2 and the comparator Q2 as the first frame count signal C1.

[0042] The latch LC2 captures the first frame count signal C1 when the vertical blanking signal Vblk transitions from a logic level of 1 to a logic level of 0. Then, the latch LC2 supplies a signal representing the count value indicated by the captured first frame count signal C1 to the comparator Q2 as the second frame count signal C2.

[0043] Comparator Q2 determines whether or not the count value indicated by the first frame count signal C1 matches the count value indicated by the second frame count signal C2. Here, when the two match, comparator Q2 determines that there is no disconnection in wiring L1, and outputs a disconnection detection signal f1, for example, with a logic level of 0, indicating that there is no disconnection. On the other hand, when the count value indicated by the first frame count signal C1 does not match the count value indicated by the second frame count signal C2, comparator Q2 determines that there is a disconnection in wiring L1, and outputs a disconnection detection signal f1 with a logic level of 1, indicating that there is a disconnection.

[0044] In addition, as described above, each of the output circuits AM2 to AMn other than the output circuit AM1 also includes a disconnection detection circuit 31 (AN1, SEL, SW1, Q1, Q2, CTR, LC1, and LC2) shown in FIG. 3 together with the operational amplifier 30, and disconnection detection signals f2 to fn that individually indicate whether or not there is a disconnection in each of the wirings L2 to Ln are output.

[0045] Hereinafter, taking the output circuit AM1 shown in FIG. 3 as an example, a disconnection detection operation will be described in which the disconnection detection circuit 31 detects whether or not there is a disconnection in the wiring L1 that connects the external terminal TM1 of the source driver 13 and the source line S1 of the display panel 20.

[0046] In addition, the disconnection detection circuit 31 uses the vertical blanking period, which is a non-display period within each frame in the video signal, to detect whether or not there is a disconnection for each vertical blanking period. Therefore, two consecutive frames (the first and second frames) are extracted, and the disconnection detection operation by the disconnection detection circuit 31 will be described separately for the case where there is no disconnection across the first and second frames and the case where a disconnection occurs immediately before the second frame.

[0047] [Case of no disconnection] FIG. 4 is a time chart showing an example of the operation waveforms in the disconnection detection circuit 31 of the output circuit AM1 when there is no disconnection in the wiring L1.

[0048] As shown in FIG. 4, within the vertical blanking period during which the vertical blanking signal Vblk maintains a logic level of 1, the switch SW1 is turned on, and the voltage of the external terminal TM1 is supplied to the comparator Q1 as the disconnection monitoring voltage FB.

[0049] Here, in response to the first pulsed (logic level 1) horizontal synchronizing signal Hs supplied during the vertical blanking period of the first frame, the selector SEL supplies the test voltage VTST to the operational amplifier 30 instead of the gradation voltage V1.

[0050] The operational amplifier 30 outputs a current to the external terminal TM1 until its output voltage, that is, the voltage of the external terminal TM1, becomes equal to the test voltage VTST. At this time, since there is no disconnection in the wiring L1, the voltage value of the disconnection monitoring voltage FB gradually increases at a speed based on the wiring capacitance of the wiring L1 and the source line S1 connected to the wiring L1.

[0051] Also, in response to the first pulsed (logic level 1) horizontal synchronizing signal Hs during the vertical blanking period of the first frame described above, as shown in FIG. 4, the counter CTR starts counting the number of pulses of the clock signal CLK from zero.

[0052] Here, since there is no disconnection in the wiring L1, for example, as shown in FIG. 4, immediately after the count value (Cout) of the counter CTR reaches "4", the voltage value of the disconnection monitoring voltage FB exceeds the reference voltage Vref. Therefore, when the voltage value of the disconnection monitoring voltage FB exceeds the reference voltage Vref, the comparator Q1 supplies a count stop signal CS of logic level 1 that prompts the stop of the counting operation to the counter CTR to stop the counting operation of the counter CTR. As a result, the counter CTR supplies the count signal Cout indicating the count value "4" to the latch LC1 as information representing the rise time from when the test voltage VTST is supplied to the non-inverting input terminal of the operational amplifier 30 until the disconnection monitoring voltage FB on the external terminal TM1 exceeds the reference voltage Vref.

[0053] The latch LC1 captures a count signal Cout indicating the count value "4" at the timing of the falling edge of the vertical blanking signal Vblk, and supplies this as the first frame count signal C1 to the latch LC2 and the comparator Q2.

[0054] Incidentally, if the wiring L1 is not disconnected before the start of the vertical blanking period of the second frame, the disconnection detection circuit 31 performs the same operation as described above even within the vertical blanking period of the next second frame.

[0055] That is, by supplying the test voltage VTST to the operational amplifier 30 instead of the gradation voltage V1, as shown in FIG. 4, the voltage value of the disconnection monitoring voltage FB increases at the same speed as in the case of the vertical blanking period of the first frame. Then, immediately after the count value (Cout) of the counter CTR reaches "4", the voltage value of the disconnection monitoring voltage FB exceeds the reference voltage Vref. Therefore, after the counter CTR supplies the test voltage VTST to the non-inverting input terminal of the operational amplifier 30, as information representing the rising time taken until the disconnection monitoring voltage FB on the external terminal TM1 exceeds the reference voltage Vref, the counter CTR supplies the count signal Cout indicating the count value "4" to the latch LC1. Thereby, the latch LC1 captures the count signal Cout indicating the count value "4" at the timing of the falling edge of the vertical blanking signal Vblk, and supplies this as the first frame count signal C1 to the comparator Q2.

[0056] On the other hand, the latch LC2 captures the first frame count signal C1 indicating the count value "4" captured by the latch LC1 during the vertical blanking period of the first frame at the timing of the falling edge of the vertical blanking signal Vblk, and supplies this as the second frame count signal C2 to the comparator Q2.

[0057] At this time, since the count value "4" indicated by the first frame count signal C1 and the count value "4" indicated by the second frame count signal C2 match, the comparator Q2 determines that there is no disconnection in the wiring L1, and outputs a disconnection detection signal f1 with a logic level 0 indicating that there is no disconnection.

[0058] [In the case of disconnection] FIG. 5 is a time chart showing an example of the operation waveforms in the disconnection detection circuit 31 when the wiring L1 is disconnected immediately before the vertical blanking period of the next second frame, although there is no disconnection in the wiring L1 at the stage of the vertical blanking period of the first frame.

[0059] Note that the operation during the vertical blanking period of the first frame shown in FIG. 5 is the same as that shown in FIG. 4, so the description of the operation is omitted.

[0060] During the vertical blanking period of the second frame shown in FIG. 5, the test voltage VTST is supplied to the non-inverting input terminal of the operational amplifier 30, and as shown in FIG. 5, the voltage value of the disconnection monitoring voltage FB increases.

[0061] However, since the wiring L1 is disconnected and the connection to the source line S1 is interrupted, the wiring capacitance at the external terminal TM1 becomes significantly smaller compared to the case where such a disconnection does not occur. Therefore, the voltage value of the disconnection monitoring voltage FB increases at a high speed by that amount. For example, when the count value (Cout) of the counter CTR is "3" as shown in FIG. 5, the voltage value of the disconnection monitoring voltage FB exceeds the reference voltage Vref. Therefore, the counter CTR stops the counting operation, and supplies the count value "3" after the stop of the counting operation to the latch LC1 as the count signal Cout representing the above-mentioned rise time. As a result, the latch LC1 captures the count signal Cout indicating the count value "3" at the timing of the falling edge of the vertical blanking signal Vblk, and supplies this to the comparator Q2 as the first frame count signal C1.

[0062] On the other hand, during the vertical blanking period of the first frame, the latch LC2 captures the first frame count signal C1 representing the count value "4" captured by the latch LC1 as the rising time described above, at the timing of the falling edge of the vertical blanking signal Vblk, and supplies this to the comparator Q2 as the second frame count signal C2.

[0063] At this time, since the count value "3" indicated by the first frame count signal C1 and the count value "4" indicated by the second frame count signal C2 do not match, the comparator Q2 determines that there is a disconnection in the wiring L1, and outputs a disconnection detection signal f1 with a logic level 1 indicating that a disconnection has occurred.

[0064] As described in detail above, in the source driver 13, disconnections of the wirings L1 to Ln individually connecting between the external terminals TM1 to TM1n and the source lines S1 to Sn are detected as follows by the disconnection detection circuits 31 provided in the output circuits AM1 to AMn.

[0065] That is, during each vertical blanking period, the disconnection detection circuit 31 supplies a test voltage VTST to the non-inverting input terminal of the operational amplifier 30 instead of the gradation voltage Vt (t is an integer from 1 to n). Further, by counting the number of pulses of the clock signal CLK from the time point when such a test voltage VTST is supplied until the disconnection monitoring voltage FB on the external terminal TMt exceeds the reference voltage Vref, the rising time of the disconnection monitoring voltage FB is measured.

[0066] Next, the disconnection detection circuit 31 compares (Q2) whether the rise time (C1) measured during the vertical blanking period of the first frame among two consecutive frames matches the rise time (C2) measured during the vertical blanking period of the second frame. Here, when both rise times (C1, C2) match, the disconnection detection circuit 31 determines that no disconnection has occurred in the wiring Lt (where t is an integer from 1 to n), and outputs a disconnection detection signal ft with, for example, a logic level 0 indicating that. On the other hand, when both rise times (C1, C2) do not match, the disconnection detection circuit 31 determines that a disconnection has occurred in the wiring Lt, and outputs a disconnection detection signal ft with a logic level 1 indicating that.

[0067] In this way, in the disconnection detection circuit 31, in view of the fact that when the wiring Lt is disconnected, the rate of change of the voltage on the external terminal TMt becomes faster compared to when it is not disconnected, when the rise times (C1, C2) of the voltage on the external terminal TMt do not match between two frames, it is determined that a disconnection has occurred.

[0068] Thereby, during normal use of the display device 100, it becomes possible to determine whether a disconnection has occurred in the wirings L1 to Ln that connect the external terminals TM1 to TMn of the source driver 13 and the source lines S1 to Sn of the display panel 20 on the source driver 13 side.

[0069] Note that in the above embodiment, the disconnection detection process is performed during the vertical blanking period as the non-display period within each frame, but the disconnection detection process as described above may be performed during a non-display period other than the vertical blanking period.

[0070] Also, in the above embodiment, the count value of the number of pulses of the clock signal by the counter CTR is used as the rise time from when the test voltage VTST is supplied to the non-inverting input terminal of the operational amplifier 30 until the voltage (FB) of the external terminal exceeds the reference voltage Vref, but the rise time itself may be measured without using a counter.

[0071] In the above-described embodiment, when the rise times (C1, C2) of the voltages of the external terminals TMt measured by the two frames do not match, it is determined that a disconnection has occurred. However, when a frequency higher than the clock signal CLK shown in FIG. 3 is adopted as the frequency of the clock signal CLK, even if no disconnection has occurred, a slight measurement error may occur in the rise times (C1, C2) measured by the two frames respectively.

[0072] Therefore, in the comparator Q2, when the difference between the rise time (C1) measured in the first frame and the rise time (C1) measured in the second frame is equal to or greater than a predetermined value (corresponding to the measurement error difference), it may be determined that a disconnection has occurred.

[0073] In the above-described embodiment, disconnection detection is performed by comparing the rise times measured in the consecutive first and second frames respectively. However, the two frames for measuring the rise time do not necessarily have to be consecutive frames.

[0074] In the above-described embodiment, the test voltage VTST is supplied to the non-inverting input terminal of the operational amplifier 30 at the timing of the horizontal synchronization signal Hs, and the counting operation of the counter CTR is started. However, the test voltage VTST may be supplied to the non-inverting input terminal of the operational amplifier 30 and the counting operation of the counter CTR may be started in response to a one-pulse timing signal generated within the vertical blanking period based on the vertical synchronization signal.

[0075] In short, the display driver according to the present invention includes a plurality of external terminals (TM1 to TM_n), and a plurality of output circuits (AM1 to AM_n) provided corresponding to each external terminal and each connected to one corresponding external terminal, which output output voltages (GV1 to GV_n) obtained by amplifying gradation voltages (V1 to V_n) based on video signals from the external terminals (TM1 to TM_n) to supply the output voltage group to the source lines (S1 to S_n) of the display panel (20) via the wirings (L1 to L_n).

[0076] Here, each of the plurality of output circuits (AM1 to AMn) may have the following operational amplifier and a disconnection detection circuit that detects whether or not the wiring connected to the external terminal of 1 above is disconnected.

[0077] That is, the operational amplifier (30) receives a gradation voltage at the input terminal and outputs a current to the external terminal of 1 above until the voltage of the external terminal of 1 above becomes equal to the voltage received at the input terminal.

[0078] The test voltage supply units (AN1, SEL) supply a test voltage (VTST) to the input terminal of the operational amplifier instead of the gradation voltage during the non-display period (for example, the vertical blanking period) of each frame in the video signal. The measurement unit (Q1, CTR) measures the rise time (Cout) as the time taken for the voltage (FB) of the external terminal of 1 above to exceed the reference voltage (Vref) after supplying the test voltage to the input terminal of the operational amplifier. The disconnection determination unit (LC1, LC2, Q2) outputs a disconnection detection signal (f1) indicating whether or not the wiring connected to the external terminal of 1 above is disconnected based on the rise time (C1) measured in one frame out of each frame and the rise time (C2) measured in other frames.

Explanation of symbols

[0079] 13 Source driver 20 Display panel 30 Operational amplifier 31 Disconnection detection circuit 100 Display device AM1~AMn Output circuit CTR Counter L1~Ln Wiring LC1, LC2 Latch Q1, Q2 Comparator SEL Selector S1~Sn Source line

Claims

1. A display driver including: a plurality of external terminals; and a plurality of output circuits provided corresponding to the plurality of external terminals respectively and each connected to a corresponding one of the plurality of external terminals, the plurality of output circuits outputting a plurality of output voltages obtained by amplifying a plurality of gradation voltages based on a video signal from the plurality of external terminals, and supplying the plurality of output voltages to a plurality of source lines of a display panel via a plurality of wirings connected to the plurality of external terminals, wherein each of the plurality of output circuits includes: an operational amplifier that receives the gradation voltage at an input terminal and outputs a current to the one external terminal until the voltage of the external terminal becomes equal to the voltage received at the input terminal; and a disconnection detection circuit that detects whether or not the wiring connected to the one external terminal is disconnected, wherein the disconnection detection circuit includes: a test voltage supply unit that supplies a test voltage to the input terminal of the operational amplifier during a non-display period of each frame in the video signal instead of the gradation voltage; a measurement unit that measures, as a rise time, a time taken until the voltage of the one external terminal exceeds a reference voltage after the test voltage is supplied to the input terminal of the operational amplifier; and a disconnection determination unit that outputs a disconnection detection signal indicating whether or not the wiring connected to the one external terminal is disconnected based on the rise time measured in one frame of each of the frames and the rise time measured in other frames.

2. The display driver according to claim 1, wherein the disconnection determination unit determines that the wiring connected to the one external terminal is disconnected when the rise time measured in the one frame and the rise time measured in the other frames do not match, and outputs the disconnection detection signal indicating that the wiring is disconnected.

3. The display driver according to claim 1, wherein the disconnection determination unit determines that the wiring connected to the one external terminal is disconnected when a difference between the rise time measured in the one frame and the rise time measured in the other frames is equal to or greater than a predetermined value, and outputs the disconnection detection signal indicating that the wiring is disconnected.

4. The measurement unit includes: a counter that starts a counting operation of counting the number of pulses of a clock signal at a timing when the test voltage is supplied to the input terminal of the operational amplifier to obtain a count value, A first comparator that compares the voltage of the external terminal with the reference voltage and supplies a count stop signal to the counter to stop the count operation when the voltage of the external terminal becomes higher than the reference voltage, and outputs the count value of the counter after the count operation stops as the rise time. The display driver according to any one of claims 1 to 3, characterized in that.

5. The one frame and the other frame are consecutive frames to each other, The disconnection determination unit, A first latch that captures the count value of the counter after the count operation stops at the timing of the end of the non-display period and outputs this as a first frame count signal, A second latch that captures the first frame count signal at the timing of the end of the non-display period and outputs this as a second frame count signal, A second comparator that compares whether the first frame count signal and the second frame count signal match, and outputs the disconnection detection signal indicating disconnection when they do not match. The display driver according to claim 4, characterized in that it includes.

6. The display driver according to any one of claims 1 to 5, characterized in that the non-display period is a vertical blanking period.

7. A signal extraction unit that extracts a horizontal synchronization signal and a vertical synchronization signal from the video signal, and generates a vertical blanking signal that represents whether it is a vertical blanking period in a binary value according to the vertical synchronization signal, The test voltage supply unit supplies the test voltage to the input terminal of the operational amplifier at the timing of the horizontal synchronization signal extracted while the vertical blanking signal represents the vertical blanking period, The counter becomes enabled only while the vertical blanking signal represents the vertical blanking period, and starts the count operation at the timing of the horizontal synchronization signal, The first latch and the second latch each capture the first frame count signal and the second frame count signal at the timing of the edge of the vertical blanking signal. The display driver according to claim 5, characterized in that.

8. A display device having a display driver including: a plurality of external terminals; and a plurality of output circuits provided corresponding to the plurality of external terminals respectively and each connected to a corresponding one of the plurality of external terminals, the plurality of output circuits outputting a plurality of output voltages obtained by amplifying a plurality of gradation voltages based on a video signal from the plurality of external terminals, and supplying the plurality of output voltages to a plurality of source lines of a display panel via a plurality of wirings connected to the plurality of external terminals. Each of the plurality of output circuits includes: an operational amplifier that receives the gradation voltage at an input terminal and outputs a current to the one external terminal until the voltage of the external terminal becomes equal to the voltage received at the input terminal; a disconnection detection circuit that detects whether or not the wiring connected to the one external terminal is disconnected. The disconnection detection circuit includes: a test voltage supply unit that supplies a test voltage to the input terminal of the operational amplifier instead of the gradation voltage during a non-display period of each frame in the video signal; a measurement unit that measures, as a rise time, the time taken from when the test voltage is supplied to the input terminal of the operational amplifier until the voltage of the one external terminal exceeds a reference voltage; a disconnection determination unit that, when the rise time measured in one frame of each of the frames does not match the rise time measured in other frames, determines that the wiring connected to the one external terminal is disconnected and outputs a disconnection detection signal indicating that the wiring is disconnected. The display device is characterized by having the above components.

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