Display panel and display device

Abstract

A display panel and a display device are provided, the display panel being disposed on a base substrate, the pixel unit including a pixel circuit and a light emitting element, the pixel circuit including a pixel unit including a driving transistor and a data writing transistor connected to the driving transistor, and a data cable connected to the data writing transistor, the data cable including a plurality of first type data cables and a plurality of second type data cables, the plurality of first type data cables being arranged along a first direction, the first type data cables extending along a second direction, the second type data cables including a first portion, a second portion and a third portion, the first portion and the second portion being connected by the third portion, the first portion and the second portion both extending along the second direction, the third portion extending along the first direction, the third portion and the second portion being disposed on different layers, the third portion and the first portion being disposed on different layers, the first portion being closer to the base substrate than the third portion, and the second portion being closer to the base substrate than the third portion.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device.

Background Art

[0002] With the continuous development of display technology, Active-Matrix Organic Light-Emitting Diode (AMOLED) display technology has increased in use in display devices such as mobile phones, tablet PCs, and digital cameras due to advantages such as self-emission, wide viewing angles, high contrast, low power consumption, and fast response.

[0003] Under-screen camera technology is a completely new technology proposed to increase the screen occupancy rate of display devices.

Summary of the Invention

[0004] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0005] At least one embodiment of the present disclosure provides a display panel including a base substrate, and a pixel unit located on the base substrate and including a pixel circuit and a light-emitting element. In the pixel unit, the pixel circuit is configured to drive the light-emitting element and includes a driving transistor and a data writing transistor, and the driving transistor is connected to the data writing transistor, and a data cable connected to the data writing transistor. The data cable includes a plurality of first-type data cables and a plurality of second-type data cables. The plurality of first-type data cables are arranged along a first direction, the first-type data cables extend along a second direction, the first direction intersects the second direction, the second-type data cable includes a first portion, a second portion, and a third portion, the first portion and the second portion are connected by the third portion, both the first portion and the second portion extend along the second direction, the third portion extends along the first direction, the third portion and the second portion are located in different layers, the third portion and the first portion are located in different layers, the first portion is closer to the base substrate than the third portion, and the second portion is closer to the base substrate than the third portion.

[0006] For example, in some embodiments of the present disclosure, the size of the third portion in the first direction is larger than the distance between the first portion and the second portion in the first direction.

[0007] For example, in some embodiments of the present disclosure, the display panel further includes a plurality of dummy lines, and the plurality of dummy lines and the third portion of the second-type data cable are located in the same layer.

[0008] For example, in some embodiments of the present disclosure, a plurality of the third portions are provided, and the plurality of dummy lines and the plurality of third portions are uniformly arranged in the display panel.

[0009] For example, in some embodiments of the present disclosure, the extending direction of the dummy line and the extending direction of the third portion are the same.

[0010] For example, in some embodiments of the present disclosure, the dummy line is connected to a constant voltage line.

[0011] For example, in some embodiments of the present disclosure, the constant voltage line includes at least one of a first power line, a second power line, and an initialization signal line.

[0012] For example, in some embodiments of the present disclosure, the display panel further includes a plurality of dummy data cables, and the plurality of dummy data cables, the first portion of the second type of data cable, and the second portion of the second type of data cable are all located in the same layer.

[0013] For example, in some embodiments of the present disclosure, the display panel further includes a first initialization signal line and a second initialization signal line, the pixel circuit further includes a first reset transistor and a second reset transistor, the first reset transistor is connected to the gate of the driving transistor and is configured to reset the gate of the driving transistor, the second reset transistor is connected to the first electrode of the light-emitting element and is configured to reset the first electrode of the light-emitting element, the first initialization signal line is connected to the gate of the driving transistor through the first reset transistor, the second initialization signal line is connected to the first electrode of the light-emitting element through the second reset transistor, the first initialization signal line and the second initialization signal line are not connected, and each is configured to apply a signal.

[0014] For example, in some embodiments of the present disclosure, the third portion is located between pixel circuits of two adjacent pixel units in the second direction.

[0015] For example, in some embodiments of the present disclosure, a plurality of the third portions are provided, and the plurality of third portions are dispersedly arranged within the display panel.

[0016] For example, in some embodiments of the present disclosure, the distance in the second direction between two adjacent third portions is greater than or equal to the sum of the sizes of two pixel units in the second direction.

[0017] For example, in some embodiments of the present disclosure, the plurality of third portions are uniformly arranged within a range that is at least half of the size of the display panel in the second direction.

[0018] For example, in some embodiments of the present disclosure, the base substrate has a first display area and a second display area, the first display area is located on at least one side of the second display area, the pixel unit includes a first pixel unit and a second pixel unit, both the pixel circuit and the light-emitting element of the first pixel unit are located in the first display area, the pixel circuit of the second pixel unit is located in the first display area, the light-emitting element of the second pixel unit is located in the second display area, the pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit via a conductive line, and the orthographic projection of the third portion onto the base substrate does not overlap with the orthographic projection of the conductive line onto the base substrate.

[0019] For example, in some embodiments of the present disclosure, the orthographic projection of the conductive line onto the base substrate partially overlaps with the orthographic projection of the pixel circuit of the first pixel unit onto the base substrate.

[0020] At least one embodiment of the present disclosure further provides a display device including any one of the above display panels.

[0021] For example, in some embodiments of the present disclosure, the display device further includes a photosensitive sensor located on one side of the display panel.

Brief Description of the Drawings

[0022] To more clearly illustrate the technical solutions according to the embodiments of the present disclosure, the accompanying drawings of the embodiments are briefly introduced below. Obviously, the accompanying drawings in the following description are only related to some embodiments of the present disclosure and do not limit the present disclosure.

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DETAILED DESCRIPTION OF THE INVENTION

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts fall within the protection scope of the present disclosure.

[0024] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those skilled in the art to which the present disclosure pertains. The "first", "second" and similar words used in the present disclosure do not indicate order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "include" or "contain" mean that the elements or things shown before such words cover the elements or things listed after such words and their equivalents, but do not exclude other elements or things. Similar words such as "connect" or "couple" are not limited to physical connection or mechanical connection, and may include direct or indirect electrical connection. "Upper", "lower", "left", "right", etc. only indicate relative positional relationships. If the absolute position of the described object changes, the relative positional relationships may also change.

[0025] With the development of display technology, the designs of conventional notch screens or water-drop screens can no longer gradually meet the user's requirements for a high screen occupation ratio of the display panel, and a series of display panels with a light-transmissive display area have emerged. In this type of display panel, hardware such as photosensitive sensors (for example, cameras) can be arranged in the light-transmissive display area. Since punching is not required, a true full screen can be realized while ensuring the practicality of the display panel.

[0026] In the prior art, a display panel having an under-display camera generally includes a first display area for normal display and a second display area for arranging the camera. The second display area generally includes a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit being connected to the light-emitting element and used to drive the light-emitting element to emit light. The pixel circuits and the light-emitting elements connected to each other are stacked in a direction perpendicular to the display panel.

[0027] In the prior art, since pixel circuits are also provided in the second display area, the light transmittance of the second display area is low, thereby resulting in a low display effect of the display panel.

[0028] FIG. 1 is a schematic structural diagram of a display panel provided according to an embodiment of the present disclosure. As shown in FIG. 1, the display panel can include a base substrate BS. The display panel includes a first display area R1 and a second display area R2, and the first display area R1 may be located on at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 may be surrounded by the first display area R1. The second display area R2 may also be provided at other positions, and the arrangement position of the second display area R2 can be determined as needed. For example, the second display area R2 may be located at the upper center of the base substrate BS, or at the upper left corner or the upper right corner of the base substrate BS. For example, hardware such as a photosensitive sensor (e.g., a camera) is provided in the second display area R2 of the display panel. For example, the second display area R2 is a light-transmissive display area, and the first display area R1 is a display area. For example, the first display area R1 is opaque and is only used for display.

[0029] FIG. 2 is a schematic diagram of a pixel unit of a display panel provided according to an embodiment of the present disclosure. The display panel includes a pixel unit 100 located on a base substrate. As shown in FIG. 2, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b. For example, the pixel circuit 100a is configured to provide a driving current for driving the light-emitting element 100b to emit light. For example, the light-emitting element 100b is an organic light-emitting diode (OLED), and the light-emitting element 100b emits red light, green light, blue light, or white light, etc. under the drive of the corresponding pixel circuit 100b. The color of the light emitted by the light-emitting element 100b can be determined as needed.

[0030] In order to improve the light transmittance of the second display area R2, only light-emitting elements may be arranged in the second display area R2, and the pixel circuits for driving the light-emitting elements in the second display area R2 may be arranged in the first display area R1. That is, by arranging the light-emitting elements and the pixel circuits separately, the light transmittance of the second display area R2 is improved.

[0031] FIG. 3 is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. As shown in FIG. 3, the display panel includes a plurality of first pixel circuits 10, a plurality of second pixel circuits 20, and a plurality of first light-emitting elements 30 located in the first display area R1, and a plurality of second light-emitting elements 40 located in the second display area R2. For example, the plurality of second pixel circuits 20 may be provided at intervals between the plurality of first pixel circuits 10.

[0032] For example, as shown in FIG. 3, at least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light-emitting element 30 among the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 onto the base substrate BS may at least partially overlap the orthographic projection of at least one first light-emitting element 30 onto the base substrate BS. The at least one first pixel circuit 10 provides a driving signal to the connected first light-emitting element 30 and drives the first light-emitting element 30 to emit light.

[0033] For example, as shown in FIG. 3, at least one second pixel circuit 20 among the plurality of second pixel circuits 20 may be connected to at least one second light-emitting element 40 among the plurality of second light-emitting elements 40 by a conductive line L1. The at least one second pixel circuit 20 provides a driving signal to the connected second light-emitting element 40 and drives the second light-emitting element 40 to emit light. As shown in FIG. 3, since the second light-emitting element 40 and the second pixel circuit 20 are located in different regions, the orthographic projection of at least one second pixel circuit 20 onto the base substrate BS does not overlap the orthographic projection of at least one second light-emitting element 40 onto the base substrate BS.

[0034] For example, in the embodiments of the present disclosure, the first display area R1 is set as a non-transmissive display area, and the second display area R2 is set as a transmissive display area. For example, light cannot pass through the first display area R1, and light can pass through the second display area R2. In this way, the display panel provided by the embodiments of the present disclosure does not need to perform punching processing on the display panel, and necessary hardware structures such as photosensitive sensors can be directly arranged at positions corresponding to the second display area R2 on one side of the display panel, laying a solid foundation for realizing a true full screen. Further, since the second display area R2 only includes light-emitting elements and does not include pixel circuits, it is beneficial to improve the light transmittance of the second display area R2 and the display effect of the display panel.

[0035] As shown in FIG. 3, the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102. The pixel circuit 100a and the light-emitting element 100b of the first pixel unit 101 are both located in the first display area R1. The pixel circuit 100a of the second pixel unit 101 is located in the first display area R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display area R2. In an embodiment of the present disclosure, the pixel circuit 100a of the first pixel unit 101 is the first pixel circuit 10, the light-emitting element 100b of the first pixel unit 101 is the first light-emitting element 30, the pixel circuit 100a of the second pixel unit 101 is the second pixel circuit 20, and the light-emitting element 100b of the second pixel unit 102 is the second light-emitting element 40. For example, the first light-emitting element 30 can be called an in-situ light-emitting element. For example, the first pixel circuit 10 can be called an in-situ pixel circuit, and the second pixel circuit 20 can be called an ex-situ pixel circuit.

[0036] For example, as shown in FIG. 3, the second light-emitting element 40 is located in the same row as the second pixel circuit 20 to which the second light-emitting element 40 is connected. That is, the light-emitting signal of the second light-emitting element 40 is emitted from the second pixel circuit in the same row. For example, the pixel circuits of the pixel units in the same row are connected to the same gate line.

[0037] As shown in FIG. 3, the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is connected to the light-emitting element (second light-emitting element 40) of the second pixel unit 102 via a conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes, but is not limited to, indium tin oxide (ITO).

[0038] As shown in FIG. 3, one end of the conductive line L1 is connected to the second pixel circuit 20, and the other end of the conductive line L1 is connected to the second light-emitting element 40. As shown in FIG. 3, the conductive line L1 extends from the first display area R1 to the second display area R2.

[0039] As shown in FIGS. 1 and 3, in some embodiments, the display panel further includes an auxiliary region Ra, and a second pixel circuit 20 may be provided in the auxiliary region Ra.

[0040] FIG. 4 is a schematic diagram of a first display region and a second display region in a display panel provided according to an embodiment of the present disclosure. As shown in FIG. 4, in the second display region R2, a light-transmissive region R0 is provided between adjacent second light-emitting elements 40. For example, as shown in FIG. 4, a plurality of light-transmissive regions R0 are connected to each other to form a continuous light-transmissive region separated by a plurality of second light-emitting elements 40. The conductive line L1 is formed of a transparent conductive material in order to increase the light transmittance of the light-transmissive region R0 as much as possible. As shown in FIG. 4, other regions of the second display region R2 except for the region where the second light-emitting element 40 is disposed may be light-transmissive regions.

[0041] FIGS. 5A to 5E are partial plan views of a display panel provided according to an embodiment of the present disclosure. Hereinafter, FIGS. 5A to 5E will be described.

[0042] FIG. 5A is a schematic diagram of a first display region and a second display region of a display panel provided according to an embodiment of the present disclosure. As shown in FIG. 5A, the second display region R2 is a light-transmissive display region, and the first display region R1 is a display region.

[0043] FIG. 5B is a schematic diagram of a first light-emitting element in a first display region and a second light-emitting element in a second display region of a display panel provided according to an embodiment of the present disclosure. FIG. 5B shows the first light-emitting element 30 and the second light-emitting element 40.

[0044] Referring to FIGS. 5A, 5B, and 3, in order to improve the display effect, the density of the second light-emitting element 40 may be equal to the density of the first light-emitting element 30. That is, the resolution of the second display area R2 is the same as the resolution of the first display area R1. Of course, in other embodiments, the density of the second light-emitting element 40 may be greater than or less than the density of the first light-emitting element 30. That is, the resolution of the second display area R2 may be greater than or less than the resolution of the first display area R1. For example, as shown in FIGS. 5B and 4, the light-emitting area of the second light-emitting element 40 is smaller than the light-emitting area of the first light-emitting element 30. FIG. 4 shows the light-emitting areas of the second light-emitting element 40 and the first light-emitting element 30 with dotted lines. For example, the light-emitting area of the light-emitting element can correspond to the area of the opening of the pixel definition layer.

[0045] FIG. 5C is a schematic diagram of conductive lines of a display panel provided according to an embodiment of the present disclosure. FIG. 5C shows a plurality of conductive lines L1.

[0046] FIG. 5D is a schematic diagram of conductive lines of a display panel provided according to an embodiment of the present disclosure. FIG. 5D shows the conductive line L1. As shown in FIG. 5D, the conductive line L1 includes a first conductive line L11, a second conductive line L12, and a third conductive line L13. In a display panel with a high PPI, in order to avoid the conductive lines being too dense, a plurality of wiring pattern layers can be formed, and an insulating layer is disposed between different wiring pattern layers. For example, the first conductive line L11 is located in the first wiring pattern layer, the second conductive line L12 is located in the second wiring pattern layer, and the third conductive line L13 is located in the third wiring pattern layer. Of course, in other embodiments, a plurality of conductive lines in other forms may also be arranged. For example, one conductive line L1 is formed by conductive portions located in different wiring pattern layers. For example, the conductive portions located in different wiring pattern layers can be connected through via holes penetrating the insulating layer.

[0047] FIG. 5E shows a first light-emitting element 30, a second light-emitting element 40, a first pixel circuit 10, a second pixel circuit 20, a connection element CE0, and a conductive line L1. Each pixel circuit is connected to the light-emitting element via the connection element CE0. That is, each pixel unit has the connection element CE0. That is, the first pixel circuit 10 is connected to the first light-emitting element 30 via the connection element CE0, and the second pixel circuit 20 is connected to the second light-emitting element 40 via the connection element CE0. For example, one end of the conductive line L1 is connected to the second pixel circuit 20 via the connection element CE0, and the other end of the conductive line L1 is connected to the second light-emitting element 40.

[0048] As shown in FIG. 5E, the conductive line L1 passes through the area where the pixel circuit of the pixel unit is located, and connects the second pixel circuit 20 and the second light-emitting element 40 on both sides of the pixel unit, respectively. For example, the area where the pixel circuit of the pixel unit is located overlaps with a plurality of conductive lines L1 passing through the area, whereby the pixel circuit is combined with the conductive line overlapping the pixel circuit to form a parasitic capacitance, resulting in a luminance difference and causing display defects such as Mura. In the first display area R1, the area where the second pixel circuit 20 is provided can be called an auxiliary area Ra (as shown in FIGS. 1 and 3), and the auxiliary area Ra can also be called a transition area. Due to the combination of the conductive line and the pixel circuit, a phenomenon in which the luminance becomes low in the auxiliary area (transition area) is likely to occur, and the darker pixel unit is the pixel unit (first pixel unit) in the first display area R1, not the second light-emitting element 40 in the second display area R2. For example, the fact that the auxiliary area is darker is more prominent in the case of high gradation than in the case of low gradation. FIG. 5E takes the first pixel circuit 10 overlapping at most two conductive lines L1 as an example, but in other embodiments, the first pixel circuit 10 may overlap more conductive lines L1. For example, as shown in FIG. 5C, in some embodiments, the first pixel circuit 10 can overlap 10 to 15 conductive lines L1. The number of conductive lines L1 overlapping one first pixel circuit 10 can be determined as needed.

[0049] In some embodiments, by compressing the size of the first pixel circuit 10 in the first direction X, an area where the second pixel circuit 20 is provided can be obtained. For example, as shown in FIG. 5E, in the auxiliary area, columns of the second pixel circuit 20 are arranged every predetermined column of the first pixel circuit 10. For example, the number of columns of the first pixel circuit 10 between two adjacent columns of the second pixel circuit 20 can be determined as needed.

[0050] FIG. 6A is a schematic diagram of a data cable in the display panel. FIG. 6B is a schematic diagram of a display defect of the display panel. FIG. 6C is a schematic cross-sectional view of a segmented data cable in the display panel.

[0051] As shown in FIG. 6A, the second display area R2 is a light-transmissive display area, separating the second pixel circuit 20 from the second light-emitting element 40, with the second pixel circuit 20 provided within the first display area R1, and the data cable of the second pixel unit 102 (refer to FIG. 3) being formed by segmentation. That is, as shown in FIG. 6A, the data cable DTn includes a first portion DT01, a second portion DT02, and a third portion DT03. As shown in FIG. 6A, both the first portion DT01 and the second portion DT02 extend along the second direction Y, the third portion DT03 extends along the first direction X, and the first portion DT01 and the second portion DT02 are connected by the third portion DT03. Since the data cable DTn includes a vertical portion and a horizontal portion, the length of the data cable DTn is greater than the length of the data cable DTm that includes only the vertical portion, and the load of the data cable DTn is greater than the load of the data cable DTm. Therefore, as shown in FIG. 6B, display defects such as dark vertical stripes occur during display on the display panel. FIG. 6B shows the dark vertical stripes MR. In an embodiment of the present disclosure, the data cable can be divided into a data cable DTm called the first type of data cable DTm and a data cable DTn called the second type of data cable DTn. For example, the first type of data cable DTm extends along the second direction Y, and the second type of data cable DTn includes a portion extending along the first direction X and also includes a portion extending along the second direction Y. For example, in an embodiment of the present disclosure, the first direction X is the row direction of the pixel unit, and the second direction Y is the column direction of the pixel unit, but it is not limited thereto. For clarity of the figure, FIG. 6A shows only two second-type data cables DTn, and the display panel can arrange a plurality of data cables DTn as needed, thereby forming a plurality of third portions DT03. The plurality of third portions DT03 are provided closer to the second display area R2. In this case, visual luminance non-uniformity display defects (Mura) due to the installation of the third portion DT03 are likely to occur on the display panel.

[0052] As shown in FIG. 6C, the display panel includes a base substrate BS and various structures located on the base substrate BS. As shown in FIG. 6C, a buffer layer BL is provided on the base substrate BS, a separation layer BR is provided on the buffer layer BL, a first insulating layer ISL1 is provided on the separation layer BR, a third portion DT03 of a second-type data cable DTn is provided on the first insulating layer ISL1, a second insulating layer ISL2 and a third insulating layer ISL3 are provided on the third portion DT03 of the second-type data cable DTn, a first portion DT01 and a second portion DT02 of the second-type data cable DTn are provided on the third insulating layer ISL3, and a fourth insulating layer ISL4 and a fifth insulating layer ISL5 are provided on the first portion DT01 and the second portion DT02 of the second-type data cable DTn. As shown in FIG. 6C, the third portion DT03 of the second-type data cable DTn is provided on the second conductive layer LY2, and the first portion DT01 and the second portion DT02 of the second-type data cable DTn are provided on the third conductive layer LY3.

[0053] As shown in FIG. 6C, the first portion DT01 is connected to the third portion DT03 through a via hole VH01 that penetrates the third insulating layer ISL3 and the second insulating layer ISL2, and the second portion DT02 is connected to the third portion DT03 through a via hole VH02 that penetrates the third insulating layer ISL3 and the second insulating layer ISL2.

[0054] FIG. 7A is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. FIG. 7B is a schematic cross-sectional view of a segmented data cable within the display panel. FIG. 7C is a schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0055] FIG. 7A shows three second-type data cables DTn and eight first-type data cables DTm. The numbers of the second-type data cables DTn and the first-type data cables DTm can be determined as needed.

[0056] For example, referring to FIGS. 2, 3, 5E, 7A, and 7B, at least one embodiment of the present disclosure provides a display panel including a base substrate BS, pixel units 100, and a data cable DT, where the pixel units 100 are located on the base substrate BS and include pixel circuits 100a and light-emitting elements 100b. The pixel circuits 100a are configured to drive the light-emitting elements 100b to emit light. The pixel circuits 100a include driving transistors and data writing transistors, the driving transistors are connected to the data writing transistors, and the data cable DT is connected to the data writing transistors. The data cable DT includes a plurality of first-type data cables DTm and a plurality of second-type data cables DTn. The plurality of first-type data cables DTm are arranged along a first direction X, the first-type data cables DTm extend along a second direction Y, the first direction X intersects the second direction Y, the second-type data cables DTn include a first portion DT01, a second portion DT02, and a third portion DT03. The first portion DT01 and the second portion DT02 are connected via the third portion DT03. Both the first portion DT01 and the second portion DT02 extend along the second direction Y, and the third portion DT03 extends along the first direction X. For example, the third portion DT03 is located in the first display region R1.

[0057] As shown in FIG. 7B, the third portion DT03 and the second portion DT02 are located in different layers, the third portion DT03 and the first portion DT01 are located in different layers, the first portion DT01 is closer to the base substrate BS than the third portion DT03, and the second portion DT02 is closer to the base substrate BS than the third portion DT03.

[0058] As shown in FIG. 7B, one end of the third portion DT03 is connected to the first portion DT01 via a via hole VH1 that penetrates the fourth insulating layer ISL4 and the fifth insulating layer ISL5, and the other end of the third portion DT03 is connected to the second portion DT02 via a via hole VH2 that penetrates the fourth insulating layer ISL4 and the fifth insulating layer ISL5.

[0059] The embodiments of the present invention have been described by taking as an example the provision of a fourth insulating layer ISL4 and a fifth insulating layer ISL5 between a fourth conductive layer LY4 and a third conductive layer LY3, but the present invention is not limited thereto. It is also possible to provide only one insulating layer between the fourth conductive layer LY4 and the third conductive layer LY3. For example, only the fifth insulating layer ISL5 is provided between the fourth conductive layer LY4 and the third conductive layer LY3. For example, the fifth insulating layer ISL5 is a planarization layer.

[0060] For example, as shown in FIGS. 6C and 7B, in the embodiments of the present disclosure, the thickness of the fifth insulating layer ISL5 is greater than the thickness of at least one of the fourth insulating layer ISL4, the third insulating layer ISL3, the second insulating layer ISL2, and the first insulating layer ISL1. In some embodiments, the thickness of the fifth insulating layer ISL5 is greater than the respective thicknesses of the fourth insulating layer ISL4, the third insulating layer ISL3, the second insulating layer ISL2, and the first insulating layer ISL1. For example, the buffer layer BL, the separation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer ISL4, and the fifth insulating layer ISL5 are all made of an insulating material. At least one of the buffer layer BL, the separation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, and the fourth insulating layer ISL4 is formed of an inorganic insulating material, and the fifth insulating layer ISL5 is formed of an organic material. For example, the inorganic insulating material includes, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the organic material includes, but is not limited to, a resin.

[0061] When compared with the display panel shown in FIG. 6B, in the display panel shown in FIG. 7B, the third portion DT03 of the second type of data cable DTn is provided on the fourth conductive layer LY4. Adjusting the third portion DT03 from the second conductive layer LY2 to the fourth conductive layer LY4 is beneficial for alleviating the dark stripe pattern display defect due to the load of the second type of data cable DTn being greater than the load of the first type of data cable DTm, and improving the display quality. For example, the square resistance of the material of the fourth conductive layer LY4 is smaller than the square resistance of the material of the second conductive layer LY2.

[0062] As shown in FIG. 7C, in the display panel provided by some embodiments of the present disclosure, the second display region R2 is surrounded by the first display region R1. The second type of data cable DTn further includes a fourth portion DT04 and a fifth portion DT05. The fourth portion DT04 extends along the second direction Y, the fifth portion DT05 extends along the first direction X, and the first portion DT01 and the fourth portion DT04 are connected via the fifth portion DT05. For example, in some embodiments, the first portion DT01 and the fourth portion DT04 are located in the same layer, and the fifth portion DT05 is not located in the same layer as the first portion DT01 and the fourth portion DT04. For example, in some embodiments, the fifth portion DT05 is located in the fourth conductive layer or the second conductive layer, and the first portion DT01 and the fourth portion DT04 are located in the third conductive layer, but not limited thereto.

[0063] As shown in FIG. 7C, the fifth portion DT05 is located in the peripheral region R3, and the fourth portion DT04 extends from the display region R0 to the peripheral region R3. As shown in FIG. 7C, the fourth portion DT04 extends from the opposite side of the second display region R2 where the second portion DT02 of the first display region R1 is disposed to the peripheral region R3.

[0064] As shown in FIG. 7C, the first portions DT01 of the plurality of first type data cables DTm and the plurality of second type data cables DTn are arranged at intervals. The number of the first type data cables DTm arranged between adjacent first portions DT01 is not limited to that shown in the figure and can be set as required.

[0065] As long as two portions connected by via holes are located in different layers, the layer where each portion of the second type data cable DTn is located can be set as required. For example, for each portion of the second type data cable DTn, two portions extending in different directions are located in different layers. Of course, other methods can also be adopted, and each of the first portion DT01 to the fifth portion DT05 shown in the figure may include sub-portions located in different layers.

[0066] FIG. 8A is a schematic diagram of a display panel provided by an embodiment of the present disclosure. FIG. 8B is a schematic plan view of a dummy line and a third portion of a second type of data cable in the display panel shown in FIG. 8A.

[0067] For example, as shown in FIG. 8A, in order to alleviate the visual Mura caused by arranging the third portion of the second type of data cable DTn, for the same second type of data cable DTn, the size of the third portion DT03 in the first direction X is not less than the shortest distance between the first portion DT01 and the second portion DT02 in the first direction X.

[0068] In some embodiments of the present disclosure, for example, in order to alleviate the visual Mura caused by arranging the third portion of the second type of data cable DTn, the display panel further includes a plurality of dummy lines DMY. For example, the plurality of dummy lines DMY and the third portion DT03 of the second type of data cable DTn are located in the same layer. For example, the plurality of dummy lines DMY and the third portion DT03 are both located in the fourth conductive layer LY4.

[0069] In the display panel provided by some embodiments of the present disclosure, dummy lines DMY are arranged to avoid the visual Mura caused by the concentration of the third portion DT03 and improve the display quality.

[0070] For example, as shown in FIGS. 8A and 8B, the display panel includes a plurality of third portions DT03. In order to alleviate or remove the visual Mura and improve the display quality, the plurality of dummy lines DMY and the plurality of third portions DT03 are uniformly arranged in the display panel.

[0071] For example, as shown in FIGS. 8A and 8B, the extending direction of the dummy line DMY is the same as the extending direction of the third portion DT03. As shown in FIGS. 8A and 8B, the dummy line DMY extends along the first direction X, and the third portion DT03 extends along the first direction X.

[0072] For example, the dummy line DMY is connected to the constant voltage line. For example, the constant voltage line includes at least one of the first power line, the second power line, and the initialization signal line. For example, the first power line may be the first power line PL1 described below, the second power line may be the second power line PL2 described below, and the initialization signal line may be the initialization signal line INT described below.

[0073] Referring to FIGS. 6A, 7A, 7C, 8A, and 8B, the display panel further includes a dummy data cable DM. The dummy data cable DM is a separated data cable. The dummy data cable DM and the first portion DT01 of the second type of data cable DTn are separated. The dummy data cable DM is positioned between two first type of data cables DTm and is separated from the first portion DT01 of the second type of data cable DTn positioned between the two first type of data cables DTm. A part of the second portion DT02 and the third portion DT03 of the second type of data cable DTn are not positioned between the two first type of data cables DTm. For example, no data signal is input to the dummy data cable DM like the data cable DT. For example, the dummy data cable DM is connected to the constant voltage line, but is not limited thereto. For example, the pixel circuit overlapping the dummy data cable DM may be a dummy pixel circuit, and the dummy pixel circuit is not connected to the light emitting element.

[0074] For example, as shown in FIGS. 8A and 8B, in order to improve the uniformity of etching, the display panel further includes a plurality of dummy data cables DM. For example, the plurality of dummy data cables DM, the first portion DT01 of the second type of data cable DTn, and the second portion DT02 of the second type of data cable DTn are all positioned in the same layer.

[0075] FIG. 9A is a schematic diagram of a display panel provided by an embodiment of the present disclosure. FIG. 9B is a schematic diagram of a display panel provided by another embodiment of the present disclosure. FIG. 9C is a schematic diagram of a display panel provided by another embodiment of the present disclosure. FIG. 9D is a schematic plan view of the dummy lines and the third portion of the second type of data cable DTn in the display panel shown in FIG. 9C.

[0076] For example, in order to reduce the influence on the pixel circuit of the third portion DT03 and reduce the load of the second type of data cable, the third portion DT03 is arranged between the pixel circuits of two adjacent pixel units in the second direction Y.

[0077] For example, as shown in FIGS. 9A to 9D, the display panel includes a plurality of third portions DT03. In order to alleviate visual Mura, the plurality of third portions DT03 are distributed and arranged in the display panel. For example, as shown in FIG. 9A, the distance between two adjacent third portions DT03 in the second direction Y is greater than or equal to the sum of the sizes of two pixel units 100 in the second direction Y. FIG. 9A shows the pixel unit 100 with an elliptical dotted line frame. For clarity of the figure, FIG. 9 shows only eight pixel units 100 located between two adjacent third portions DT03.

[0078] For example, the distance between two adjacent third portions DT03 in the second direction Y is greater than or equal to the sum of the sizes of ten pixel units 100 in the second direction Y. The distance between two adjacent third portions DT03 in the second direction Y can be determined according to the dispersion degree of the plurality of third portions DT03.

[0079] For example, as shown in FIGS. 9A to 9D, in order to alleviate visual Mura, a plurality of third portions DT03 are uniformly arranged within at least half of the size of the display panel in the second direction Y. For example, as shown in FIGS. 9C and 9D, a plurality of third portions DT03 are uniformly arranged within a region on one side of the second display region R2 of the first display region R1. For example, the distance between the two farthest third portions DT03 is more than half of the size of the display region R0 in the second direction Y. The size of the display panel in the second direction Y can refer to the length of the display panel in the second direction Y. In FIGS. 6A, 7A, 7C, 8A, 8B, 9A to 9D, via holes for connecting two components through the insulating layer are represented by black dots. Two portions intersecting at the position of the black dot are connected, and portions intersecting at positions without black dots are not connected, and the two are separated by the insulating layer therebetween.

[0080] As shown in FIGS. 9C and 9D, the display panel further includes a plurality of dummy lines DMY. For the plurality of dummy lines DMY, reference can be made to the previous description and will not be repeated here.

[0081] FIGS. 6A, 7A, 7C, 8A, 8B, 9A to 9D show the center line a0 of the display panel. For example, the display panel is arranged symmetrically with respect to the center line a0. For example, the center line a0 is parallel to the second direction Y.

[0082] As shown in FIGS. 6A, 7A, 7C, 8A, 8B, 9A to 9D, some dummy lines DMY are separated by the second display region R2, and on the opposite side of the second display region R2, the dummy lines DMY include a first dummy portion DMY1 located on one side of the second display region R2 and a second dummy portion DMY2 located on the other side of the second display region R2. The dummy lines DMY do not pass through the second display region R2.

[0083] As shown in FIGS. 6A, 7A, 7C, 8A, 8B, 9A to 9D, the display panel includes a display area R0 and a peripheral area R3, and the display area R0 includes a first display area R1 and a second display area R2. That is, the base substrate BS has a display area R0 and a peripheral area R3 located on at least one side of the display area R0.

[0084] For example, referring to FIGS. 2 and 3, the pixel unit 100 is located on the base substrate BS and includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is configured to drive the light-emitting element 100b. The pixel circuit 100b includes a driving transistor T1 (see FIG. 10A) and a data writing transistor T2 (see FIG. 10A), and the driving transistor is connected to the data writing transistor.

[0085] For example, referring to FIGS. 10A and 10B, the data cable DT is connected to the data writing transistor T2 and is configured to provide a data signal to the pixel circuit 100a.

[0086] FIG. 10A is a schematic diagram of a pixel circuit provided according to an embodiment of the present disclosure. FIG. 10B is a layout diagram of a pixel circuit provided according to an embodiment of the present disclosure. FIG. 10C is a cross-sectional view taken along line A-B of FIG. 10B. FIG. 10D is a layout diagram of a pixel circuit provided according to an embodiment of the present disclosure. FIG. 10E is a cross-sectional view taken along line C-D of FIG. 10D. The pixel circuit shown in FIG. 10A may be a pixel circuit of a general low-temperature poly-silicon (LTPS) AMOLED in the related art.

[0087] FIG. 10A shows a pixel circuit of a pixel unit of a display panel. As shown in FIG. 10A, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor T1, and one storage capacitor Cst. The six switching transistors are a data write transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7, respectively. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer positioned between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is an anode, and the second electrode E2 is a cathode. Usually, the threshold compensation transistor T3 and the first reset transistor T6 use dual-gate thin film transistors (TFTs) to reduce the leakage risk.

[0088] As shown in FIG. 10A, the display panel includes a gate line GT, a data cable DT, a first power line PL1, a second power line PL2, an emission control signal line EML, an initialization signal line INT, a reset control signal line RST, and the like. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, and the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data cable DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the emission control signal line EML is configured to provide an emission control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. The first initialization signal line INT1 is configured to provide a first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, and their magnitudes may be, for example, in the range between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 may both be equal to or less than the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT1 are connected and are both configured to provide an initialization signal Vinit to the pixel unit 100. That is, the first initialization signal line INT1 and the second initialization signal line INT2 are both called the initialization signal line INT, the first initialization signal Vinit1 is equal to the second initialization signal Vinit2, and both are Vinit.

[0089] As shown in FIG. 10A, the driving transistor T1 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as a scan signal SCAN, a data signal DATA, a first voltage signal VDD, and a second voltage signal VSS.

[0090] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), and the light-emitting element 100b emits red light, green light, blue light, or white light by driving the corresponding pixel circuit 100a. For example, one pixel includes a plurality of pixel units. One pixel can include a plurality of pixel units that emit different colors of light. For example, one pixel includes, but is not limited to, a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light. The number of pixel units included in one pixel and the light emission of each pixel unit can be determined as needed.

[0091] For example, as shown in FIG. 10A, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first electrode T21 of the data writing transistor T2 is connected to the data cable DT, and the second electrode T22 of the data writing transistor T2 is connected to the first electrode T11 of the driving transistor T1.

[0092] For example, as shown in FIG. 10A, the pixel circuit 100a further includes a threshold compensation transistor T3, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, the first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0093] For example, as shown in FIG. 10A, the display panel further includes an emission control signal line EML, the pixel circuit 100a further includes a first emission control transistor T4 and a second emission control transistor T5, the gate T40 of the first emission control transistor T4 is connected to the emission control signal line EML, the first electrode T41 of the first emission control transistor T4 is connected to the first power line PL1, the second electrode T42 of the first emission control transistor T4 is connected to the first electrode T11 of the driving transistor T1, the gate T50 of the second emission control transistor T5 is connected to the emission control signal line EML, the first electrode T51 of the second emission control transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second emission control transistor T5 is connected to the first electrode E1 of the light-emitting element 100b.

[0094] As shown in FIG. 10A, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1, and the second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b and is configured to reset the first electrode E1 of the light-emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 via the first reset transistor T6. The second initialization signal line INT2 is connected to the first electrode E1 of the light-emitting element 100b via the second reset transistor T7. For example, the first initialization signal line INT1 is connected to the second initialization signal line INT2 so that the same initialization signal is input, but is not limited thereto. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 may also be insulated from each other and configured to input signals respectively.

[0095] For example, as shown in FIG. 10A, the first electrode T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, the first electrode T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second electrode T72 of the second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b. For example, as shown in FIG. 10A, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0096] As shown in FIG. 10A, the first power line PL1 is configured to provide the first voltage signal VDD to the pixel circuit 100a. The pixel circuit further includes a storage capacitor Cst. The first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second electrode Cb of the storage capacitor Cst is connected to the first power line PL1.

[0097] For example, as shown in FIG. 10A, the display panel further includes a second power line PL2 connected to the second electrode 201 of the light-emitting element 100b.

[0098] FIG. 10A shows a first node N1, a second node N2, a third node N3, and a fourth node N4. For example, in some embodiments, referring to FIGS. 5C, 5E, and 10A, capacitances are formed between the first node N1 and the conductive line L1, between the conductive line L1 and the fourth node N4, and couplings are formed between the conductive line L1 and the first node N1 and the fourth node N4, respectively, thereby causing a luminance difference and display defects such as Mura, which affect the display quality.

[0099] As shown in FIG. 10B, the pixel circuit includes a driving transistor T1 including a gate T10. Referring to FIGS. 10B and 10C, the second electrode Cb of the storage capacitor Cst has an opening OPN1, and one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1. The connection electrode CE1 is also called the first gate signal line SL1. As shown in FIG. 10B, the first gate signal line SL1 is connected to the gate T10 of the driving transistor T1.

[0100] As shown in FIG. 10B, the first gate signal line SL1 is connected to the second gate signal line SL2. The gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 constitute a gate signal portion PT1. The potentials of the gate signal portion PT1 are the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided. In this case, the gate T10 of the driving transistor T1 and the first gate signal line SL1 constitute the gate signal portion PT1. For example, the second gate signal line SL2 is the second electrode T62 of the first reset transistor T6.

[0101] Referring to FIGS. 10B and 10C, in order to stabilize the potential of the gate signal portion PT1, the display panel provided by the embodiment of the present disclosure provides a shield electrode SE and a constant voltage line L0 configured to provide a constant voltage to the pixel circuit. The shield electrode SE is connected to the constant voltage line L0, whereby the voltage of the shield electrode SE is stabilized, serving as a shield, and preventing the conductive line L1 from affecting the potential of the grid signal portion PT1. The orthogonal projection of the first gate signal line SL1 onto the base substrate BS covers the orthogonal projection of the shield electrode SE onto the base substrate BS.

[0102] Referring to FIGS. 10B to 10D, in order to exert a good shielding effect by the shield electrode and increase the shielding amount, the orthogonal projection of the first gate signal line SL1 onto the base substrate BS completely covers the orthogonal projection of the shield electrode SE onto the base substrate BS.

[0103] For example, in order to alleviate display non-uniformity (mura) and improve the display effect, the distance between the boundary of the orthographic projection of the first gate signal line SL1 onto the base substrate BS and the boundary of the orthographic projection of the shield electrode SE onto the base substrate BS is 1.75 μm or more. Since the area occupied by the pixel unit is limited, the distance by which the shield electrode SE exceeds the first gate signal line SL1 can be restricted. For example, in some embodiments, in order to obtain a better shielding effect, the distance between the boundary of the orthographic projection of the first gate signal line SL1 onto the base substrate BS and the boundary of the orthographic projection of the shield electrode SE onto the base substrate BS is 2.33 μm or more.

[0104] As shown in FIG. 10B, the display panel further includes a block BK, the block BK is connected to the first power line PL1, the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 are connected via a conductive connection portion CP, and the orthographic projection of the block BK onto the base substrate BS at least partially overlaps with the orthographic projection of the conductive connection portion CP of the threshold compensation transistor T3 onto the base substrate BS. As shown in FIG. 10B, the blocks BK of adjacent column pixel units are used to block the conductive connection portion CP of the threshold compensation transistor T3 of the pixel units in the current column.

[0105] For example, as shown in FIGS. 10B, 6G, and 6H, when the display panel includes the second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 onto the base substrate BS covers the orthographic projection of the block BK onto the base substrate BS. Further, for example, the boundary of the orthographic projection of the block BK onto the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 onto the base substrate BS. For example, the distance by which the boundary of the orthographic projection of the block BK onto the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 onto the base substrate BS is 1.75 μm or more. For example, the distance by which the boundary of the orthographic projection of the block BK onto the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 onto the base substrate BS is 2.33 μm or more. Of course, in other embodiments, it is also possible to replace the function of the block BK with the shield electrode SE, or the orthographic projection of the second gate signal line SL2 onto the base substrate BS covers the orthographic projection of the block BK onto the base substrate BS and also covers the orthographic projection of the shield electrode SE onto the base substrate BS.

[0106] For example, the material of the first gate signal line SL1 is different from the material of the second gate signal line SL2. For example, the material of the first gate signal line SL1 includes a metal, and the material of the second gate signal line SL2 includes a conductive material obtained by making a semiconductor material conductive.

[0107] For example, as shown in FIGS. 10B and 10D, in order to reduce the wiring, the first power line PL1 is used as the constant voltage line L0. In other embodiments, in order to reduce the wiring, the first initialization signal line INT1 can be used as the constant voltage line, or the second initialization signal line INT2 can also be used as the constant voltage line. The constant voltage line L0 is not limited to the first power line PL1, the first initialization signal line INT1, and the second initialization signal line INT2, and any signal line that supplies a constant voltage within the pixel circuit can be used as the constant voltage line L0. In the embodiments of the present disclosure, the first power line PL1 is taken as an example to illustrate the constant voltage line L0. However, when a signal line that supplies a constant voltage other than the first power line PL1 is adopted as the constant voltage line L0, the shape of the shield electrode SE can be adjusted and connected to the signal line that supplies the constant voltage.

[0108] As shown in FIG. 10D, the shield electrode SE is connected to the constant voltage line L0 via the via hole H21. For example, the constant voltage line L0 is located in the third conductive layer LY3, and the via hole H21 can penetrate the fourth insulating layer ISL4 and the fifth insulating layer ISL5.

[0109] Referring to FIGS. 10C and 10E, a buffer layer BL is provided on the base substrate BS, a separation layer BR is provided on the buffer layer BL, an active layer LY0 is provided on the separation layer BR, a first insulating layer ISL1 is provided on the active layer LY0, a first conductive layer LY1 is provided on the first insulating layer ISL1, a second insulating layer ISL2 is provided on the first conductive layer LY1, a second conductive layer LY2 is provided on the second insulating layer ISL2, a third insulating layer ISL3 is provided on the second conductive layer LY2, a third conductive layer LY3 is provided on the third insulating layer ISL3, the third conductive layer LY3 includes a connection electrode CE01, the connection electrode CE01 penetrates the via hole H3 of the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer ISL3 and is connected to the second electrode T52 of the second light-emitting control transistor T5, a fourth insulating layer ISL4 and a fifth insulating layer ISL5 are provided on the third conductive layer LY3, a fourth conductive layer LY4 is provided on the fourth insulating layer ISL4 and the fifth insulating layer ISL5, the fourth conductive layer LY4 includes a connection electrode CE02, the connection electrode CE02 is connected to the connection electrode CE01 via a via hole H22 penetrating the fourth insulating layer ISL4 and the fifth insulating layer ISL5, a sixth insulating layer ISL6 is provided on the fourth conductive layer LY4, and the light-emitting element 100b (second light-emitting element 30) is connected to the connection electrode CE02 via a via hole H31 (as shown in FIGS. 10D and 10E) penetrating the sixth insulating layer ISL6. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. For example, the connection element CE0 includes the connection electrode CE01 and the connection electrode CE02.

[0110] As shown in FIG. 10B, one end of the connection electrode CE1 is connected to the gate T10 of the drive transistor T1 via the via hole H1, and the other end of the connection electrode CE1 is connected to the second electrode T62 of the first reset transistor T6 via the via hole H2. One end of the connection electrode CE2 is connected to the first initialization signal line INT1 via the via hole H4, and the other end of the connection electrode CE2 is connected to the first electrode T61 of the first reset transistor T6 via the via hole H5. One end of the connection electrode CE3 is connected to the second initialization signal line INT2 via the via hole H6, and the other end of the connection electrode CE3 is connected to the first electrode T71 of the second reset transistor T7 via the via hole H7. The first power supply line PL1 is connected to the first electrode T41 of the first light emission control transistor T4 via the via hole H8. The first power supply line PL1 is connected to the second electrode Cb of the storage capacitor Cst via the via hole H9. The first power supply line PL1 is connected to the block BK via the via hole Hk. The data cable DT is connected to the first electrode T21 of the data writing transistor T2 via the via hole H0.

[0111] For example, in the manufacturing process of a display panel, a self-alignment process is adopted, and a semiconductor pattern layer is made conductive using the first conductive layer LY1 as a mask. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, the semiconductor pattern layer is doped to a high concentration by ion implantation. As a result, portions not covered by the first conductive layer LY1 of the semiconductor pattern layer become conductive, forming the source regions (first electrodes T11) and drain regions (second electrodes T12) of the driving transistor T1, the source regions (first electrodes T21) and drain regions (second electrodes T22) of the data writing transistor T2, the source regions (first electrodes T31) and drain regions (second electrodes T32) of the threshold compensation transistor T3, the source regions (first electrodes T41) and drain regions (second electrodes T42) of the first light emission control transistor T4, the source regions (first electrodes T51) and drain regions (second electrodes T52) of the second light emission control transistor T5, the source regions (first electrodes T61) and drain regions (second electrodes T62) of the first reset transistor T6, and the source regions (first electrodes T71) and drain regions (second electrodes T72) of the second reset transistor T7. Portions covered by the first conductive layer LY1 of the semiconductor pattern layer retain semiconductor characteristics, and therein are formed the channel regions of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7. For example, as shown in FIG. 10B, the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light emission control transistor T5 are integrally formed, the first electrode T51 of the second light emission control transistor T5, the second electrode T12 of the driving transistor T1, and the first electrode T31 of the threshold compensation transistor T3 are integrally formed, the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2, and the second electrode T42 of the first light emission control transistor T4 are integrally formed, and the second electrode T32 of the threshold compensation transistor T3 and the second electrode T62 of the first reset transistor T6 are integrally formed.In some embodiments, as shown in FIG. 10B, the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 can be integrally formed.

[0112] For example, the channel region of the transistor used in the embodiments of the present disclosure may be single crystal silicon, polycrystalline silicon (e.g., low temperature polycrystalline silicon), or a metal oxide semiconductor material (such as IGZO, AZO). In one embodiment, all of the transistors are P-type low temperature polycrystalline silicon (LTPS) thin film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (such as IGZO, AZO), and the metal oxide semiconductor thin film transistor has a lower leakage current and helps to reduce the gate leakage current of the driving transistor T1.

[0113] For example, the transistors used in the embodiments of the present disclosure can include various structures such as top gate, bottom gate, or dual gate structures. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual gate thin film transistors that help to reduce the gate leakage current of the driving transistor T1.

[0114] For example, as shown in FIG. 10E, the display panel further includes a pixel definition layer PDL and a spacer PS, and the pixel definition layer PDL has an opening OPN configured to define the light emitting area (light emitting region, effective light emitting area) of the pixel unit. The spacer PS is configured to support a fine metal mask when forming the light emitting functional layer FL.

[0115] For example, the opening OPN is the light-emitting region of the pixel unit. The light-emitting functional layer FL is located on the first electrode E1 of the light-emitting element 100b, the second electrode E2 of the light-emitting element 100b is located on the light-emitting functional layer FL, and as shown in FIG. 10E, a sealing layer CPS is provided for the light-emitting element 100b. The sealing layer CPS includes a first sealing layer CPS1, a second sealing layer CPS2, and a third sealing layer CPS3. For example, the first sealing layer CPS1 and the third sealing layer CPS3 are inorganic material layers, and the second sealing layer CPS2 is an organic material layer. For example, the first electrode E1 is the anode of the light-emitting element 100b, and the second electrode E2 is the cathode of the light-emitting element 100b, but it is not limited thereto.

[0116] For example, as shown in FIGS. 10B and 10D, the orthographic projection of the block BK onto the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 onto the base substrate BS, and the orthographic projection of the shield electrode SE onto the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 onto the base substrate BS. Thereby, both the block BK and the shield electrode SE serve to shield the gate signal portion PT1. Naturally, in some other embodiments, the block BK may not be provided, or the orthographic projection of the block BK onto the base substrate BS may not overlap with the orthographic projection of the second gate signal line SL2 onto the base substrate BS.

[0117] For example, as shown in FIGS. 10B and 10D, the left block BK extends to the pixel unit on the left side of the pixel unit shown in the figure, blocking the conductive connection portion CP of the threshold compensation transistor T3, and the right block BK extends by being connected to the block BK connected to the pixel unit on the right side of the pixel unit shown in the figure.

[0118] As shown in FIGS. 10B and 10D, the channel of each transistor and the first and second electrodes on both sides of the channel are located in the active layer LY0. The first reset control signal line RST1, the gate line GT, the gate T10 of the drive transistor (the first electrode Ca of the storage capacitor Cst), the emission control signal line EML, and the second reset control signal line RST2 are located in the first conductive layer LY1. The first initialization signal line INT1, the second electrode Cb of the storage capacitor Cst, and the second initialization signal line INT2 are located in the second conductive layer LY2. The data cable DT, the first power supply line PL1, the connection electrodes CE1, CE2, CE3, and the connection electrode CE01 are located in the third conductive layer LY3. The shield electrode SE is located in the fourth conductive layer LY4.

[0119] As shown in FIGS. 10B and 10D, the first initialization signal line INT1, the first reset control signal line RST1, the gate line GT, the emission control signal line EML, the second initialization signal line INT2, and the second reset control signal line RST2 all extend along the first direction X. As shown in FIGS. 10B and 10D, both the data cable DT and the first power supply line PL1 extend along the second direction Y.

[0120] In the embodiments of the present disclosure, that the orthographic projection of element A on the base substrate BS covers the orthographic projection of element B on the base substrate BS means that the orthographic projection of element A on the base substrate BS completely covers the orthographic projection of element B on the base substrate BS. That is, the orthographic projection of element A on the base substrate BS covers the orthographic projection of element B on the base substrate BS, and the area of the orthographic projection of element A on the base substrate BS is less than or equal to the area of the orthographic projection of element B on the base substrate BS.

[0121] For example, in some embodiments of the present disclosure, each pixel circuit 100a is provided with any of the above-described shield electrodes SE. That is, the first pixel circuit 10 of the first pixel unit 101 and the second pixel circuit 20 of the second pixel unit 102 are both provided with any of the above-described shield electrodes SE. For example, the first pixel circuit 10 of the first pixel unit 101 includes the shield electrode SE, and the second pixel circuit 20 of the second pixel unit 102 includes the shield electrode SE. Naturally, other forms of the shield electrode SE can also be used.

[0122] For example, the transistors in the pixel circuit according to the embodiments of the present disclosure are all thin-film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of a metal material. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed of a metal material such as nickel or aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are formed of materials such as titanium and aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 each have a structure composed of three sub-layers of Ti / AL / Ti, but are not limited thereto. For example, the base substrate may use a glass substrate or a polyimide substrate, but is not limited thereto and can be selected as needed. For example, the buffer layer BL, the separation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, the fifth insulating layer ISL5, and the sixth insulating layer ISL6 are all formed of a heat insulating material. The materials of the first electrode E1 and the second electrode E2 of the light emitting element can be selected as needed. In some embodiments, the first electrode E1 can use at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 can adopt a structure laminated with three sub-layers of ITO-Ag-ITO. In some embodiments, the second electrode E2 may be a metal with a low work function such as at least one of magnesium and silver, but is not limited thereto.

[0123] For example, referring to the layout diagram and cross-sectional view of the embodiments of the present disclosure, the display panel provided by at least one embodiment of the present disclosure can be manufactured by the following method. (1) Form a buffer layer BL and a separation layer BR on a base substrate BS. (2) Form a semiconductor thin film on the spacer layer BR. (3) Pattern the semiconductor thin film to form a semiconductor pattern layer. (4) Form a first insulating thin film on the semiconductor pattern layer. (5) Form a first conductive thin film on the first insulating thin film, and pattern the first conductive thin film to form a first conductive layer LY1. (6) Using the first conductive layer LY1 as a mask, dope the semiconductor pattern layer to form an active layer LY0. (7) Form a second insulating thin film on the first conductive layer LY1. (8) Form a second conductive thin film on the second insulating layer ISL2, and pattern the second conductive thin film to form a second conductive layer LY2. (9) Form a third insulating thin film on the second conductive layer LY2. (10) Pattern at least one of the first insulating thin film, the second insulating thin film, and the third insulating thin film to form via holes while forming a first insulating layer ISL1, a second insulating layer ISL2, and a third insulating layer ISL3. (11) Form a third conductive thin film, and pattern the third conductive thin film to form a third conductive layer LY3. Each component of the third conductive layer LY3 is connected to the underlying element through a via hole. (12) Form a fourth insulating thin film and a fifth insulating thin film, pattern the fourth insulating thin film and the fifth insulating thin film, and form a fourth insulating layer ISL4 and a fifth insulating layer ISL5 while forming via holes. (13) Form a fourth conductive thin film, and pattern the fourth conductive thin film to form a fourth conductive layer LY4. (14) Form at least one insulating layer, and form at least one transparent conductive layer including a conductive line L1. (15) Form a first electrode E1 of the light-emitting element. (16) Form a pixel definition layer PDL and a spacer layer PS. (17) Form a light-emitting functional layer FL. (18) Form a second electrode E2 of the light-emitting element. (19) Form a sealing layer CPS.

[0124] For example, referring to FIGS. 2 and 3, the base substrate BS has a first display region R1 and a second display region R2, the first display region R1 is located on at least one side of the second display region R2, the pixel unit includes a first pixel unit and a second pixel unit, the pixel circuit and the light-emitting element of the first pixel unit are both located in the first display region, the pixel circuit of the second pixel unit is located in the first display region, the light-emitting element of the second pixel unit is located in the second display region, and the pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit via a conductive line L1.

[0125] FIG. 11 is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. FIGS. 12A to 12C are schematic diagrams of display panels provided according to another embodiment of the present disclosure. FIG. 13 is a schematic diagram of a display panel provided according to another embodiment of the present disclosure. FIGS. 14A to 14H are schematic diagrams of display panels provided according to some other embodiments of the present disclosure.

[0126] As shown in FIG. 11, the third portion DT03 of the second type of data cable is located in the fourth conductive layer LY4. Some first pixel circuits 10 and / or some second pixel circuits 20 in the display panel provided according to some embodiments of the present disclosure are shown in FIG. 11. The display substrate shown in FIG. 11 may not be provided with a shield electrode SE.

[0127] Compared with the display panel shown in FIG. 11, in the display panel shown in FIG. 12A, the shape of the shield electrode SE is adjusted. For example, as shown in FIG. 12B, in order to make the potential of the gate signal portion PT1 more stable, the orthographic projection of the gate T10 of the driving transistor T1 on the base substrate BS covers the orthographic projection of the shield electrode SE on the base substrate BS. The shield electrode SE can be set to different shapes as required.

[0128] When compared with the display panel shown in FIG. 11, in the display panel shown in FIG. 12A, a first initialization signal line INT1 and a second initialization signal line INT2 are separately provided and configured such that signals are respectively applied thereto. In FIGS. 10B, 10D, and 11, the first initialization signal line INT1 of the previous pixel circuit is the second initialization signal line INT2 of the next pixel circuit, and it is taken as an example that the same initialization signal is input to the first initialization signal line INT1 and the second initialization signal line INT1. The arrangement method of the initialization signal lines can be adjusted as required.

[0129] For example, in an embodiment of the present disclosure, by arranging the third portion DT04 in the fourth conductive layer LY4 instead of the second conductive layer LY2, it becomes easier to arrange the first initialization signal line INT1 and the second initialization signal line INT2 shown in FIG. 12A in the second conductive layer LY2. That is, it is advantageous to arrange the first initialization signal line INT1 and the second initialization signal line INT2 between the emission control signal line EML and the second reset control signal line RST2.

[0130] FIG. 12B shows the first pixel unit 10, and a plurality of conductive lines L1 penetrate the first pixel unit 10, that is, the orthographic projection of the plurality of conductive lines L1 on the base substrate partially overlaps the orthographic projection of the first pixel unit 10 on the base substrate. The number of conductive lines L1 overlapping the first pixel unit 10 is not limited to that shown in the figure.

[0131] FIG. 12C shows the second pixel unit 20, and the conductive line L1 is connected to the second pixel unit 20. As shown in FIG. 12C, the conductive line L1 and the second pixel unit 20 are connected via a via hole H31 penetrating an insulating layer. As shown in FIG. 12C, at least one conductive line L1 does not penetrate the second pixel unit 20 and is not connected to the second pixel unit 20, that is, the orthographic projection of some conductive lines L1 on the base substrate partially overlaps the orthographic projection of the second pixel unit 20 on the base substrate. The number of conductive lines L1 overlapping the second pixel unit 20 is not limited to that shown in the figure.

[0132] As shown in FIGS. 12A to 12C, the orthographic projection of the third portion DT03 onto the base substrate BS does not overlap with the orthographic projection of the conductive line L1 onto the base substrate BS, reducing the overlap between signal lines and improving defects such as thinning or disconnection of the conductive line L1 due to the overlap between the conductive line L1 and the structure of the fourth conductive layer LY4. For example, the size of the pixel circuit in the second direction Y can be compressed, but is not limited thereto, so that there is a space for arranging the third portion DT03 that does not overlap with the conductive line L1. In the display panel provided by the embodiments of the present disclosure, the size of the pixel circuit in the second direction Y is not limited.

[0133] For example, as shown in FIGS. 12B, 12C, and 5E, the orthographic projection of the conductive line L1 onto the base substrate BS partially overlaps with the orthographic projection of the pixel circuit of the first pixel unit onto the base substrate BS.

[0134] For example, FIGS. 10B, 10D, and 11 show an example in which the first initialization signal line INT1 and the second initialization signal line INT2 are connected and the same initialization signal is input. As shown in FIGS. 12A to 12C, two different initialization signal lines may be provided to apply signals to the first initialization signal line INT1 and the second initialization signal line INT2, respectively.

[0135] For example, as shown in FIGS. 12A to 12C, the display panel further includes a first initialization signal line INT1 and a second initialization signal line INT2. Referring to FIGS. 10A, 12A, and 12C, the pixel circuit 100a further includes a first reset transistor T6 and a second reset transistor T7. The first reset transistor T6 is connected to the gate of the driving transistor T1 and is configured to reset the gate of the driving transistor T1. The second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b and is configured to reset the first electrode E1 of the light-emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6, and the second initialization signal line INT2 is connected to the first electrode E1 of the light-emitting element 100b through the second reset transistor T7. The first initialization signal line INT1 and the second initialization signal line INT2 are not connected and are configured to have signals applied thereto respectively. When adjusting the third portion DT04 to the fourth conductive layer LY4, it becomes easy to dispose the initialization signal lines on the first reset transistor T6 and the second reset transistor T7 respectively. That is, the connected two first initialization signal lines INT1 and second initialization signal line INT2 are disposed.

[0136] As shown in FIG. 13, the third portion DT03 penetrates a plurality of first pixel units 10 along the first direction X. For clarity, FIG. 13 shows only a part of the structure.

[0137] In FIGS. 14A to 14H, a data cable DT is shown in the left part of the center line a0 of the display panel, and for the sake of clarity of the figure, the data cable DT is not shown in the right part of the center line a0 of the display panel. In FIGS. 14A to 14H, the line extending in the first direction X that overlaps with the via hole indicated by the black dot is the third part DT03, and the line that does not overlap with the via hole and extends in the first direction X is the dummy line DMY. The shield electrode is not shown in FIG. 14H, and the shield electrode may be arranged in a rectangular area where the horizontal line intersects the vertical line. For example, at least one shield electrode may be arranged in one rectangular area. At least one row of pixel units may be arranged between two adjacent horizontal lines along the second direction Y. In FIGS. 14A to 14G, one shield electrode SE corresponds to one pixel circuit. Of course, in the display panel, the shield electrode SE may not be provided. In this case, the shield electrode SE in FIGS. 14A to 14G can be regarded as a pixel circuit.

[0138] As shown in FIG. 14A, in order to reduce the load, the third part DT03 of the second type of data cable DTn is located in the fourth conductive layer LY4. As shown in FIG. 14A, the shield electrode SE and the third part DT03 of the second type of data cable DTn are located in the fourth conductive layer LY4. For the shield electrode SE, reference can be made to the previous description and will not be repeated here.

[0139] As shown in FIG. 14B, a plurality of third portions DT03 are distributed and arranged on the display panel. In the second direction Y, a plurality of pixel units or a plurality of rows of pixel units are provided at intervals between adjacent third portions DT03. In FIG. 14B, taking the example that eight pixel units or eight rows of pixel units are provided at intervals between adjacent third portions DT03 in the second direction Y, those skilled in the art can set the number of pixel units arranged between adjacent third portions DT03 as needed according to the requirements. In FIG. 14B, the third portion DT03 located on the left side of the center line a0 of the display panel and the third portion DT03 located on the right side of the center line a0 of the display panel are symmetrically arranged with respect to the center line a0 of the display panel.

[0140] Compared with the display panel shown in FIG. 14B, in the display panel shown in FIG. 14C, the third portion DT03 located on the left side of the center line a0 of the display panel and the third portion DT03 located on the right side of the center line a0 of the display panel are arranged in a staggered manner in the second direction Y.

[0141] Compared with the display panel shown in FIG. 14B, in the display panel shown in FIG. 14D, a dummy line DMY is provided, and the size of the third portion DT03 in the first direction X is increased.

[0142] Compared with the display panel shown in FIG. 14C, in the display panel shown in FIG. 14E, the size of the third portion DT03 in the first direction X is increased.

[0143] Compared with the display panel shown in FIG. 14C, in the display panel shown in FIG. 14F, a dummy line DMY is provided, and the size of the third portion DT03 in the first direction X is increased.

[0144] In the display panel shown in FIG. 14G and the display panel shown in FIG. 14A, a dummy line DMY is provided, and the size of the third portion DT03 in the first direction X is increased.

[0145] In the display panel shown in FIG. 14H and the display panel shown in FIG. 14C, a dummy line DMY is provided, and the size of the third portion DT03 in the first direction X is increased.

[0146] As shown in FIGS. 14A to 14D and FIG. 14G, the third portion DT03 does not exceed the center line a0. Of course, the embodiments of the present disclosure are not limited thereto unless different third portions DT03 are connected.

[0147] As shown in FIGS. 14E, 14F, and 14H, the third portion DT03 exceeds the center line a0 of the display panel.

[0148] In other embodiments of the present disclosure, different numbers of pixel units can be arranged between two third portions DT03 adjacent in the second direction Y. The embodiments of the present disclosure do not limit the number of pixel units arranged between two third portions DT03 adjacent in the second direction Y. Further, the embodiments of the present disclosure do not limit the number of pixel units arranged between the first portions DT01 of adjacent second-type data cables DTn.

[0149] In the embodiments of the present disclosure, the following situation is described as an example. In the case of the second-type data cable DTn, the closer the second portion DT02 is to the center line a0, the longer the length of the portion of the third portion DT03 located at the two via holes connecting the first portion DT01 and the second portion DT02. Those skilled in the art can adjust the connection method as needed. For example, in some other embodiments, in the case of the second-type data cable DTn, the closer the second portion DT02 is to the center line a0, the shorter the length of the portion of the third portion DT03 located between the two via holes connecting the first portion DT01 and the second portion DT02.

[0150] At least one embodiment of the present disclosure provides a display device including any one of the above display panels.

[0151] FIG. 15A and FIG. 15B are schematic diagrams of a display device provided by an embodiment of the present disclosure. As shown in FIGS. 15A and 15B, the photosensitive sensor SS is provided on one side of the display panel DS and is located in the second display area R2. Ambient light can be sensed by the photosensitive sensor SS through the second display area R2. As shown in FIG. 15B, the side of the display panel where the photosensitive sensor SS is not provided is the display side where an image can be displayed.

[0152] For example, the display device is a full-screen display device of an under-screen camera. For example, the display device includes an OLED or includes an OLED product. For example, the display device includes any product or component having a display function, such as a television, a digital camera, a mobile phone, a wristwatch, a tablet computer, a notebook computer, a navigator, etc., including the above display panel.

[0153] FIG. 16 is an operation timing diagram of the pixel circuit shown in FIG. 10A. As shown in FIG. 16, in one frame display period, the driving method of the pixel unit includes a first reset phase t1, data writing and threshold correction, a second reset phase t2, and a light emission phase t3. When the reset control signal RESET is at a low level, the gate of the driving transistor T1 is reset, and when the scan signal SCAN is at a low level, the first electrode E1 (for example, the anode) of the light emitting element 100b is reset. For example, as shown in FIG. 10A, when the scan signal SCAN is at a low level, the data voltage VDATA is written, and at the same time, the threshold voltage Vth of the driving transistor T1 is obtained, and the data voltage VDADA including the data information of the data cable is stored in the capacitor Cst. When the light emission control signal line EML is at a low level, the light emitting element 100b emits light, and the voltage holding of the first node N1 (gate point) (the light emission stability of the light emitting element 100b) is maintained by the storage capacitor Cst. During the driving process of the pixel circuit 10, in the light emission phase, in order to keep the potential of the signal holding terminal constant, a storage capacitor is used to hold the voltage signal, a voltage is formed between the gate and the source of the driving transistor, the driving transistor is controlled to form a driving current, and the light emitting element 100b is driven to emit light.

[0154] As shown in FIG. 16, in the reset phase t1, the light emission control signal EM is set to an off voltage, the reset control signal RESET is set to an on voltage, and the scan signal SCAN is set to an off voltage.

[0155] As shown in FIG. 16, in the data writing and threshold compensation phase and the second reset phase t2, the light emission control signal EM is set to an off voltage, the reset control signal RESET is set to an off voltage, and the scan signal SCAN is set to an on voltage.

[0156] As shown in FIG. 16, in the light emission phase t3, the light emission control signal EM is set to an on voltage, the reset control signal RESET is set to an off voltage, and the scan signal SCAN is set to an off voltage.

[0157] As shown in FIG. 16, both the first voltage signal ELVDD and the second voltage signal ELVSS are constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0158] For example, the on - voltage in the embodiments of the present disclosure refers to the voltage that can conduct the first electrode and the second electrode of the corresponding transistor, and the off - voltage refers to the voltage that can cut off the first electrode and the second electrode of the corresponding transistor. When the transistor is a P - type transistor, the on - voltage is a low voltage (e.g., 0V), and the off - voltage is a high voltage (e.g., 5V). When the transistor is an N - type transistor, the on - voltage is a high voltage (e.g., 5V), and the off - voltage is a low voltage (e.g., 0V). The drive waveforms shown in FIG. 16 are all described by taking P - type transistors as examples. For example, the on - voltage is a low voltage (e.g., 0V), and the off - voltage is a high voltage (e.g., 5V), but it is not limited thereto.

[0159] Referring to FIGS. 10A and 16 together, in the first reset phase t1, the light - emission control signal EM is at the off - voltage, the reset control signal RESET is at the on - voltage, and the scan signal SCAN is at the off - voltage. At this time, the first reset transistor T6 is in the conducting state, and the second reset transistor T7, the data - writing transistor T2, the threshold - compensation transistor T3, the first light - emission control transistor T4, and the second light - emission control transistor T5 are in the off - state. The first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the drive transistor T1, stores it in the storage capacitor Cst, resets the drive transistor T1, and erases the data stored during the previous (previous frame) light emission.

[0160] During data writing and threshold compensation, in the second reset phase t2, the emission control signal EM is at an off voltage, the reset control signal RESET is at an off voltage, and the scan signal SCAN is at an on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in a conductive state, the second reset transistor T7 is in a conductive state, and in order to reset the light emitting element 100b, the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the first electrode E1 of the light emitting element 100b. However, the first emission control transistor T4, the second emission control transistor T5, and the first reset transistor T6 are in an off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first electrode of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA, and writes the data voltage VDATA to the first electrode of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 is turned on to connect the driving transistor T1 in a diode structure, thereby charging the gate of the driving transistor T1. After the charging is completed, the gate voltage of the driving transistor T1 is VDATA + Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and compensates the gate voltage of the driving transistor T1 according to the scan signal SCAN for the threshold voltage. In this phase, the voltage difference across both ends of the storage capacitor Cst is ELVDD - VDATA - Vth.

[0161] In the light-emitting phase t3, the light-emitting control signal EM is at an on voltage, the reset control signal RESET is at an off voltage, and the scan signal SCAN is at an off voltage. The first light-emitting control transistor T4 and the second light-emitting control transistor T5 are in a conductive state, and the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in an off state. The first voltage signal ELVDD is transmitted to the first electrode of the driving transistor T1 through the first light-emitting control transistor T4. The gate voltage of the driving transistor T1 is maintained at VDATA + Vth. The light-emitting current I flows into the light-emitting element 100b through the first light-emitting control transistor T4, the driving transistor T1, and the second light-emitting control transistor T5, and the light-emitting element 100b emits light. That is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM and control the light-emitting element 100b to emit light according to the light-emitting control signal EM. The light-emitting current I satisfies the following saturation current formula. [Number] However, μn is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1, respectively, and Vgs is the voltage difference between the gate and source of the driving transistor T1 (i.e., the first electrode of the driving transistor T1 in this embodiment).

[0162] From the above formula, it can be seen that the current flowing through the light-emitting element 100b is independent of the threshold voltage of the driving transistor T1. Therefore, this pixel circuit compensates very well for the threshold voltage of the driving transistor T1.

[0163] For example, the ratio of the time length of the light-emitting phase t3 to the 1-frame display period is adjustable. Thus, by adjusting the ratio of the time length of the light-emitting phase t3 to the 1-frame display time, the emission luminance can be controlled. For example, by controlling the scanning drive circuit or the additional drive circuit in the display panel, the ratio of the time length of the light-emitting phase t3 to the 1-frame display period can be adjusted.

[0164] For example, the embodiments of the present disclosure are not limited to the specific pixel circuit shown in FIG. 10A, and other pixel circuits capable of realizing the compensation of the driving transistor can be used. Based on the description and teachings of the implementation method in the present disclosure, all other arrangement methods that can be easily imagined by those skilled in the art without creative labor fall within the protection scope of the present disclosure.

[0165] As described above, the 7T1C pixel circuit is taken as an example for description, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, and is not limited in the embodiments of the present disclosure. Of course, the display panel may also include pixel circuits having less than 7 transistors.

[0166] In the embodiments of the present disclosure, elements located in the same layer can be formed from the same film layer by the same patterning process. For example, elements located in the same layer may be arranged on the surface away from the base substrate of the same element.

[0167] Note that for clarity, in the drawings used to illustrate the embodiments of the present disclosure, the thickness of the layer or region is enlarged. When an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, it is understood that it is directly located "on" or "under" the other element, or there may be intervening elements.

[0168] In embodiments of the present disclosure, the patterning or patterning process may include only a photolithography process, or a photolithography process and an etching process, or may include printing, inkjet, and other processes for forming a predetermined pattern. The photolithography process refers to a process of forming a film, exposing, developing, etc. using a photoresist, a mask plate, an exposure machine, etc. to form a pattern. According to the structure formed in the embodiments of the present disclosure, the corresponding patterning process can be selected.

[0169] If there is no conflict, the features of the same and different embodiments of the present disclosure can be combined with each other.

[0170] The above are only specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Modifications or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Claims

1. A display panel, comprising: a base substrate; a pixel unit located on the base substrate and including a pixel circuit and a light-emitting element, wherein the pixel circuit is configured to drive the light-emitting element and includes a driving transistor and a data writing transistor, and the driving transistor is connected to the data writing transistor; a data cable connected to the data writing transistor; the data cable includes a plurality of first-type data cables and a plurality of second-type data cables; the plurality of first-type data cables are arranged along a first direction, the first-type data cables extend along a second direction, and the first direction intersects the second direction; the second-type data cable includes a first portion, a second portion, and a third portion, and the first portion and the second portion are connected via the third portion; both the first portion and the second portion extend along the second direction, and the third portion extends along the first direction; the third portion and the second portion are located in different layers, the third portion and the first portion are located in different layers, the first portion is closer to the base substrate than the third portion, and the second portion is closer to the base substrate than the third portion; a plurality of the third portions are provided, and the plurality of third portions are dispersedly arranged in the display panel.

2. The display panel according to claim 1, wherein a size of the third portion in the first direction is equal to or greater than a shortest distance between the first portion and the second portion in the first direction.

3. The display panel according to claim 1 or 2, further comprising a plurality of dummy lines, wherein the plurality of dummy lines and the third portion of the second-type data cable are located in the same layer.

4. The display panel according to claim 3, wherein a plurality of the third portions are provided, and the plurality of dummy lines and the plurality of third portions are uniformly arranged in the display panel.

5. The display panel according to claim 3 or 4, wherein an extending direction of the plurality of dummy lines is the same as an extending direction of the third portion.

6. The display panel according to any one of claims 3 to 5, wherein the plurality of dummy lines are connected to a constant voltage line.

7. The constant voltage line includes at least one of a first power supply line, a second power supply line, and an initialization signal line, and the display panel according to claim 6.

8. Further including a plurality of dummy data cables, and the plurality of dummy data cables, the first portion of the second type of data cable, and the second portion of the second type of data cable are all located in the same layer, and the display panel according to claim 6.

9. Further including a first initialization signal line and a second initialization signal line, The pixel circuit further includes a first reset transistor and a second reset transistor, the first reset transistor is connected to the gate of the driving transistor and is configured to reset the gate of the driving transistor, the second reset transistor is connected to the first electrode of the light-emitting element and is configured to reset the first electrode of the light-emitting element, The first initialization signal line is connected to the gate of the driving transistor through the first reset transistor, and the second initialization signal line is connected to the first electrode of the light-emitting element through the second reset transistor, The first initialization signal line and the second initialization signal line are not connected and are each configured to have a signal applied thereto, and the display panel according to any one of claims 1 to 8.

10. The third portion is located between the pixel circuits of two adjacent pixel units in the second direction, and the display panel according to any one of claims 1 to 9.

11. The distance between the two farthest third portions is at least half of the size of the display area of the display panel in the second direction, and the display panel according to any one of claims 1 to 10.

12. The distance between two adjacent third portions in the second direction is not less than the sum of the sizes of two pixel units in the second direction, and the display panel according to any one of claims 1 to 11.

13. The plurality of third portions are uniformly arranged within at least half of the size of the display panel in the second direction, and the display panel according to any one of claims 1 to 12.

14. The base substrate has a first display area and a second display area, and the first display area is located on at least one side of the second display area, The pixel unit includes a first pixel unit and a second pixel unit. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area. The pixel circuit of the second pixel unit is located in the first display area, and the light-emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit via a conductive line. The display panel according to any one of claims 1 to 13, wherein the orthographic projection of the third portion onto the base substrate does not overlap the orthographic projection of the conductive line onto the base substrate.

15. The display panel according to claim 14, wherein the orthographic projection of the conductive line onto the base substrate partially overlaps the orthographic projection of the pixel circuit of the first pixel unit onto the base substrate.

16. The display panel according to any one of claims 1 to 15, wherein the plurality of first-type data cables are arranged at intervals from the first portion of the plurality of second-type data cables.

17. The display panel according to any one of claims 1 to 16, wherein the second-type data cable further includes a fourth portion and a fifth portion. The fourth portion extends along the second direction, the fifth portion extends along the first direction, and the first portion and the fourth portion are connected via the fifth portion.

18. A display device including the display panel according to any one of claims 1 to 17.

19. The display device according to claim 18, further including a photosensitive sensor located on one side of the display panel.

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