TSV Processing Window and Enhancement of Filling Performance by Long Pulse Output and Slope Portion Formation

Abstract

A method for electroplating metal into features of an electronic device partially fabricated on a substrate having high open area portions is provided, which includes initiating a bulk electrical fill phase with a high level current pulse, reducing the current to a baseline current level, and optionally increasing the current in one or more steps until electroplating is complete.

Description

Background Art

[0001] (Cross - reference to related applications) The PCT application form is submitted herewith with this specification as part of this application. Each application for which this application claims benefit or priority, as identified in the concurrently submitted PCT application form, is hereby incorporated by reference in its entirety as if fully set forth herein.

[0002] A through - silicon via (TSV) is a vertical electrical connection that completely penetrates a silicon wafer or die. TSV technology can be used to create 3D packages and 3D integrated circuits (ICs). TSV technology provides interconnection of vertically aligned electronic elements by internal wiring that significantly reduces the complexity and overall dimensions of multi - chip electronic circuits.

[0003] Typical TSV processing involves steps of forming a TSV via hole, depositing an isotropic diffusion barrier and a conductive seed layer, and subsequently filling the TSV via hole with metal. Copper is typically used as the conductive metal for TSV filling because it supports the high current densities encountered in complex integration such as 3D packages and 3D integrated circuits, as well as increased device speeds. Moreover, copper has good thermal conductivity and is available in a very pure state.

[0004] TSV via holes typically have a high aspect ratio, and depositing copper into such structures without voids due to the high aspect ratio is a difficult task. Copper CVD deposition requires complex and costly precursors, while PVD deposition often results in voids and limited step coverage. Electroplating is a more common method of depositing copper into TSV structures, but it also presents a set of challenges due to the large size and high aspect ratio of the TSVs.

[0005] In a typical TSV electrofilling process, the substrate is electrically biased negatively and brought into contact with a plating solution that may contain copper sulfate as a source of copper ions, sulfuric acid to control conductivity, and several organic additives known as inhibitors, accelerators, and levelers. Isometric filling, which involves depositing a significant amount of copper on the TSV sidewalls, can cause seam voids.

[0006] The background and contextual descriptions included herein are provided generally only for the purpose of presenting the background of the present disclosure. Much of the present disclosure presents the results of the inventors, and such results are only described in the "Background Art" section or presented as background elsewhere in this specification, and do not mean that they are recognized as prior art.

Summary of the Invention

[0007] Disclosed herein are methods and systems for electroplating a metal using a current waveform having a pulse. In one aspect of the embodiments disclosed herein, a method of electroplating a metal is disclosed, the method comprising contacting a plating solution having metal ions with a substrate, the substrate having a feature that provides at least about 0% to 9% open area on the surface of the substrate; applying an electrofilling current waveform to the substrate in contact with the plating solution, the electrofilling current waveform comprising (i) a pulse having a duration from about 10 seconds to about 200 seconds and having a magnitude at least about twice the magnitude of the baseline current, and (ii) a substantially constant current stage following the pulse and having an average magnitude of the baseline current; and filling at least a portion of the feature with metal.

[0008] In some implementations, the pulse of the electrical charge current waveform may include an initial step change that increases the magnitude of the current applied to the substrate, followed by a slope portion that reduces the magnitude of the current applied to the substrate. In some implementations, the duration of the slope portion may be at least 10 seconds. In some implementations, the slope portion may be a linear change between the magnitude of the pulsed current and the magnitude of the baseline current. In some implementations, the electrical charge current waveform may further include a second substantially constant current step that has an average magnitude greater than the magnitude of the baseline current. In some implementations, the electrical charge current waveform may further include one or more additional substantially constant current steps that each have an average magnitude greater than the magnitude of the baseline current. In some implementations, the electrical charge current waveform may further include a pre-pulse induction period, during which no current may be applied to the substrate, or an induction period current may be applied to the substrate, and the induction period current may have an average magnitude between about 30 mA and 200 mA. In some implementations, when applied to the substrate, the baseline current creates a current density between about 0.01 mA / cm 2 ~10 mA / cm 2 . In some implementations, the substrate may be a semiconductor wafer having an integrated circuit fabricated at least partially thereon.

[0009] In some embodiments, the substrate may be a 300 mm semiconductor wafer. In some embodiments, the features on the substrate are through-silicon vias. In some embodiments, the through-silicon vias have an aperture width or diameter of at least about 0.1 micrometer on average on the substrate surface. In some embodiments, the through-silicon vias have a depth of at least about 10 micrometers on average. In some embodiments, the through-silicon vias have an aspect ratio of about 4 or more on average. In some embodiments, the metal may be copper. In some embodiments, the electroplating solution contains a source of divalent copper ions. In some embodiments, the electroplating solution does not contain a source of monovalent copper ions. In some embodiments, the electroplating solution has a pH of about 0 to 1. In some embodiments, the electroplating solution contains an accelerator and an inhibitor. In some embodiments, the accelerator may be SPS. In some embodiments, the change in the electrofill current waveform from the pulse to the baseline current may be substantially immediate.

[0010] In another aspect of the embodiments disclosed herein, a method of electroplating a metal includes contacting a substrate having features with an electroplating solution having metal ions, and applying an electrofill current waveform to the substrate in contact with the electroplating solution, the electrofill current waveform including (i) a pulse having a duration from about 10 seconds to about 200 seconds and having a magnitude of at least about 2 times the magnitude of the baseline current, and (ii) a substantially constant current stage following the pulse and having an average magnitude of the baseline current, and filling at least a portion of the features with the metal.

[0011] In another aspect of the embodiments disclosed herein, an electroplating system is disclosed, the system comprising: an electroplating cell configured to include an anode and to contain an electroplating solution having metal ions; a wafer holder configured to support a substrate inside the electroplating cell; and one or more controllers configured to contact a substrate having features with the electroplating solution having metal ions and apply to the substrate in contact with the electroplating solution an electrofill current waveform comprising: (i) a pulse having a duration from about 10 seconds to about 200 seconds and having a magnitude at least about twice the magnitude of a baseline current, and (ii) a substantially constant current phase following the pulse and having an average magnitude of the baseline current, to fill at least a portion of the features with metal.

[0012] In some implementations, the pulse of the electrofill current waveform may include an initial step change that increases the magnitude of the current applied to the substrate, followed by a ramp that decreases the magnitude of the current applied to the substrate. In some implementations, the duration of the ramp may be at least 10 seconds. In some implementations, the ramp may be a linear change between the magnitude of the pulsed current and the magnitude of the baseline current. In some implementations, the electrofill current waveform may further include (iii) a second substantially constant current phase having an average magnitude greater than the magnitude of the baseline current. In some implementations, the electrofill current waveform may further include (iv) one or more additional substantially constant current phases each having an average magnitude greater than the magnitude of the baseline current. In some implementations, the electrofill current waveform may further include an induction period preceding the pulse, during which no current may be applied to the substrate, or an induction period current may be applied to the substrate, and the induction period current has an average magnitude between about 30 mA and 200 mA. In some implementations, when applied to the substrate, the baseline current creates a current density between about 0.01 mA / cm 2 and 10 mA / cm 2 on the substrate. In some implementations, the substrate may be a semiconductor wafer having at least partially fabricated integrated circuits thereon.

[0013] In some implementations, the substrate may be a 300 mm semiconductor. In some implementations, the features on the substrate are through-silicon vias. In some implementations, the through-silicon vias have an aperture width or diameter of at least about 0.1 micrometer on average on the substrate surface. In some implementations, the through-silicon vias have a depth of at least about 10 micrometers on average. In some implementations, the through-silicon vias have an aspect ratio of about 4 or more on average. In some implementations, the metal may be copper. In some implementations, the electroplating solution contains a source of divalent copper ions. In some implementations, the electroplating solution does not contain a source of monovalent copper ions. In some implementations, the electroplating solution has a pH of about 0 to 1. In some implementations, the electroplating solution contains an accelerator and an inhibitor. In some implementations, the accelerator may be SPS. In some implementations, the change in the electrofill current waveform from the pulse to the baseline current may be substantially instantaneous.

[0014] These and other features of the disclosed embodiments will be described in detail below with reference to the accompanying drawings.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0024] Introduction This specification provides techniques for reducing voids in plated features, such as silicon through vias (TSVs) or wafer level packaging (WLP). A TSV is a via for electrical connection that completely penetrates a semiconductor workpiece, such as a silicon wafer or die. In this disclosure, various terms are used to describe semiconductor workpieces. For example, "wafer" and "substrate" are used interchangeably. A typical TSV process involves forming a TSV via, depositing an isotropic diffusion barrier and a conductive seed layer on the substrate, and subsequently filling the TSV via with metal. TSV vias typically have a high aspect ratio, and due to the high aspect ratio, depositing copper into such a structure void - free is a difficult task. TSVs typically have an aspect ratio of 4:1 or more, such as 10:1 or more, and even 20:1 or more (e.g., reaching about 30:1), the width of the opening is about 0.1 μm or more, such as about 5 μm or more, and the depth is about 50 μm or more and about 100 μm or more, etc., about 5 μm or more. Examples of TSVs include features of 5 μm×50 μm and 10 μm×100 μm. Filling such large concave features is particularly difficult when coating with an acid - sensitive seed layer using conventional techniques. Chemical vapor deposition (CVD) of copper requires complex and costly precursors, while physical vapor deposition (PVD) often results in voids and limited step coverage. The process of depositing or plating a metal onto a conductive surface via an electrochemical reaction is generally called electroplating, plating, or electro - filling. Electroplating is a more common method for depositing copper into a TSV structure, but also presents a series of challenges due to the large size and high aspect ratio of TSVs.

[0025] Figure 1 illustrates the distribution of plating solution components when a substrate 100 having a concave feature or via 103 is in contact with a plating solution 120. A schematic cross-sectional view of the substrate 100 is shown. The substrate 100 includes a layer 101 of silicon and a via 103 etched into the silicon 101. In some embodiments, a dielectric liner (not shown) may be deposited over the silicon 101. A diffusion barrier layer 105, such as a bilayer of Ti / TiN, Ta / TaN, or W / WN, is present over the dielectric layer. A seed layer 107, such as a cobalt, copper, or nickel seed layer, is present on top of the barrier layer 105 and is exposed to the electroplating solution 120. In some embodiments, an isotropic laminate film may be present on the substrate. The electroplating solution 120 contains metal salts, acids, and additives such as accelerators and inhibitors. As shown in Figure 1, in a typical TSV electrofilling process, the substrate 100 is electrically biased negatively and brought into contact with the plating solution 120 in a plating bath, which generally includes a metal salt such as copper sulfate or copper methanesulfonate as a source of copper ions, an acid such as sulfuric acid or methanesulfonic acid to control conductivity, along with additives such as chloride ions, and various functional classes of organic additives known as inhibitors, accelerators, and leveling agents.

[0026] Damascene processing is a method for forming metal lines on an integrated circuit. In some cases, TSVs are used in conjunction with Damascene processing to create 3D packages and 3D integrated circuits by providing interconnections for vertically aligned electronic elements through internal wiring. Such 3D packages and 3D integrated circuits can significantly reduce the complexity and overall dimensions of multi-chip electronic circuits. During Damascene processing, or on the surface of an integrated circuit formed within a TSV, the conductive pathways are generally filled with copper.

[0027] The disclosed methods and apparatus can be used to electroplate various concave features, but are particularly advantageous for filling TSV substrates with a large open area that is a small portion of the flat geometric surface area of the substrate occupied by the TSVs.

[0028] When electrically filling a feature, it is desirable to avoid voids. One way to avoid voids during electrical filling is to limit the current applied. It has been found that voids are reduced by limiting the current below an empirically determined threshold. However, reducing the applied current may not remove voids in wafers having a high open area as described herein. FIG. 2 shows four different features 200a-200d, each of which has voids 202a-202d, where the applied current increases from 200a to 200d. At high currents, voids are present, such as in features 200c and 200d. Typically, as seen with voids 202c and 202d, reducing the current results in voids being formed at a higher location. However, reducing the current does not remove the voids, and voids are also formed at a lower location at a low enough current, as shown by void 202b. At a low enough current, instead of pocket voids as seen in features 200b-200d, seam voids occur as seen in feature 200a. Increasing the current from feature 200a resulted in pocket voids as seen in feature 200b. As a result, it appeared that there was no current at which electroplating would not incorporate voids.

[0029] The solution discovered by the inventors to reduce voids for wafers with a high open area is to start the bulk electrical filling period using high current pulses. By increasing the current for a short period, e.g., from a few seconds to a few minutes, and subsequently reducing the current to the first bulk electrical filling current step, the presence of seam voids and pocket voids is reduced.

[0030] The current waveform depicts the current applied throughout the electroplating process. Figure 4B shows several different current waveforms. The "no pulse" waveform in Figure 4B exemplifies a typical waveform where the current is at a minimum or zero during the induction period and then followed by a step change to the bulk electrofilling period. Figure 4B shows only a single step change during the bulk electrofilling period, but there may be multiple step changes within the scope of the bulk electrofilling period. As further discussed below, the other waveforms in Figure 4B illustrate various pulse techniques.

[0031] Technical Terms Wafer or substrate As used herein, the terms "semiconductor wafer" or "semiconductor substrate" or simply "substrate" refer to a substrate having semiconductor material anywhere within its body, and those skilled in the art understand that the semiconductor material need not be exposed. The semiconductor substrate may include one or more dielectric layers and conductive layers formed across the entire surface of the semiconductor material. Wafers used in the semiconductor device industry are typically circular semiconductor substrates that may have a diameter of, for example, 200 mm, 300 mm, or 450 mm. The following detailed description describes electrochemical plating, also referred to herein as "electroplating" or simply "plating," and the subsequent etching of the material plated on the wafer. However, those skilled in the art will recognize that there are suitable alternative implementations to the implementations described herein, and that the disclosed electroplating operations may be performed on workpieces of various shapes and sizes made from various materials. In addition to semiconductor wafers, other workpieces on which the disclosed implementations may be utilized include various articles such as printed circuit boards (PCBs). In some embodiments, the wafer may be glass with through-silicon vias rather than through-silicon vias.

[0032] Additive To apply to TSVs and, optionally, to WLP, electroplating may be performed at low current to avoid the formation of pinch off voids and accommodate copper diffusion in high aspect ratio features. Additives may be included in the electroplating solution to change the behavior of the electroplating solution on the substrate to allow bottom-to-top filling of the features. Examples of additives include inhibitors, accelerators, and levelers. In some embodiments, the inhibitor may serve both as an inhibitor and a leveler (e.g., the inhibitor may have "leveling characteristics"). An example of an additive package may include 60 g / L of Cu, 60 g / L of sulfuric acid, and 50 ppm of chloride with HSL-A accelerator and HSL-B inhibitor available from Moses Lake Industries, Moses Lake, WA.

[0033] During electroplating, changes in the additives on the wafer surface cause voltage drift during the constant current electroplating stage. For example, without being limited to a particular theory, it is believed that the surface concentration of the inhibitor adsorbed on the wafer surface decreases over time because the inhibitor is displaced by the adsorption of the accelerator, thereby reducing polarization and the voltage between the electrodes. The locally high surface concentration of the accelerator adsorbed at the bottom of the via causes an increase in the plating rate within the via and bottom-to-top filling. As the via approaches near-complete filling, the local acceleration effect decreases and the polarization increases, partly due to the inhibitor and / or leveler replacing the accelerator within the via. This decrease in accelerator activity reduces the formation of large bulges across the via surface and is generally referred to as "leveling". The inhibitor as used herein may have leveling characteristics.

[0034] Inhibitor While not wishing to be limited to any particular theory or mechanism of operation, inhibitors (either alone or in combination with other solvents) are believed to be surface polarization compounds that cause a significant increase in voltage drop across the entire substrate-electrolyte interface, particularly when present in combination with surface chemically adsorbed halides (e.g., chlorides or bromides). The halide may serve as a chemisorption bridge between the inhibitor molecule and the substrate surface. The inhibitor not only increases the local polarization of the substrate surface in the region where the inhibitor is present relative to the region where the inhibitor is absent, but also generally increases the polarization of the substrate surface. The increase in (local and / or general) polarization corresponds to an increase in resistivity / impedance and thus slower plating at a given applied potential.

[0035] Inhibitors are not incorporated very much into the deposited film but are thought to slowly deteriorate over time by electrolysis or chemical decomposition in the bath. Inhibitors are often relatively large molecules and in many instances are essentially polymers (e.g., polyethylene oxide, polypropylene oxide, polyethylene glycol, polypropylene glycol, etc.). Other examples of inhibitors include polyethylene oxide and polypropylene oxide with S- and / or N-containing functional groups, block polymers of polyethylene oxide and polypropylene oxide, etc. Inhibitors can have linear, branched, or both structures. It is common for inhibitor molecules with different molecular weights to coexist in commercially available inhibitor solutions. Due in part to the large size of inhibitors, the diffusion of these compounds into concave features may be relatively slow compared to other solution components.

[0036] Some inhibitors include leveling characteristics. A leveler may be used in combination with an inhibitor and / or an accelerator, but some inhibitors may include sufficient leveling behavior in the disclosed embodiments.

[0037] Although not wishing to be limited to any theory of operation or mechanism of operation, the leveler serves (either alone or in combination with other solvents) as an inhibitor of the agent and is thought to counteract the depolarization effect associated with the accelerator, particularly in areas such as the field region of the substrate being processed, especially in the exposed portions of the substrate and on the sidewalls of the features. The leveler may locally increase the polarization / surface resistivity of the substrate, thereby slowing the local electrodeposition reaction in the area where the leveler is present. The local concentration of the leveler is determined to some extent by mass transport. Therefore, the leveler acts primarily on surface structures having a geometry that protrudes away from the surface. This action "smoothes" the surface of the electrodeposited layer. In many cases, the leveler reacts or is consumed at or near the diffusion-limited rate at the substrate surface, and therefore, continuously supplying the leveler is thought to be beneficial for maintaining uniform plating conditions over time in many situations.

[0038] Redox compounds are generally classified as redox based on their electrochemical functions and effects and do not require a specific chemical structure or chemical formula. However, redox often contains one or more nitrogens, amines, imides, or imidazoles and may also contain sulfur functional groups. Certain redox contain one or more five-membered and six-membered rings and / or derivatives of conjugated organic compounds. The nitrogen group may form part of the cyclic structure. In amine-containing redox, the amine may be a primary alkylamine, secondary alkylamine, or tertiary alkylamine. Moreover, the amine may be an arylamine or a heterocyclic amine. Examples of amines include, but are not limited to, dialkylamine, trialkylamine, arylalkylamine, triazoles, imidazole, triazole, tetrazole, benzimidazole, benzotriazole, piperidine, morpholine, piperazine, pyridine, oxazole, benzoxazole, pyrimidine, quinoline, and isoquinoline. Imidazole and pyridine may be particularly useful. An example of a redox is Janus Green B. Redox compounds may also contain an ethoxide group. For example, a redox may contain a general backbone similar to that found in the main chain of polyethylene glycol or polyethylene oxide with fragments of amines functionally inserted throughout the chain (e.g., Janus Green B). Examples of epoxides include, but are not limited to, epihalohydrins such as epichlorohydrin or epibromohydrin, and polyepoxide compounds. Polyepoxide compounds having two or more epoxide moieties linked together by ether-containing chains may be particularly useful. Some redox compounds are polymers, while others are not. Examples of polymeric redox compounds include, but are not limited to, polyethyleneimine, polyamidoamine, and reaction products of amines with various oxygen epoxides or sulfides. An example of a non-polymeric redox is 6-mercaptohexanol. Another example of a redox is polyvinylpyrrolidone (PVP).

[0039] Accelerator Although it is desired not to be limited to any activity theory or mechanism, it is believed that accelerators (either alone or in combination with other solvents) tend to locally reduce the polarization effect associated with the presence of inhibitors, thereby locally increasing the electrodeposition rate. The reduced polarization effect is most pronounced in the area where the adsorbed accelerator is most concentrated (i.e., polarization decreases as a function of the local surface concentration of the adsorbed accelerator). Examples of accelerators include, but are not limited to, dimercaptolpropane sulfonic acid, dimercaptolethane sulfonic acid, mercaptopropane sulfonic acid, mercaptoethane sulfonic acid, bis-(3-sulfopropyl) disulfide (SPS), and their derivatives. Accelerators may become strongly adsorbed on the substrate surface and, as a result of the plating reaction, generally do not move laterally on the surface but are generally not significantly incorporated into the film. As a result, accelerators remain on the surface when depositing metal. When filling a recess, the local accelerator concentration increases on the surface inside the recess. Accelerators tend to be smaller molecules when compared to inhibitors, indicating that they diffuse more quickly into concave features.

[0040] Bottom-up filling In the bottom-up filling mechanism, concave features on the plating surface tend to be plated with metal from the bottom to the top of the feature, from the sidewalls inward toward the center of the feature. The deposition rate can be controlled within the feature and in the field region to achieve uniform filling and avoid incorporation of voids into the feature. The three types of additives described above are beneficial for achieving bottom-up filling and each acts to selectively increase or decrease polarization at the substrate surface.

[0041] In the later stages of plating, especially when overburden accumulates, the accelerator may undesirably increase in certain areas (e.g., the features filled above), resulting in plating locally faster than desired. A leveler may be used to counteract this effect. Without a leveler, the features may become overfilled and may tend to create bulges. Thus, in the later stages of bottom-up fill plating, the leveler is beneficial in creating a relatively flat deposit.

[0042] By using a combination of inhibitor, accelerator, and leveler, it may be possible to fill features from the inside of the sidewalls bottom-up without voids while creating a relatively flat deposited surface. Since the exact identification / composition of the additive compounds is typically maintained as a trade secret by the additive suppliers, information regarding the exact nature of these compounds is not publicly available.

[0043] Open area As used herein, the term "open area" may refer to the small portion of the substrate surface occupied by a via or other feature. The open area is measured across the entire plane on the surface of the substrate without considering the depth of the feature. The techniques described herein may be particularly suitable for substrates having a "high" open area, e.g., an open area wider than 0.9% or wider than about 1%. Medium or low open areas may generally be less than 0.9% or less than about 1%. Substrates with a high open area may have a greater number of TSVs than typical TSVs and / or TSVs with a larger diameter than typical TSVs.

[0044] Electrical fill current waveform As used herein, the term "electroplating current waveform" or "current waveform" may refer to a graph of the current applied during electroplating as a function of time. A typical current waveform may have an initial induction period, followed by a bulk electroplating period. The induction period may have very little or no flowing current. The bulk electroplating period may have a series of constant current steps. For example, it may have 2 to 6 steps. The steps may increase in magnitude sequentially. The bulk electroplating period may be divided into one or more steps that increase the current during the plating process. The techniques described herein may initiate a bulk electroplating period with a substantially constant portion following a pulse. Generally, the techniques described herein describe the current values when applied to a 300 mm wafer and may be appropriately adjusted for wafers of different sizes. The current density value is based on the flat (blanket) surface area of the wafer and does not consider the additional surface area provided by the features of the substrate.

[0045] Pulse As used herein, the term "pulse" may refer to a large increase in current before reducing the current until the first step of the bulk electroplating period. The current of the pulse is higher than that of the bulk electroplating period and, in some embodiments, may be at least twice the current of the current step following the bulk electroplating period. The reduction of the current from the pulse to the first step of the bulk electroplating period may be achieved in various ways, including an immediate step change, a reduction over time ("ramp"), or any other function that reduces from the pulse current to the bulk electroplating current. The pulse may have one or more ramps and / or one or more step changes.

[0046] Copper The copper-containing metals discussed in this specification refer to "copper" including, without limitation, pure copper metal, copper alloys with other metals, and copper metal impregnated with non-metallic species such as organic and inorganic compounds (e.g., levelers, accelerators, inhibitors, surfactants, etc.) used during the electroplating operation. Copper is typically used as a conductive metal in TSV filling because it supports the high current densities encountered in complex integration, such as for 3D packages and 3D integrated circuits. Copper also supports high device speeds. Moreover, copper has good thermal conductivity and is available in a very pure state.

[0047] The electroplating process will be described mainly with reference to copper plating, and more particularly to TSV copper damascene plating. However, it is understood that the methods and related apparatus configurations provided herein can be used to perform plating of other metals and alloys, such as Co, Au, Ag, Ni, Ru, Pd, Sn, In, and alloys of any of these, such as Sn / Ag alloys or Sn / In alloys, and for through-resist plating. The plating electrode contains a source of the required metal ions (metal salts) and typically an acid to increase the electrolyte conductivity.

[0048] Background - Open Area and TSV Plating Current For TSV wafers with a relatively low open area in conventional electroplating operations (e.g., the open area is less than about 0.9%), one approach is to plate at the highest possible current without introducing voids. At particularly high currents, it is generally observed that the filled features have voids. As described with reference to FIG. 2, higher currents typically cause voids, such as voids 202c and 202d. When working with wafers having a low or medium open area, the process window is defined by the highest possible current without introducing voids. The optimal current may have the fastest fill rate without introducing voids, and may be the highest current that does not introduce voids, or a lower current. As the current increases, the fill rate may reach a maximum value and decrease from the high current before voids occur, such that the optimal current may be less than the possible maximum without introducing voids.

[0049] However, this procedure was found not to work on TSV wafers having a relatively high open area, e.g., at least 0.9% or more. When plating on wafers having such a relatively high open area, as described above, it was observed that voids were formed at high currents. However, when transitioning to lower currents, voids still occurred and ultimately, seams were observed to form within the features, such as seen in feature 200a of FIG. 2. The seams suggest that plating is occurring on the sidewalls of the features under these conditions.

[0050] In an attempt to find an appropriate current processing window for plating features within a high open area, the inventors have investigated in detail the potential mechanism's consideration of this apparent plating on the sidewalls. FIG. 5 is a polarization diagram for plating a wafer 502 with a low open area and a wafer 504 with a high open area. During the time window 505, the potential of the wafer 502 with a low open area gradually increases as plating occurs until a stable potential is reached. In contrast, the potential of the wafer 504 with a high open area takes much longer to polarize during the time window 505. The inventors considered that this "shoulder" might be the result of plating ions that require lower polarization, such as first copper ions rather than second copper ions.

[0051] Although not wishing to be limited by theory, the problem of seam formation within the TSV feature may sometimes be due to the presence of first copper ions inside the feature when starting the bulk filling process. The plating of first copper ions when starting the bulk electroplating period may be reflected by the initial low polarization in the curve of FIG. 5. Plating wafers with a wider open area has more first copper ions and / or a lower driving force for electroplating, which appears as a larger polarization delay.

[0052] Prior to bulk electroplating, first copper ions may accumulate locally at a high concentration inside the feature. The equilibrium concentration of first copper ions near the Cu seed layer in the acidic electroplating solution becomes higher as the potential approaches the open circuit potential. Therefore, a higher concentration of first copper ions is predicted near the wafer during the induction period without current or with a very low current (0 mA to 60 mA on a 300 mm wafer). Eventually, during electroplating, the excess first copper ion concentration decreases as the first copper ions are reduced to copper metal.

[0053] As a result, the local concentration of cuprous ions is relatively high close to the surface of the wafer to be plated or being plated. This state exists at least initially during the bulk electroplating period of the process. Eventually during electroplating, the excess cuprous ion concentration decreases as the cuprous ions are reduced to copper metal. The concentration of cuprous ions in the field region is rapidly reduced by the convection caused by wafer rotation. However, the cuprous ions within the vias remain at a higher concentration for a longer time because the convection does not reach deep within the vias. Blanket wafers plated at various currents do not show shoulders in the voltage profile (do not show data), and it has been observed that they support rapid consumption of cuprous ions outside the vias. The polarization delay shown in FIG. 5 further supports this well, and after the time window 505, the polarization curves for the low-open area wafer 502 and the high-open area wafer 504 realign. As the open area increases, which means that there are more features where the cuprous ion concentration remains high even under strong convection, a longer delay is observed as shown in FIG. 5, and after the time window 505 when the cuprous ions within the vias are reduced, the polarization curves for the low-open area wafer 502 and the high-open area wafer 504 realign.

[0054] A higher concentration of only cuprous ions may be insufficient to cause voids, but cuprous ions form complexes with additives or by-products of additives within the features, and the cuprous ions that form complexes are thought to adhere to the sidewalls or otherwise interfere with the inhibitory effect of inhibitor molecules on the sidewalls of the filled features. Since plating on the sidewalls is not suppressed early in the deposition process, plating may occur on the sidewalls, which can create seams within the filled features.

[0055] In contrast to cuprous ions, cupric ions may not interfere with the suppression on the sidewalls of the wafer features. However, since a copper seed layer is present and much of the interface is created on the wafer surface where there are features within, cuprous ions may remain locally concentrated within the features.

[0056] The interference from the first copper ions is thought to be less severe in wafers with low open areas, due to the contribution from the high local current within the via being smaller relative to the total current. After the induction period, the first plating is easier within the via than in the field because the concentration of the first copper ions within the via is higher (i.e., it reduces at a lower overvoltage). For some waveforms, the via current density is significantly higher than the current density of the field that causes polarization, and there is no intense sidewall growth. To have the same via filling environment for wafers with high open areas, a similarly higher current density should be maintained within the via compared to the field area.

[0057] For example, when the open area increases from 0.05% to 0.5% with a via (opening in the depth direction) of 10 μm × 100 μm, the total surface area on the substrate surface increases from 102% to 120% (100% is the blanket wafer area of a 300 mm wafer). As an example, the total current may increase by more than 200% (in the case of high open areas) to achieve a similar via current density and field current density (field current density × field area + via current density × via surface area). The current calculation based on the increase in surface area and bulk filling current may significantly underestimate the optimal current for wafers with high open areas. (It may be appropriate for substrates with low open areas.) Low-current plating may slow down the initial polarization during the initial bulk filling stage and is thought to cause sidewall growth. Moreover, a higher current may be useful only during the initial stage of plating while there is an abundance of the first copper ions within the via. Once all the excess first copper ions are reduced and the concentration of the first copper ions within the feature approaches the concentration within the bulk solution, the current may be changed to a lower bulk filling current. Some embodiments of the present disclosure may address the locally high concentration of the first copper ions present within the feature when starting the bulk electrical filling period of the deposition process.

[0058] Process Flow FIG. 3 presents a flow diagram regarding process 301 of electroplating metal among the features of a wafer that may be a wafer with TSVs and high open areas in some embodiments. Starting from operation 300, as described herein, a substrate having features to be filled is brought into contact with an electroplating solution having metal ions. During the induction period, a minimum current, such as between about 0 mA and 120 mA for a 300 mm wafer, may be applied to the wafer. The induction current may reduce the rate at which the copper seed layer inside the feature converts to a second copper ion.

[0059] In operation 304, the features are filled with metal through a bulk electrofill process by applying a current waveform to the wafer. FIG. 4A provides an illustration of an example of the current and voltage waveforms. As may be understood, the current starts at zero or a minimum level and is followed by pulses with a ramp up to a first bulk electrofill current stage and then to a second current stage. The voltage waveform generally follows the current waveform.

[0060] The bulk electrical filling operation 304 starts with a pulse in operation 304A. The pulse may be realized using various waveforms. FIG. 4B illustrates not only four different pulses but also waveforms without a pulse. The pulse generally reaches a maximum value and then immediately drops to the first current stage or reduces to the first current stage over a period of time. In some embodiments, the maximum current of the pulse is at least about twice the current of the first current stage, or between about 3 times and about 5 times the current of the first stage. In some embodiments, the maximum current of the pulse may be about 2 A for a 300 mm wafer, or between about 0.5 A and 5 A for a 300 mm wafer. In some embodiments, the duration of the pulse is at least about 10 seconds before dropping to the first current stage. In some embodiments, the pulse reduces linearly over time to the first current stage (the "ramp"). The duration of the ramp may be at least 30 seconds. In some embodiments, the duration of the pulse including the ramp may be between about 10 seconds and 200 seconds. In some embodiments, rather than immediately ramping down as shown in FIG. 4B, the maximum current is maintained for a duration such as at least 10 seconds before ramping down. In some embodiments, the ramp down may be non-linear and reduced by different functions.

[0061] The effects of various pulse waveforms are illustrated by FIG. 4C, which shows the average ramp height for the waveforms illustrated in FIG. 4B after completion of the electroplating process. Generally, a higher average ramp height is better as it indicates a faster plating rate. The 15-second pulse shows the minimum height or plating rate but also provided a void-free deposition. The 40-second pulse and the ramping-down pulses have a better ramp height or plating rate, and the two ramping-down current waveforms had a slightly better ramp height. This may be due to the ramp reducing the first copper ions or better following the decrease in the first copper ion concentration over time. However, the risk of voids increases as the current increases.

[0062] In operation 304B, apply a first current step or add a baseline current. As described above, in a typical electroplating process, the current may be increased in a number of steps. After applying the pulse, the current is reduced to the baseline and the electroplating potentially proceeds through a number of steps. The step of reducing to the baseline current after the pulse may be important to avoid creating voids, and problems associated with high current may occur in features 200c and 200d of FIG. 2 if the applied current is maintained at the pulse value for a long time. Using the baseline current or the first current step may help to stabilize the bottom-to-top filling mechanism before increasing the current in subsequent steps. Since the plating rate generally increases with higher current, it is advantageous to maximize the applied current as long as voids do not occur. Operation 304C is an iterative operation that increases the current by a factor of one or more to achieve an increase in the plating rate. Generally, each current step increases the current substantially instantaneously. In operation 306, the electrofilling process is completed and operation 306 may include the step of transferring the wafer to a different tank or processing chamber, or performing a different process on the wafer.

[0063] Wafer Fill Rate and Uniformity In addition to reducing the presence of voids, another benefit of the techniques described herein is to improve the fill rate and fill uniformity between regions of a die or wafer having high and low open areas. FIG. 6 illustrates that low open areas may be filled void-free regardless of whether a pulse is implemented. However, using a pulse allows features to be filled faster without the presence of voids. Similarly, high open areas may have voids when the current waveform does not include a pulse, as discussed above. By using a pulse as described herein, high open areas can not only be filled void-free or with reduced voids, but also at a faster rate. This may be due to the pulse increasing the nucleation effect with respect to bottom-up fill without increasing the risk or presence of voids. This may also be due to the pulse reducing sidewall growth. Removing first copper ions may improve the significant difference between bottom-up fill and sidewall / field growth.

[0064] FIG. 7 demonstrates how the fill rate may become more uniform across the entire die or wafer. Without a pulse, the dense or high open area portions of the die may have a reduced plating rate compared to the isolated or low open area portions of the die. By using a pulse, the fill rate uniformity may be increased between portions of a die having high and low open areas. Greater uniformity of the plating rate across the entire wafer is preferred because there is less overburden that needs to be removed in subsequent processing.

[0065] In some embodiments, the pulse techniques described herein may be used with wafers having open areas between about 0.01% and 5%. Pulses are useful for avoiding voids in high open area wafers, but the pulses described herein may be used with wafers having lower open areas to increase the fill rate and fill uniformity, as described with reference to FIG. 7. As a result, the pulse techniques described herein are not limited to high open area wafers.

[0066] Electroplating Solution Generally, the electroplating solution can contain one or more copper salts including, without limitation, copper sulfate, copper methanesulfonate, copper propanesulfonate, copper gluconate, copper pyrophosphate, copper sulfamate, copper nitrate, copper phosphate, copper chloride, and various combinations thereof. In some embodiments, copper sulfate and alkanesulfonate copper are preferred copper ion sources. In some embodiments, a mixture of copper sulfate and alkanesulfonate copper may be used. The concentration of copper ions in a typical electrolyte is at least about 10 g / L, such as between about 10 g / L and 200 g / L. In some embodiments, a high concentration of copper is preferred for faster plating. For example, in some embodiments, a high copper electrolyte containing at least about 40 g / L, such as at least about 60 g / L (e.g., between about 40 g / L and 200 g / L, such as between about 60 g / L and 150 g / L) of Cu 2+ ions is used. In some embodiments, electroplating is performed at room temperature (e.g., at about 20 °C to 25 °C), but in other embodiments, it may be preferable to perform electroplating at a higher temperature to increase the solubility of the copper salt and thus the available copper ion concentration. The higher temperature also allows for faster diffusion of the copper ions and thus a higher achievable plating rate. For example, in some embodiments, electroplating is performed at a high solution temperature of about 30 °C to 80 °C, such as between about 40 °C and 60 °C. Most commonly, plating is performed at an electrolyte temperature of about 20 °C to 60 °C.

[0067] In some embodiments (but not necessarily), the electrolyte further comprises acids such as sulfuric acid, methanesulfonic acid, propanesulfonic acid, nitric acid, phosphoric acid, hydrochloric acid, and various combinations thereof. For example, in one embodiment, the electrolyte solution contains copper sulfate and sulfuric acid. When using sulfuric acid and / or methanesulfonic acid, a concentration of at least about 1 g / L, such as about 60 g / L, is preferred. The acid acts to increase the conductivity of the electrolyte. Preferably, an electrolyte having a conductivity of at least about 40 mS / cm, such as an electrolyte having a conductivity between about 200 mS / cm and 300 mS / cm, is used. Such an electrolyte can be obtained, for example, by using sulfuric acid and / or methanesulfonic acid at a concentration of at least 1 g / L, such as about 60 g / L. In some embodiments, the electrolyte comprises sulfuric acid and / or methanesulfonic acid at a concentration between about 10 g / L and 200 g / L. In some implementation forms, a highly acidic electrolyte containing at least about 0.4 M of a strong acid, such as a strong acid between about 1 M and 2 M, is preferred for high-speed plating. For example, in some embodiments, a highly acidic electrolyte containing sulfuric acid, methanesulfonic acid, or a mixture thereof between about 40 g / L and 200 g / L is used. In some embodiments, about 60 g / L of sulfuric acid is used and / or the electrolyte has about 0.6 M of a strong acid.

[0068] In some embodiments, the plating solution contains chloride ions at a concentration between about 5 ppm and 300 ppm.

[0069] In some embodiments, the plating solution may further contain an accelerator. The accelerator may help increase the deposition rate and promote dense nucleation leading to a film with a fine structure and may contain sulfur, oxygen, or nitrogen functional groups. In some embodiments, the accelerator contains an S-S disulfide group. The accelerator may be present, for example, at a low concentration level between 1 ppm and 200 ppm. Examples of accelerators include 3-mercapto-1-propanesulfonic acid, bis-(3-sodiumsulfopropyl disulfide) (SPS), and N,N-dimethyl-dithiocarbamylpropylsulfonate (DPS).

[0070] In some embodiments, the plating solution may further include an electrochemical inhibitor. The inhibitor is an additive that reduces the plating rate and is typically present in the plating bath at a higher concentration than the accelerator, for example, at 5 ppm to 1,000 ppm. The inhibitor is generally a high molecular weight polymeric surfactant such as polyethylene glycol (PEG) and polyethylene oxide (PEO), or a block copolymer of both. The inhibitor molecules adsorb on the surface to form a barrier layer against copper ions, thereby slowing down the deposition rate. Since the inhibitor is large in size and slow in diffusion rate, it may not reach the lower part of the TSV as readily as the wafer area, which results in a lower initial concentration at the bottom of the TSV. Thus, most of the inhibitory effect occurs first at the surface of the substrate (the field region), which helps to reduce the overburden and avoid the TSV hole from "closing". In some embodiments, an accelerator is used in combination with the inhibitor. The large size of the inhibitor allows it to diffuse into the feature slower than the accelerator, and thus there is an initial increase in the accelerator at the bottom with respect to the feature. This then creates an inhibitory difference between the field and the bottom of the feature that stops the adsorption of the inhibitor and thus drives the bottom-to-top filling.

[0071] In some embodiments, the plating solution may include a leveler. The leveler is an additive that aims to deactivate the accelerated surface moving at high speed and also polarize the field. The leveler is present at a very low concentration, such as 1 ppm to 500 ppm, if any, and the blocking effect of the leveler at the surface is very localized. The leveler is also generally electrochemically activated. The reaction rate of the leveler at the surface, combined with the generally low concentration of the leveler, often drives the leveler by diffusion effects. As a result, the leveler mainly selectively reduces the deposition at the high points of the plated substrate and levels the low points. Furthermore, this behavior can be used to enhance the copper plating rate at the base of the TSV relative to the growth rate at the wafer field. In some cases, the leveler may contain a functional group containing a nitrogen atom that tends to form a complex with Cu(I) ions at the wafer interface.

[0072] In some embodiments, the additive further reduces the in-field current density (and plating rate) at the upper lip of the TSV relative to the in-field current density in the field obtained in the absence of the additive. The additive helps to achieve void-free filling by increasing the relative plating rate at the bottom of the feature relative to the feature opening and can be used in synergy with DSI compounds. This difference is often referred to as "uniform electrodeposability".

[0073] Examples of suitable electrolyte compositions are listed below. 1. 60 g / l Cu 2+ (in the form of copper sulfate) / 60 g / l H2SO4 / 60 ppm Cl - + 60 ppm benzyl dimethyl hexadecyl ammonium chloride 2. 50 g / l Cu 2+ (in the form of copper sulfate) / 100 g / l H2SO4 / 50 ppm Cl - + 50 ppm benzyl dimethyl hexadecyl ammonium chloride 3. 70 g / l Cu 2+ (in the form of copper sulfate) / 50 ppm benzyl dimethyl hexadecyl ammonium chloride 4. 50 g / l Cu 2+ (in the form of copper sulfate) / 100 g / l H2SO4 + 50 ppm benzyl dimethyl hexadecyl ammonium chloride 5. 50 g / l Cu 2+ / 10 g / l H2SO4 + 30 ppm tonzonium bromide 6. 120 g / l Cu 2+ (in the form of copper methanesulfonate) / 20 g / l methanesulfonic acid / 50 ppm Cl - + 1 ppm accelerator + 200 ppm inhibitor + Enthone DVF200C

[0074] Apparatus FIG. 8 presents an example of an electroplating cell in which electroplating may be performed. In many cases, an electroplating apparatus includes one or more electroplating cells in which a substrate (e.g., a wafer) is processed. Only one electroplating cell is shown in FIG. 8 for clarity. Additives (e.g., accelerators, inhibitors, and leveling agents) are added to the electrolyte to optimize bottom-to-top electroplating. However, the electrolyte with additives may react with the anode in an undesirable way. Thus, the anode and cathode regions of the plating cell may be separated by a membrane so that plating solutions of different compositions may be used in each region. The plating solution in the cathode region is called the catholyte, and the plating solution in the anode region is called the anolyte. Several engineering designs can be used to introduce the anolyte and catholyte into the plating apparatus.

[0075] Referring to FIG. 8, a schematic cross-sectional view of an electroplating apparatus 801 according to one embodiment is shown. The plating tank 803 contains a plating solution (having the composition as provided herein) indicated at a level 805. The catholyte portion of this container is adapted to receive a substrate in the catholyte. The wafer 807 is immersed in the plating solution and is held by a clam-shell substrate holder 809 mounted on a rotatable spindle 811 that allows rotation of the clam-shell substrate holder 809, for example, together with the wafer 807. A general description of a clam-shell type plating apparatus having aspects suitable for use in the present invention is described in detail in U.S. Patent No. 6,156,167 to Patton and U.S. Patent No. 6,800,187 to Reid, which are hereby incorporated by reference in their entirety.

[0076] The anode 813 is disposed below the wafer inside the plating bath 803 and is separated from the wafer area by membranes 815, preferably ion-selective membranes. For example, a Nafion® cationic exchange membrane (CEM) may be used. The area below the anode membrane is often referred to as the "anode chamber". The ion-selective anode membrane 815 allows ion transfer between the anode and cathode areas of the plating cell, while preventing particles generated at the anode from entering the vicinity of the wafer and contaminating the wafer. The anode membrane is also useful for redistributing the flow of current during plating, thereby improving plating uniformity. A detailed description of suitable anode membranes is provided in U.S. Patent Nos. 6,126,798 and 6,569,299, both of which are hereby incorporated by reference in their entirety. Ion-exchange membranes such as cation-exchange membranes are particularly suitable for these applications. These membranes are typically made from ionomer materials such as perfluorinated copolymers containing sulfonic acid groups (e.g., Nafion®), sulfonated polyimides, and other materials known to those skilled in the art suitable for cation exchange. Selected examples of suitable Nafion® membranes include the N324 membrane and the N424 membrane available from Dupont de Nemours Co.

[0077] During plating, ions obtained from the plating solution deposit on the substrate. Metal ions must diffuse through the diffusion boundary layer and into the TSV holes or other features. A typical method of assisting diffusion is by the convective flow of the electroplating solution supplied by the pump 817. Additionally, wafer rotation may be used, not only with a vibration stirring member or a sonic stirring member. For example, the vibration transducer 808 may be attached to the clam shell substrate holder 809.

[0078] Pump 817 continuously supplies the plating solution to the plating bath 803. Generally, the plating solution flows upward through the anode membrane 815 and the diffusion plate 819 to the center of the wafer 807, and then radially outward across the entire surface of the wafer 807. Additionally, the plating solution may be provided from the side of the plating bath 803 into the anode region of the bath. The plating solution then overflows from the plating bath 803 and flows into the overflow reservoir 821. The plating solution is then filtered (not shown) and returned to the pump 817 to complete the recirculation of the plating solution. In certain plating cell configurations, a conservative permeable or ion-selective membrane is used to circulate a separate electrolyte through a portion of the plating cell that includes the anode while preventing mixing with the main plating solution.

[0079] The reference electrode 831 is located outside the plating bath 803 within a separate chamber 833, which is replenished by overflow from the main plating bath 803. Alternatively, in some embodiments, the reference electrode is positioned as close as possible to the substrate surface, and the reference electrode chamber is connected to the side or directly beneath the wafer substrate via a capillary tube or by another means. In some of the preferred embodiments, the apparatus further includes a contact sensing lead wire that connects to the periphery of the wafer and is configured to sense the potential of the metal seed layer at the periphery of the wafer without carrying any current to the wafer.

[0080] The reference electrode 831 is typically employed when it is desirable to electroplate at a controlled potential. The reference electrode 831 may be one of various types commonly used, such as mercury / mercurous sulfate, silver chloride, saturated calomel, or copper metal. The contact sensing lead wire in direct contact with the wafer 807 may, in some embodiments, be used in addition to the reference electrode for more accurate potential measurements (not shown).

[0081] Using a DC power supply 835, the flow of current to the wafer 807 can be controlled. The power supply 835 has a negative output lead wire 839 that is electrically connected to the wafer 807 through one or more slip rings, brushes, and contacts (not shown). The positive output lead wire 841 of the power supply 835 is electrically connected to the anode 813 located within the plating bath 803. The power supply 835, the reference electrode 831, and a contact sensing lead wire (not shown) can be connected to a system controller 847, thereby enabling modulation of the current and potential provided to the elements of the electroplating cell, among other things. For example, the controller may be configured to electroplate in a potential-controlled current-controlled manner. The controller may include program instructions that not only specify the levels of current and voltage that need to be applied to the various elements of the plating cell, but also the times at which these levels need to be changed. When applying a forward current, the power supply 835 biases the wafer 807 to have a negative potential with respect to the anode 813. As a result, current flows from the anode 813 to the wafer 807, and electrochemical reduction (e.g., Cu 2+ + 2e - = Cu 0 ) occurs on the surface of the wafer (cathode), and as a result, a conductive layer (e.g., copper) is deposited on the surface of the wafer. The inert anode 814 may be installed below the wafer 807 inside the plating bath 803 and separated from the wafer area by a membrane 815.

[0082] The apparatus may also include a heater 845 for maintaining the temperature of the plating solution at a specific level. The plating solution may be used to transfer heat to the other elements of the plating bath. For example, when loading the wafer 807 into the plating bath, the heater 845 and the pump 817 may be turned on and the plating solution may be circulated through the electroplating apparatus 801 until the temperature of the entire apparatus becomes substantially uniform. In one embodiment, the heater is connected to the system controller 847. The system controller 847 may be connected to a thermocouple to receive feedback on the temperature of the plating solution inside the electroplating apparatus and determine the need for additional heating.

[0083] The controller typically includes one or more storage devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc. In certain embodiments, the controller controls all of the activities of the plating apparatus. A non-transitory machine-readable medium containing instructions for controlling the processing operations according to this embodiment may be connected to the system controller.

[0084] Typically, there is a user interface associated with the controller 847. The user interface may include a display screen, a graphical software display of the apparatus and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc. The computer program code for controlling the plating process can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. The processor executes the compiled object code or script to perform the tasks identified by the program. An example of a plating apparatus that may be used according to the embodiments herein is the Lam Research Saber tool. Electroplating can be performed among the components forming a larger electroplating apparatus.

[0085] FIG. 9 shows a schematic top view of an example of an electrodeposition apparatus. The electrodeposition apparatus 900 can include three separate electroplating modules 902, 904, and 906. The electrodeposition apparatus 900 can also include three separate modules 912, 914, and 916 configured for various processing operations. For example, in some embodiments, one or more of modules 912, 914, and 916 can be spin rinse drying (SRD) modules. In other embodiments, one or more of modules 912, 914, and 916 can be post - electrofill modules (PEMs), each configured to perform functions such as edge bezel removal, backside etching, and pickling of the substrate after processing the substrate by one of electroplating modules 902, 904, and 906.

[0086] The electrodeposition apparatus 900 includes a central electrodeposition chamber 924. The central electrodeposition chamber 924 is a chamber that holds the chemical solution used as the electroplating solution within electroplating modules 902, 904, and 906. The electrodeposition apparatus 900 also includes a dosing system 926 that can store and deliver additives for the electroplating solution. The chemical dilution module 922 can store and mix the chemicals to be used as the etching solution. The filtration and pumping unit 928 filters the electroplating solution for the central electrodeposition chamber 924 and pumps it into the electroplating modules.

[0087] The system controller 930 provides the electronic control and interface control required to operate the electrodeposition apparatus 900. The system controller 930 (which can include one or more physical controllers and logical controllers) controls some or all of the characteristics of the electroplating apparatus 900.

[0088] Signals for monitoring the process may be provided from various process tool sensors through the analog and / or digital input connections of the system controller 930. Signals for controlling the process may be output onto the analog and digital output connections of the process tool. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, optical position sensors, and the like. Processing conditions may be maintained using appropriately programmed feedback and control algorithms along with the data obtained from these sensors.

[0089] The hand-off tool 940 may select a substrate from a substrate cassette such as cassette 942 or cassette 944. Cassette 942 or 944 may be a FOUP (front opening unified pod). A FOUP is a sealed box designed to securely and safely hold substrates in a controlled environment and allow the substrates to be removed for processing or measurement by a tool equipped with a compatible load port and robotic handling system. The hand-off tool 940 may hold the substrate using a vacuum fixture or some other attachment mechanism.

[0090] The hand-off tool 940 may interface with a wafer handling station 932, a cassette 942 or 944, a transfer station 950, or an exposure apparatus 948. From the transfer station 950, the hand-off tool 946 may access the substrate. The transfer station 950 may be in a slot or position where the hand-off tools 940 and 946 may pass the substrate without passing through the exposure apparatus 948. However, in some embodiments, the hand-off tool 946 may align the substrate properly in a straight line on the hand-off tool 946 to ensure accurate delivery to the electroplating module, and the hand-off tool 946 may align the substrate with the exposure apparatus 948. The hand-off tool 946 may also deliver the substrate to one of the electroplating modules 902, 904, or 906, or to one of the three separate modules 912, 914, and 916 configured for various processing operations.

[0091] An example of a processing operation according to the method described above proceeds as follows. That is, (1) deposit copper or other material on the substrate within the electroplating module 904, (2) rinse and dry the substrate within the SRD in module 912, and (3) perform edge bezel removal within module 914.

[0092] An apparatus configured to effectively circulate the substrate through successive plating, rinsing, drying, and PEM processing operations may be useful to implement for use in a manufacturing environment. To achieve this, module 912 may be configured as a spin rinse dryer and an edge bezel removal chamber. When using such a module 912, it is only necessary to transfer the substrate between the electroplating module 904 and module 912 for copper plating and EBR operations. In some embodiments, the method described herein is implemented within a system comprising an electroplating apparatus and a stepper.

[0093] An alternative embodiment of the electrodeposition apparatus 1000 is schematically illustrated in FIG. 10. In this embodiment, the electrodeposition apparatus 1000 has a pair of electroplating cells 1007 each containing an electrodeposition bath in a paired or multiple “duet” configuration. In addition to electrodeposition itself, the electrodeposition apparatus 1000 may perform a variety of other electrodeposition-related processes and sub-steps, such as spin-rinsing, spin-drying, wet etching of metals and silicon, electroless deposition, pre-wetting and pre-chemical treatment, reduction, annealing, electrolytic etching and / or electrolytic polishing, photoresist stripping, and surface pre-activation. FIG. 10 schematically shows the electrodeposition apparatus 1000 as viewed from below to above, revealing only a single level or “floor” in the figure, but those skilled in the art should readily understand that such an apparatus, such as the Lam Sabre (trademark) 3D tool, may potentially have two or more “stacked” levels on top of each other, each having the same type or different types of processing stations.

[0094] Referring again to FIG. 10, the substrate 1006 to be electroplated is generally supplied to the electroplating apparatus 1000 through the front-end loading FOUP 1001. In this example, the substrate 1006 driven in multiple dimensions by the spindle 1003 is carried from the FOUP to the main substrate processing area of the electroplating apparatus 1000 via the front-end robot 1002 which can move and store the substrate 1006 from one station to another available station. In this example, two front-end accessible stations 1004 and also two front-end accessible stations 1008 are shown. The front-end accessible stations 1004 and 1008 may include, for example, a pre-treatment station and a spin rinse drying (SRD) station. The lateral movement of the front-end robot 1002 from side to side is achieved using the robot stack 1002a. Each of the substrates 1006 may be held by a cup / cone assembly (not shown) driven by a spindle 1003 connected to a motor (not shown), and the motor may be attached to the mounting bracket 1009. Also shown in this example are four “duets” of the electroplating cells 1007, for a total of eight electroplating cells 1007. A system controller (not shown) may be coupled to the electroplating apparatus 1000 to control some or all of the properties of the electroplating apparatus 1000. The system controller may be programmed or otherwise configured to execute instructions according to the processes already described herein.

[0095] System controller In some implementations, the controller may be part of a system that may be part of the above examples. Such a system may comprise semiconductor processing equipment including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specialized processing components (such as wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing a semiconductor wafer or substrate. The electronics may sometimes be referred to as a "controller" that may control various components or subsections of one or more systems. Depending on the processing requirements and / or the type of system, the controller may be programmed to control the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, output settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer into and out of tools and other transfer tools, and / or any of the processes disclosed herein including load locks connected to or interfacing with the specialized system.

[0096] Generally, a controller may be defined as an electronic circuit having various integrated circuits, logic circuits, memories, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. The integrated circuit may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions transmitted to the controller in the form of various individual settings (or program files) that define operating parameters for performing specific processing on a semiconductor wafer, for a semiconductor wafer, or for a system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to achieve one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon oxide, surfaces, circuits, and / or dies of a wafer.

[0097] The controller may be part of a computer integrated with, coupled to, networked to the system in some other way, or a combination thereof, or may be coupled to the computer. For example, the controller may be in the “cloud” or may be all or part of the host computer system of a semiconductor factory, thereby enabling remote access to wafer processing. The computer may monitor the current progress of the fabrication operation, examine the history of past fabrication operations, enable remote access to the system to examine trends or performance metrics from multiple fabrication operations, change the parameters of the current process, set the process steps following the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide a processing recipe to the system via a network that may include a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings, and the parameters and / or settings are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by comprising one or more separate controllers networked together operating towards a common purpose, such as the processing and control described herein. An example of such a distributed controller for such a purpose is one or more integrated circuits on a chamber in communication with one or more remotely located integrated circuits that are combined (e.g., at the platform level or as part of a remote computer) to control the processing on the chamber.

[0098] Without limitation, an exemplary system may include a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0099] As noted above, depending on one or more processing steps to be performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, neighboring tools, adjacent tools, tools located throughout the factory, the main computer, another controller, or tools used in material handling to transport the wafer container between the location of the tool and / or the load port within the semiconductor manufacturing facility.

[0100] FIG. 11 depicts a simplified cross-sectional view of an electroplating apparatus. The apparatus includes an electroplating cell 1101, and a substrate 1102 is positioned within a substrate holder 1103. The substrate holder 1103, often called a cup, may support the substrate 1102 around its periphery. An anode 1104 is positioned near the bottom of the electroplating cell 1101. The anode 1104 is separated from the substrate 1102 by a membrane 1105 supported by a membrane frame 1106. The membrane frame 1106 may be referred to as an anode chamber membrane frame since it defines the top of the anode chamber that houses the anode. Further, the anode 1104 is separated from the substrate 1102 by an ion-resistive element 1107. The ion-resistive element 1107 includes an opening that allows an electrolyte to move through the ion-resistive element 1107 and impinge on the substrate 1102. A front insert 1108 is positioned above the ion-resistive element 1107 and closest to the periphery of the substrate 1102. The front insert 1108 may be annular as shown and need not be azimuthally uniform. The front insert 1108 may also be referred to as a direct and alternating current limiting ring.

[0101] The anode chamber 1112 is below the membrane 1105 and where the anode 1104 is located. The ion - resistant element manifold 1111 is above the membrane 1105 and below the ion - resistant element 1107. The inlet 1116, which may be connected to the water injection groove 1140, delivers the catholyte to the ion - resistant element manifold 1111 and may act to inject water into the membrane 1105 during electroplating. In this example, the inlet 1116 and the water injection groove 1140 are supplied by the electrolyte passing through the catholyte inlet 1118. The AC / DC manifold 1110 is above the ion - resistant element 1107 and below the substrate 1102. The height of the AC / DC manifold is considered to be the distance between the plane of the substrate 1102 and the ion - resistant element 1107 (excluding the rib 1115 on the upper surface of the ion - resistant element 1107 if present). In some cases, the AC / DC manifold may have a height between about 1 mm and 4 mm, or between about 0.5 mm and 15 mm. The two side surfaces of the AC / DC manifold 1110 are defined by the front insert 1108 that acts to enclose the AC / DC flowing electrolyte inside the AC / DC manifold 1110. The side inlet 1113 leading to the AC / DC manifold 1110 is provided azimuthally opposite to the side outlet 1114 leading to the AC / DC manifold 1110. At least a part may form the side inlet 1113 and the side outlet 1114 by the front insert 1108. As indicated by the arrows in FIG. 11, the electrolyte enters the AC / DC manifold 1110 from the catholyte inlet 1118 through the side inlet 1113 and moves out of the side outlet 1114. Furthermore, the electrolyte may enter the ion - resistant element manifold 1111 through one or more inlets leading to the ion - resistant element manifold 1111 (e.g., inlets in the water injection groove 1140 and / or other inlets), enter the AC / DC manifold 1110 through the openings in the ion - resistant element 1107, and move out of the side outlet 1114. After passing through the side outlet 1114, the electrolyte overflows over the weir wall 1109. The electrolyte can be recovered and reused.

[0102] In some embodiments, the ionically resistive element 1107 approximates a nearly constant and uniform current source closest to the substrate (cathode), and thus may be referred to in some situations as a high resistance virtual anode (HRVA) or a channeled ionically resistive element (CIRP). Typically, the ionically resistive element 1107 is placed very close to the wafer. In contrast, an anode that is also very close to the substrate has a significantly lower tendency to supply a nearly constant current to the wafer, but merely supports the equipotential surface at the anode metal surface, thereby allowing the current to be maximized when the net resistance from the anode surface to the end (e.g., to the surrounding contacts on the wafer) is lower. For this reason, the ionically resistive element 1107 is referred to as a high resistance virtual anode (HRVA), which does not imply that the ionically resistive element 1107 and the high resistance virtual anode (HRVA) are electrochemically interchangeable. Under certain operating conditions, the ionically resistive element 1107 approximates a virtual uniform current source more closely and may be more appropriately referred to as a virtual uniform current source, and a nearly constant current is supplied from the entire upper surface of the ionically resistive element 1107.

[0103] The ion - resistant element 1107, although not in all but in many implementation forms, is spatially and ionically separated from each other and includes micro - sized through - holes (typically less than 0.04 inches) that do not form interconnect channels inside the body of the ion - resistant element. Such through - holes are often referred to as non - communicating through - holes. Such through - holes typically extend vertically, although not necessarily, and often in one direction, to the plating surface of the wafer (in some embodiments, the non - communicating through - holes are angled with respect to the wafer generally parallel to the front surface of the ion - resistant element). The through - holes are often parallel to each other. The through - holes are often arranged in a square array. When not, the layout is a staggered spiral pattern. These through - holes reconstruct both the flow of ionic current parallel to the middle surface and (in some cases) the flow of fluid, straightening the paths of both the current flow and the fluid flow towards the wafer surface, so they are different from a 3D porous network where channels extend in three dimensions to form an interconnected pore structure. However, in some embodiments, such a porous plate having a network of interconnected pores may be used as the ion - resistant element. When the distance from the top surface of the plate to the wafer is short (e.g., about 1 / 10 of the size of the wafer radius, e.g., a gap of less than about 5 mm), the divergence of both the current flow and the fluid flow is locally limited, partitioned, and aligned with the ion - resistant element channels.

[0104] One example of an ion - resistant element 1107 is a disk made of an ionically and electrically resistive solid non - porous dielectric material. The material is also chemically stable in the plating solution used. In certain cases, the ion - resistant element 1107 has between about 6,000 and 12,000 non - communicating through - holes and is made of a ceramic material (e.g., aluminum oxide, stannic oxide, titanium oxide, or a mixture of metal oxides) or a plastic material (e.g., polyethylene, polypropylene, polyvinylidene difluoride (PVDF), polytetrafluoroethylene, polysulfone, polyvinyl chloride (PVC), polycarbonate, etc.). The ion - resistant element 1107, in many embodiments, has a spread that is substantially the same as that of the wafer (e.g., when used with a 300 mm wafer, the ion - resistant element 1107 has a diameter of about 300 mm) and is positioned very close to the wafer, for example, directly below the wafer in an electroplating apparatus where the wafer surface faces downwards. Preferably, the plating surface of the wafer is within about 10 mm, more preferably within about 5 mm, of the closest ion - resistant element surface. To achieve this, the top surface of the ion - resistant element 1107 may be flat or substantially flat. In many cases, both the top surface and the bottom surface of the ion - resistant element 1107 are flat or substantially flat. However, in some embodiments, the top surface of the ion - resistant element 1107 includes a series of linear ribs as further described below.

[0105] As described above, the total ionic resistance and the total flow resistance of the plate 1107 depend on both the thickness of the plate, and the total porosity of the holes (the ratio of the area available for flow through the plate) and the size / diameter of the holes. A less porous plate has a faster collision flow rate and a greater ionic resistance. When comparing plates with the same porosity, a plate with smaller diameter 1D holes (and thus more 1D holes) acts as a point current source that can spread over a greater portion of the same gap, and also has more individual current sources with a higher total pressure drop (high viscosity flow resistance), resulting in a finer and more uniform current distribution on the wafer.

[0106] In some cases, about 1% to 10% of the ion - resistant element 1107 is an open area through which ion current can flow (and through which electrolyte can pass if there are no other elements obstructing the opening). In certain embodiments, about 2% to 5% of the ion - resistant element 1107 is an open area. As a specific example, the open area of the ion - resistant element 1107 is about 3.2%, and the effective total open cross - sectional area is about 23 cm 2 ². In some embodiments, the diameter of the non - through holes formed within the ion - resistant element 1107 is from about 0.01 inch to 0.08 inch. In some cases, the diameter of the holes is between about 0.02 inch and 0.03 inch, or between about 0.03 inch and 0.06 inch. In various embodiments, the holes have a diameter of at most about 0.2 times the gap distance between the ion - resistant element 1107 and the wafer. The cross - section of the holes is generally circular, but it need not be. Further, for ease of construction, all the holes within the ion - resistant element 1107 may have the same diameter. However, it is not necessary, and the individual size and local density of the holes may vary across the surface of the ion - resistant element when specific requirements dictate.

[0107] The ion-resistive element 1107 shown in FIG. 11 includes a series of linear ribs 1115 that extend into / out of the page. The ribs 1115 may be referred to as protrusions. The ribs 1115 are positioned on the uppermost surface of the ion-resistive element 1107 and in many cases are oriented such that the length of the rib (e.g., the longest dimension of the rib) is perpendicular to the direction of the AC flowing electrolyte. In certain embodiments, the ribs 1115 may be oriented such that their length is parallel to the direction of the AC flowing electrolyte. The ribs 1115 affect the fluid flow and current distribution within the AC manifold 1110. In an example, the AC of the electrolyte is mostly restricted to the region above the uppermost surface of the ribs 1115, creating a high-speed AC of the electrolyte within this region. In the area between adjacent ribs 1115, the current delivered upward through the ion-resistive element 1107 redistributes and becomes more uniform before being delivered to the substrate surface.

[0108] In FIG. 11, the direction of the direct and alternating current electrolyte is from left to right (e.g., from the side inlet 1113 to the side outlet 1114), and the rib 1115 is oriented such that the length of the rib 1115 extends into / out of the page. In certain embodiments, the rib 1115 may have a width between about 0.5 mm and 1.5 mm, or between about 0.25 mm and 10 mm (measured left to right in FIG. 11). The rib 1115 may have a height between about 1.5 mm and 3.0 mm, or between about 0.25 mm and 7.0 mm (measured top to bottom in FIG. 11). The rib 1115 may have a height:width aspect ratio (height / width) between about 5 / 1 and 2 / 1, or between about 7 / 1 and 1 / 7. The rib 1115 may have a pitch between about 10 mm and 30 mm, or between about 5 mm and 150 mm. The rib 1115 may have a variable length that extends beyond the surface of the ion resistance element 1107 (measured into / out of the page of FIG. 11). The distance between the upper surface of the rib 1115 and the surface of the substrate 1102 may be between about 1 mm and 4 mm, or between about 0.5 mm and 15 mm. The rib 1115 may be provided across the entire area having approximately the same extent as the substrate, as shown in FIG. 11. The channels / openings within the ion resistance element 1107 may be positioned between adjacent ribs 1115, or may extend through the ribs 1115 (in other words, the ribs 1115 may or may not be channeled). In some other embodiments, the ion resistance element 1107 may have a flat (e.g., rib-free) upper surface. The electroplating apparatus shown in FIG. 11, including the ion resistance element with ribs thereon, is further discussed in U.S. Patent No. 9,523,155, entitled "ENHANCEMENT OF ELECTROLYTE HYDRODYNAMICS FOR EFFICIENT MASS TRANSFER DURING ELECTROPLATING", which is hereby incorporated by reference in its entirety.

[0109] The device may include various additional elements when required for a particular application. In some cases, an edge flow element may be provided within the AC / DC manifold, closest to the perimeter of the substrate. The edge flow element may be shaped and positioned to promote a high degree of electrolyte flow (e.g., AC / DC) near the edge of the substrate. The edge flow element may be annular or arcuate in some embodiments, and may be azimuthally uniform or non-uniform. The edge flow element is further discussed in U.S. Patent Application Publication No. 14 / 924,124, entitled "EDGE FLOW ELEMENT FOR ELECTROPLATING APPARATUS", filed on October 27, 2015, which is hereby incorporated by reference in its entirety.

[0110] In some instances, the apparatus may include a sealing member for temporarily sealing the AC / DC manifold. The sealing member may be annular or arcuate and may be positioned closest to the edge of the AC / DC manifold. The annular sealing member may seal the entire AC / DC manifold, while the arcuate sealing member may seal a portion of the AC / DC manifold (in some instances, leaving the side outlet open). During electroplating, the sealing member may repeatedly engage and seal the AC / DC manifold and disengage to release the seal. The sealing member may be engaged and disengaged by moving a substrate holder, an ion resistive element, a front insert, or another portion of the apparatus that engages the sealing member. The sealing member, and the method of modulating the AC / DC, are further discussed in U.S. Patent Application Publication No. 15 / 225,716, filed Aug. 1, 2016, entitled "DYNAMIC MODULATION OF CROSS FLOW MANIFOLD DURING ELECTROPLATING," and U.S. Patent Application Publication No. 15 / 161,081, filed May 20, 2016, entitled "DYNAMIC MODULATION OF CROSS FLOW MANIFOLD DURING ELECTROPLATING," each of which is hereby incorporated by reference in its entirety.

[0111] In various embodiments, one or more electrolyte jets may be provided to deliver additional electrolyte above the ion - resistant element. The electrolyte jets may deliver electrolyte closest to the perimeter of the substrate, or closer to the center of the substrate, or both. The electrolyte jets may be oriented at any position and may deliver direct or alternating flowing electrolyte, impinging electrolyte, or combinations thereof. The electrolyte jets are further discussed in U.S. Patent Application Publication No. 15 / 455,011, filed Mar. 9, 2017, titled "ELECTROPLATING APPARATUS AND METHODS UTILIZING INDEPENDENT CONTROL OF IMPINGING ELECTROLYTE", which is hereby incorporated by reference in its entirety.

[0112] Conclusion Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The embodiments disclosed herein may be practiced without some or all of these specific details. In other instances, well - known processing operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. Further, while the disclosed embodiments are described in relation to specific embodiments, it is to be understood that the specific embodiments are not intended to limit the disclosed embodiments. Note that there are many alternative ways to implement the processes, stems, and apparatuses of the present embodiments. Therefore, the present embodiments should be considered illustrative and not restrictive, and the embodiments should not be limited to the details shown herein. This disclosure includes the following application examples. [Application Example 1] A method for electroplating a metal, comprising: contacting an electroplating solution having metal ions with a substrate, the substrate having features providing at least about 0.9% open area on a surface of the substrate; applying an electrofill current waveform to the substrate in contact with the electroplating solution, the electrofill current waveform comprising (i) a pulse having a duration from about 10 seconds to about 200 seconds and having a magnitude at least about twice the magnitude of a baseline current, and (ii) a substantially constant current stage following the pulse and having an average magnitude of the baseline current; filling at least a portion of the features with the metal; and a method comprising: [Application Example 2] The method according to Application Example 1, wherein the pulse of the electrofill current waveform comprises an initial step change increasing the magnitude of the current applied to the substrate, followed by a ramp reducing the magnitude of the current applied to the substrate. [Application Example 3] The method according to Application Example 2, wherein the duration of the ramp is at least 10 seconds. [Application Example 4] The method according to Application Example 2, wherein the ramp is a linear change between the magnitude of the current of the pulse and the magnitude of the baseline current. [Application Example 5] The method according to any one of Application Examples 1 to 4, wherein the electrofill current waveform further comprises (iii) a second substantially constant current stage having an average magnitude greater than the magnitude of the baseline current. [Application Example 6] The method according to any one of Application Examples 1 to 5, wherein the electrofill current waveform further comprises (iv) one or more additional substantially constant current stages each having an average magnitude greater than the magnitude of the baseline current. [Application Example 7] The method according to any one of Application Examples 1 to 6, wherein the electric filling current waveform further includes an induction period preceding the pulse, and during the induction period, no current is applied to the substrate, or an induction period current having an average magnitude between about 30 mA and 200 mA is applied to the substrate. [Application Example 8] The method according to any one of Application Examples 1 to 7, wherein when applied to the substrate, the baseline current creates a current density between about 0.1 mA / cm 2 and 10 mA / cm 2 on the substrate. [Application Example 9] The method according to any one of Application Examples 1 to 8, wherein the substrate is a semiconductor wafer having at least a partially fabricated integrated circuit thereon. [Application Example 10] The method according to any one of Application Examples 1 to 9, wherein the substrate is a 300 mm semiconductor wafer. [Application Example 11] The method according to any one of Application Examples 1 to 10, wherein the feature on the substrate is a silicon through via. [Application Example 12] The method according to Application Example 11, wherein the silicon through via has an opening width or diameter of at least about 0.1 micrometer on average on the surface of the substrate. [Application Example 13] The method according to Application Example 11, wherein the silicon through via has a depth of at least about 10 micrometers on average. [Application Example 14] The method according to Application Example 11, wherein the silicon through via has an aspect ratio of about 4 or more on average. [Application Example 15] The method according to any one of Application Examples 1 to 14, wherein the metal is copper. [Application Example 16] The method according to any one of Application Examples 1 to 15, wherein the electroplating solution includes a source of divalent copper ions. [Application Example 17] The method according to any one of Application Examples 1 to 15, wherein the electroplating solution does not contain a source of monovalent copper ions. [Application Example 18] The method according to any one of Application Examples 1 to 17, wherein the electroplating solution has a pH between about 0 and 1. [Application Example 19] The method according to any one of Application Examples 1 to 18, wherein the electroplating solution includes an accelerator and an inhibitor. [Application Example 20] The method according to Application Example 19, wherein the accelerator is SPS. [Application Example 21] A method according to any one of Application Examples 1 to 20, wherein the change in the electroplating current waveform from the pulse to the baseline current is substantially instantaneous. [Application Example 22] A method for electroplating a metal, comprising: contacting an electroplating solution having metal ions with a substrate having features; applying an electroplating current waveform to the substrate in contact with the electroplating solution, the electroplating current waveform comprising: (i) a pulse having a duration from about 10 seconds to about 200 seconds and having a magnitude at least about twice the magnitude of the baseline current, and (ii) a substantially constant current stage following the pulse and having an average magnitude of the baseline current; filling at least a portion of the features with the metal; and a method comprising the steps of: [Application Example 23] An electroplating system for electroplating a metal, comprising: an electroplating cell configured to include an anode and contain an electroplating solution having metal ions; a wafer holder configured to support a substrate inside the electroplating cell; one or more controllers, contacting the electroplating solution having the metal ions with the substrate having features, applying to the substrate in contact with the electroplating solution an electroplating current waveform comprising: (i) a pulse having a duration from about 10 seconds to about 200 seconds and having a magnitude at least about twice the magnitude of the baseline current, and (ii) a substantially constant current stage following the pulse and having an average magnitude of the baseline current; filling at least a portion of the features with the metal; and one or more controllers configured to: and an electroplating system comprising: [Application Example 24] The electroplating system according to Application Example 23, wherein the pulse of the electroplating current waveform comprises an initial stage change that increases the magnitude of the current applied to the substrate, followed by a slope that reduces the magnitude of the current applied to the substrate. [Application Example 25] The electroplating system according to Application Example 24, wherein the duration of the slope is at least 10 seconds. [Application Example 26] The electroplating system according to Application Example 24, wherein the inclined portion is a linear change between the magnitude of the current of the pulse and the magnitude of the baseline current. [Application Example 27] The electroplating system according to any one of Application Examples 23 to 26, wherein the electroplating current waveform further includes a second substantially constant current stage having an average magnitude greater than the magnitude of the baseline current. [Application Example 28] The electroplating system according to any one of Application Examples 23 to 27, wherein the electroplating current waveform further includes one or more additional substantially constant current stages each having an average magnitude greater than the magnitude of the baseline current. [Application Example 29] The electroplating system according to any one of Application Examples 23 to 28, wherein the electroplating current waveform further includes an induction period preceding the pulse, and during the induction period, no current is applied to the substrate, or an induction period current having an average magnitude between about 30 mA and 200 mA is applied to the substrate. [Application Example 30] The electroplating system according to any one of Application Examples 23 to 29, wherein when applied to the substrate, the baseline current creates a current density between about 0.1 mA / cm 2 ~10 mA / cm 2 on the substrate. [Application Example 31] The electroplating system according to any one of Application Examples 23 to 30, wherein the substrate is a semiconductor wafer having at least partially fabricated integrated circuits thereon. [Application Example 32] The electroplating system according to any one of Application Examples 23 to 31, wherein the feature on the substrate is a silicon through via. [Application Example 33] The electroplating system according to Application Example 32, wherein the silicon through via has an average opening width or diameter of at least about 0.1 micrometer on the surface of the substrate. [Application Example 34] The electroplating system according to Application Example 32, wherein the silicon through via has an average depth of at least about 10 micrometers. [Application Example 35] An electroplating system according to Application Example 32, wherein the silicon through via has an aspect ratio of about 4 or more on average. [Application Example 36] An electroplating system according to any one of Application Examples 23 to 35, wherein the metal is copper. [Application Example 37] An electroplating system according to any one of Application Examples 23 to 36, wherein the electroplating solution includes a source of divalent copper ions. [Application Example 38] An electroplating system according to any one of Application Examples 23 to 36, wherein the electroplating solution does not contain a source of monovalent copper ions. [Application Example 39] An electroplating system according to any one of Application Examples 23 to 38, wherein the electroplating solution has a pH of about 0 to 1. [Application Example 40] An electroplating system according to any one of Application Examples 23 to 39, wherein the change in the electrofill current waveform from the pulse to the baseline current is substantially instantaneous.

Claims

1. A method for electroplating a metal, comprising: contacting an electroplating solution having metal ions with a substrate, wherein the substrate has a feature that provides at least 0.9% open area on a surface of the substrate; applying an electrofill current waveform to the substrate in contact with the electroplating solution, the electrofill current waveform comprising: (i) a pulse having a duration from 10 seconds to 200 seconds and having a magnitude at least twice the magnitude of a baseline current, and (ii) a constant current stage following the pulse and having an average magnitude of the baseline current; filling at least a portion of the feature with the metal; and the feature of the substrate is a silicon through via, a concave feature, or a via. A method.

2. The method according to claim 1, wherein the pulse of the electrofill current waveform comprises an initial stage change that increases the magnitude of the current applied to the substrate, followed by a slope that reduces the magnitude of the current applied to the substrate.

3. The method according to claim 2, wherein the duration of the slope is at least 10 seconds.

4. The method according to claim 2, wherein the slope is a linear change between the magnitude of the current of the pulse and the magnitude of the baseline current.

5. The method according to any one of claims 1 to 4, wherein the electrofill current waveform further comprises (iii) a second constant current stage having an average magnitude greater than the magnitude of the baseline current.

6. The method according to any one of claims 1 to 5, wherein the electrofill current waveform further comprises (iv) one or more additional constant current stages each having an average magnitude greater than the magnitude of the baseline current.

7. The method according to any one of claims 1 to 6, wherein the electrofill current waveform further comprises an induction period preceding the pulse, during which no current is applied to the substrate or an induction period current having an average magnitude between 30 mA and 200 mA is applied to the substrate.

8. The method according to any one of claims 1 to 7, wherein when applying to the substrate, the baseline current creates a current density between 0.1 mA / cm 2 and 10 mA / cm 2 on the substrate.

9. The method according to any one of claims 1 to 8, wherein the substrate is a semiconductor wafer having at least partially fabricated integrated circuits thereon.

10. The method according to any one of claims 1 to 9, wherein the substrate is a 300 mm semiconductor wafer.

11. The method according to any one of claims 1 to 10, wherein the feature on the substrate is a silicon through via.

12. The method according to claim 11, wherein the silicon through via has an opening width or diameter of at least 0.1 micrometer on average on the surface of the substrate.

13. The method according to claim 11, wherein the silicon through via has a depth of at least 10 micrometers on average.

14. The method according to claim 11, wherein the silicon through via has an aspect ratio of 4 or more on average.

15. The method according to any one of claims 1 to 14, wherein the metal is copper.

16. The method according to any one of claims 1 to 15, wherein the electroplating solution comprises a source of divalent copper ions.

17. The method according to any one of claims 1 to 15, wherein the electroplating solution does not contain a source of monovalent copper ions.

18. The method according to any one of claims 1 to 17, wherein the electroplating solution has a pH of 0 to 1.

19. The method according to any one of claims 1 to 18, wherein the electroplating solution comprises an accelerator and an inhibitor.

20. The method according to claim 19, wherein the accelerator is SPS.

21. The method according to any one of claims 1 to 20, wherein the change in the electrofill current waveform from the pulse to the baseline current is immediate.

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