Trigger generating circuit and waveform measuring device

Abstract

To provide a trigger generation circuit and a waveform measurement device, which may enhance convenience of waveform measurement.SOLUTION: A trigger generation circuit 20 comprises: a trigger signal generation unit configured to output a trigger signal TR for allowing a signal progressing circuit 10 to acquire an input signal IN; and a trigger counter 28 configured to output the number of outputs of the trigger signal TR.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a trigger generation circuit and a waveform measurement device.

Background Art

[0002] Conventionally, a trigger generation circuit of a digital oscilloscope has been known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a waveform measurement device such as a digital oscilloscope, depending on the state of the processor when a trigger for notifying the timing of acquiring a signal waveform is output, the signal waveform may not be acquired even though the trigger is output. When there is no acquisition result of the signal waveform, the user of the waveform measurement device cannot confirm whether the signal waveform was not acquired because the trigger was not output, or whether the signal waveform was not acquired even though the trigger was output.

[0005] If the user can recognize that the signal waveform was not acquired even though the trigger was output, the user can change the settings related to the acquisition of the signal waveform. By appropriately changing the settings, the convenience of waveform measurement is enhanced.

[0006] The present disclosure has been made in view of the above points, and an object thereof is to provide a trigger generation circuit and a waveform measurement device that can enhance the convenience of waveform measurement.

Means for Solving the Problems

[0007] The trigger generation circuit according to some embodiments includes a trigger signal generation unit that outputs a trigger signal for causing a signal processing circuit to acquire an input signal, and a trigger counter that outputs the number of times the trigger signal has been output. By doing so, the settings of the waveform measurement device can be changed so as to reduce the number of trigger signals that are ignored by the user. As a result, the convenience for acquiring the waveform of the input signal can be enhanced.

[0008] The trigger generation circuit according to one embodiment may further include a pulse counter that counts the number of pulses included in the input signal. The pulse counter may measure the time when the pulses included in the input signal arrive. By doing so, it becomes easier for the user to recognize whether there are any missed pulses. As a result, it becomes easier for the user to determine whether to change the settings of the waveform measurement device.

[0009] In the trigger generation circuit according to one embodiment, the trigger signal generation unit may be configured to be able to acquire a setting signal that specifies the condition for outputting the trigger signal. By doing so, the settings of the trigger signal generation unit can be easily changed. As a result, the convenience for acquiring the waveform of the input signal can be enhanced.

[0010] The waveform measurement device according to some embodiments includes a trigger generation circuit, a signal processing circuit, and a display device. The trigger generation circuit has a trigger signal generation unit that outputs a trigger signal for specifying the timing at which the signal processing circuit starts acquiring an input signal, and a trigger counter that outputs the number of times the trigger signal has been output. The signal processing circuit starts acquiring the input signal based on the trigger signal and processes the acquired input signal. The display device displays the number of times the trigger signal has been output from the trigger generation circuit and the number of times the input signal has been acquired by the signal processing circuit. By doing so, the settings of the waveform measurement device can be changed so as to reduce the number of trigger signals that are ignored by the user. As a result, the convenience for acquiring the waveform of the input signal can be enhanced.

Advantages of the Invention

[0011] According to the trigger generation circuit and the waveform measurement device according to the present disclosure, the convenience of waveform measurement can be enhanced.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0013] Embodiments according to the present disclosure will be described while contrasting with comparative examples.

[0014] (Comparative Example) As shown in FIG. 1, a waveform measurement device 90 according to a comparative example includes a signal processing circuit 91, a trigger generation circuit 92, a storage device 93, and a display device 94.

[0015] The trigger generation circuit 92 generates a trigger signal based on the input signal and outputs it to the signal processing circuit 91. The trigger generation circuit 92 is configured to generate a timing trigger signal for causing the signal processing circuit 91 to start acquiring the input signal.

[0016] The signal processing circuit 91 acquires and analyzes the input signal. When the signal processing circuit 91 acquires a trigger signal from the trigger generation circuit 92, it starts acquiring the input signal and stores the input signal acquired over a predetermined period in the storage device 93. The signal processing circuit 91 analyzes the number of rising or falling edges of the pulses included in the signal stored in the storage device 93, or the timing at which the pulses rise and fall. The signal processing circuit 91 causes the display device 94 to display the waveform of the signal stored in the storage device 93, or causes the display device 94 to display the analysis result of the signal stored in the storage device 93.

[0017] As shown in FIG. 2, an input signal represented by IN is input to the waveform measurement device 90. The trigger generation circuit 92 generates a pulse-shaped trigger signal represented by TR. The signal processing circuit 91 starts acquiring the input signal (IN) when the pulse of the trigger signal (TR) rises. The period during which the signal processing circuit 91 acquires the input signal in response to the trigger signal is represented by AP.

[0018] When the trigger signals represented by TR1 and TR3 are generated, the period (AP) during which the signal processing circuit 91 acquires the input signal starts. The input signal acquired by the signal processing circuit 91 in response to the trigger signal (TR1) is represented by AW1. The input signal acquired by the signal processing circuit 91 in response to the trigger signal (TR3) is represented by AW2.

[0019] After the signal processing circuit 91 acquires the input signal represented by AW1, it enters a state where it cannot acquire the input signal for a predetermined period for storage, analysis, or display of the input signal. The period during which the signal processing circuit 91 is in a state where it cannot acquire the input signal is represented by DP. The trigger signal represented by TR2 is generated during the period represented by DP. The signal processing circuit 91 cannot start acquiring the input signal when the trigger signal represented by TR2 is generated. Therefore, although the trigger signal represented by TR2 is output from the trigger generation circuit 92, the input signal is not acquired in the signal processing circuit 91. The pulse represented by LW included in the input signal input during the period represented by DP is not acquired by the signal processing circuit 91.

[0020] In the waveform measurement device 90 according to the comparative example, the display device 94 displays the waveforms of the input signals represented by AW1 and AW2 or the analysis results. Therefore, although the user of the waveform measurement device 90 can recognize the fact that two input signals represented by AW1 and AW2 have been acquired, the user cannot recognize that the input signals were not acquired in response to the trigger signal represented by TR2. That is, the user cannot recognize that the trigger signal represented by TR2 has been ignored.

[0021] As described above, in the waveform measurement device 90 according to the comparative example, even if the trigger signal is ignored, the user cannot recognize it. If the user could recognize that the trigger signal has been ignored, the user could set the waveform measurement device 90 so that it is difficult for the trigger signal to be generated during the period represented by DP.

[0022] Hereinafter, a waveform measurement device 1 (see FIG. 3) that enables the user to recognize that the trigger signal has been ignored will be described.

[0023] (Configuration example of the waveform measurement device 1 according to an embodiment of the present disclosure) As shown in FIG. 3, a waveform measurement device 1 according to an embodiment includes a signal processing circuit 10, a trigger generation circuit 20, a storage device 30, and a display device 40. The trigger generation circuit 20 generates a trigger signal based on an input signal represented by IN. The signal processing circuit 10 starts acquiring the input signal based on the trigger signal output from the trigger generation circuit 20. In other words, the trigger signal specifies the timing at which the signal processing circuit 10 starts acquiring the input signal. The signal processing circuit 10 may store the acquired signal in the storage device 30. The signal processing circuit 10 may analyze the acquired signal. The signal processing circuit 10 may cause the display device 40 to display the waveform of the acquired signal. The signal processing circuit 10 may cause the display device 40 to display the analysis result of the waveform of the acquired signal. The signal processing circuit 10 may cause the display device 40 to display the number of waveforms of the acquired signal. That is, the signal processing circuit 10 may process the acquired input signal.

[0024] The trigger generation circuit 20 includes a trigger counter 28. The trigger counter 28 counts the number of times the trigger generation circuit 20 has generated a trigger signal. The trigger generation circuit 20 outputs the number of times counted by the trigger counter 28 to the signal processing circuit 10. The signal processing circuit 10 may cause a display device 40 to display the number of times the trigger signal has been generated and the number of waveforms of the signal acquired by the signal processing circuit 10.

[0025] When the number of times the trigger signal has been generated is equal to the number of waveforms of the signal acquired by the signal processing circuit 10, the waveforms of the input signal have been acquired on all occasions when the trigger signal was generated. When the number of waveforms of the signal acquired by the signal processing circuit 10 is less than the number of times the trigger signal has been generated, the signal processing circuit 10 has failed to acquire the waveform of the input signal on some of the occasions when the trigger signal was generated. That is, some of the trigger signals have been ignored.

[0026] The user of the waveform measuring device 1 can recognize whether the waveforms of the input signal have been acquired on all occasions when the trigger signal was generated by comparing the number of times the trigger signal has been generated with the number of waveforms of the signal acquired by the signal processing circuit 10. Conversely, the user of the waveform measuring device 1 can recognize that the waveforms of the input signal have not been acquired on some of the occasions when the trigger signal was generated by comparing the number of times the trigger signal has been generated with the number of waveforms of the signal acquired by the signal processing circuit 10.

[0027] Hereinafter, a configuration example of the waveform measuring device 1 will be described.

[0028] <Signal processing circuit 10> The signal processing circuit 10 is configured such that an input signal and a trigger signal are input thereto. The signal processing circuit 10 may include a signal input terminal to which the input signal is input. The signal processing circuit 10 may include a trigger input terminal to which the trigger signal is input. The signal processing circuit 10 is configured to start acquiring the waveform of the input signal when the trigger signal is input. The signal processing circuit 10 may be configured to sample the input signal for a predetermined period after starting to acquire the waveform of the input signal. The signal processing circuit 10 may be configured to be able to set the sampling rate. The signal processing circuit 10 may be configured to be able to set a predetermined period (the period for acquiring the input signal once) for sampling the input signal.

[0029] The signal processing circuit 10 may store the acquired waveform data of the input signal in a storage device 30 or the like. The waveform data is represented as a set of data of signal intensities at each time. The signal processing circuit 10 may generate an image for displaying the acquired waveform of the input signal on the display device 40 and output the image to the display device 40. The waveform image may be generated such that the horizontal axis represents time and the vertical axis represents signal intensity. The signal processing circuit 10 may analyze the acquired waveform data of the input signal and display the analysis result on the display device 40. The signal processing circuit 10 may display on the display device 40 the number of acquired waveform data of the input signal and the number of trigger signals generated by the trigger generation circuit 20. The signal processing circuit 10 may display on the display device 40 the comparison result between the number of acquired waveform data of the input signal and the number of trigger signals generated by the trigger generation circuit 20.

[0030] The signal processing circuit 10 may be configured to include a processor such as a CPU (Central Processing Unit). The signal processing circuit 10 may execute various operations such as acquisition, storage, analysis, or display of the input signal by executing a predetermined program.

[0031] The signal processing circuit 10 may be configured to be able to set its operation according to an input from a user. The signal processing circuit 10 may be configured to be able to set, for example, a predetermined period for sampling or a sampling rate, etc. The signal processing circuit 10 may be configured to be able to set a scale of time or signal intensity in an image of the waveform of the input signal to be acquired. Also, the signal processing circuit 10 may be configured to set or control the operation of the trigger generation circuit 20.

[0032] The signal processing circuit 10 may be connected to an input device in order to receive an input from a user. The signal processing circuit 10 may include an input device. The input device may include, for example, a keyboard or physical keys, or may include a touch panel or a touch sensor or a pointing device such as a mouse. The input device is not limited to these examples and may be configured to include various other devices.

[0033] <Trigger generation circuit 20> As illustrated in FIG. 4, the trigger generation circuit 20 includes an input circuit 21, comparators 22 and 23, flip - flops 24 and 25, an OR circuit 26, a delay circuit 27, and a trigger counter 28. At least some of the other components of the trigger generation circuit 20 other than the trigger counter 28 are also collectively referred to as a trigger signal generation unit. That is, the trigger generation circuit 20 may include a trigger signal generation unit and a trigger counter 28. The comparator 22 is also referred to as a first comparator. The comparator 23 is also referred to as a second comparator. The flip - flop 24 is also referred to as a first flip - flop. The flip - flop 25 is also referred to as a second flip - flop. The configuration of FIG. 4 is an example of the configuration of the trigger generation circuit 20. The trigger generation circuit 20 may be configured in various other manners.

[0034] The input circuit 21 amplifies or attenuates the input signal so as to adjust the intensity of the input signal represented by IN. The input circuit 21 may adjust the intensity of the input signal so that the maximum value of the intensity of the input signal falls within the specifications of the comparators 22 and 23.

[0035] Comparator 22 outputs the result of comparing the intensity of the input signal adjusted by input circuit 21 with the first intensity represented by L1. When the intensity of the input signal adjusted by input circuit 21 is greater than the first intensity, comparator 22 outputs a HI signal; when the intensity of the input signal adjusted by input circuit 21 is less than or equal to the first intensity, comparator 22 outputs a LO signal. The signal output by comparator 22 is represented as C1. The output signal (C1) of comparator 22 is input to the clock (CLK) of flip-flop 24.

[0036] Comparator 23 outputs the result of comparing the intensity of the input signal adjusted by input circuit 21 with the second intensity represented by L2. When the intensity of the input signal adjusted by input circuit 21 is greater than the second intensity, comparator 23 outputs a HI signal; when the intensity of the input signal adjusted by input circuit 21 is less than or equal to the second intensity, comparator 23 outputs a LO signal. The signal output by comparator 23 is represented as C2. The output signal (C2) of comparator 23 branches and is input to the clock (CLK) of flip-flop 25, delay circuit 27, and OR circuit 26.

[0037] When a rising signal is input as the clock (CLK), flip-flop 24 holds the level of the signal input to the input terminal (D1) and outputs the held signal level from the output terminal (Q1). When a falling signal is input as the clock (CLK), flip-flop 25 holds the level of the signal input to the input terminal (D2) and outputs the held signal level from the output terminal (Q2). When a falling signal is input to the set of flip-flop 24, regardless of whether the level of the signal input to the input terminal is HI or LO, the level of the signal to be held is set to HI. When a falling signal is input to the reset of flip-flops 24 and 25, regardless of whether the level of the signal input to the input terminal is HI or LO, the level of the signal to be held is set to LO.

[0038] The input terminal (D1) of the flip-flop 24 is connected to the ground terminal (LO). Therefore, the LO signal is input to the input terminal (D1) of the flip-flop 24. The clock (CLK) of the flip-flop 24 is connected to the output of the comparator 22. Therefore, the output signal (C1) of the comparator 22 is input to the clock (CLK) of the flip-flop 24. The set of the flip-flop 24 is connected to the output of the OR circuit 26. Therefore, the output signal (SET) of the OR circuit 26 is input to the set of the flip-flop 24. The reset of the flip-flop 24 is input with a reset signal (RS). The reset signal (RS) is input from the signal processing circuit 10.

[0039] The input terminal (D2) of the flip-flop 25 is connected to the output of the flip-flop 24. Therefore, the output signal (Q1) of the flip-flop 24 is input to the input terminal (D2) of the flip-flop 25. The clock (CLK) of the flip-flop 25 is connected to the output of the comparator 23. Therefore, the output signal (C2) of the comparator 23 is input to the clock (CLK) of the flip-flop 25. The reset of the flip-flop 25 is connected to the output of the delay circuit 27. The delay circuit 27 outputs a signal (C2_DL) obtained by delaying the output signal (C2) of the comparator 23. Therefore, the output signal (C2_DL) of the delay circuit 27 is input to the reset of the flip-flop 25.

[0040] The OR circuit 26 outputs the logical OR of the input signals. The OR circuit 26 outputs HI when at least one of the multiple inputs is HI, and outputs LO when all the inputs are LO. The OR circuit 26 has, as input terminals, a terminal for inputting a signal obtained by negating the reset signal (RS) (a signal obtained by inverting the logic of the reset signal (RS) with an inverter), a terminal connected to the output of the comparator 23, and a terminal connected to the output of the flip-flop 24. The OR circuit 26 outputs the logical OR of the negated reset signal (RS), the output signal (C2) of the comparator 23, and the output signal (Q1) of the flip-flop 24 as a signal represented by SET to the set of the flip-flop 24.

[0041] The trigger generation circuit 20 outputs the output signal (Q2) of the flip-flop 25 as a trigger signal (TR). The trigger counter 28 is connected to the output of the flip-flop 25 and counts the number of times the trigger signal (TR) is output (the number of times the pulse of the trigger signal rises).

[0042] With reference to the time chart illustrated in FIG. 5, the changes in the signals of each component of the trigger generation circuit 20 are described. Assume that the input signal (IN) is a signal that changes continuously as illustrated. The input signal may be a pulse signal.

[0043] At time (T1), the reset signal (RS) rises to HI. At this time, SET input to the set of the flip-flop 24 falls to LO. When SET becomes LO, the output signal (Q1) of the flip-flop 24 rises to HI. When the output signal (Q1) of the flip-flop 24 becomes HI, SET falls to LO.

[0044] At time (T2), the intensity of the input signal (IN) becomes greater than the second intensity (L2). At this time, the output signal (C2) of the comparator 23 rises to HI. Next, at time (T3), the intensity of the input signal (IN) becomes greater than the first intensity (L1). At this time, the output signal (C1) of the comparator 22 rises to HI. When the output signal (C1) of the comparator 22 rises, the flip-flop 24 enters a state where the clock (CLK) is input and holds the LO signal input to the input terminal (D1). As a result, the output signal (Q1) of the flip-flop 24 falls to LO.

[0045] At time (T4), the intensity of the input signal (IN) becomes less than the first intensity (L1). At this time, the output signal (C1) of the comparator 22 falls to LO. Next, at time (T5), the intensity of the input signal (IN) becomes less than the second intensity (L2). At this time, the output signal (C2) of the comparator 23 falls to LO. When the output signal (C2) of the comparator 23 becomes LO, SET, which is the output of the OR circuit 26, falls to LO. When SET falls, at time (T6), the output signal (Q1) of the flip-flop 24 is set to HI.

[0046] At time (T7), the intensity of the input signal (IN) becomes greater than the second intensity (L2). At this time, the output signal (C2) of the comparator 23 rises to HI. Next, at time (T8), the intensity of the input signal (IN) becomes smaller than the second intensity (L2). At this time, the output signal (C2) of the comparator 23 falls to LO. The output signal (C2) of the comparator 23 is input to the clock (CLK) of the flip-flop 25. When the output signal (C2) of the comparator 23 becomes LO, a falling signal is input to the clock (CLK) of the flip-flop 25. At this time, the flip-flop 25 holds the HI signal input from the flip-flop 24 at the input terminal (D2). As a result, the output signal (Q2) of the flip-flop 25 becomes HI. That is, the flip-flop 25 outputs a HI signal as the trigger signal (TR).

[0047] On the other hand, it falls to LO at time (T9) which is delayed by the time represented by DL, the output of the delay circuit 27. When the output of the delay circuit 27 falls, a falling signal is input to the reset of the flip-flop 25. At this time, the output signal (Q2) of the flip-flop 25 becomes LO. As a result, the trigger signal (TR) is output as a pulse signal that becomes HI only from time (T8) to time (T9).

[0048] The trigger counter 28 may count that the trigger signal (TR) has been generated when the trigger signal (TR) rises, or may count that the trigger signal (TR) has been generated when the trigger signal (TR) falls.

[0049] The trigger counter 28 may be installed inside the trigger generation circuit 20 as described above. The trigger counter 28 may be built into a trigger signal generation unit such as the flip-flop 25. By being installed inside the trigger generation circuit 20, the trigger counter 28 is less likely to be affected by factors such as delays in the wiring. As a result, the trigger counter 28 is less likely to miscount the number of times the trigger signal is generated. The trigger counter 28 may be connected between the trigger generation circuit 20 and the signal processing circuit 10 as a separate component from the trigger generation circuit 20.

[0050] As described above, the trigger generation circuit 20 may acquire a reset signal (RS) or a signal representing the first intensity (L1) and the second intensity (L2) from the signal processing circuit 10. The conditions for generating the trigger signal are controlled by the reset signal (RS) or the like. That is, the conditions under which the trigger signal generation unit of the trigger generation circuit 20 outputs the trigger signal are specified by the reset signal (RS) or the signal representing the first intensity (L1) and the second intensity (L2). The signal that specifies the conditions for outputting the trigger signal is also referred to as a setting signal. The trigger signal generation unit is configured to be able to acquire the setting signal.

[0051] <Storage device 30> The storage device 30 stores the waveform of the input signal acquired by the signal processing circuit 10. The storage device 30 may store various information used in the operation of the signal processing circuit 10 or a program for realizing the functions of the processor of the signal processing circuit 10. The storage device 30 may function as a work memory for the processor of the signal processing circuit 10. The storage device 30 may be configured to include, for example, a semiconductor memory or the like. The signal processing circuit 10 may be configured to include at least a part of the storage device 30.

[0052] <Display device 40> The display device 40 is configured to display the information output from the signal processing circuit 10. The display device 40 may display an image of the waveform of the input signal. The display device 40 may display the analysis result of the waveform of the input signal. The display device 40 may display an image for receiving an input for setting the operation of the signal processing circuit 10. The display device 40 may be configured to include various displays such as, for example, a liquid crystal display.

[0053] <Arithmetic device 50> The waveform measurement device 1 may further include an arithmetic device 50. The arithmetic device 50 may execute a part of the functions of the signal processing circuit 10. The arithmetic device 50 may be configured to set, for example, the operation of the signal processing circuit 10 or the trigger generation circuit 20. The arithmetic device 50 may set the sampling rate or a predetermined period of sampling in the signal processing circuit 10. The arithmetic device 50 may set the first intensity (L1) and the second intensity (L2) input to the trigger generation circuit 20. The arithmetic device 50 may output a reset signal (RS) input to the trigger generation circuit 20.

[0054] <Regarding the communication of each component of the waveform measurement device 1> At least a part of the components of the waveform measurement device 1 may include communication devices that communicate with each other by wire or wirelessly. The communication device may include, for example, a communication interface such as a LAN (Local Area Network) or RS-232C or RS-485. The communication device is not limited to these and may be configured to include various other communication interfaces.

[0055] (Operation example of the waveform measurement device 1) The waveform measurement device 1 according to the present embodiment generates a trigger signal in response to an input signal, and starts acquiring the waveform of the input signal by the trigger signal. The waveform measurement device 1 counts and displays the number of times the trigger signal is generated and the number of waveforms of the acquired input signal. The user can recognize whether the waveform of the input signal is acquired in response to the trigger signal or whether there is a trigger signal that has been ignored based on the number of times the trigger signal is generated and the number of waveforms of the acquired input signal.

[0056] As illustrated in FIG. 6, assume that a pulse signal is input to the waveform measuring device 1 as an input signal (IN). The trigger generation circuit 20 generates a trigger signal (TR) including the pulse signal. The trigger generation circuit 20 counts the number of times the trigger signal (TR) is generated, as represented by CT. When the trigger generation circuit 20 generates the trigger signal (TR1), it sets the count (CT) to 1. When the trigger generation circuit 20 generates the trigger signal (TR2), it sets the count (CT) to 2. When the trigger generation circuit 20 generates the trigger signal (TR3), it sets the count (CT) to 3. By doing so, the trigger generation circuit 20 can count the number of times the trigger signal is generated.

[0057] The signal processing circuit 10 starts acquiring the waveform of the input signal (IN) when the pulse of the trigger signal (TR) rises. The period during which the signal processing circuit 10 acquires the waveform of the input signal in response to the trigger signal (TR) is represented by AP. On the other hand, after the end of the period (AP) during which the signal processing circuit 10 acquires the waveform of the input signal, the signal processing circuit 10 enters a state where it cannot acquire the waveform of the input signal for a predetermined period for storing, analyzing, or displaying the waveform of the input signal. The period during which the signal processing circuit 10 is in a state where it cannot acquire the waveform of the input signal is represented by DP.

[0058] When trigger signals represented by TR1 and TR3 among the trigger signals (TR) are generated, a period (AP) during which the signal processing circuit 10 acquires the waveform of the input signal starts. The waveform of the input signal acquired by the signal processing circuit 10 in response to the trigger signal (TR1) is represented by AW1. The waveform of the input signal acquired by the signal processing circuit 10 in response to the trigger signal (TR3) is represented by AW2. On the other hand, when the trigger signal represented by TR2 is generated, the signal processing circuit 10 is in a state where it cannot acquire the waveform of the input signal. That is, the trigger signal represented by TR2 is generated during the period represented by DP. In this case, although the trigger signal represented by TR2 is output from the trigger generation circuit 20, the waveform of the input signal is not acquired in the signal processing circuit 10. As a result, the waveform of the pulse (LW) included in the input signal (IN) input during the period represented by DP is not acquired by the signal processing circuit 10.

[0059] The signal processing circuit 10 causes the display device 40 to display the acquired waveform of the input signal. By doing so, the user of the waveform measuring device 1 can recognize the fact that the waveforms of the two input signals represented by AW1 and AW2 have been acquired. Also, the signal processing circuit 10 acquires the number of times the trigger signal (TR) is generated from the trigger generation circuit 20 and causes the display device 40 to display it. By doing so, the user of the waveform measuring device 1 can recognize the number of times the trigger signal (TR) is generated. The signal processing circuit 10 may cause the display device 40 to display the number of times the trigger signal is generated together when one waveform of the input signal is acquired. When the number of times the trigger signal is generated is greater than the number of waveforms of the acquired input signal, the signal processing circuit 10 may cause the display device 40 to display that there is an ignored trigger signal. The timing for causing the display device 40 to display the number of times the trigger signal is generated may be determined as appropriate.

[0060] In the example of FIG. 6, the user of the waveform measurement device 1 can recognize that the number of waveforms of the acquired input signal is two. Also, the user can recognize that the number of times the trigger signal (TR) is generated is three. Then, the user can recognize that there are waveforms of input signals that have not been acquired in addition to the waveforms of the two input signals represented by AW1 and AW2. That is, the user can recognize that one of the trigger signals (TR) has been ignored. The user may change the settings of the signal processing circuit 10 or the trigger generation circuit 20 so as to reduce the number of trigger signals (TR) to be ignored in the measurement of signals in subsequent times. The user may change the sampling rate of the input signal in the signal processing circuit 10. The user may change the length of the period during which the input signal is acquired at one time in the signal processing circuit 10. The user may change the values of the first intensity (L1) and the second intensity (L2) used in the trigger generation circuit 20. The user may change the condition or timing for outputting the reset signal (RS) to the trigger generation circuit 20. The user may change various settings of the waveform measurement device 1 not limited to these examples.

[0061] The user may change the setting of the trigger signal generation unit of the trigger generation circuit 20 by changing the setting signal output to the signal processing circuit 10 or the arithmetic device 50. Since the trigger signal generation unit is configured to be able to acquire the setting signal, the setting of the trigger signal generation unit can be easily changed. As a result, the convenience for acquiring the waveform of the input signal can be enhanced.

[0062] As described above, according to the waveform measurement device 1 and the trigger generation circuit 20 according to the present embodiment, the user can recognize the number of times the trigger signal is generated. By doing so, the user can change the settings of the waveform measurement device 1 so as to reduce the number of trigger signals to be ignored. As a result, the convenience for acquiring the waveform of the input signal can be enhanced.

[0063] (Other Embodiments) Other embodiments of the waveform measurement device 1 will be described.

[0064] <Input of Multiple Channels> The waveform measurement device 1 may have a plurality of channels at the input terminal so that each of the plurality of input signals can be separately input. Each channel branches the signal to the signal processing circuit 10 and the trigger generation circuit 20. The trigger generation circuit 20 may have n channels at the input terminal as illustrated in FIG. 7. Each channel is represented as CH_1 to CH_n. The trigger generation circuit 20 includes input circuits 211 to 21n connected to each channel (CH_1 to CH_n). The input circuits 211 to 21n are each connected to a circuit that generates a trigger signal. The trigger generation circuit 20 may be configured to generate a trigger signal when the input signal satisfies the condition in at least one channel. The trigger generation circuit 20 may be configured to generate a trigger signal when the input signal satisfies the condition in a plurality of channels. The trigger generation circuit 20 may be configured to generate a trigger signal when the input signal satisfies the condition in all channels.

[0065] As described above, the trigger generation circuit 20 may include a trigger counter 28 inside. When the input signal is input to a plurality of channels, it may be difficult to determine whether a trigger signal has been generated. By providing the trigger counter 28 inside the trigger generation circuit 20, the trigger counter 28 is less likely to miscount the number of times the trigger signal has been generated regardless of the timing at which the trigger signal is generated.

[0066] <Pulse Counting in Trigger Generation Circuit 20> When the input signal includes a pulse signal, the signal processing circuit 10 may analyze the input signal to analyze the number of pulse signals included in the input signal, or the rising or falling time of the pulse signal. The signal processing circuit 10 may also calculate the duty ratio of the pulse signal included in the input signal.

[0067] The waveform measurement device 1 may be configured to count the number of pulse signals included in the input signal by the trigger generation circuit 20. Specifically, as illustrated in FIG. 7, the trigger generation circuit 20 may be configured to branch the input signal into an input circuit 21 and a pulse counter 29. When the trigger generation circuit 20 has a plurality of channels at the input terminal, in each channel, the trigger generation circuit 20 may be configured to branch the input signal into input circuits 211 to 21n and pulse counters 291 to 29n.

[0068] The pulse counter 29 counts the number of pulses included in the input signal input to each channel. When the trigger generation circuit 20 has four channels at the input terminal, as illustrated in FIG. 8, it is assumed that an input signal is input to each channel (CH1 to CH4). The channel represented by CH1 includes four pulses that rose at the times represented by T13, T15, T18, and T21. The channel represented by CH2 includes six pulses that rose at the times represented by T11, T15, T17, T18, T19, and T20. The channel represented by CH3 includes five pulses that rose at the times represented by T12, T14, T16, T19, and T21. The channel represented by CH4 includes six pulses that rose at the times represented by T11, T15, T18, T19, T20, and T21.

[0069] The pulse counter 29 counts the number of pulses in each channel. The trigger generation circuit 20 outputs the number of pulses counted by the pulse counter 29 to the signal processing circuit 10 or the arithmetic unit 50. The signal processing circuit 10 or the arithmetic unit 50 may cause the display device 40 to display the number of pulses counted by the pulse counter 29.

[0070] Here, assume that the waveforms of the input signals acquired by the signal processing circuit 10 are two waveforms represented by AW1 and AW2. At this time, the waveforms of the pulses rising at the times represented by T17 and T18 are not acquired by the signal processing circuit 10. When the number of pulses included in the waveform of the input signal acquired by the signal processing circuit 10 is less than the number of pulses counted by the pulse counter 29, the user can recognize that there are missed pulses. Conversely, when the number of pulses included in the waveform of the input signal acquired by the signal processing circuit 10 matches the number of pulses counted by the pulse counter 29, the user can recognize that there are no missed pulses. Even when the number of waveforms of the acquired input signals is less than the number of trigger signals, if there are no missed pulses, the user may leave the settings of the waveform measuring device 1 as they are. In other words, the user may change the settings of the waveform measuring device 1 when there are missed pulses.

[0071] As described above, by counting pulses with the pulse counter 29, it becomes easier for the user to recognize whether there are missed pulses. As a result, it becomes easier for the user to determine whether to change the settings of the waveform measuring device 1.

[0072] The pulse counter 29 may be configured to measure the time when a pulse arrives. By measuring the time when a pulse arrives, it becomes easier for the user to recognize whether a pulse has arrived outside the period during which the waveform of the input signal is acquired by the signal processing circuit 10. As a result, it becomes easier for the user to determine whether to change the settings of the waveform measuring device 1.

[0073] Although the embodiments according to the present disclosure have been described based on the drawings and examples, it should be noted that those skilled in the art can make various modifications or alterations based on the present disclosure. Therefore, it should be noted that these modifications or alterations are included in the scope of the present disclosure. For example, the functions included in each component can be rearranged so as not to be logically contradictory, and a plurality of components can be combined into one or divided.

Explanation of Symbols

[0074] 1 Waveform measurement device 10 Signal processing circuit 20 Trigger generation circuit (21(211~21n): Input circuit, 22, 23: Comparator, 24, 25: Flip-flop, 26: OR circuit, 27: Delay circuit, 28: Counter, 29(291~29n): Pulse counter) 30 Storage device 40 Display device 50 Arithmetic unit

Claims

1. A trigger signal generation unit that outputs a trigger signal for causing a signal processing circuit to acquire an input signal, and a trigger counter that counts and outputs the number of times the trigger signal has been output, including a period during which the signal processing circuit is in a state where it cannot acquire the input signal. A trigger generation circuit comprising the above.

2. The trigger generation circuit according to claim 1, further comprising a pulse counter that counts the number of pulses included in the input signal.

3. The trigger generation circuit according to claim 2, wherein the pulse counter measures the time when the pulses included in the input signal arrive.

4. The trigger generation circuit according to any one of claims 1 to 3, wherein the trigger signal generation unit is configured to be able to acquire a setting signal that specifies a condition for outputting the trigger signal.

5. A trigger generation circuit having a trigger signal generation unit that outputs a trigger signal for specifying a timing at which a signal processing circuit starts acquiring an input signal, and a trigger counter that counts and outputs the number of times the trigger signal has been output, including a period during which the signal processing circuit is in a state where it cannot acquire the input signal, a signal processing circuit that starts acquiring the input signal based on the trigger signal and processes the acquired input signal, and a display device that displays the number of times the trigger signal has been output from the trigger generation circuit and the number of input signals acquired by the signal processing circuit. A waveform measurement device comprising the above.

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