Register write suppression

Abstract

Techniques for allocating registers for a processor are provided, the techniques including identifying a first instruction of an instruction dispatch set that satisfies all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of the instruction dispatch set that does not satisfy all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating a register for the second instruction.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefits of U.S. Patent Application No. 16 / 697,147, entitled "REGISTER WRITE SUPPRESSION," filed on November 26, 2019, which is hereby incorporated by reference in its entirety.

Background Art

[0002] Register renaming is a technique that enables instructions with certain architectural register dependencies to be executed out - of - order in an out - of - order processor. More specifically, register renaming removes false dependencies, so that only true read - after - write data dependencies remain. Write - after - write and write - after - read are false dependencies.

[0003] According to register renaming, free physical registers in a register file for writing instruction results are assigned to instructions. Moreover, different physical registers are assigned to two instructions that write to the same architectural register. If those two instructions do not have a read - after - write data dependency, the two instructions can be dispatched out of order. Register renaming provides certain advantages, but the depth of speculative execution is limited by the number of physical registers available for assignment.

[0004] A more detailed understanding can be obtained from the following description given by way of example together with the accompanying drawings.

Brief Description of the Drawings

[0005]

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DETAILED DESCRIPTION OF THE INVENTION

[0006] Techniques are provided for allocating registers to a processor. The techniques include identifying a first instruction of a first instruction dispatch set that meets all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of a second instruction dispatch set that does not meet all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating a register to the second instruction.

[0007] FIG. 1 is a block diagram of an exemplary device 100 in which aspects of the present disclosure are implemented. Device 100 includes, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may optionally also include an input driver 112 and an output driver 114. It will be understood that device 100 may include additional components not shown in FIG. 1.

[0008] Processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, each of which is a CPU or GPU. Memory 104 may be located on the same die as processor 102 or may be located separately from processor 102. Memory 104 includes volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0009] Storage device 106 includes a fixed storage device or a removable storage device (e.g., hard disk drive, solid state drive, optical disk, flash drive). Input device 108 includes a keyboard, keypad, touch screen, touch pad, detector, microphone, accelerometer, gyroscope, biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE802 signals). Output device 110 includes a display, speaker, printer, tactile feedback device, one or more lights, antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE802 signals).

[0010] Input driver 112 communicates with processor 102 and input device 108, enabling processor 102 to receive inputs from input device 108. Output driver 114 communicates with processor 102 and output device 110, enabling processor 102 to send outputs to output device 110. Note that input driver 112 and output driver 114 are optional components and that device 100 operates in the same manner when input driver 112 and output driver 114 are not present.

[0011] FIG. 2 is a block diagram of an instruction execution pipeline 200 located within the processor 102 of FIG. 1. Although one particular configuration for the instruction execution pipeline 200 is shown, it should be understood that a wide variety of instruction execution pipelines fall within the scope of the present disclosure. The instruction execution pipeline 200 fetches instructions from memory, executes the instructions, outputs data to memory, and modifies the state of elements associated with the instruction execution pipeline 200, such as registers within the register file 218.

[0012] The instruction execution pipeline 200 includes an instruction fetch unit 204 that uses an instruction cache 202 to fetch instructions from system memory (such as memory 104), a decoder 208 that decodes the fetched instructions, a functional unit 216 that performs computations to process the instructions, a load store unit 214 that loads data from system memory via a data cache 220 or stores data to system memory, and a register file 218 that includes registers for storing working data for the instructions.

[0013] The decoder 208 generates micro-operations and dispatches the micro-operations to a retire queue 210. Note that the term "instruction" may be used interchangeably with the term "micro-operation" in this specification when referring to an instruction after decoding. In other words, when a particular unit past the decoder stage 208 is said to perform a particular action regarding an instruction, in those instances, the term "instruction" refers to the micro-operations output by the decoder stage 208.

[0014] The register mapper 209 maps the architectural registers specified by the instruction output by the decoder 208 to the physical registers of the register file 218. The register mapper 209 maps the free registers of the register file 218 to the architectural registers written by the instruction. Also, the register mapper 209 maintains a table indicating which architectural register is mapped to which physical register, and uses this table to map the input registers of the instruction to the correct physical registers. The register mapper 209 releases the physical register in response to subsequent actions for the instruction to which the physical register is assigned, assigns a new physical register to the architectural register mapped to the released physical register, and saves the instruction itself that causes the new physical register to be assigned. In other words, the physical register is released in response to the value of the physical register that is no longer needed by the instruction. This value is no longer needed when the architectural register is overwritten and the instruction that overwrote the architectural register is saved.

[0015] The retirement queue 210 tracks the instructions that are currently in-flight and ensures in-order retirement of the instructions, even though out-of-order execution is allowed while they are in-flight. The term "in-flight instruction" refers to an instruction that has been received by the retirement queue 210 but has not yet been retired. Retirement occurs when the instruction has completed (all operations have been performed in the functional unit 216 and / or the load / store unit 214), has not been executed speculatively, or is no longer being executed speculatively. The reservation station 212 maintains the in-flight instructions and tracks the instruction operands. When all operands are ready for the execution of a particular instruction, the reservation station 212 sends the instruction to the functional unit 216 or the load / store unit 214 for execution. The completed instructions are marked for retirement in the retirement queue 210 and are retired when they are at the head of the retirement queue 210. Retirement refers to the operation of committing the result of the instruction to the architectural state of the processor. For example, an instruction can be executed speculatively and out-of-order. If the speculation fails, the instruction is not retired but instead is flushed from the pipeline 200. At the point of retirement, the instruction is, in most cases, no longer being executed speculatively, and thus the result of that instruction is "committed" to the state of the pipeline 200.

[0016] The various elements of the instruction execution pipeline 200 communicate via a common data bus 222. For example, the functional unit 216 and the load / store unit 214 write results to the common data bus 222, and the results may be read by the reservation station 212 for the execution of dependent instructions or may be read by the retirement queue 210 as the final processing result of the in-flight instructions that have completed execution. Also, the load / store unit 214 reads data from the common data bus 222. For example, the load / store unit 214 reads the result from the completed instruction from the common data bus 222 and writes the result to memory via the data cache 220 for a store instruction.

[0017] Figure 3 is a diagram showing exemplary phases related to register naming. The first phase 300 shows the instructions in program order and shows the architectural registers other than physical registers. Four exemplary instructions are shown. Instruction 1 inputs values in architectural registers R1 and R2 and outputs a value to architectural register R3. Instruction 2 inputs values in architectural registers R3 and R4 and outputs a value to architectural register R1. Instruction 3 inputs values in architectural registers R5 and R7 and outputs a value to architectural register R3. Instruction 4 inputs values in architectural registers R3 and R2 and outputs a value to architectural register R4.

[0018] The register naming for these exemplified instructions is shown in register naming phase 310. In this phase, the architectural register written by each instruction is assigned to the physical register file. For Instruction 1, the register mapper 209 assigns physical register PhysReg3 to architectural register R3. For Instruction 2, the register mapper 209 assigns physical register PhysReg10 to architectural register R1. For Instruction 3, the register mapper 209 assigns physical register PhysReg11 to architectural register R3. For Instruction 4, the register mapper 209 assigns physical register PhysReg12 to architectural register R4.

[0019] Note that the architectural register written by instruction 3 is the same as the architectural register written by instruction 1, but the physical registers used are different. This difference allows instructions 1 and 3 to execute out of program order with respect to each other. For example, pipeline 200 executes instruction 3 before instruction 1 or instruction 2. More specifically, the value written to architectural register R3 by instruction 1 is not consumed until after instruction 2, after instruction 3 has overwritten that architectural register. Thus, instruction 3 and subsequent instructions refer to a physical register different from the physical register mapped to architectural register R3 with respect to instruction 1.

[0020] For register input, register mapper 209 maps the physical register holding the value read to the input architectural register. Due to the small sample size of the instructions illustrated in FIG. 3, the sources of data for architectural registers R1, R2, R4, R5, R7 are not shown. However, in one example, as shown in FIG. 3, the physical registers mapped to those architectural registers are generated in a previous instruction (not shown) and are presumed to be placed in the physical registers mapped to those architectural registers. Thus, for example, the value for architectural register R1 is placed in physical register PhysReg1, and thus R1 is mapped to physical register PhysReg1. For the same reason, architectural registers R2, R4, R5, R7 are mapped to physical registers PhysReg2, PhysReg4, PhysReg5, PhysReg7, respectively. Register mapper 209 can use default registers for architectural registers that have not yet been written.

[0021] In some situations, the input value for a newer, exemplified instruction is the same as the output value of an older, exemplified instruction. In those situations, the architectural register that holds the input value for the newer instruction is mapped to the physical register that holds the output of the older instruction. In the example being illustrated, instruction 2 reads from architectural register R3 that holds the value generated by instruction 1. Thus, in instruction 2, architectural register R3 is mapped to physical register PhysReg3, and physical register PhysReg3 is the physical register that is allocated to instruction 1 and mapped to architectural register R3 for instruction 1. Further, instruction 4 reads from the value written to architectural register R3 by instruction 3. In instruction 3, architectural register R3 is mapped to physical register PhysReg11, and thus, in instruction 4, architectural register R3 is mapped to PhysReg11.

[0022] After register mapping, reservation station 212 dispatches the instructions to functional unit 216 and / or load / store unit 214. The first dispatch 320 includes instructions 1 and 3 because instructions 2 and 4 have data dependencies, and thus, execution cannot start until those data dependencies are satisfied. Note that even when instructions 1 and 3 write to the same architectural register, instructions 1 and 3 are both dispatched. Register renaming enables those instructions to be both dispatched. After the data dependencies are satisfied, in the second dispatch, instructions 2 and 4 are dispatched.

[0023] Register naming is important for the proper functioning of out-of-order processors and, in some situations, register naming can result in pressure on register file 218. Here, the term "pressure" refers to a large number of allocated registers resulting from a large number of in-flight instructions. Also, in some situations, some of the allocations are unnecessary because the written values are not consumed. Thus, reducing the allocations in such situations improves register file utilization, which reduces stalls and thereby improves performance. Also, reducing the allocations reduces the register file output because there are fewer writes.

[0024] One aspect of instruction execution associated with register pressure due to register naming is writing flags to a flag register. Flags are values that indicate the state between instructions. There are many examples of flags, some of which include a carry flag that indicates whether there is a carry in the most significant arithmetic logic unit bit position in the result of an operation, a parity flag that indicates whether the last result was even or odd, a zero flag that indicates whether the result of the last operation was zero, a sign flag that indicates the sign of the last operation, and many other flags such as those specified in the FLAGS register in the x86 instruction set architecture. Generally, most or all arithmetic logic unit (ALU) instructions such as addition and subtraction write to a flag register. Thus, in an architecture that allocates a separate physical flag register from data registers, each ALU instruction allocates a new flag register. In many instances, the writes to the flag registers that are executed are not consumed, and thus such allocations are wasted.

[0025] FIG. 4 is a diagram illustrating a technique for physical register allocation to reduce register file pressure according to an example. In FIG. 4, decoder 208 generates and dispatches instruction dispatch set 402. Instruction dispatch set 402 includes a plurality of instructions 404. In some embodiments, this instruction dispatch set 402 is generated within a single cycle. Thus, in some instances, decoder 208 dispatches a plurality of instructions each cycle. In some embodiments, instruction dispatch set 402 is generated over multiple cycles, and thus, the operations performed by register mapper 209 are performed over multiple cycles. In some embodiments, instruction dispatch set 402 includes consecutive instructions 404 in program order that do not have intervening instructions. In one example, instruction dispatch set 402 includes two back-to-back instructions 404 in program order, and the two back-to-back instructions 404 allow register mapper 209 an opportunity to suppress the allocation to the older of those two instructions 404.

[0026] To implement a technique for register allocation that reduces register file pressure, the register mapper 209 detects that at least one instruction in the instruction dispatch set 402 meets a set of allocation suppression criteria. The set of allocation suppression criteria for an instruction includes the following. The first criterion is that the instruction 404 is not the most recent instruction 404 in the instruction dispatch set 402. The second criterion is that the instruction writes a flag that is all overwritten by a newer instruction 404 in the instruction dispatch set 402. The third criterion is that a newer instruction 404 in the instruction dispatch set 402 does not read any of the flags written by the instruction 404. If all criteria of the set of allocation suppression criteria are met for the instruction 404, the register mapper 209 suppresses the allocation of a flag register to the instruction 404. If at least one criterion of the set of allocation suppression criteria is not met for the instruction 404, the register mapper 209 does not suppress the allocation of a flag register to the instruction 404 and allocates a flag register to the instruction 404.

[0027] To provide further detail of the above description, different instructions can write different flags. In one example, an add instruction writes a set of flags including a carry flag, a zero flag, and a parity flag. A subtract instruction writes those same flags. In an example where the instruction dispatch set 402 includes two consecutive instructions 404 (and two or fewer instructions), the two consecutive instructions 404 write the same flags, and the newer instruction 404 does not read any of the flags written by the older instruction 404. In this example, the flag write of the first instruction 404 is suppressed because such flags are not used. In another example of two consecutive instructions 404, the older instruction 404 writes a set of flags, and the newer instruction 404 writes a superset of the set of flags including the set of flags written by the older instruction 404. Further, the newer instruction 404 does not read any of the flags written by the older instruction 404. In this example, the flag writes of the older instruction are suppressed because those flag writes are not used. In another example, the older instruction 404 writes a set of flags, and the newer instruction 404 does not write all of the flags written by the older instruction 404. In this example, the flag write is not suppressed for the older instruction 404. In yet another example, the newer instruction 404 and the older instruction 404 write the same flags, but the newer instruction reads at least one of the flags of the older instruction 404. In this example, the flag write of the older instruction 404 is not suppressed. In the above, the description that a flag write is suppressed means, in some embodiments, that no register is assigned to the flags being written. In other embodiments, this description means that the flag write is not executed.

[0028] As described above, in a situation where instruction 404 satisfies a set of allocation suppression criteria, register allocation for instruction 404 is suppressed. The effect of not allocating a flag register to any particular instruction 404 is that instruction 404 does not write to any of its flags, and the register file pressure is reduced compared to a scenario where the technique of FIG. 4 is not used.

[0029] In some embodiments, the flag register has a renaming space separate from the data register. Another renaming space means that register mapper 209 allocates a physical register to an architectural flag register independent of the physical register mapped to the data register. This is in contrast to a configuration where, every time a data register is allocated, a space (a register (entry) in register file 218 including spaces for both the data register and the flag register) for the flag is also allocated. In embodiments where the flag register has a renaming space separate from the data register, in addition to writing to the flag, the technique of not allocating the above-described flag register is applied to instructions (such as ALU instructions) that execute tasks and also to instructions that write to a flag instead of a data register when the flag is written.

[0030] In other embodiments, the flag register has the same renaming space as the data register. In such embodiments, an entry in the register file includes spaces for both the data register and the flag register. Thus, when an instruction that executes an operation including writing to a data register while writing to a flag is executed, a space in the register file is allocated to the data register and the flag register as a single unit. In such embodiments, it may be possible to reduce the register file pressure by suppressing register allocation. However, in some situations, it may not be possible to reduce the register file pressure even for instructions that satisfy all of the register allocation suppression criteria.

[0031] More specifically, in some situations, the older instruction 404 writes only flags and does not write data. In addition, the older instruction 404 meets all register allocation suppression criteria for the newer instruction 404 that either writes only flags or writes both flags and data. In this situation, the allocation to the older instruction 404 is suppressed because not all of the register file entries for that instruction 404 are used. In particular, instruction 404 does not write data and the flags written by instruction 404 are not used.

[0032] However, in other situations, the older instruction writes both data and flags. In addition, the older instruction 404 meets all register allocation suppression criteria (for the flags) for the newer instruction 404 that either writes only flags or writes both flags and data. In this situation, the allocation to the older instruction 404 is not suppressed because the entries in the register file are needed for the data of the older instruction 404. However, in this situation, the writing of flags to the older instruction 404 is suppressed because those flags are not used.

[0033] It is possible to apply the register suppression technique to registers other than the flag register. More specifically, instead of the register mapper 209 determining whether one or more instructions 404 in the instruction dispatch set 402 meet the register allocation suppression criteria for flags, the register mapper 209 determines whether one or more instructions 404 in the instruction dispatch set 402 meet the register allocation suppression criteria for data. For a second criterion otherwise specified herein, this criterion is that an instruction writes to a data register overwritten by at least one newer instruction 404 of the instruction dispatch set 402. For a third criterion otherwise specified herein, this criterion is that the newer instruction 404 of the instruction dispatch set 402 does not read a register under consideration. For an instruction 404 that meets the register allocation suppression criteria, the register allocation is suppressed.

[0034] FIG. 5 is a flowchart of a method 500 for assigning physical registers in a register file to instructions, according to an example. Method 500 will be described with respect to the system of FIGS. 1-4, but one of ordinary skill in the art will recognize that any system configured to execute the steps of method 500 in any technically feasible order will fall within the scope of the present disclosure.

[0035] Method 500 begins at step 502, where register mapper 209 identifies a first instruction of instruction dispatch set 402 that meets all register assignment suppression criteria of a set of register assignment suppression criteria. The set of register assignment criteria is described elsewhere herein. Instruction dispatch set 402 is described elsewhere herein.

[0036] At step 504, because the first instruction meets all register assignment suppression criteria, register mapper 209 suppresses register assignment for the first instruction. As described elsewhere herein, in another register renaming space register file, suppressing register assignment for a flag register with respect to the first instruction means that the flag register assigned to the first instruction is not assigned to that instruction, and thus at least one additional register is available for use by a different instruction. As described elsewhere herein, in a non-separate namespace register file, when flags and data share slots in the register file, suppressing register assignment means either suppressing the assignment of the entire register file slot or not writing to a portion of the register file slot, with another portion of the register file slot being used for another purpose (e.g., data).

[0037] In step 506, register mapper 209 identifies a second instruction of an instruction dispatch set that does not meet all of the register assignment suppression criteria of the set of register assignment suppression criteria. In step 508, in response to step 506, register mapper 209 does not suppress register assignment for the second instruction.

[0038] In some embodiments, method 500 is executed to determine whether to suppress flag register assignment. In other embodiments, method 500 is executed to determine whether to suppress data register assignment.

[0039] In some embodiments, in some situations, register assignment is suppressed, but instruction execution pipeline 200 later determines that a written register value is required. One example of such a situation is when an instruction within instruction dispatch set 402 suppresses register assignment, but instruction execution pipeline 200 detects that an exception has occurred and thus a value that has not been written is required. In such a situation, instruction execution pipeline 200 flushes the instruction and replays the instruction without suppressing the write.

[0040] In some embodiments, an additional criterion for the register assignment suppression criterion is that the instruction for which the criterion is tested is not a branch instruction.

[0041] It should be understood that many variations are possible based on the disclosure herein. Although features and elements have been described above in specific combinations, each feature or element may be used alone without other features and elements, in various combinations with other features and elements, or in various combinations without other features and elements.

[0042] The various functional units illustrated and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, instruction cache 202, instruction fetch unit 204, decoder 208, register mapper 209, save queue 210, reservation station 212, data cache 220, load / store unit 214, functional unit 216, register file 218, and common data bus 222) may be implemented as hardware circuitry, software executed on a programmable processor, or a combination of hardware and software. The methods provided may be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, general purpose processors, dedicated processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using the results of other intermediate data (such instructions that may be stored on a computer-readable medium) including hardware description language (HDL) instructions and netlists to be processed. The results of such processing may be a mask work used in a semiconductor manufacturing process to manufacture a processor implementing aspects of the embodiments.

[0043] The methods or flowcharts provided herein may be implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include magnetic media such as read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, internal hard disks, and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method for allocating registers of a processor, comprising: suppressing allocation of a flags register for a first instruction of an instruction dispatch set in response to the first instruction satisfying all register allocation suppression criteria of register allocation suppression criteria, the register allocation suppression criteria including a requirement that the first instruction writes a flag that is overwritten by one or more new instructions of the instruction dispatch set; Executing the first instruction to generate data to be stored in a data register; and allocating a flags register for a second instruction of the instruction dispatch set in response to the second instruction not satisfying all register allocation suppression criteria. method.

2. the register allocation suppression criteria include a requirement that the first instruction is not the newest instruction of the instruction dispatch set.

10. The method of claim 1.

3. the register allocation suppression criteria include a requirement that the first instruction is not the newest instruction in the instruction dispatch set, and a requirement that instructions in the instruction dispatch set newer than the first instruction are prohibited from reading a flag written by the first instruction.

10. The method of claim 1.

4. the register allocation suppression criteria include a requirement that instructions newer than the first instruction in the instruction dispatch set be prohibited from reading a flag written by the first instruction; 10. The method of claim 1.

5. the register allocation suppression criteria include criteria relating to data registers; 10. The method of claim 1.

6. the instruction dispatch set includes instructions that are consecutive in program order with no intervening instructions; 10. The method of claim 1.

7. suppressing allocation of a flags register for the first instruction includes suppressing allocation of a register written to by the first instruction.

10. The method of claim 1.

8. an instruction processing subsystem for allocating registers of a processor, a decode unit configured to dispatch an instruction dispatch set; a circuit, The circuit comprises: suppressing allocation of a flags register for a first instruction of an instruction dispatch set in response to the first instruction satisfying all register allocation suppression criteria of register allocation suppression criteria, the register allocation suppression criteria including a requirement that the first instruction writes a flag that is overwritten by one or more new instructions of the instruction dispatch set; Executing the first instruction to generate data to be stored in a data register; allocating a flag register for a second instruction of the instruction dispatch set in response to the second instruction not satisfying all register allocation suppression criteria; configured to: Instruction processing subsystem.

9. the register allocation suppression criteria include a requirement that the first instruction is not the newest instruction of the instruction dispatch set. The instruction processing subsystem of claim 8.

10. the register allocation suppression criteria include a requirement that the first instruction is not the newest instruction in the instruction dispatch set, and a requirement that instructions in the instruction dispatch set newer than the first instruction are prohibited from reading a flag written by the first instruction. The instruction processing subsystem of claim 8.

11. the register allocation suppression criteria include a requirement that instructions newer than the first instruction in the instruction dispatch set be prohibited from reading a flag written by the first instruction; The instruction processing subsystem of claim 8.

12. The instruction dispatch set includes instructions that are consecutive in program order with no intervening instructions. The instruction processing subsystem of claim 8.

13. the register allocation suppression criteria include criteria relating to data registers; The instruction processing subsystem of claim 8.

14. the instruction dispatch set includes instructions that are consecutive in program order with no intervening instructions; The instruction processing subsystem of claim 8.

15. suppressing allocation of a flags register for the first instruction includes suppressing allocation of a register written to by the first instruction. The instruction processing subsystem of claim 8.

16. A processor for allocating processor registers, a decode unit configured to dispatch an instruction dispatch set; A circuit comprising: suppressing allocation of a flags register for a first instruction of an instruction dispatch set in response to the first instruction satisfying all register allocation suppression criteria of register allocation suppression criteria, the register allocation suppression criteria including a requirement that the first instruction writes a flag that is overwritten by one or more new instructions of the instruction dispatch set; Executing the first instruction to generate data to be stored in a data register; allocating a flag register for a second instruction of the instruction dispatch set in response to the second instruction not satisfying all register allocation suppression criteria; and a circuit configured to: one or more functional units configured to execute either or both of the first instructions and the second instructions. Processor.

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